EP0312720A3 - Double buffered graphics design system - Google Patents

Double buffered graphics design system Download PDF

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Publication number
EP0312720A3
EP0312720A3 EP88112554A EP88112554A EP0312720A3 EP 0312720 A3 EP0312720 A3 EP 0312720A3 EP 88112554 A EP88112554 A EP 88112554A EP 88112554 A EP88112554 A EP 88112554A EP 0312720 A3 EP0312720 A3 EP 0312720A3
Authority
EP
European Patent Office
Prior art keywords
frame buffer
pixel data
data stored
buffer memory
accordance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP88112554A
Other languages
German (de)
French (fr)
Other versions
EP0312720A2 (en
Inventor
Kendall Poul Auel
James Anthony Delwiche
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tektronix Inc
Original Assignee
Tektronix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tektronix Inc filed Critical Tektronix Inc
Publication of EP0312720A2 publication Critical patent/EP0312720A2/en
Publication of EP0312720A3 publication Critical patent/EP0312720A3/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/399—Control of the bit-mapped memory using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Image Generation (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)

Abstract

A graphic display system comprises a video display controller including two similar frame buffer memories for alternatively receiving and storing incoming pixel data and for periodically refreshing a display on a screen selectively in accordance with pixel data stored by either one of the two frame buffer memories. While the video display controller periodically refreshes the screen display in accordance with the pixel data stored in a first of the frame buffer memories, incoming pixel data is stored in the second frame buffer memory. The video display controller begins periodically refreshing the screen display in accordance with the pixel data stored in the second frame buffer memory. Updated pixel data stored in the second frame buffer memory is then copied into the first frame buffer memory.
EP88112554A 1987-10-20 1988-08-02 Double buffered graphics design system Withdrawn EP0312720A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11090287A 1987-10-20 1987-10-20
US110902 1987-10-20

Publications (2)

Publication Number Publication Date
EP0312720A2 EP0312720A2 (en) 1989-04-26
EP0312720A3 true EP0312720A3 (en) 1990-06-13

Family

ID=22335558

Family Applications (1)

Application Number Title Priority Date Filing Date
EP88112554A Withdrawn EP0312720A3 (en) 1987-10-20 1988-08-02 Double buffered graphics design system

Country Status (2)

Country Link
EP (1) EP0312720A3 (en)
JP (1) JPH01134524A (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5061919A (en) * 1987-06-29 1991-10-29 Evans & Sutherland Computer Corp. Computer graphics dynamic control system
US5050102A (en) * 1989-04-28 1991-09-17 Sun Microsystems, Inc. Apparatus for rapidly switching between output display frames using a shared frame gentification memory
FR2674361B1 (en) * 1991-03-19 1995-11-24 Jaeger ELECTRONIC CIRCUIT FOR CONTROLLING A GRAPHIC SCREEN, PARTICULARLY A LIQUID CRYSTAL SCREEN
EP0525986B1 (en) * 1991-07-26 1996-11-13 Sun Microsystems, Inc. Apparatus for fast copying between frame buffers in a double buffered output display system
US5331417A (en) * 1992-09-15 1994-07-19 Digital Pictures, Inc. System and method of displaying a plurality of digital video images
US5831638A (en) * 1996-03-08 1998-11-03 International Business Machines Corporation Graphics display system and method for providing internally timed time-varying properties of display attributes
US7012601B2 (en) 2000-09-07 2006-03-14 Actuality Systems, Inc. Line drawing for a volumetric display
DE60124566T2 (en) 2000-09-07 2007-09-06 Actuality Systems, Inc., Reading VOLUMETRIC IMAGE DISPLAY DEVICE
JP2002123488A (en) 2000-10-16 2002-04-26 Sony Corp Method and device for controlling equipment
WO2011104582A1 (en) 2010-02-25 2011-09-01 Nokia Corporation Apparatus, display module and methods for controlling the loading of frames to a display module
US9251555B2 (en) 2012-06-08 2016-02-02 2236008 Ontario, Inc. Tiled viewport composition
EP2672480B1 (en) * 2012-06-08 2016-11-16 2236008 Ontario Inc. Tiled viewport composition
CN109885271A (en) * 2019-03-18 2019-06-14 青岛海信电器股份有限公司 Data display and treating method, device and electronic equipment

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0194092A2 (en) * 1985-02-25 1986-09-10 Computer Graphics Laboratories, Inc. Display system and method
EP0219552A1 (en) * 1985-04-08 1987-04-29 Anritsu Corporation Device for displaying polar coordinates in raster scanning system
EP0231061A2 (en) * 1986-01-21 1987-08-05 International Business Machines Corporation Improvements in or relating to graphic display systems
EP0237706A2 (en) * 1986-02-14 1987-09-23 International Business Machines Corporation Electrical display system
EP0268687A1 (en) * 1986-05-21 1988-06-01 Fanuc Ltd. System for saving image data

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0194092A2 (en) * 1985-02-25 1986-09-10 Computer Graphics Laboratories, Inc. Display system and method
EP0219552A1 (en) * 1985-04-08 1987-04-29 Anritsu Corporation Device for displaying polar coordinates in raster scanning system
EP0231061A2 (en) * 1986-01-21 1987-08-05 International Business Machines Corporation Improvements in or relating to graphic display systems
EP0237706A2 (en) * 1986-02-14 1987-09-23 International Business Machines Corporation Electrical display system
EP0268687A1 (en) * 1986-05-21 1988-06-01 Fanuc Ltd. System for saving image data

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN vol. 26, no. 6, November 1983, pages 2906,2907, New York, US; W. HALL et al.: "Low cost, high resolution IBM 3101 Graphics" *

Also Published As

Publication number Publication date
EP0312720A2 (en) 1989-04-26
JPH01134524A (en) 1989-05-26

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