JPH08211849A - Display control device - Google Patents

Abstract

PURPOSE: To display a hard window at the arbitrary position on the screen of a display device whose one screen is constituted of plural display panels. CONSTITUTION: A line buffer part 30 is provided in between a frame memory 20 and a liquid crystal display device 10. The liquid crystal display device 10 is constituted of two liquid crystal panels for an upper screen and a lower screen 10U, 10L. The serial port of the frame memory 20 and input terminals of the liquid crystal panel for the upper screen 10U and the liquid crystal panel for the lower screen 10L are connected respectively to the input port 31 and respective output ports 36U, 36L of the line buffer part 30. Then, image data read out from the serial port of the frame memory 20 are successively stored in four line buffers 34U, 35U, 34L, 35L and image data stored in two line buffers are inputted to the liquid crystal display panels for the screens 10U and 10L respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device for reading image data from an image memory (frame memory or video RAM) and controlling the display device to display the image.

[0002]

2. Description of the Related Art In recent years, the demand for flat panel displays typified by liquid crystal display devices has rapidly increased with the spread of notebook personal computers and sub-notebook personal computers. In addition, research and development are being actively pursued to realize large-sized wall-mounted TVs and wide-screen displays by making them thinner.

FIG. 37 is a diagram for explaining a general screen display method on a CRT display. The example shown in the figure is a diagram showing an example in which screen display is performed by an interlaced scanning method.

Display screen (screen) 100 of the display device
A phosphor is applied on the top, and in the figure, A → B, C →
An image is displayed while sequentially irradiating an electron beam on one point (pixel) of the phosphor screen by a scanning line 101 indicated by arrows D, ... I → J. The trajectory of the electron beam moving from one scanning line 101 to the next scanning line 101 is a horizontal retrace line 102.
It is called (broken line arrow B → C, D → E, ... H → I), and the movement trajectory of the electron beam from the end of display of one screen to the beginning of the next screen is the vertical retrace line 103. It is called (fine broken arrow J → A).

In addition, the brightness of the pixel is modulated by modulating the intensity of the electron beam applied to the pixel in the display, which is read out from the image data (luminance data) stored in the frame memory 200. Done by

FIG. 38 is a block diagram of the frame memory 200. The frame memory 200 is also called a bitmap memory, and has a display data area 210 in which image data corresponding to each pixel of the display screen 100 is stored in a one-to-one correspondence.
have. In FIG. 38, for example, the image data corresponding to the pixel A of the display screen 100 shown in FIG. 37 is stored in the address A ′ of the display data area 210, and the image data corresponding to the pixel H is the address of the display data area 210. It is stored in H '. Then, in accordance with the scanning line 101 described above, the image data to be displayed is displayed in the display data area 21.
The image is read from 0 and the image is displayed on the display screen 100.

By the way, a "hard window" is known as a concept of a window display system in an information processing apparatus. 39 and 40 are views for explaining the concept of the hard window 310 and the method of storing it in the frame memory 200.

The hard window 310 is a base screen 30 displayed on the entire display screen 100 as shown in FIG.
It is a logical screen displayed as a window in 0.
In the frame memory 200, as shown in FIG. 40, the image data of the base screen 300 and the image data of the hard window 310 are in different areas 2 respectively.
30 and 240. The contents of the hard window 310 are mapped onto a part (or the whole) of the base screen 300 by a hardware circuit, and the image on the display screen 100 is rewritten. That is, the image can be rewritten by mapping the hard window 310 on the base screen 300 without rewriting the contents (image data) of the base screen 300.

Next, referring to FIGS. 41 and 42,
A method of displaying the hard window 310 will be described. Figure 41
In, the hard window 310 is displayed on a part of the base screen 300 of the display screen 100. Further, in the figure, the scanning lines 101 are a → b, c → d, ... W →
This is indicated by the arrow x. Further, in particular, the scanning line 101 'for displaying the hard window 310 is changed from h → i, l →
m, ... T → u.

Corresponding to the display screen 100, the image data of the base screen 300 and the image data of the hard window 310 are stored in areas 230 and 240 in the frame memory 200 as shown in FIG. ing. Further, in FIG. 42, the scanning line 1 shown in FIG.
The storage position of the image data of the base screen 300 read corresponding to 01 corresponds to the scanning line 101 of the arrow a → b, c → d, ... W → x a ′ → b ′, c ′ → d ',
It is shown by the arrow of w '→ x' .... Also, h → j,
The storage positions of the image data of the hard window 310 read corresponding to the scanning lines 101 ′ of l → m, ..., T → u are made h ′ → corresponding to the scanning lines 101 ′.
It is shown by arrows of j ′, l ′ → m ′, ... t ′ → u ′.

That is, when the display screen 100 shown in FIG. 41 is displayed, the image data is read from the frame memory 200 from the area 230 a ′ → b ′, corresponding to the scanning of the display of the base screen 300. c '→ d',
It is performed in the order of e ′ → f ′. Then, when the process goes from g ′ to h ′, the reading position of the image data is moved to the area 240 in order to shift to the reading of the image data of the hard window 310. That is, g → j, k → n, o
In scan line 101 of → r, s → v, h ′ of area 240
The image data is read from → i ', l' → m ', p' → q ', l' → n '. Then, in the scan line of w → k, the image data storage area 23 of the base screen 300 is again displayed.
Reading of image data is started from 0 (w ′ →
x ').

In this way, on the actual screen, a logical screen different from the base screen 300 can be displayed as a hard window 300 on a part (or all) of the entire display screen.

[0013]

However, there is a problem in that the above-described method of displaying a hard window cannot be applied to a large-screen liquid crystal display device used as a display of an information processing device.

The reason for this will be described below. FIG. 43 shows
It is a figure which shows the structure of the liquid crystal display device currently generally used as a display of an information processing apparatus, and the structure of the frame memory corresponding to this.

Since the liquid crystal display panel has a low manufacturing yield for a large screen, two panels (a liquid crystal display panel) 31 for an upper screen and a lower screen as shown in FIG.
A display screen 300 of one screen is composed of 0 and 320. Corresponding to this panel configuration, frame memories 410 and 420 are provided in a one-to-one correspondence with each of the panels 310 and 320. These memories 410 and 420 are composed of, for example, dual port RAMs, and the image data drawn in the respective memories 410 and 420 are output from their serial ports to the corresponding panel 31.
0, 320 is output.

As described above, since the frame memory is completely separated for the upper screen and the lower screen, the upper screen panel 310 can display only the contents of the upper screen frame memory 410 and the lower screen panel. 320 has a mechanism capable of displaying only the contents of the lower screen frame memory 420.

The left side of FIG. 44 shows the internal structure of the frame memories 410 and 420 for the upper screen and the lower screen. In the figure, an area a of the upper screen frame memory 410 is a drawing area of image data of the base screen of the upper screen panel 310, and an area b of the lower screen frame memory 420.
Is a drawing area of image data of the base screen of the lower screen panel 320. The area c of the frame memory 410 is used as a drawing area such as a window attached to the upper base screen. Similarly, the area d of the frame memory 420 is used as a drawing area such as a window attached to the base screen of the lower screen.

Therefore, the liquid crystal display panel 30
The base screen of 0 is displayed by the upper screen frame memory 41.
This is performed by reading image data from the area a of 0 and the area b of the lower screen frame memory 420. The physical memory map of the frame memories 410 and 420 is shown in FIG.
However, this makes access to the frame memories 410 and 420 when the CPU displays a screen on the liquid crystal display 300 very inefficient, which reduces the processing capacity of the CPU. Lower.
Therefore, the CPU and the frame memories 410 and 420
And ATB (Addres Transfer Buffer) not shown
44 is provided on the right side of FIG. 44 by providing a mechanism (hardware) for converting a logical address into a physical address such as an MMU (Memory Management Unit) to physically separate the CPUs. Continuous logical address space (logical memory space) shown in
It is accessible by 500. Address spaces a ', b', c ', and d'correspond to regions a, b, c, and d of the frame memories 410 and 420, respectively. As a result, the CPU can successively and efficiently access the area a of the frame memory 410 and the area b of the frame memory 410 by accessing the logical addresses a ′ and b ′.

Next, consider the case where a hard window is displayed in a system using the address translation mechanism as described above. FIG. 45 shows an example in which the hard window h is displayed on the panel 310 of the upper screen. In this case, the image data of the hard window is drawn in a part of the area c of the frame memory 410 for the upper screen. In this example, as shown in the lower part of the figure, the image data of the hard window h is stored in the area c of the frame memory 410 for the upper screen.
And is input to the panel 310 on the upper screen. Then, the hard window h is displayed on the panel 310 of the upper screen. Therefore, in this case, the display of the hard window h is possible.

Next, FIG. 46 shows an example in which the hard window h is displayed on the panel 310 of the upper screen, as described above. The image data of the hard window h is as shown in the lower part of FIG. It is stored in the area d of the frame memory 410 for the lower screen. As described above, the image data output from the frame memory 410 is performed by the panel 32 on the lower screen.
It is possible only for 0, and it is impossible to output to the panel 310 of the upper screen as shown by the broken line on the lower side of the figure. Therefore, in this case, the hard window h cannot be displayed.

Similarly, it is impossible to display the image of the hard window h drawn in the area c of the frame memory 410 for the upper screen on the panel 320 of the lower screen. It is also impossible to display the hard window across the upper and lower panels 310 and 320.

As described above, the conventional liquid crystal display device 3 has a structure in which one screen is displayed by the upper and lower separated panels.
In 00, the display of the hard window could not be completely realized.

An object of the present invention is to completely realize display of a hard window in a liquid crystal display device having a display panel divided into upper and lower parts.

[0024]

The present invention is premised on a display control device for displaying a hard window on the screen of a display device in which one screen is composed of a plurality of display panels.
The following means are provided.

The frame memory stores the image data of the base screen and the image data of the hard window. A plurality of line buffers are provided corresponding to each display panel, and each line buffer stores the image data of the base screen or the hard window read from the frame memory.

The control means reads out the image data of the base screen or the hard window from the frame memory according to the scanning sequence on the screen of the display device, inputs the image data into the line buffer, and The image data stored in the plurality of line buffers is input to the display panel according to the scanning order.

In the above structure, two line buffers are provided for each display panel, and the control means uses the two line buffers for reading image data from the frame memory and for the liquid crystal display panel. It is also possible to adopt a configuration in which the image data to be used is alternately switched for output.

The display panel is, for example, a liquid crystal display panel.

[0029]

The CPU or the like writes the image data displayed on the screen of the display device into the frame memory for each frame. This image data includes that for the base screen and that for the hard window.

The control means reads the image data of the base screen or the hard window in a frame from the frame memory according to the scanning order on the screen of the display device, and inputs the image data to the line buffer. At the same time, the image data stored in the plurality of line buffers is input to the display panel according to the scanning order.

Therefore, by configuring the control means by hardware, a hardware window at an arbitrary position in the base screen displayed on the screen of the display device in which one screen is composed of the plurality of display panels is formed. It is possible to display at high speed.

[0032]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a circuit configuration of a liquid crystal display control device according to an embodiment of the present invention.

The liquid crystal display device 10 includes two liquid crystal display panels 10U and 10L to form one display screen.
A horizontal drive circuit and a vertical drive circuit for driving the liquid crystal display panels 10U and 10L to display are provided in the periphery thereof. The first liquid crystal display panel (upper screen liquid crystal display panel) 10U displays the upper screen image of the entire screen, and the second liquid crystal display panel (lower screen liquid crystal display panel) 10L displays the lower screen image of the entire screen. Is displayed. The two liquid crystal display panels 10U and 10L have the same number of scanning lines.

The frame memory 20 is a dual port
It is composed of a memory, and its serial port output a is connected to an input terminal 31 of a line buffer unit 30 described later. The frame memory 20 stores a base screen display area 22 that stores image data of a base screen displayed on the entire screen of the liquid crystal display device 10, and image data of a logical screen of a hard window displayed on the base screen. It comprises a hard window buffer area 24. Generally, there are a plurality of logical screens, and the image data of the logical screen is read out and displayed on the liquid crystal display prosecution 10 as needed.

The line buffer section 30 includes two first and second upper screen (upper) line buffers 34 for storing image data for one line (one scanning line) of the upper screen.
U and 35U, and two first and second lower screen (lower side) line buffers 34L and 35L for storing image data for one line (one scanning line) of the lower screen, for a total of four. It has a line memory. These line buffers 34
U, 34L, and 35L are FIFO (first-in first-out: Firs
t In First Out) Memory. The line buffer unit 30 has one input port 31 and two output ports 3
6U and 36L are provided, and the image data output from the serial port of the frame memory 20 is input to the input port 31. Also, the output port 36 for the upper screen
Image data from U to the upper screen liquid crystal display panel 10U
From lower screen output port 36L to lower screen liquid crystal display panel 1
The image data to 0L is output.

The input terminals of the two first and second line buffers 34U, 35U for the upper screen are alternately connected to the serial port of the frame memory 20 at a timing described in detail later. Similarly, the input terminals of the two first and second line buffers 34L and 35L for the lower screen are alternately arranged at the timings described in detail later.
Connected to the serial port of. Moreover, the output terminals of the two line buffers 34U and 35U for the upper screen are alternately connected to the output port 36U for the upper screen liquid crystal display panel 10U at a timing described later in detail. Similarly, the output terminals for the two line buffers 34L and 35L for the lower screen are alternately connected to the output port 36L for the lower screen liquid crystal display panel 10L at the timing described later in detail. Switching of these connections is performed, for example, via a demultiplexer (not shown).

FIG. 2 is a diagram showing an example of the configuration of the line buffer section 30. The first demultiplexer 32 receives the frame memory 20 from its input terminal I (input port 31).
Input the image data output from the serial port. Further, a current number CLN is input to the select signal input terminal S from a line counter 50 described later as a kind of select signal. This current number CLN
As will be described later, indicates which scan line on the screen displayed on the liquid crystal display device 10 the image data currently output from the serial port of the frame memory 20 is displayed on. Then, depending on the value of the current number CLN, the image data input to the input terminal I is output to the four output terminals Y _u1 , Y _u2 , Y _l1 or Y.
Output from any one of _l2 . The output terminal Y _u1 ,
Y _u2 , Y _l1 , and Y _l2 are respectively a first upper screen line buffer 34U, a second upper screen line buffer 35U,
It is connected to the input ports of the first lower screen line buffer 34L and the second lower screen line buffer 35L.

The function of the first demultiplexer 32 is:
It is as follows. When CLN = 2n (n = 0, 1, 2, ... Max ₁ ), the input image data is output from the output terminal Yu ₁ to the first upper screen line buffer 34U. Note that max ₁ is a value that is ½ of the number of lines on the upper screen (however, the number of lines on the upper screen is an even number line and starts from the 0th line). When CLN = 2n + 1, the second from the output terminal _Yu2
Output the input image data to the upper screen line buffer 35U. When CLN = 2 m (m = S, S + 1, ... e), the output terminal Y _l1 to the first lower screen line buffer 3
Output the input image data to 4L. However, S is a value of 1/2 of the first line of the lower screen, and e is (final line-1) of the lower screen.
1/2 the value of. Also in this case, the number of lines on the lower screen is an even number.) When CLN = 2m + 1, the output terminal Y _l2 to the second
Therefore, the input image data is output to the lower screen line buffer 35L. Therefore, the 0th line image data of the upper screen is stored in the first upper screen line buffer 34U. The image data of the first line on the upper screen is stored in the second upper screen line buffer 35U. Thereafter, similarly, the image data of the second and subsequent lines on the upper screen is the same as the first upper screen line buffer 34U and the second upper screen line buffer 35U.
It is stored in U alternately.

The image data of the 2nd line (the 0th line of the lower screen) is the first lower screen line buffer 34.
Stored in L. The image data of the (2m + 1) th line (second line of the lower screen) is stored in the second lower screen line buffer 35L. Thereafter, in the same manner, the image data of the second and subsequent lines of the lower screen is displayed in the first lower screen line buffer 34L and the second lower screen line buffer 35L.
It is stored alternately in L.

The second demultiplexer 33 includes a first upper screen line buffer 34U and a second upper screen line buffer 34U, respectively.
35U, first and second lower screen line buffer 34
4 input terminals I connected to L and 35L output ports
_{It has U1} , I _U2 , I _L1 and I _L2 . The current line number CLN output from the line counter 50 is input to the select signal input terminal S, and the input terminal I _U1 or I _{U1 is} input according to the current line number CLN.
Image data input to _U2 is displayed on the upper LCD screen 1
The image data input to the input terminal I _L1 or I _L2 is output to 0U to the lower screen liquid crystal display panel 10L.

The functions of the second demultiplexer 33 are summarized as follows. When CLN = 2n + 1 or 2m + 1, the first upper screen image buffer 34U input from the input terminal I _U1
LCD for the upper screen image data stored output terminal Y via a _u (for the upper screen output port 36U) on the display panel 1
The image data stored in the first lower screen image buffer 34L, which is input to the 0U from the input terminal I _L1, is output via the output terminal Y _L (the lower screen output port 36L) to the screen liquid crystal display panel 10L. Output to. When CLN = 2n or 2m, onto a screen for a liquid crystal display panel 10U via the output terminal Y _u image data stored in the second on the screen image buffer 35U inputted from the input terminal I _U2, input The image data stored in the second lower screen image buffer 35L input from the terminal I _L2 is output to the lower screen liquid crystal display panel 10L.

As a result, the image data of the same line on the upper screen and the lower screen are simultaneously input from the line buffer section 30 to the upper screen display panel 10U and the lower screen display panel 10L, respectively.

Liquid crystal display device timing signal generation circuit 40
Is a sequencer that generates a timing signal for generating the operation timing of the entire system shown in FIG. 1, and generates various timing signals from a reference clock generated by an internal or external crystal oscillator (not shown).
Output.

These timing signals include the following. A signal CL1 output to the liquid crystal display device 10 ... A signal that determines the timing of writing the display data for I lines read in the shift register provided inside the liquid crystal display device 10 into the liquid crystal screen. Which line is written is specified by the line selector. After the writing is completed, the content of the line selector is incremented to specify the line to be written next.

The line selector is provided inside the liquid crystal display device 10. CL2: Timing signal for writing the display data sent from the line buffer unit 30 into the shift register bit by bit. When the data is written, the display data stored in the shift register is sequentially sent to the registers in the subsequent stages when new display data is serially input bit by bit. (The number of stages of the shift register is equal to the number of dots in the horizontal direction of the liquid crystal display device, and it is possible to read data for one line of the liquid crystal display device by all the shift registers. FLM ... First line It is called a marker, and if CL1 is output while this signal is being output, the line selector is reset to point to the first line (that is, the top line) of the liquid crystal display device. Signal output to frame memory 20 RAS (row address / strobe signal): signal for fetching row address signal on address bus into frame memory 20. CAS (column address / strobe signal): address bus A signal for loading the upper column address signal into the frame memory 20. DT / OE ... Dual port A signal for controlling the data output of the random port of the frame memory 20 which is a memory and the data transfer control between the data register and the memory cell inside the frame memory 20. SC ... For input / output of serial data inside the frame memory 20 Clock signal for serially inputting / outputting data from the data buffer via the serial port (also serves as a frame memory serial read clock) Signal output to line counter 50 Signal for incrementing contents of line counter 50 (first Increment signal) and a signal for resetting (first reset signal).
It is the same signal as CL1 and FLM. Signal Output to Horizontal Dot Counter 60 A signal (second increment signal) for incrementing the contents of the lateral dot counter 60 and a signal (second reset signal) for resetting.

The second increment signal is the CL
2. The second reset signal is the same signal as CL1. The line counter 50 is a counter that counts the scanning line position CLN on the display screen of the liquid crystal display device 10 of the image data to be read from the frame memory 20, and the timing signal generation circuit 40 adds the first increment signal. It is incremented by "1" every time. Further, when the first reset signal FLM is applied from the timing signal generation circuit 40, it is reset to "0".

The horizontal dot counter 60 is used in the liquid crystal display device 1.
The counter is a counter for counting the current display dot position (display pixel position) at the time of each raster scan of 0, and is incremented by "1" every time the first increment signal is added from the timing signal generation. Further, when the second reset signal CL1 is applied from the timing signal generation circuit 40, it is reset to "0".

As shown in FIG. 3, the upper screen hard window register set 70U includes a hard window start line register RSL and a hard window end register R.
EL, hard window start horizontal dot (dot) register RSD, and hard window end horizontal dot (dot)
t) Consists of a register RED.

Hard window start line register RS
L ... A register that stores the raster scanning position of the first line of the hard window displayed on the upper screen. Hard window end line register REL ... A register for storing the raster scanning position of the last line of the hard window displayed on the upper screen. Hard window start horizontal dot register RSD ... A register for storing the first pixel position in each raster scan of the hard window. Hard window end horizontal dot register RED ... A register for storing the first pixel position in each raster scan of the hard window. The lower screen hard window register set 70L has the same configuration as the upper screen hard window register 70U, except that the value set in each register is a value related to the lower screen hard window.

The upper screen hard window register set 70U and the lower screen hard window register set 70
D is connected to a bus 100 of a CPU (not shown), and the upper and lower screen register sets 70U and 70 are connected to each other.
Data is set in each register in D by the CPU.

The upper screen comparator 80U receives a signal (current line number) indicating the current raster scan increment from the line counter 50, and a signal (current line number) indicating the current display pixel position from the horizontal dot counter 60.
Horizontal dot number) Enter the CDN. Also, each register value is input from the upper screen hard window register set 70U. Then, based on these signals and register values, a first hard window start address output enable signal indicating a start timing at which image data of a hard window to be displayed on the upper screen from the frame memory 20 is instructed, and the hardware from the frame memory 20 is output. A first base screen restoration address output enable signal BO for instructing a start timing at which the reading of the image data of the window is finished and the image data of the upper screen of the base screen should be read again
E is output to the upper screen address generation circuit 90U.

Similar to the upper screen comparator 80U, the lower screen comparator 80L sends a signal indicating the current raster scanning position (current line number) from the line counter 50 and the current display pixel position (current) from the horizontal dot counter 60.・ Input the signal indicating the horizontal dot number. Also, each register value is input from the lower screen hard window register set 70D. Then, a second hard window start address output enable signal for instructing a start timing at which the image data of the hard window to be displayed on the lower screen from the frame memory 20 is read from these signals and each register value, and the hardware from the frame memory 20. After the reading of the image data of the window is completed, the second base screen restoration address output permission signal for instructing the start timing to read the image data of the lower screen of the base screen again is output to the lower screen address generation circuit 90D.

FIG. 4 is a block diagram showing a configuration example of the upper screen comparator 80U and the lower screen comparator 80L. The line number comparator 801 inputs the current number CLN output from the line counter 50 and the data set in the hard window start line register RSL and the hard window end line register REL. Then, the current line number C
LN value VAL CLN is the value VAL set in the register RSL Value VAL of RSL and the register REL
Period within the range of REL (VAL RSL ≦ VAL
CLN ≦ VAL REL period), dot
The first dot comparator 803 and the second dot comparator 8 are activated by activating the comparator output permission signal.
Output to 05.

In addition to the dot comparator output enable signal, the first dot comparator 803 outputs the current horizontal dot number CDN and the hard window start horizontal dot register RSD output from the horizontal dot counter 60.
Enter the setting value of. Then, the value of the current horizontal dot number CDN and the value of the hard window start horizontal dot register RSD VAL By comparing with RSD, the hard window start address permission signal is output when the two values become equal during the period when the dot comparator output permission signal is active. This signal is a signal instructing the timing of switching the reading of the image data from the frame memory 20 from the image data of the base screen to the image data of the logical screen of the hard window.

The second dot comparator 805 outputs the current horizontal dot number CD output from the horizontal dot counter 60 in addition to the dot comparator output enable signal.
Input N and the set value of the hard window end horizontal dot register RED. Then, the current horizontal dot number CDN and the hard window end horizontal dot register RED
Value of VAL As compared with RED, during the period in which the dot comparator output permission signal is active, the base screen restoration address output permission signal is output when the values of both are equal. This signal is a signal instructing the timing of switching the reading of the image data from the frame memory 20 from the image data of the logical screen of the hard window to the image data of the base screen.

FIG. 5 is a block diagram showing a configuration example of the upper screen address generation circuit 90U. The logical screen start address register RLPS is set with the address of the first pixel of the logical screen displayed as a hard window on the upper screen of the liquid crystal display device 10 stored in the hard window buffer area 24 of the frame memory 20. .

Base screen Top address generation circuit 901
Is supplied with the current line number CLN from the line counter 50 and the upper screen comparator 8
A base screen start address output permission signal is input from 0U. The current line number CL of the base screen displayed on the upper screen of the liquid crystal display device 10 stored in the base screen display area 22 in the frame memory 20 when the base screen output permission signal is active.
The address of the leading pixel on the scanning line designated by N is generated and output to the frame memory 20.

The hard line start line register M is a register in which the top scanning line of the hard window displayed on the upper screen of the liquid crystal display device 10 is set. The hard window Top address generation circuit 902 sets the address set in the logical screen start address register RLPS, the current line number CLN, and the hard line start line register M every time the hard window start address output enable signal becomes active. The head address of each line of the logical screen of the hard window is generated on the basis of the line information to be generated and output to the frame memory 20.

The hard window end horizontal dot register (β-1) is a register in which the horizontal dot position of the last pixel of the hard window displayed on the upper screen of the liquid crystal display device 10 is set.

Base screen restoration address generation circuit 903
Is the horizontal dot position information of the last pixel of the hard window set in the current line number CLN and the hard window end horizontal dot register (β-1) when the base screen restoration address output permission signal becomes active. In the base screen display area 22 of the frame memory 20 in which the pixels of the base screen displayed subsequently to the last pixel of the hard window are stored in each scan line in which the hard window is displayed on the upper screen, An address is generated and output to the frame memory 20. Although not shown in FIG. 4, the output of the storage address of the first pixel of each line of the base screen in the base screen display area 22 is output to the upper screen address generation color 90U.
A base screen start address output permission signal for instructing is also generated.

The lower screen address generation circuit 90L has the same structure as the upper screen address generation circuit 90L, and differs only in the values set in the logical screen start address register RLPS and the hard window start line register M.

Next, the operation of the embodiment having the above configuration will be described. 6 and 7 are views showing various display modes of the hard window and a storage method of display data (image data) of the hard window in the hard window buffer area 24 of the frame memory 20 corresponding to the display mode. is there.

FIG. 6 shows two hard windows 201.
FIG. 3 is a diagram showing an example in which U and 201L are separately displayed on an upper screen liquid crystal panel 10U and a lower screen liquid crystal display panel 10L of the liquid crystal display device 10, respectively. That is, in this case, two hard windows 201 are provided on the upper screen and the lower screen.
U and 201L are displayed separately. In this case, the following four parameters are necessary to display the hard window 201U displayed on the upper screen on the upper screen liquid crystal display panel 10U.

Upper hard window start line Upper hard window end line Upper hard window start horizontal dot address Upper hard window end horizontal dot address In order to display the hard window 201L displayed on the lower screen on the lower screen liquid crystal panel 10L The following four parameters are required.

Lower hard window start line Lower hard window end line Lower hard window start horizontal dot address Lower hard window end horizontal dot address Further, in order to realize the hard window display as shown in FIG. 6 (b). The following two pieces of address information of the frame memory 20 are required.

A. Storage start address of display data of logical screen of upper hard window stored in hard window buffer area 24 of frame memory b. Storage start address of display data of logical screen of lower hard window stored in the hard window buffer area 24. Next, in FIG. 7, one hard window is an upper screen liquid crystal panel 10U and a lower screen liquid crystal panel. It is a figure which shows the example displayed as a continuous 1 screen over 10L.

Also in this case, the above-mentioned a. b.
Parameters are required. However, in this case, the parameter values are the same as those described above. FIG. 8 is a diagram showing a specific configuration example of the frame memory 20 used in the following description. The frame memory 20 has a lateral width of 1024 dots as shown in FIG. A base screen display area 22 having a capacity of 640 dots × 480 lines is provided at the head thereof. Also,
In the hard window buffer area 24 of the frame memory 20, the Mth line to the 239th line (final line) on the upper screen in the vertical direction as shown in FIG.
On the lower screen, a logical screen of a rectangular hard window that is displayed from the 0th line (first line) to the Nth line, and is also displayed from the α dot to the (β-1) dot in the horizontal direction. Image data is stored (here, it is assumed that M <N, α <320, β> 320, and M is an even number). The image data is bit-mapped and stored in the hard window buffer area 24 from the address U of the frame memory 20 in the same image as the screen image shown in FIG. Therefore, as shown in FIG. 3A, the top address of the logical screen of the upper screen of the hard window is the address U on the frame memory 20, and the top address of the lower screen of the logical screen is the address {U +
(240-M) × 1024}. This is because the line difference between the top lines of the logical screens of the upper and lower screens of the hard window is (240-M), and the address difference for one line is 1024 bits, which is the same as the horizontal width of the frame memory. Is.

Next, the display control operation of this embodiment will be described using the model shown in FIG. FIG. 9 shows a case where the image data of the 0th line (0th line of the upper screen on the liquid crystal display device 10) of the first frame (first frame) displayed on the liquid crystal display device 10 is read from the frame memory 20. It shows the state. Further, FIG. 10 is a timing chart for explaining the operation shown in FIG.

FIG. 10A is a timing chart of the serial read clock applied from the liquid crystal display timing signal generation circuit 40 to the serial control terminal SC of the frame memory 20. Further, FIG. 7B is a timing chart of the address signal applied to the frame memory 20 from the upper screen address generation circuit 90U.

Further, FIGS. 9C and 9D are respectively diagrams from the upper screen comparator 80U to the upper screen address generation circuit 90U.
5 is a timing chart of a hard window start address output permission signal and a base screen restoration address output permission signal added to the. Further, FIG. 7E shows the first serially read out from the serial port of the frame memory 20 in synchronization with the serial read clock shown in FIG. 0
It is an output timing chart of image data of a line.
Further, FIG. 6F is a timing chart of a clock applied to the liquid crystal display device 10 from the liquid crystal display device timing signal generation circuit 40 and used by the liquid crystal display device 10 to input image data from the line buffer unit 30. is there. Further, FIG. 9G is a timing chart of data input to the upper screen liquid crystal display panel 10U of the liquid crystal display device 10 from the upper screen line buffer 34U or 35U of the line buffer unit 30. Then, FIG. 7H is a timing chart of image data input from the lower screen line buffer 34L or 35L of the line buffer unit 30 to the lower screen liquid crystal display panel 10L of the liquid crystal display device 10.

Prior to the frame memory serial read clock shown in FIG. 10A, the top address of the 0th line is input to the frame memory 20 from the upper screen address generation circuit 90U as shown in FIG. 10B. And the same figure
When the frame memory serial read clock shown in (a) is input to the frame memory 20, the base screen display area 22 of the frame memory 20 is displayed as shown in FIG.
To 0th line of image data are sequentially output from the serial port to the line buffer unit 30. The output image data is immediately stored in the first upper screen line buffer 34U of the line buffer unit 30. This time,
As shown in (g) and (h) of the same drawing, second line buffers (buffers for odd lines) 34L and 35L for the upper and lower screens, respectively.
The stored data is simultaneously output to the liquid crystal display device 10. The content of this stored data is not fixed yet, but it is not the image data to be displayed, but the image data of the next line is output immediately, so there is no practical problem (data that has not been determined is output. Is the number 1
0 to only a few hundred microseconds). Since the hard window is not displayed on this 0th line, the frame memory 2
The address is input to 0 only once in the first time.
After that, the read address is automatically incremented inside the frame memory 20 in synchronization with the frame memory read clock, and serially output from the frame memory 20 up to the last 639th dot image data of the 0th line. It

Subsequently, the address output to the frame memory 20 is switched from the upper screen address generation circuit 90U to the lower screen address generation circuit 90L, and as shown in FIG. 11, the frame memory 20 is switched to the display screen of the liquid crystal display device 10. The image data displayed on the 240th line (0th line of the lower screen) is output to the first lower screen line buffer 34L of the line buffer unit 30. FIG. 12 is a timing chart for explaining this image data output operation, and FIGS. 12A to 12H are the same as FIGS. 9A to 9H.

Since this line is included in the area for displaying the hard window, the image data of the base screen is output up to the (α-1) th dot, but from the αth dot to the (β-1) th dot. Must output the image data of the logical screen displayed as a hard window (see FIGS. 12 (a) and 12 (e)). Therefore, the lower screen address generation circuit 90L synchronizes with the hard window start address permission signal output from the lower screen comparator 80L as shown in FIG. After outputting the storage address of the image data of the (α-1) th dot of the line, the storage address of the image data of the first pixel of the logical screen of the hard window displayed on the 240th line, that is, {U + (240
-M) × 1024} address value is set to the frame memory 20.
(See FIG. 12 (b) and (c)). After that, the frame memory 20 increments the above address value in synchronization with the frame memory serial read clock shown in FIG. 12 (a) and, as shown in FIG. 12 (e), from the α-th dot of the 240th line ( β-1) Output the image data of the logical screen of the hard window up to the dot to the first lower screen line buffer 34L of the line buffer unit 30.

As described above, the frame memory 24th
After the image data of the logical screen of the hard window displayed up to the (β-1) th dot of the 0th line is output, the base screen restoration address output enable signal is output from the lower screen comparator 80D as shown in FIG. 12 (d). Is output. When this signal is applied, the lower screen address generation circuit 90D causes the β of the 240th line of the base screen as shown in FIG. 12 (b).
The storage address of the image data of the dot is output to the frame memory 20. As a result, as shown in FIG. 12 (e), the frame memory 20 is stored in the base screen display area 22 from its serial port in synchronization with the frame memory read clock as shown in FIG. 12 (b). The image data of the base screen from the β dot to the 1023 dot of 240 lines is output to the first lower screen line buffer 34U.

By the above operation, as shown in FIG. 10, the line buffer section 30 stores all the image data to be displayed on the 0th line of the upper and lower liquid crystal display panels 10U and 10D of the liquid crystal display device 10. . In this state, these image data are not yet output to the liquid crystal display device 10. Therefore, as shown in FIGS. 12 (g) and 12 (h),
Random data that has not been determined yet is output to the liquid crystal display panels 10U and 10L.

Then, when all the image data to be displayed on the first line of the upper and lower screens of the liquid crystal display device 10 is stored in the line buffer section 30 in this way, FIG.
The two liquid crystal display panels 10U and 10L of the liquid crystal display device 10 are synchronized with the liquid crystal display device data input clock applied from the liquid crystal display unit timing signal generation circuit 40 shown in (f).
Respectively input image data serially from the first upper screen line buffer 34U and the first lower screen line buffer 34L of the line buffer unit 30, and the image data are input to the 0th line of each display screen. Is displayed.

In this way, the upper and lower liquid crystal display panels 10U and 10U are connected from the frame memory 20 to the line buffer section 30.
When the image data to be displayed on the same line L is prepared, the image data is simultaneously output from the line buffer unit 30 to the upper and lower liquid crystal display panels 10U and 10L.
For this reason, in the frame memory 20 which does not have one serial port, the line buffer unit 30 has the liquid crystal display device 10.
The image data is output to the line buffer unit 30 at twice the speed at which the image data is output. That is, FIG.
As shown in (a) and (f), the serial read clock of the frame memory 20 has a frequency twice that of the data input clock of the liquid crystal display device 10.

13 and 14 are diagrams for explaining the operation of reading the image data of the first line (the first line of the upper screen) of the liquid crystal display device 10 from the frame memory 20 into the line buffer section 30. Also, FIG. 15 and FIG.
FIG. 6 is a diagram illustrating an operation in which the image data of the 241st line (the 1st line of the lower screen) of the liquid crystal display device 10 is read into the line buffer section 30 from the frame memory 20.

The reading operation of the image data of the first line and the 241st line is basically the same as that of the image data of the 0th line and the 240th line described above, but the first line and the above The image data of the 241st line is the second upper screen line buffer 3 respectively.
5U and the second lower screen line buffer 35D. In addition, in parallel with the reading of the image data, the first upper screen line buffer 34 of the line buffer unit 30 is read.
U and the first lower screen line buffer 34D serially output image data of the 0th line and the 240th line to the upper screen liquid crystal display panel 10U and the lower screen display panel 10D of the liquid crystal display device 10, respectively ( Figure 14 (g),
(h) and FIG. 16 (g), (h)).

Subsequently, as shown in FIG. 17, the image data of the second line is read from the frame memory 20, and the image data is stored in the first upper screen line buffer 34U, and at the same time, the second line Upper screen line buffer 35
From the L and second lower screen line buffers 35D, the image data of the first half of the 1st line and the 241st line are respectively displayed on the upper screen display panel 10L and the lower screen display panel 10D.
Are typed into and displayed on those screens. FIG. 18 is a timing chart for explaining the operation of each block at this time.

Next, as shown in FIG. 19, the image data of the 242nd line is read from the frame memory 20, and the image data is read by the first lower screen line buffer 34.
At the same time as being stored in L, from the second upper screen line buffer 35U and the second lower screen line buffer 35L,
The image data of the latter half of the first line and the 241st line are input to the upper screen display panel 10U and the lower screen display panel 10L, respectively, and are displayed on those screens. FIG. 20 is a timing chart for explaining the operation of each block at this time.

Thereafter, similarly, the line buffer unit 30
In the inside, the line buffers for storing the image data are alternately switched, and the image data after the third line and after the 243rd line (the third line of the lower screen) are input to the line buffer unit 30 from the frame memory 20. It At the same time as the input of the image data, the image data of the second and subsequent lines and the 242nd line (the second line of the lower screen) and subsequent lines from the line buffer unit 30 are respectively displayed on the upper display panel 10U and the lower display panel. Input to 10L and displayed on those screens.

In this way, from the 0th line to the (M-
1) In the image display up to the line, the reading of the image data from the frame memory 20 to the upper screen line buffers 34U and 35U of the line buffer unit 30 is considered from the base screen display area 22.

However, from the M-th line, the display of the hard window logic screen is also started on the upper screen liquid crystal display panel 10U (see FIG. 8). Therefore, next, referring to FIGS. 21 to 24, the image data of the Mth line is read from the frame memory 20 into the line buffer unit 30, and the image data is further read from the line buffer unit 30 for the upper screen liquid crystal. The operation until it is transferred and displayed on the display panel 10U will be described.

The basic operation in this case is similar to that in the case where the image from the 0th line to the Nth line is displayed on the lower screen liquid crystal display panel 10L described above. That is,
As shown in FIGS. 21 and 22, first, from the base screen display area 22 to the 0th dot of the Mth line (α−
1) The image data up to the dot is read and stored in the first upper screen line buffer 34U (FIG. 2).
2 (e)). Then, as shown in FIG. 22 (c), the upper window comparator 80U outputs a hard window start address output permission signal to the upper window address generation circuit 90U, and the upper window address generation circuit 90U receives the input of the signal. Then, the storage address U of the image data of the αth dot of the Mth line of the hard window buffer memory 24 is output to the frame memory 20 (see FIGS. 22B and 22C). As a result, the frame memory 20 is displayed in FIG.
The address U is sequentially incremented internally in synchronization with the frame memory serial read clock shown in
The image data of the logical screen of the hard window from the αth dot to the (β-1) th dot of the Mth line stored in the hard window buffer memory 24 from the serial port is transferred to the first upper part of the line buffer section 30. It is output to the screen line buffer 34U (see FIG. 22 (e)).
Subsequently, the base screen restoration address output permission signal is sent from the upper screen comparator 80U to the upper screen address generation circuit 90U.
(FIG. 22 (d)), the upper screen address generation circuit 90U outputs the β dot image data of the Mth line of the base screen in the base screen display area 22 to the frame memory 20. The storage address is output (see FIG. 22 (b)). As a result, the frame memory 20
The storage address is sequentially incremented in synchronization with the frame memory serial read clock, and the base screen image data from the βth dot to the 639th dot of the Mth line from the serial port is transferred to the first upper screen line buffer. It is output to 34U (see FIG. 21 (e)). By the above operation, the image data to be displayed on the Mth line of the upper screen display panel 10U is stored in the first upper screen line buffer 34U of the line buffer unit 30.

As described above, while the image data of the Mth line is being stored in the first upper screen line buffer 34U, as shown in FIG. The first half of the (M-1) -th line image data and the {240+ (M-1)}-line image data from the second line screen buffer 35L and the second lower screen line buffer 35L are the upper screen liquid crystal display panel, respectively. 10U
Is output to the lower screen liquid crystal display panel 10L and displayed on the screen.

23 and 24 are diagrams for explaining the operation of reading the (240 + M) th line image data from the frame memory 20 to the second lower screen line buffer unit 35L of the line buffer unit 30. As shown in FIG. This (240+
Since the image data of the (M) line is the image data of the base screen, as shown in FIGS. 24 (c) and 24 (d), the lower window comparator 80D outputs the hard window start address enable signal and the base screen restore address output enable signal. Is not output. Therefore, when the storage address of the image data of the first pixel of the (240 + M) th line in the base screen display area 22 is input to the frame memory 20 from the lower screen address generation circuit 90D (see FIG. 24 (b)), the storage address is stored. The address is sequentially incremented in synchronization with the frame memory serial read clock shown in FIG. 24 (a), and from the serial port to the first lower screen line buffer 34L of the line buffer unit 30, the (240 + M) th line base screen image is displayed. The image data is output (see FIG. 24 (e)).
As a result, in the first lower screen line buffer 34L, the second (2nd) to be displayed on the lower screen display panel 10L is displayed.
The image data of the 40 + M) line base screen is stored. At the same time, from the second upper screen line buffer 35U and the second lower screen line buffer 35L, the image data of the (M-1) th line and the {2th line, respectively.
The latter half of the image data of the 40+ (M-1) line is the upper screen liquid crystal display panel 10U and the lower screen display panel 10.
It is output to L and displayed on those screens (see FIGS. 23 and 24 (g) and (h)).

Subsequently, the frame memory 20 sequentially outputs the image data of the (M + 1) th line and the image data of the {240+ (M + 1)} line to the line buffer unit 30, and the line buffer unit 30 outputs the image data. To the liquid crystal display device 10, the image data of the Mth line and the (240th)
The image data of the + M) line is output. These operations are shown in FIGS. 25 to 28. The operation in this case is different only in the addresses output from the upper screen address generation circuit 901U and the lower screen address generation circuit 90L to the frame memory 20, and other than that is shown in FIGS. 21 to 24 described above. The operation is almost the same.

Similarly, thereafter, in the upper screen, the reading of the image data from the (M + 2) th line to the 238th line and the screen display from the (M + 1) th line to the 237th line are performed, and in the lower screen, the {240+
From the (M + 2)} line, the {240+ (M + 238)}
Reading of image data up to the line and the {240+ (M
The screen display from the (+1)} line to the (240 + 237) th line is performed.

Subsequently, as shown in FIG. 29, the image data of the 239th line is input from the frame memory 20 to the second upper screen line buffer 35U of the line buffer unit 30. At the same time, the image data of the first half of the 238th line from the first upper screen line buffer 34U is transferred to the upper screen liquid crystal display panel 10 of the liquid crystal display device 10.
U to the 47th screen from the first lower screen line buffer 34L
The image data of the first half of 7 lines is input to the lower screen liquid crystal display panel 10L. FIG. 30 is an operation timing chart of each block at this time. As shown in the figure, the operation at this time is the same as that described with reference to FIG.

Next, as shown in FIG. 31, the image data of the 479th line is input from the frame memory 20 to the second lower screen line buffer 35L of the line buffer unit 30. At the same time, the image data of the second half of the 238th line from the first upper screen line buffer 34U is transferred to the upper screen liquid crystal display panel 10U of the liquid crystal display device 10.
From the first lower screen line buffer 34L to the 478th line
The image data of the latter half of the line is input to the lower screen liquid crystal display panel 10L. FIG. 32 is an operation timing chart of each block at this time. As shown in the figure,
The operation at this time is the same as that described with reference to FIG.

As described above, the image data of the 239th line of the upper screen and the lower screen is read from the frame memory 20, and the image data is stored in the line buffer unit 30. At the same time, on the liquid crystal display device 10, images on the 237th line and the 478th line are displayed on the upper screen and the lower screen, respectively.

As described above, all the image data of the first frame including the logical screen displayed as the hard window of the liquid crystal display device 10 is read from the frame memory 20 to the line buffer section 30. At this point, the image data of the second frame has already been written in the base screen display area 22 and the hard window buffer area 24 of the frame memory 20. Then, again in the same manner as above, the reading of the image data from the frame memory 20 to the line buffer unit 30 is also started from the 0th line for the second frame.

33 and 34 are diagrams for explaining the operation at this time. That is, the operation in this case is almost the same as that shown in FIG. 9 and FIG. 10 described above, but the second upper screen line buffer 35 of the line buffer unit 30 is operated.
The U and second lower screen line buffers 35L store the image data of the 240th line and the 479th line of the frame, respectively, instead of the unconfirmed data. Then, as shown in FIGS. 34 (e), (g), and (h), the image data of the 0th line of the second frame is stored at the same time from the frame memory 20 into the first lower screen line buffer 34U. The image data of the first half of the 240th line and the 479th line is read from the second upper screen line buffer 35U and the second lower screen line buffer 35L, respectively, and these image data of the liquid crystal display device 10 are read. It is displayed on the upper screen display panel 10U and the lower screen display panel 10L.

Next, as shown in FIG. 35, the image data of the 240th line of the second frame is read from the frame memory 20 and stored in the first lower screen line buffer 35U of the line buffer section 30. At the same time, from the second upper screen line buffer 34L and the second lower screen line buffer 35L, the second frame 239
The image data of the latter half of the line and the image data of the latter half of the 479th line are input to the upper screen display panel 10L and the lower screen display panel 10D, and the entire image of the first frame is displayed on the liquid crystal display device 10. To be done. At this time,
FIG. 3 is a timing chart explaining the operation of each block.
It is 6.

In the above embodiment, the two liquid crystal display panels 10U and 10L form one screen, but the present invention is not limited to this, and a larger number of liquid crystal display panels can form one screen. It is also applicable to the configured liquid crystal display device. In this case, for example, the first and second line buffers may be provided corresponding to each liquid crystal display panel. Further, in this embodiment, two line buffers are provided for each of the liquid crystal display panels 10U and 10L, but it is also possible to substitute one line buffer for the two line buffers. In this case, for example, the capacity of the line buffer may be set larger than that of one scanning line, and the input and output of image data may be performed asynchronously in the line buffer. Further, the present invention is not necessarily limited to the liquid crystal display device, and can be applied to all display devices in which one screen is composed of a plurality of display panels of other forms. Further, the number of hard windows displayed on one screen is not limited to one, and it is applicable to a display device in which a plurality of hard windows are simultaneously displayed on the base screen. .

[0097]

According to the present invention, the image data read from the frame memory can be input to any display panel among the plurality of display panels via the line buffer. Thus, it becomes possible to display a hard window at any position on the screen in a display device having one screen. Further, since the display of the hard window can be performed by hardware control, it is possible to speed up the application software for displaying the hard window. Also,
This also makes it possible to speed up a computer system that uses a display device that displays a hard window.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a liquid crystal display control device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a line buffer unit.

[Figure 3] Upper screen and lower screen hard window register
It is a figure which shows the structure of a set.

FIG. 4 is a block diagram showing a configuration example of an upper screen comparator and a lower screen comparator.

FIG. 5 is a block diagram showing a configuration example of an upper screen and lower screen address generation circuit.

FIG. 6 is a diagram showing an example in which two hard windows are separately displayed on an upper screen liquid crystal panel and a lower screen liquid crystal display panel of a liquid crystal display device.

FIG. 7 is a diagram showing an example in which one hard window is displayed as one continuous screen across an upper screen liquid crystal panel and a lower screen liquid crystal panel.

FIG. 8 is a diagram showing a specific configuration example of a frame memory 20 used in this embodiment.

FIG. 9 is a diagram showing a state when the image data of the 0th line of the first frame displayed on the liquid crystal display device is read from the frame memory 20.

FIG. 10 is a timing chart explaining the operation shown in FIG.

FIG. 11 is a diagram illustrating a state in which image data displayed on the 240th line of the display screen of the liquid crystal display device is output from the frame memory to the first lower screen line buffer of the line buffer unit.

12 is a timing chart explaining the operation shown in FIG.

FIG. 13 is a diagram illustrating an operation of reading image data of a first line of a liquid crystal display device from a frame memory into a line buffer unit.

14 is a timing chart illustrating the operation shown in FIG.

FIG. 15 is a view showing a liquid crystal display device having a frame memory 241.
It is a figure explaining operation which image data of a line is read by a line buffer part.

16 is a timing chart explaining the operation shown in FIG.

FIG. 17 is a diagram illustrating an operation of reading image data of a second line from a frame memory and storing the image data in a first upper screen line buffer.

18 is a timing chart illustrating the operation shown in FIG.

FIG. 19 is a diagram showing an operation of reading the image data of the 242nd line from the frame memory and storing the image data in the first lower screen line buffer.

20 is a timing chart illustrating the operation shown in FIG.

FIG. 21 is a diagram showing an operation in which image data of the Mth line is read from the frame memory and is stored in the first upper screen line buffer.

22 is a timing chart illustrating the operation shown in FIG.

FIG. 23 is a diagram showing a second part of the line buffer unit from the frame memory.
FIG. 7 is a diagram illustrating an operation of reading image data of the (240 + M) th line into the lower screen line buffer unit.

FIG. 24 is a timing chart explaining the operation shown in FIG. 23.

FIG. 25 is a view showing the second part of the line buffer unit from the frame memory.
FIG. 7 is a diagram showing an operation of reading the (M + 1) -th line image data into the upper screen line buffer.

FIG. 26 is a timing chart explaining the operation shown in FIG. 25.

FIG. 27 is a second section of the line buffer section from the frame memory.
{240+ (M + 1)} in the lower screen line buffer
It is a figure which shows the operation | movement in which the image data of a line is read.

FIG. 28 is a timing chart explaining the operation shown in FIG. 27.

FIG. 29 is a diagram showing an operation in which image data of a 239th line is read from a frame memory into a second upper screen line buffer of the line buffer unit.

FIG. 30 is a timing chart explaining the operation shown in FIG. 29.

FIG. 31 is a diagram showing an operation of inputting image data of line 479 from the frame memory to the second lower screen line buffer of the line buffer unit.

FIG. 32 is a timing chart explaining the operation shown in FIG. 31.

FIG. 33 is a diagram showing an operation of reading the 0th line image data of the 2nd frame from the frame memory into the first upper screen line buffer of the line buffer section;

FIG. 34 is a timing chart explaining the operation shown in FIG. 33.

FIG. 35 is a diagram showing the 240th frame of the second frame from the frame memory.
It is a figure which shows the operation | movement which the image data of a line are read and stored in the 1st lower screen line buffer of a line buffer part.

FIG. 36 is a timing chart explaining the operation shown in FIG. 35.

FIG. 37 is a diagram for explaining a general screen display method on a CRT display.

38 is a configuration diagram of a frame memory used for screen display in the CRT display shown in FIG. 37.

FIG. 39 is a diagram illustrating the concept of a hard window.

FIG. 40 is a diagram illustrating a method of storing image data of the hard window in the frame memory shown in FIG. 38.

FIG. 41 is a diagram showing a state in which a hard window is displayed on a part of the base screen on the display screen.

42 is a diagram illustrating the hard window display shown in FIG.
It is a figure explaining the reading order of the image data from a frame memory.

FIG. 43 is a diagram showing a configuration of a liquid crystal display device currently generally used as a display of an information processing device and a configuration of a frame memory corresponding thereto.

[Fig. 44] Fig. 44 is a diagram illustrating an internal configuration of frame memories for the upper screen and the lower screen and a method of converting a physical memory space of the two frame memories into a logical memory space accessed by a CPU.

FIG. 45 is a diagram showing an example of a case where a hard window is displayed on the panel of the upper screen.

FIG. 46 is a diagram showing an example in which a conventional liquid crystal display device cannot display a hard window.

[Explanation of symbols]

 10 liquid crystal display device 10U upper screen liquid crystal display panel 10L lower screen liquid crystal display panel 20 film memory 22 base screen display area 24 hard window buffer area 30 line buffer section 32 first demultiplexer 33 second demultiplexer 34U first Upper screen line buffer 34L First lower screen line buffer 35U Second upper screen line buffer 35L Second lower screen line buffer 40 Liquid crystal display device timing signal generation circuit 50 Line counter 60 Horizontal dot counter 70U Upper Screen hard window register set 70L Lower screen hand window register set 80U Upper screen comparator 80L Lower screen comparator 90U Upper screen address generation circuit 90L Lower screen address generation circuit

Claims (3)

[Claims] 1. A display control device for displaying a hard window on a screen of a display device having one screen composed of a plurality of display panels, and a frame memory for storing image data of the base screen and image data of the hard window, A plurality of line buffers provided corresponding to each display panel for storing the image data of the base screen or the hard window read from a frame memory, and the frame in accordance with the scanning order on the screen of the display device. The image data of the base screen or the hard window is read from the memory, the image data is input to the line buffer, and the image data stored in the plurality of line buffers is input to the display panel according to the scanning order. And a control means for Display control apparatus according to symptoms. 2. The two line buffers are provided for each display panel, and the control means uses the two line buffers for reading image data from the frame memory and for displaying an image on the liquid crystal display panel. The display control device according to claim 1, wherein the display control device is used by switching for data output. 3. The display control device according to claim 1, wherein the display panel is a liquid crystal display panel.