KR100472478B1 - Method and apparatus for controlling memory access - Google Patents

Abstract

A method and apparatus for controlling memory access are disclosed. In order to control the access of the frame memory in the liquid crystal display device, the memory access control device divides a system clock at a predetermined division ratio to generate an LCD clock, and generates a control signal for accessing the frame memory. Below, each half period before the LCD clock consists of an input buffer for writing data into the frame memory, and under the control of the control section, every half cycle of the LCD clock consists of an output buffer for reading data from the memory. According to this, the clock signal used for accessing one LCD frame memory is controlled to perform a write operation in the first half cycle and a read operation in the latter half cycle, thereby reducing the load of the microprocessor given to the LCD when displaying still images. You can minimize the delay time when you want to switch the LCD screen contents.

Description

Method and apparatus for controlling memory access

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access control method and apparatus, and more particularly to a memory for controlling a write operation in a preceding half cycle and a read operation in a later half cycle in a clock signal used for accessing a frame memory storing image data of one frame. The present invention relates to an access control method and apparatus.

In general, the operation of the frame memory used in a liquid crystal display (hereinafter referred to as LCD) device shows that when the power is turned on, the central processing unit (MCU) and peripheral devices are initialized, and then one frame is stored in the LCD frame memory. The initial image data of is written and the initial image data configured in the LCD frame memory is displayed on the LCD. Then, if screen switching is necessary, the previous image data of the LCD frame memory is deleted, new image data is written to the LCD frame memory, and the image data of the newly configured LCD frame memory is displayed on the LCD to be performed until the power is turned off. It worked.

However, in case of LCD device that supports one frame memory, the contents of one frame memory must be erased every time the screen is reconfigured, and the image data of one frame must be written again. Had a problem.

In order to solve this problem, two frame memories may be provided to store image data currently displayed in one frame memory and image data to be displayed next in another frame memory. There is a problem that the increase in manufacturing cost due to the additional, and even if you want to change a part of the image data of one frame to rewrite the image data of the entire frame.

An object of the present invention is to provide a memory access control method for controlling a write operation in a previous half cycle and a read operation in a later half cycle of a clock signal used in a frame memory access that stores image data of one frame. It is.

Another object of the present invention is to provide an apparatus most suitable for realizing the memory access control method.

In order to achieve the above technical problem, the memory access control method according to the present invention includes a frame clock for storing image data processed by a microprocessor and a system clock divided by a predetermined division ratio, and a control signal for accessing the frame memory. A liquid crystal display device having a control unit for generating a data, comprising: (a) in response to the LCD clock and a control signal, data is transferred to the frame memory every half cycle before the LCD clock in accordance with the LCD clock and a control signal; Controlling to write; And (b) controlling to read data from the frame memory every half cycle after the LCD clock in accordance with the LCD clock and control signal.

In order to achieve the above technical problem, the memory access control apparatus according to the present invention divides a system clock into a predetermined division ratio in order to control the access of a frame memory for storing image data processed by a microprocessor in a liquid crystal display device. A controller for generating an LCD clock and generating a control signal for accessing the frame memory; An input buffer for writing image data into the frame memory every half cycle of the LCD clock in accordance with an LCD clock and a control signal provided from the controller; And an output buffer for reading image data from the memory in every half period after the LCD clock in accordance with the LCD clock and the control signal provided from the controller.

Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a configuration of a memory access control apparatus according to an embodiment of the present invention, which includes a control unit 11, an input buffer 13, a memory 16, and an output buffer 17.

The control unit 11 is for controlling the operation of the input buffer 13, the memory 16 and the output buffer 17. The control unit 11 receives a system clock, which is the main clock of the system to which the memory 16 is applied, as a predetermined input. An LCD clock divided by the division ratio is generated, and a control signal 12 including an LCD clock, a write control signal, a read control signal, a chip select signal, and the like is supplied to the input buffer 13 and the output buffer 17. On the other hand, when the write control signal, the read control signal, the chip select signal, etc. are generated from the input buffer 13 and the output buffer 17 as another embodiment, these signals can be received and applied to the memory 16. have.

The input buffer 13 stores image data processed by a microprocessor (not shown) under the control of the controller 11, and then writes the write address, the write control signal, the chip select signal, and the like every half period before the LCD clock. The control signal 14 and the write data 15 which are included are applied to the memory 16. That is, the writing operation of the memory 16 is performed continuously at half period difference of the LCD clock.

The memory 16 is composed of a static RAM (SRAM) or the like, and is used to store one frame of image data. A write operation is performed in the half cycle before the LCD clock and a read operation is performed in the latter half cycle.

The output buffer 17 applies a control signal 18 including a read address, a read control signal, and a chip select signal to the memory 16 every half cycle after the LCD clock under the control of the controller 11. The data 19 stored in the read address is read out and stored. That is, the read operation of the memory 16 is continuously performed at half-cycle difference of the LCD clock.

2 is a waveform diagram of each signal in FIG. 1, (a) is a system clock, (b) is an LCD clock, and (c) to (f) are signals used for a writing operation of the memory 16. (c) represents the write address, (d) represents the chip select signal, (e) represents the write control signal, (f) represents the write data, and (g) to (j) represent the read operation of the memory 16. As signals used, (g) indicates a read address, (h) indicates a chip select signal, (i) indicates a read control signal, and (j) indicates read data. On the other hand, the LCD clock b is a signal obtained by dividing the system clock a at a predetermined division ratio.

Next, the operation of the present invention having the above-described configuration will be described with reference to FIG. 2.

First, in an exemplary embodiment of the present invention, the LCD clock b divided by the system clock a is divided into two, and in the previous half period T1 of the LCD clock b, the memory 16 is written for the write operation. Various control signals (c, d, e) and data (f) are applied to the memory (16), and in each subsequent half period (T2) various control signals (g, h, i) for the read operation of the memory (16). ) Is applied to read the data f.

The input buffer 13 is used to transfer image data supplied from a microprocessor (not shown) to the memory 16. The input buffer 13 is implemented by at least one FIFO, preferably two FIFOs, and is controlled by the controller 11. The data f can be successively written to the corresponding write address c of the memory 16 in the T1 section of the LCD clock b. That is, while data is written from one FIFO to the memory 16, the microprocessor requests image data and fills the other FIFO alternately with each other. Data writing to the memory 16 is possible.

The output buffer 17 is for transferring image data read out from the LCD frame memory 16 to a later stage, for example, an LCD controller (not shown), and may be made of a register or the like. The output buffer 17 latches the data j of the read address g corresponding to the read address g from the memory 16 in the T2 section of the LCD clock b under the control of the controller 11 and transfers it to the rear end.

On the other hand, when a part of the image data displayed on the LCD is changed, the input buffer 13 receives the data of the changed part from the microprocessor, and writes in the area corresponding to the write address designated by the control unit 11 in the memory 16. Done. In this case, the write operation is performed in the T1 section of the LCD clock b. On the other hand, in the output buffer 17, data corresponding to the read address is sequentially transmitted to the rear end through the output buffer 17 in the T2 section of the LCD clock b irrespective of the writing operation performed on the changed portion. .

As described above, according to the present invention, one LCD frame memory is provided, and a write operation of the memory is performed by controlling to perform a write operation in a previous half cycle and a read operation in a later half cycle in a clock signal used for accessing the LCD frame memory. Since the overread operation is continuously performed at half cycles of the LCD clock, the microprocessor load can be reduced when displaying still images on the LCD even when only one LCD frame memory is used. In addition, there is an effect of minimizing the delay time even if you want to switch the LCD screen content in whole or in part.

Although the present invention has been described with reference to the above embodiments, it is merely illustrative, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. . Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a block diagram showing the configuration of a memory access control apparatus according to an embodiment of the present invention; and

FIG. 2 is a waveform diagram of each signal in FIG. 1.

* Explanation of symbols for main parts of the drawings

11 ... control section 12, 14, 18 ... control signal 13 ... input buffer 15 ... write data

16 ... Memory 17 ... Output buffer 19 ... Readout data

Claims (4)

In the liquid crystal display device, in order to control the access of the frame memory that stores the image data processed by the microprocessor, A controller which divides a system clock at a predetermined division ratio to generate an LCD clock, and generates a control signal for accessing the frame memory; An input buffer for writing image data into the frame memory every half cycle of the LCD clock in accordance with an LCD clock and a control signal provided from the controller; And  And an output buffer for reading image data from the memory in every half period after the LCD clock, in accordance with the LCD clock and the control signal provided from the controller. 2. The apparatus of claim 1, wherein the LCD clock divides the system clock into two. The method of claim 1, wherein the input buffer comprises first and second FIFOs, and the operation of requesting image data from the first FIFO and filling the second FIFO while the image data is written to the frame memory is performed. A memory access control device which is alternately performed with each other. A frame memory for storing image data processed by a microprocessor, and an LCD clock which divides a system clock at a predetermined division ratio, and a control unit for generating a control signal for accessing the frame memory. To control access to (a) controlling to write data to the frame memory every half period before the LCD clock in accordance with the LCD clock and control signal; And and (b) controlling to read data from the frame memory every half cycle after the LCD clock in accordance with the LCD clock and control signal.