JPH06214549A - Apparatus and method for display in double buffer-type output display system - Google Patents

Abstract

PURPOSE: To provide the device and method which send data to a frame buffer at low cost and so that no frame break is made. CONSTITUTION: This output display system includes a 1st frame buffer 29, a 2nd frame buffer 28, a device which transfers data from the 2nd frame buffer 28 to an output display device 33, and a device which writes new data only to the 1st frame buffer, and further includes a device which controls transfer of data to the respective frame buffers and a device which reads data out of the 1st frame buffer 29 in the same operation and writes data to the 2nd frame buffer 28.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to computer output displays, and more particularly to a method and apparatus for eliminating frame drops from computer output displays by using a low cost double buffering scheme.

[0002]

BACKGROUND OF THE INVENTION A typical computer system produces data that is displayed on an output display device. This output display is usually a cathode ray tube and displays a large number of full-screen images, the screen of which is visible to the observer's eye if the program being displayed is capable of producing continuous motion. As you can see, they occur sequentially very rapidly. Data is written to the frame buffer to generate individual images (frames) that are displayed sequentially. The frame buffer stores information about each illuminable position (each pixel) of the display device to generate a full screen image. For example, the display could be capable of displaying the pixels contained in about one thousand horizontal rows, each having about one thousand pixels. This information in each frame is all written to the frame buffer before being scanned into the display.

When data describing one entire picture exists in the frame buffer, the frame is transferred to the display device. Typically, data is transferred from the frame buffer to the display device pixel by pixel, starting at the top left corner of the display device and proceeding left to right and top to bottom row by row toward the bottom right corner of the display device. In order for pictures to appear consecutively on the output display, successive frames in the frame buffer must be continuously scanned to the output display at a rate of 30 frames per second or more.

While each frame of data is being scanned into the display, new data that should appear in the next frame must be transferred to the frame buffer. Generally, only the modified data is replaced with the old data in the frame buffer at the location representing that pixel location on the screen. All unchanged data stays unchanged in the frame buffer. New data to be displayed in one frame may be written in any part of the frame buffer at any time. A two-port video random access memory (VRAM) is used as the frame buffer to write information to the frame buffer and simultaneously scan from the frame buffer to the output display device. Data is written through one port and scanned into the display through the other port. Since a VRAM requires a significantly large number of transistors because it has two ports, a normal dynamic access RAM (DRA) is required.
M) more expensive.

If the data is being introduced into the VRAM frame buffer at the same time that the information is being scanned into the display, the information being scanned into the display is offset in time but two consecutive. It can also come from a frame. For example, if the scan is progressing faster than the data is being written to the frame buffer and a portion of the frame buffer that is being modified (writing) is being scanned into the display device, the portion of the display will be Derived from what should be the first frame, partly in the second part that follows
Derived from what should be the frame of. Displaying each part of two temporally shifted frames at the same time is called a frame break. In a situation where information changes rapidly, such as real-time video, the image can be significantly distorted, and this frame loss can be confusing.

A double buffering scheme is used to eliminate frame loss. The double buffering scheme uses two complete frame buffers, each capable of storing one complete frame. Data is written to one frame buffer and scanned from the other to the display. This scheme, when in its simplest form, uses a pair of VRAM frame buffers and is implemented by multiplexing the data in one of the frame buffers into a display device. In this form, the data is never written to the frame buffer during the time it is being scanned into the display. Once one frame has been completely written, that frame may be scanned into the display,
All subsequent data may be written to another frame buffer. No frame loss can occur because data is never written to a frame buffer while the contents are being scanned into the display. This simple form of double buffering is somewhat expensive because it uses two complete VRAM frame buffers and includes a control signal generator circuit and a multiplexer to perform the switching of the two frame buffers.

One of the main goals of computer designers is to
To run several individual programs on one computer and display them simultaneously on the output display of that computer. Normally, when displaying several individual programs on the output display of a computer, the individual programs will appear in one window. A window is usually a rectangular area of the screen, which can be moved, scaled, and otherwise manipulated. If several programs can be run at the same time and displayed in several windows at the same time, the work performed using that computer will be sped up. Normally, the information written in the windows here by different individual programs is written at different speeds. For example, information directed to a window displaying real-time video changes very quickly, while information typed from the keyboard into a word processor and displayed in another window changes much slower. Therefore, the rate at which the frame changes varies from program to program.

The simplest form of double buffering scheme described above is
Very useful when one program is running on the output display. However, if several programs are simultaneously running in different windows of the same output display, this form of double buffering is inadequate. This is because in a simple form of double buffering, the entire contents of each frame buffer must be scanned into the display. When writing data to several windows at an asynchronous rate, the timing at which the writing occurs varies from window to window. Therefore, it is difficult to adjust the timing of writing so that writing does not occur in the frame buffer that is scanning the display device. To solve this problem, an advanced form of double buffering was used that added another buffer called the window identification (ID) plane.
The window identification plane provides one storage location for each pixel displayed on the output display. At those positions of the window ID plane, the identification of the window to which the data of each pixel is related is stored. This plane can be used to select which buffer the pixel comes from for display at any given time. Therefore, the window ID plane may be used to scan the display data from a window that has no data written at the time of scanning. That is, when a plurality of active windows appear on the output display device at the same time, the double buffering method of this form can prevent frame loss.

This second form of double buffering would only use two complete forms of VRAM frame buffers and circuitry for multiplexing and controlling the two frame buffers to the display. Instead, an ID plane including a storage position for each pixel of the display device and a circuit for selecting a pixel based on a window in which a pixel to be displayed appears are added, which results in extremely high cost.

According to experiments, in the first double buffer system and the second double buffer system, multiplexing is performed between two VRAM buffers and two VRAM buffers or between individual pixels. We have found a configuration that is considered to reduce the cost required for the control circuit to operate. One form of the double buffer method used in the prior art for cost reduction uses a single-port DRAM frame buffer instead of one VRAM frame buffer, and scans from either frame buffer to a display device. A control circuit for is unnecessary. Instead, scan all frames from a single VRAM framebuffer to the display,
All new data is written to the DRAM frame buffer. When the writing is completed, the data in the DRAM frame buffer is transferred from the DRAM frame buffer to the VRAM frame buffer by the central processing unit. This requires the processor to read the data from the DRAM and then write the data to the VRAM frame buffer. This operation is typically performed by blocks of data large (eg, 32 bits) that the processor can transfer over its bus. The transfer is repeated many times until completed.

The double buffering system of this embodiment has one VRAM
Since a cheaper DRAM buffer is used instead of the frame buffer and a control circuit for multiplexing is omitted, the cost is much lower than that of the other forms. This configuration works properly with software compliant with the X11 standard (X window) that does not expect to see more than one frame buffer and stores the information to be transferred to the frame buffers as part of main memory. It is also useful. To this software, the DRAM frame buffer appears to be part of main memory. Also,
This configuration also has the advantage that the central processing unit can selectively control the area to be transferred, so that individual windows can be transferred from the invisible DRAM frame buffer to the VRAM frame buffer.

However, the transfer of information from the DRAM frame buffer to the VRAM frame buffer is relatively slow compared to the normal scanning speed to the display device. Therefore,
Writing to the VRAM frame buffer can occur at the location where information is being scanned into the display. Therefore,
Out of frame issues occur. If the writing should proceed at a faster rate than the scan to the display, then it is still cheaper to eliminate this problem by performing the write below the row being scanned and to implement a double buffering scheme. It would be possible to use different circuits.

[0013]

SUMMARY OF THE INVENTION Accordingly, one object of the present invention is to reduce the cost of the prior art double dampening arrangement while retaining the ability to prevent out-of-frame. Another, more specific object of the invention is to increase the rate of transfer between frame buffers in a system that scans information from only one of the two frame buffers to an output display.

[0014]

The above and other objects of the present invention are directed to a first frame buffer; a second frame buffer; a means for transferring data from the second frame buffer to an output display device. And; means for writing data only to the first frame buffer, and means for controlling the transfer of data to each frame buffer; reading data from the first frame buffer during the same operation, and And a unit for writing the read data into the second frame buffer. The above and other objects and features of the present invention will be better understood by referring to the following detailed description in conjunction with the drawings. In the drawings, like reference numerals refer to like elements throughout the several views.

(Notation and Terminology) In the following detailed description, there are portions where operations on data bits inside a computer memory are presented in symbolic form. Such explanations and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An action is an action that requires a physical manipulation of a physical quantity. Usually, those quantities are remembered,
It takes the form of an electrical or magnetic signal that can be transferred, combined, compared, and otherwise manipulated, but is not necessarily so. In some cases, these signals are referred to as bits, values, elements, symbols, characters, mainly because they are commonly used terms.
It has been found convenient to call terms, numbers, and so on. It should be remembered, however, that all such terms and related terms should be associated with the appropriate physical quantity and are merely labels labeled with such quantity.

Further, the manipulations performed are often referred to in terms such as addition or comparison, which are commonly associated with intelligent movements performed by an operator, but which form a part of the invention described herein. The ability of such an operator in any of the operations is unnecessary and is often undesirable. The motion is the motion of the machine. In all cases, it should be borne in mind the distinction between the method behavior when operating a computer and the method of computation itself. The present invention relates to an apparatus and method for operating a computer in processing electrical signals or other physical (eg mechanical, chemical) signals to generate other desired physical signals.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. 1, there is shown a circuit 10 constructed in accordance with the prior art. Circuit 10 shows only the basic portion of the circuit required to supply data to the terminals of the output display used in a typical computer system. The other parts necessary to carry out the operations of the computer are well known to the person skilled in the art and are not shown in the figures. Shown is a central processing unit 12 that can control the operation of the entire computer system, which in FIG. 1 represents the circuitry that provides the data to be displayed on the output display 14. In order to carry out the transfer of data from the central processing unit 12 to the output display unit 14, the first
Frame buffer 16 and second frame buffer 1
Use 7.

In the simplest form of double buffering described above, data is written from the central processing unit 12 to one frame buffer and scanned from the other frame buffer to the output display unit 14. In its simplest form, a pair of VRAM frame buffers are used to do this, and one frame of data in one frame buffer 16 or 17 is multiplexed by a multiplexer 19 to a display device. The data transferred by the multiplexer 19 is converted from the digital form to the analog form by the digital / analog converter 20 and is scanned by the display device. In this form of double buffering, no data is ever written to the frame buffer 16 or 17 while it is being scanned into the display. 1 in frame buffer 16 or 17
Once one frame has been completely written, the data in that frame buffer may then be scanned into the display and the other frame buffer may be written with new data. No frame loss can occur because data is never written to the frame buffer while it is being scanned into the display.

In order to realize the double buffering method of this embodiment, two frame buffers each composed of an expensive VRAM are used, so that the cost is somewhat increased. Further, the above configuration requires a control signal generating circuit for selecting a frame buffer which gives information to be multiplexed to the display device, and a multiplexer 19 for switching between the two frame buffers 16 and 17.

In order to reduce the cost, the conventional structure is one in which the frame buffer 16 is VRA.
DRAM is used instead of M. Since the DRAM has one port, the frame buffer 16 does not provide an output to the display device 14 that can be directly scanned. Therefore, the signal line from the frame buffer 16 to the multiplexer 19 (indicated by a broken line in the figure) is unnecessary. Further, since there is no output transfer from the frame buffer 16 to the multiplexer 19, the multiplexer 19 (also indicated by a broken line) is not provided. Since there is no multiplexer, the control circuit that selects either frame buffer 16 or 17 for scanning to display device 14 is also unnecessary and eliminated. This significantly reduces the cost of the system.

All new data is written to the frame buffer 16 by the central processing unit 12. All data is scanned from frame buffer 17 to display device 14.
When there is a change in the frame stored in the frame buffer 16, the frame is transferred to the frame buffer 17. In order to carry out this transfer, the control circuit 23 in the central processing unit 12 uses the frame buffer 1 to be read.
Select part of 6. That portion is typically 32 bits, or some amount that is typically equal to the width of the bus. By reading this data, the central processing unit 1
Latch to 2. This read typically requires three clock periods for row addressing by control circuit 23 and four clock periods for column addressing. Next, the central processing unit 12 writes the information read from the frame buffer 16 in the frame buffer 17. Also for this, the control circuit 2 in the frame buffer 17 is usually used.
It requires 3 clock cycles for row addressing by 3 and 3 clock cycles for column addressing in the frame buffer. In practice, the central processing unit 12 reads the frame buffer 16 and the frame buffer 1 so that the central processing unit 12 and the frame buffer 17 do not simultaneously access the bus.
Another clock period for column addressing is required when reading the frame buffer 16 during a read operation to provide a dead cycle on the bus between it and the subsequent write cycle for 7.

As described above, in order to transfer a predetermined amount of information from the frame buffer 16 to the frame buffer 17 in this configuration, a total of 13 or more clock cycles are required. This transfer is repeated a sufficient number of times to transfer a desired amount of data (may be the same amount as one frame) from the frame buffer 16 to the frame buffer 17. This process is relatively slow, about 2 per second when copying all frames.
It will be imagined that only 0 frames can be transferred. On the other hand, a typical display device has a frame buffer 17
Therefore, it seems that information is being received at a rate of 76 frames per second. The scanning proceeds at a speed of about 3 times the writing speed to the frame buffer 17. Therefore, with this low-cost configuration, scanning of the display device may catch up with writing of data from the frame buffer 16 to the frame buffer 17, and a frame outage may occur.

In order to prevent the problem of out-of-frames in this low cost double buffer system, the configuration of the invention shown in FIG. 2 was devised. This configuration 25 is a central processing unit 27.
, A first frame buffer 28 which may be composed of VRAM, a second frame buffer 29 which may be composed of DRAM, and a digital / analog converter 31.
And an output display device 33. Configuration 25 functions much like the lowest cost configuration of FIG. That is,
DRAM for all new data by the central processing unit 27
It is written in the frame buffer 29. All the data is scanned from the VRAM frame buffer 28 to the display device 33. When new data is written in the frame stored in the frame buffer 29, the frame is transferred to the frame buffer 28. To perform this transfer, central processing unit 27 reads a selected portion of frame buffer 29, typically a 32-bit portion, and writes the data to frame buffer 28. This process is repeated many times until the desired amount of data has been transferred.

Compared with the time required to transfer data from frame buffer 16 to frame buffer 17 in the configuration of FIG. 1, the configuration of the present invention transfers data approximately four times faster. That is, about 80 frames per second can be written from frame buffer 29 to frame buffer 28, and breaks in the frames scanned into the display will be avoided.

High speed copying of data from the frame buffer 29 to the frame buffer 28 is executed as follows. Rather than providing a single control circuit 23 to control the selection of data to be accessed by both frame buffers 16 and 17 as in the configuration of FIG. 1, configuration 25 has a central processing unit 27 (or frame buffers 28 and 29). Other devices for controlling the rendering and reading from the device) include a pair of individual control circuits 34 and 35. The first of these circuits 34 controls access to the frame buffer 29,
The second control circuit 35 controls access to the frame buffer 28. By utilizing separate control circuits 34 and 35, the two frame buffers 28 and 29 could be accessed simultaneously. At the time of rendering, the central processing unit writes the data only in the frame buffer 29 as in the previous configuration. However, if the data should be read from the frame buffer 29 and written to the frame buffer 28, the control circuit 34 selects the appropriate row and column addresses for the frame buffer 29, and the control circuit 35 causes the same row for the frame buffer 28. Select address and column address. The control circuit 34 then reads the accessed data in the frame buffer 29 and drives the data out onto the bus where the information is written to the same accessed address in the frame buffer 28. Since the data is not latched by the central processing unit 27, there is no need to provide a dead cycle for the bus turnaround to prevent two devices from accessing the bus at the same time.

With this configuration, much access time can be saved. First, because there are no separate read and write cycles, the row and column selections for the two frame buffers are done simultaneously, halving the time. Second, no clock cycle is required for bus turnaround. Third, since it is not necessary for the control circuit to first address one frame buffer and then another.
The row address will essentially be latched on the first transfer. This avoids having to spend time on subsequent line accesses for the rest of the particular line to be displayed. Therefore, after accessing the first portion of the data, in subsequent transfers from one row, one access for three clocks for both reading the frame buffer 29 and writing the data to the frame buffer 28. All you have to do is spend your time. This is less than a quarter of the time required by conventional circuits.

Since the time required for copying from the frame buffer 29 to the frame buffer 28 is shortened to less than one quarter, when the present invention is adopted, the number of frames exceeds four times that in the conventional double buffer configuration. Data can be written to the frame buffer 28. That is, while the maximum scanning speed from the frame buffer is 76 frames per second, data exceeding 80 frames per second can be written in the frame buffer 28. At this speed, scanning cannot keep up with writing to frame buffer 28 and no frame drops occur. However, in order to ensure that the copy does not catch up with the scan, all copies between frame buffer 29 and frame buffer 28 must start at the point to be displayed below the point where the scan is being performed. There is. This is simply done by referencing the row position of the scan in the circuit that controls the scanning of information from the frame buffer 28 to the display.

Although the present invention has been described in terms of a preferred embodiment, it will be appreciated by those skilled in the art that various modifications and changes can be made without departing from the spirit of the invention. Therefore, the invention should be measured by the appended claims.

[Brief description of drawings]

FIG. 1 is a block diagram showing a conventional configuration for reducing the cost of a double buffer configuration.

FIG. 2 is a block diagram of an arrangement for implementing a double buffering scheme in accordance with the present invention.

[Explanation of symbols]

 27 Central Processing Unit 28 First Frame Buffer 29 Second Frame Buffer 31 Digital / Analog Converter 33 Output Display Device 34, 35 Control Circuit

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Chris Malakowski United States 95051 California, Santa Clara Slashway 3775 (72) Inventor Bruce McIntyre United States 95014 California, Cappacino No. 8 E. Rodriguez Avenue · 20090 (72) Inventor Guy Moffat United States 94306 California · Palo Alto El Carmelo · 181 A

Claims (2)

[Claims] 1. A first frame buffer; a second frame buffer; a means for transferring data from the second frame buffer to an output display device; a means for writing new data only to the first frame buffer. Means for controlling the transfer of data to the respective frame buffers;
An output display device comprising means for simultaneously reading data from the first frame buffer and writing data to the second frame buffer. 2. A method for controlling the transfer of data to an output display system, the step of transferring new data to be displayed to a first frame buffer; the data for updating the display device being the first frame. Reading from the buffer and simultaneously writing the data into the second frame buffer; from the second frame buffer to the output display device 1
A display method comprising a process of transferring data for a frame.