JPS5995646A - Arithmetic control system - Google Patents

Abstract

PURPOSE:To reduce an overhead required for a conditional branch by writing a couple of arithmetic data and a state variable in a storage device and processing the arithmetic data according to an instruction code and the state variable. CONSTITUTION:An instruction containing an instruction code OPC and a state variable specifying code and data consiting of arithmetic data A and B and state variables CA and CB are read out of the storage device 14 and stored in an instruction register 4 and input registers 5 and 6 respectively. The instruction code OPC and variables CA and CB are decoded 2 and a computing element 1 processes the data A and B according to the conditions of those three kinds of parameters and outputs the arithmetic result X and an overflow signal V to a state variable generating circuit 3. The circuit 3 generates a state variable CX to be outputted according to the signals X and V and code SC and inputs it to an output buffer 7. The buffer 7 stores a couple of the variable CX and arithmetic result X in the device 14. An address generating circuit 8 is controlled by the output signal of the decoder 2 to perform conditional branching operation and arithmetic integrally by one instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic control method, and particularly to an arithmetic control method that controls all arithmetic operations in an information processing device.

Generally, a processor of an information processing device executes an operation according to an instruction code fetched from a storage device. The operation is normally performed regardless of the state of the data, such as whether the data to be operated on is a positive number, a negative number, or a number over 70-. If you want to change the processing depending on the state of the data, first execute an instruction to check the state of the data, and then execute all conditional branch instructions that branch depending on the state. This one-item branch realizes processing branching.

For example, when executing IA+l B I J, check the positive and negative of B in advance, and if @B is positive, [h-4-
If BJ and B are negative, it is necessary to branch to a routine that executes l'A-BJ.

Further, for example, an example will be described in which, if the calculation data A read from the storage device is equal to the constant "T"', the constant "S" is added to it, and if the calculation data A is not equal, the calculation data A is output as is.

In this case, first, an instruction is executed to load operation data A from the storage device into an input register.

Next, CO compares this calculation data A with constant “T”.
Execute the MPA command.

Next, if the comparison results do not match, a JUMP conditional branch instruction is executed.

Finally, if there is no branching, execute the ADI instruction to fully add the constant "S" to the operation data 8.

Thus, the above example requires four instructions to execute.

In conventional arithmetic control methods, there is no information indicating the state of the data itself, but there are flags (e.g. sign flag, carry flag, parity flag, etc.) that indicate the state after the operation. and executes a conditional branch. However, this 72 flag is typically reset each time an instruction is executed, independent of the previous state. Therefore, an instruction that refers to this 7 lag can be set to 7 depending on the desired instruction.
It must be executed after the lag is set and before the flag is changed by another instruction.

In this way, in conventional arithmetic control methods, when processing differs depending on the state of the data, the overhead required for state judgment and conditional branching that refers to it takes up a large proportion of the processing that is actually performed on the data. It had the disadvantage of being large.

An object of the present invention is to provide an arithmetic control method that reduces the overhead required for five conditional branches.

That is, one object of the present invention is to provide an information processing device in which an operation is performed using an instruction code and a plurality of operand data, based on the above consideration, to add a group of flags for operation control to the operand data. 7: A storage device for storing data with a 7-group flag is provided, and the entire process to be performed by the arithmetic unit is determined based on the instruction code and the flag group read from the storage device, and after the arithmetic processing, the calculation result and the instruction code are An object of the present invention is to provide an arithmetic control method that can reduce the overhead required for two-conditional branching by adding a group of flags modified by the above to the arithmetic output data and writing them into the storage device.

The arithmetic control method of the present invention includes a storage device that stores instructions including an instruction code and a state variable designation code, and data including arithmetic data and state variables.

an arithmetic unit that outputs an operation result obtained by operating the operation data according to the instruction code read from the storage device and the state variable, and writing the operation result to the storage device to be stored as the operation data; and a state variable generation circuit for generating a state variable output to be written and stored in the storage device as a pair with the operation result according to the result and the state variable designation code read from the storage device. Ru.

That is, the arithmetic control method of the present invention stores flag group-attached data in which a flag group for arithmetic control is added to the operand data in an information processing device that performs an arithmetic operation using an instruction code and a plurality of operand data. determining the processing to be performed by the arithmetic unit based on the instruction code and the flag group read from the storage device;
After the arithmetic processing, a flag group modified by the arithmetic result and the instruction code is added to the arithmetic output data and written in the storage device.

Next, an embodiment of the present invention will be described in detail with reference to the drawings. Fig. 1 is a block diagram showing an embodiment of the present invention.

It is a schematic block diagram of an arithmetic control method in which the state variable 'f is 1 bit, and FIGS. 2(a) and 2(b) are arithmetic explanations showing an example of the relationship between the input conditions of the arithmetic unit and the arithmetic operation in the arithmetic control method. 3 are state variable explanatory diagrams for explaining the operating conditions of the state variable generation circuit in the arithmetic control method.

In the embodiment shown in FIG. 1, the instruction includes an instruction code and a state variable designation code for generating a state variable output.

The arithmetic control system shown in FIG.
6, the output buffer 7, the address generation circuit 8, the multiplexer 9, the control signal lines lO~13, and the buses 100~
It is composed of 117 and °.

Figure 2 (a) shows that the operation to be executed is determined by the result of the exclusive OR of the instruction code OPC and the two input state variables CA and C8 (for the JUMP instruction, the state variable of input register 5). It shows. Figure 2(b)
2(a) shows the calculation result X output from the calculation unit 1 after the calculation determined by FIG. 2(a) is executed.

Further, FIG. 3 shows that the generated state variable output cx is determined by the state of the state variable designation code 8C and the calculation result X.

The operation of the arithmetic control method shown in FIG. 1 will be explained below.

When an instruction is executed, first the instruction register 4. The data read from the storage device 14 to the input registers 5 and 6 and placed on the data bus 114 is transferred to the buses 101, 102.1.
03, it will be 2 times.

That is, the instruction register 4 stores an instruction including an instruction code OPC and a state variable designation code SC, and the input registers 5 and 6 store state variables CA, CB and operation data A, B, respectively.

The state variables CA and CB are read out from the storage device 14 (or other registers) in pairs together with the calculation data A and B.

The instruction code UPC and two state variables CA and CB are.

The signals are input to the instruction decoder 2 via buses 104, 105, and 106e, respectively. This 381! The parameters determine the processing command for the arithmetic unit 1 and the control for the address generation circuit 8 under the conditions shown in FIG. 2(a).

First, the arithmetic unit 1 receives a processing instruction determined under the conditions shown in FIG. Calculation is performed on the calculation data A and B input via l0JII, and the second
The calculation result X is sent to buses 110 and 111 according to figure (b).
Output. The state variable generation circuit 3 uses this calculation result X,
The over 70-signal ■ output from the arithmetic unit 1 and the state variable designation code SC input via the bus 109'e.
The state variable Cx to be output is generated. The production conditions are as shown in FIG. The operation result X outputted to the bus 111 is driven to the data bus ttl by the output buffer 7 via the multiplexer 9 except for the COMP instruction. C(JMP instruction, the operation data A on the bus 116 is input to the output buffer 7.

The switching signal of this multiplexer 9 is sent to the instruction decoder 2.
is generated.

On the other hand, the control signal 11 output from the instruction decoder 2 is input to the address generation circuit 8 and controls the program counter. That is, after the calculation is completed by the control signal 11,
It is determined whether to increment the log2m counter or set it to the branch destination address.

The above operation will be explained using two simple examples.

As a first example, we will take up the operation ``If the operation data A read from the storage device is ``T'', add ``S''''. The commands listed in Figure 2 (a) are used.

First, a LOAD instruction is executed to read operation data A from the storage device 14, and the input register 5 is read out from the storage device 14 via the data bus.
Then, "T" is also latched into the input register 6. In addition,
State variable CA at this time.

e may be either "1" or 00".

Next, C (JMPAI (E command) input register 5
The calculation data stored in the input register 6 is compared with "T" stored in the input register 6. The operation of the CL) MPA E instruction is to subtract the contents of input register 5 and input register 6 in the arithmetic unit, but the contents of input register 5 (bus 117) are sent to output buffer 7 via multiplexer 9. Modified state variable (signal +l1l12)'
The signal is output to the input register 5 and then relatched to the input register 5. This @, state variable specification code SCi “101”
Please specify. That is, if the operation result X obtained by executing the COMPARE instruction is equal to "0", the state variable output CX is set to "1" if it is not equal to "O" by 1, and the result is relatched in the input register 5. As a result, only the state variables of input register 5 are changed.

Subsequently, the ADD instruction is executed. The input register 6 has “0” as the state variable CB and “S” as the calculation data B.
Enter. This ADD instruction has two input state variables C
A and CB are compared, and if they are equal, addition is performed, and if they are not equal, NOP is performed. That is, COM
If the state variable CA obtained by executing the PARE instruction is "0", "r+si" is output as the operation result X, and if it is "1", the value of the input register 5 is output as is.

Thus, in the case of the first example, execution of three instructions is sufficient if the present invention is applied.

In the first example described above, depending on the value to the calculation data, A
The process temporarily branches to execute either DL) or NOP, but after execution, the same sequence will be executed again. This is the same for other instructions that combine an operation and a NOP (except JUMPk), and the conventional branch operation using a conditional branch instruction is no longer necessary.

By the way, if a comparison between the calculation data A and "1" has been executed and the comparison result has already been stored in the storage device 14 as the state variable CA (each address of the storage device 14 contains the calculation data and the state (variables are stored in pairs and addressed simultaneously), use LOAD
Then, the AL)D instruction can be executed immediately. That is, since the state of the calculation data is stored in the memory as a state variable, the COMPARE instruction is no longer necessary. State variables are regenerated when all operations are executed, not just COMPA) LE instructions, so if you store the state variables generated as a result of some operation in the storage device along with the data, Its state can be extracted at any time and used for other operations. Conventionally,
This was only temporarily preserved as the state after the calculation.

Next, the operation of a conditional branch instruction will be explained.

As shown in FIGS. 2(a) and 2(b), whether one branch is taken or not is determined by the value of the state variable CA of the input register 5. That is, the instruction code input to the instruction decoder 2 (by JPC and state variable cA).

A signal indicating the success or failure of the branch is generated and the control signal 1
It is output to the address generation circuit 8 as 1.

In response to this, the address generation circuit 8 generates a program.
Control the value of a counter.

Next, as a second example, the case of ``if the addition results in an overflow, jump to address Z'''' will be explained.

First, an ADL command with the state variable designation code SC set to "111" is executed. State variable output Cx at this time
and the operation result X is transferred from the output buffer 7 to the bus 113,
14.103? latched into the input register 5 via r:

Next, one conditional branch instruction “JUMP (OPC=O110)”
The success or failure of the branch is determined by the instruction code and the value of the state variable CA stored in the input register 5. In this case, the sequence of "operation" → "conditional branch" is essentially the same as the conventional method.

However, as in the first example described above, the calculation result X and state variable output Cx are stored in the storage device 1 as calculation data and state variables.
4, the data can then be accessed at any time on the LOA.
D and then execute a conditional branch immediately after that.

This was not possible with conventional methods.

Although one embodiment of the present invention has been described above, it is clear that by using a plurality of bits as a state variable and expanding the state variable designation code, it becomes possible to perform even more diverse conditional operations. In cases where processing differs depending on the state of data, the present invention eliminates conditional branching and reduces the associated setting of conditional determiners, making it possible to shorten processing time. Performance can be significantly improved.

The arithmetic control method of the present invention adds a state variable generation circuit, writes the generated state variables as a pair with calculation data in a storage device, and calculates the calculation data according to the instruction code and state variable during calculation. Since the conditional branching operation and the arithmetic operation can be processed integrally with one instruction, the overhead required for the conditional branching can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 (aλ(b) is an operation explanatory diagram for explaining the operation of the arithmetic unit shown in FIG. 1, and FIG. 3 is a state variable explanation for explaining the operation of the state variable generation circuit shown in FIG. 1. It is a diagram. 1... Arithmetic unit, 2... Instruction decoder,
3... State variable generation circuit, 4... Instruction register, 5.6... Input register, 7...
...Output buffer 7, 8...Address generation circuit, 9...Multiplexer, 10-12...
...Control signal, 14...Storage device, 100-1
17...Bus, OPC...Instruction code, SC...State variable specification code, A, B...Calculation data, X... Calculation result. CA, CB...State variables Cx/Old...How the state variables appear.

Claims (1)

[Claims] a storage device for storing instructions including an instruction code and a state variable designation code, and data consisting of operation data and state variables; and a storage device for calculating the operation data according to the instruction code and the state variable read from the storage device. an arithmetic unit that writes the obtained arithmetic result into the storage device and outputs the result to be stored as the arithmetic data; and a computation unit that outputs the arithmetic result to be stored as the arithmetic data in the storage device; and a state variable generation circuit for generating a state variable output to be written to and stored in the storage device.