JPS6364130A - Branching instruction control method - Google Patents

Abstract

PURPOSE:To shorten an instruction executing time by reading the instruction of a branch destination address and executing the instruction immediately after the branch instruction in parallel by a pipeline control. CONSTITUTION:A pipeline register selecting circuit 17 is set to select an address register 3, an incrementer 7 and a pipeline register file 8. The reading address of a memory 1 is accommodated in the register 3, this is outputted through a multiplexer 2 to the memory 1 and the output data of the memory 1 are inputted to the file 8. The incrementer 7 adds +1 to an address and outputs it to a multiplexer 5. As the result A+1 is accommodated to the register 3. The data accommodated to the file 8 by a pipeline control circuit 10 decode an instruction A with an instruction register and an instruction decoder 12 through a multiplexer 11, at the time of an operation instruction, an operation and operation control circuit 14 is operated and the operation result is sent to a branch deciding circuit 16. Thus, the reading of the instruction and the execution are performed in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a branch instruction control method for an electronic computer used in the information processing field, measurement control field, and the like.

2. Description of the Related Art Conventionally, this type of branch instruction control method executes a branch instruction after execution of an arithmetic instruction, and branches to a predetermined branch destination when a branch condition is met.

However, in the conventional branch instruction control method described above, (1) an arithmetic instruction is executed and a branch condition is generated as a result.

(2) Check whether the branch condition is met using a branch control instruction, and if it is true, calculate the branch destination address.

■ Read and execute the instruction at the address calculated above.

Control is performed in a sequential manner, and the above instruction execution time is determined by the sum of (1), (2), and (2), so there is a problem that it takes a long time.

SUMMARY OF THE INVENTION The present invention aims to solve these conventional problems and to provide a branch instruction control method that can shorten instruction execution time.

Means for Solving the Problems In order to achieve the above object, the present invention pipelines instruction read execution, causes a branch instruction to act on a branch condition of an operation result to be executed thereafter, The execution of the arithmetic instruction immediately after the branch instruction and the reading of the branch destination address are performed in parallel.

Effects The present invention has the following effects due to the above configuration. That is, (1) By executing a branch instruction, a branch destination address is calculated, and a branch condition for branching is set according to the operation result generated by the instruction to be executed thereafter.

■ While executing the arithmetic instruction, read the instruction at the branch destination address calculated in (■) above.

(2) If the result of the operation satisfies the branch condition set in (2) above, execute the instruction at the branch destination address determined in (2) above.

In this way, execution time can be shortened by executing the arithmetic instruction and reading the instruction at the branch destination address in parallel in (1) above.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, 1 is a memory that stores instructions to be executed. 2 is a multiplexer for inputting an address to memory 1; 3 and 4 are address registers for temporarily storing an address to read from memory 1; multiplexer 2 selects address register 3 or 4 as the address to memory 1. Numerals 5 and 6 are multiplexers, both of which are connected to an incrementer 7 and an instruction execution sequence control circuit 13, which will be described later. One of them is selected and outputted to address registers 3 and 4, respectively. 7
is an incrementer that increments the memory address output from the multiplexer 9-2 and outputs it to the multiplexers 5 and 6. 8 and 9 are pipeline register selection circuits 17 that store data (instructions) from memory 1;
The signal determines which of them the data in the memory 1 is input to, and also determines which of their outputs is input to the multiplexer 11, which will be described later. 10
is a pipeline control circuit that controls writing and reading of the pipeline register file 8.9. 11 is a multiplexer, and pipeline register selection circuit 17
According to the signal, any of the inputs of the pipeline register file 8.9 is output to the instruction register and instruction decoder 12. The instruction register and instruction decoder 12 temporarily stores instructions to be executed, and interprets the instructions.
Select the circuit corresponding to the instruction. 13 is an instruction execution sequence control circuit; 14 is an arithmetic and arithmetic control circuit; 15 is a branch condition register;
A branch condition is set when a branch instruction is executed in . A branch determination circuit 16 determines whether or not to branch based on the inputs of the arithmetic and arithmetic control circuit 14 and the branch condition register 15, and outputs the result to the instruction execution sequence control circuit 13 and pipeline register selection circuit 17.

Pipeline register selection circuit 17 is branch judgment circuit 16
According to the output from (depending on whether the branch condition is met or not)
, controls multiplexer 5.6, pipeline register files 8, 9, and multiplexer 11 as described above.

Next, a branch instruction control method will be explained with reference to the branch control sequence chart shown in FIG.
Assume that settings are made to select incrementer 7 and pipeline register file 8. The read address of memory 1 is stored in address register 3 (
A), this is output as an address to the memory 1 via the multiplexer 2, and the output data of the memory 1 is input to the pipeline register file 8.

When the data is stored in the pipeline register file 8, the incrementer 7 increments the address by 1 and outputs this to the multiplexer 5.

As a result, A+1 is stored in address register 3,
This means that the address to memory 1 has been increased by 1. On the other hand, the data input to the pipeline register file 8 is stored in the pipeline register file 8 by the pipeline control circuit 10, and this data is stored in the pipeline register file 8 by the multiplexer 11.
is input to the instruction register and instruction decoder 12 via the instruction register and instruction decoder 12. The instruction register and instruction decoder 12 decode the instruction A, and if it is an arithmetic instruction, the arithmetic and arithmetic control circuit 14 is activated;
The result of the calculation is sent to the branch determination circuit 16. As described above, the reading of an instruction and its execution (reading from address A to A+5, execution to address A+3) are performed in parallel.

If the output data (instruction) from the pipeline register file 8 is a branch instruction, for example, if the instruction at address A+3 is an instruction to branch to B if the subsequent operation result is ZERO, the instruction register and instruction decoder 1
The instruction is decoded at step 2, and the instruction register and instruction decoder 12 activate the instruction execution sequence control circuit 13.

The instruction execution sequence control circuit 13 sets the branch condition in the branch condition register 15 and activates the pipeline register selection circuit 17 to select the address register 4, multiplexer 6, and pipeline register file 9 as the instruction input path. instruct them to do so. At the same time, the branch address is calculated and the result is the calculation result),
Write to address register 4. As a result, address B is output from the address register 4 to the memory 1, and the data is stored in the pipeline register file 9.

In parallel with this operation, the instruction at address A+4 is transferred to the pipeline register file 8, multiplexer 11, instruction register and instruction decoder 12, arithmetic and arithmetic control circuit 14.
The calculation result is sent to the branch judgment circuit 16. The branch determination circuit 16 compares the calculation result of the calculation and calculation control circuit 14 with the contents of the branch condition register 15 set by the branch instruction, and sends the result to the instruction execution sequence control circuit 13 and the pipeline register selection circuit 17. If the branch condition is satisfied, the pipeline register selection circuit 17 selects multiplexer 6, address register 4,
Select pipeline register file 9 (i.e. B
+1, B+2, . . .), and the instruction execution sequence control circuit 13 clears the branch condition register 15. If not established, the pipeline register selection circuit 17 selects the multiplexer 5, address register 3, and pipeline register file 8 (i.e., A+5, A+6, . . .
・) Select.

Effects of the Invention In the present invention, as described above, a branch instruction sets a branch condition for subsequent operation instructions, and pipeline control allows reading of the instruction at the branch destination address and execution of the instruction immediately after the branch instruction. can be executed in parallel, and therefore the instruction execution time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining a branch instruction control method in an embodiment of the present invention, and FIG. 2 is a sequence chart of the method of the present invention. 1...Memory, 2...Multiplexer, 3, 4...
・Memory address register, 5, 6 ・Multiplexer, 7...Address incrementer, 8, 9...Pipeline register file, 1O...Pipeline control circuit, 12...Instruction register and instruction decoder,
11... Multiplexer, 13... Instruction execution sequence control circuit, 14... Arithmetic and arithmetic control circuit, 1
5... Branch condition register, 16... Branch judgment circuit,
17...Pipeline register selection circuit.

Claims (1)

[Claims] The execution of read instructions is pipelined, the branch instruction acts on the branch condition of the operation result executed after this, and the execution of the operation instruction immediately after the branch instruction and the read of the branch destination address are performed in parallel. Characteristic branch instruction control method.