JPH01147723A - Pipe line processing system for information processor - Google Patents

Abstract

PURPOSE:To decrease a delay due to the processing time of a branching instruction or a floating decimal point instruction by carrying out a short pipe line action in an action mode in which a processor can carry out a privileged instruction, and executing the long pipe line action of an arithmetic execution in the other mode. CONSTITUTION:An instruction controller 1 reads the instruction from a memory controller 2, decodes it, obtains a logical address by an address calculation if needed, reads an operand from the device 2, and transfers an operating code, the operand, operating information, etc., to an arithmetic unit 3. Operating units 35 and 36 are provided at the unit 3, and a floating decimal point operation and a binary basic operation are respectively carried out. The former requires three cycles for digit matching, an operation and normalization, on the contrary, the latter requires only one cycle. When the device is in the mode which can carry out the privileged instruction with a smaller floating decimal point instruction frequency and a larger branching instruction frequency, the unit 36 is selected, the short pipe line action is carried out, and the processing time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing apparatus that performs pipeline processing, and particularly to a pipeline processing method.

[Conventional technology]

Conventionally, in the J3 of this type of information processing device, operations using floating point instructions and decimal instructions are complicated, and therefore the operations take a plurality of V cycles to execute. Additionally, some supercomputers and large accounting machines have arithmetic units that are pipelined.

[Problem that the invention seeks to solve]

1- In the conventional information processing device described above, floating point instructions, 10y1 instruction, etc. require multiple cycles to execute operations, so when such instructions are executed, the pipeline becomes clogged and the throughput of instruction execution slows down. was decreasing.

In addition, when a computing device is pipelined, such as in a supercomputer, it becomes possible to execute operations continuously, so there is no sagging in the pipeline and the throughput does not decrease. This method has disadvantages such as a delay in determining branch prediction failure and a delay in determining address modification registers because the single bib line generated becomes longer.

[Means for solving problems]

In the pipeline processing method of the information processing device of the present invention, when the processing device is in the fz operation mode in which privileged instructions can be executed,
A short pipeline operation is performed without performing pipeline processing for calculation execution, and in other operation modes, pipeline processing for calculation execution is performed to perform good pipeline operation.

[Effect]

In the privileged instruction executable operation mode where the frequency of floating point instructions is low and the frequency of branch instructions is high, by performing short pipeline operations without pipeline processing of operations, it is possible to avoid reducing the number of bars during branch processing. In addition, in an operation mode in which floating point instructions are frequently used and branch instructions are used, such as branch instructions and small privileged instructions cannot be executed, pipeline processing of operations can be performed to reduce delays caused by floating point instructions.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of an information processing apparatus to which the pipeline processing method of the present invention is applied.

This embodiment is comprised of an instruction control device 1, a storage control device 2, an arithmetic device 3, and the like.

The instruction control device 1 reads the instruction from the storage control device 2, decodes it, and if necessary, calculates the address to immediately obtain an address, reads the operand from the storage control device 2, and plays the operation code, operand, operation information, etc. Transfer to 3.

The arithmetic unit 3 performs operations based on information set by the instruction control unit 1, and updates the main memory through various registers, statuses, or the storage control unit 2.

In the instruction control device 1, a bit field of the instruction register (IR) 11 specifies a general register file (C
In the case of an RX type instruction, the contents of the register are not read from the GR) 13, but the base value at index 1 is read from the general-purpose register file 13 in order to generate an address. This index 1, the base value is in register (XR) 15 along with the displacement value directly specified by the instruction.
, (BR)16, and (DR)14, respectively.

Based on the values of these registers 14, 15, and 16, an operand address is generated from the address register (ADR) 17 and stored! 1.11 is sent to all devices m2 and held in the address register (MAR) 21. This operand address is address translation 141! (TLB)22
Address conversion is performed, and the address is held in the address register (PAR) 23 together with the directory information read from the address array (AA) 22 of the cache, and used as the read address of the data array (DA) 24. From this, the operand is read from the data array 24 and sent to the performance device 3. On the other hand, the first operand of the RX type instruction and the first operand of the RR type instruction. The register number where the second operand is stored is register (IDR) 18
, via decoding information queue (IDQ) 19 @n device 3
and is held in register (EDII) 31. In the arithmetic unit 3, the instruction control unit 1
Operands are read from the general register file (GR) 32 based on the register numbers sent from the GR. One of the read register values is set as the first operand in the operational register (DARO, FDARO) 51.41. The value of the other register is selected by the operand and selector (SEL) 33 sent directly or via the data buffer (DB) 34 from the memory system tIl device 2, and the value of the arithmetic register (DARl, FDARl) is selected as the second operand.
I) set to 52.42. Performed unit 35.36
Each performs a binary Hanagi operation b and a floating point drop n. The Operator 1nit (FALJ) 35 performs floating point operations, but floating point operations require digit alignment of the floating point number before the operation and normalization afterward22.
A plurality of 1noicles are required for the calculation. In this embodiment, one cycle is required to match the digits of the operand, one cycle is required for addition and subtraction, and one cycle is required to normalize the result of operation i, and three cycles are required for operation n of floating point numbers. On the other hand, the arithmetic unit (BAU) 36 performs basic binary operation 9,
Is the binary operator a floating point number? It is more accurate than 1Xi0, and in this embodiment ends with Q1 recycle. Note that the arithmetic unit 35 has registers 41, 42, 44, 45,
47.49, Digit U circuit 43, Floating point arithmetic circuit (F
A L kJ ') 46, a normalization circuit 48, and the arithmetic unit 36 includes registers 51.52.54.5.
5.56, it is composed of a logic section n circuit (ΔLU) 53.

The selection circuit 37 selects and outputs the output of the register 49.54.56 according to the value of a flag indicating the operation mode (privileged mode) provided in psw<not shown) and instruction decoding information. operating modes in which privileged instructions are not executable;
In other words, in slave mode or user mode, pipeline processing for execution of the operation p is performed, so in order to shorten the pipeline length of the operation units 35 and 36, a register (DCR) that holds the result of the binary basic operation 9 is used. .

DDR) 55.56 is used.

FIG. 2(a) is a time chart of the pipeline in the tree operation mode. In the figure, D, A.

P, C, L, E, N, S are decoding cycles, respectively.
It shows an address generation cycle, a paging cycle, a cache read cycle, a digit V cycle, an arithmetic cycle, a normalization cycle, and a store cycle. The arithmetic execution cycle for binary basic instructions also takes three cycles for floating point instructions, and is controlled so that the pipeline flows smoothly.

*) J fl mode in which privileged instructions can be executed, that is,
~101 in privileged or supervisor mode
00 pipeline processing is not performed, and the
Since there is no need to worry about the length of the pipeline in units 35 and 36, registers (DCR) are used.

DDR) 55.56 are bypassed and not used. In FIG. 2(b), there is a time sheet of 43 pipelines in the main motion mode. The pipeline shown in FIG. 2(b) is different from the one shown in FIG. 2(a) in that there is no 1-cycle or N-cycle in the binary basic instruction pipeline; l1g! Recycle is only one cycle, the E cycle. However, floating point instructions require 1. , E, N"cycles are required, so if the binary Lt instruction follows, there will be 2 vacant cycles and the throughput will decrease. FIG. 2(c),
(d) is a time chart 1 sheet of branch instruction processing (branch prediction failure n) in two pipeline modes. The branch direction of a branch instruction is determined when the execution of the instruction immediately before the branch instruction is completed. These 111 points also determine whether the branch prediction was successful or not, and if the prediction fails, the decoding process starts from there. FIG. 2(C) shows a time chart of failure in branch prediction in the perform-by-line mode in an operating mode in which privileged instructions cannot be executed. In the same figure, the binary 1j-tree instruction immediately before the branch instruction is shown in Figure 51.
The processing cycle ends in N cycles, but the success/failure of branch prediction is not known until this cycle ends. Therefore, in the case of a failure, there is a delay of five cycles in the execution of the branch destination instruction. FIG. 2(d) is a time chart of branch prediction failure in a non-oil-sheared pipeline when the privileged instruction is executable<E operation t--do. In the figure, the execution-only processing cycle of the binary basic instruction immediately before the branch instruction ends in cycle E, and when this cycle ends, it is known whether the branch prediction has succeeded or failed.

Therefore, in the case of branch prediction failure, there is a delay of three cycles in the execution of the branch destination instruction, but the delay is two cycles less than in the case shown in FIG. 2(C).

In this way, in the En9 pipeline mode, extra cycles are avoided even when processing instructions that require multiple cycles for arithmetic processing, such as floating point instructions.
The delay due to measurement failure is significant. On the other hand, in non-branched pipeline mode operation, when processing an instruction that requires multiple cycles for i# processing, such as a 2-round decimal point instruction, pipeline processing will be disrupted by the number of execution cycles, but branch Y It has the characteristic that the measurement failure is J and the Ruokakure is small.

〔Effect of the invention〕

As explained in 1 above, the present invention is applicable to 11! When the device is in an operating mode in which it can execute privileged instructions, it does not perform the pipelining process of execution execution, but performs a short vibe line operation, and in other IIIIf'1 modes, it performs
A good pipeline fJ that performs pipeline processing of j
＋ '／＋ J, S, T? In the special instruction executable operation mode where the frequency of floating point instructions is low and the vA degree of branch instructions is large, the branch processing time is reduced by performing a short vibe line operation without pipeline processing of the operation p, and the floating J point In the privileged instruction disable operation mode where the frequency of instructions is high and the frequency of branch instructions is small (1α), pipeline processing of performance 0 is performed, which has the effect of reducing delays caused by floating point instructions.

[Brief explanation of the drawing]

Fig. 1 is a schematic diagram of an embodiment of an information processing raccoon head to which the vibe line processing method of the present invention is applied, and Fig. 2 is a time chart in this embodiment. 1... Instructions Control device, 2... Storage control device, 3... Playing device, 35... Floating point arithmetic unit, 36... Binary basic playing unit.

Claims (1)

[Claims] In an information processing device that performs advance control, when the processing device is in an operation mode in which it can execute privileged instructions, it does not perform pipeline processing for execution of operations, but performs a short pipeline operation, and in other operation modes, it does not perform pipeline processing for execution of operations. A pipeline processing method for information processing equipment that performs pipeline processing and performs good pipeline operation.