JPH031234A - Information processor - Google Patents

Abstract

PURPOSE:To accelerate the execution of an instruction by executing the instruction such as a load instruction, a store instruction, and a branch instruction, etc., not using a computing element and an other instruction using the computing element in parallel. CONSTITUTION:When an instruction decoder decodes plural instructions in an instruction string in parallel, an instruction control means judges a decoded instruction, and sends out the low-order bits of an arithmetic input registers 12 and 13 to the low-order bit of an arithmetic output register 14 bypassing the computing element 9 by using data buses 12b and 13b when the instruction using the computing element 9 is executed. Also, the instruction not using the computing element 9, for example, a data transfer instruction between the registers 12 and 13, the load instruction of the data transfer instruction between the registers 12, 13 and a memory 1, and the store instruction, etc., is executed in parallel with the instruction using the computing element 9. Thereby, it is possible to execute the processing of the instruction without increasing the number of computing elements 9, and to improve performance.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an information processing device, and particularly to an information processing device that simultaneously executes an instruction that uses an arithmetic unit and an instruction that does not use an arithmetic unit in parallel. It is related to.

[Conventional technology]

Conventionally, in information processing devices, a pipeline control method has been the mainstream method for speeding up the execution of instruction processing. This pipeline control method divides the processing of one instruction into multiple independent stages, overlaps the processing of different stages of multiple instructions, and runs them simultaneously, reducing the effective execution processing time of one instruction. This is a control method that shortens the time.

Furthermore, a parallel processing method is also used in which a plurality of arithmetic units l- are used to simultaneously execute a plurality of instructions in parallel in each arithmetic unit. An example of an information processing device using this type of parallel processing method is, for example,
There is one described in Publication No. 16335.

However, in a parallel processing system using a plurality of arithmetic units, it is difficult to synchronize each instruction in a program that sequentially executes instructions due to the transfer of processing results between each instruction. On the other hand, the above-mentioned Japanese Patent Application Publication No. 6
The information processing apparatus described in Japanese Patent No. 1-16335 is equipped with a circuit that determines the resources required for processing an instruction, and uses an instruction control method that allows overtaking of instructions to speed up instruction processing.

[Problem to be solved by the invention]

By the way, when speeding up instruction processing using the pipeline control method, it is possible to increase the independence of each stage of processing of one instruction and increase the degree of multiplicity of processing at each stage. It is necessary to shorten the effective execution processing time of one instruction. Therefore, in order to increase speed, it is necessary to make each stage smaller so that execution of one instruction is completed in each stage, but in this case, if the flow of processing at each stage is disrupted, the flow of the pipeline will be disrupted. This method has the disadvantage that it requires a lot of time to normalize the disturbance, and the overhead due to the disturbance in the pipeline becomes large.

In addition, in parallel processing methods that use multiple processing units,
Due to the above-mentioned synchronization problem, the logic of instruction execution control becomes complicated, the control method for implementation becomes complicated, and the amount of hardware required increases. Furthermore, even if multiple arithmetic units are provided, in actual program processing, the arithmetic result of the previous instruction is often used in the immediately following instruction, so multiple arithmetic units can be used to efficiently perform parallel processing. There is a problem that there is often little that can be done, and processing performance does not improve even though a large amount of hardware is provided.

The present invention has been made to solve the above problems.

An object of the present invention is to provide an information processing device that can simultaneously execute instructions that use an arithmetic unit and instructions that do not use an arithmetic unit.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

In order to achieve the above object, the information processing device of the present invention includes an instruction decoder that decodes a plurality of instructions in an instruction string in parallel, an arithmetic unit, and an arithmetic unit that bypasses the arithmetic unit and outputs the lower bits of the arithmetic input register. The data path to be sent to the lower bits of the register and the instruction decoded by the instruction decoder are determined, and when an instruction that uses an arithmetic unit is executed, an instruction that does not use an arithmetic unit is executed using the arithmetic unit using the data path. It is characterized by comprising an instruction control means that executes the instructions to be used simultaneously and in parallel.

[Effect]

According to the above means, the information processing device includes: an instruction decoder, an arithmetic unit, and a data path that bypasses the arithmetic unit;
Command control means are provided. When the instruction decoder decodes multiple instructions in the instruction sequence in parallel, the instruction control means determines the decoded instruction, and when executing an instruction that uses an arithmetic unit, calculates the lower bits of the arithmetic input register using the data path. Instructions that bypass the unit and send to the lower bits of the operation output register, and do not use the operation unit, such as data transfer instructions between registers, data transfer instructions between registers and memory, load instructions, and store instructions, Executes in parallel with instructions that use arithmetic units.

As a result, instructions can be processed in parallel without increasing the number of arithmetic units, and performance can be improved.

The data path that bypasses the arithmetic unit and sends the lower bits of the arithmetic input register to the lower bits of the arithmetic output register consists of a selector that independently selects the upper and lower bits of the input register of the arithmetic unit, and a selector that independently selects the upper and lower bits of the input register of the arithmetic unit. It consists of a path that allows data to be transferred from the register to the output register without passing through the arithmetic unit, and a selector that selects the transfer data from the path and the output data from the arithmetic unit and supplies it to the output register. Further, the instruction decoder decodes at least two instructions simultaneously in parallel, and the instruction control means determines which instructions do not use an arithmetic unit and which instructions use an arithmetic unit can be executed in parallel, and control the processing of the instructions. I do. Instructions that use arithmetic units are controlled by microprograms, and instructions that do not use arithmetic units are controlled by hardware logic path control. In this way, parallel execution of instructions is
Since path control by hardware is only added, controlling the parallel execution of instructions that can be executed in parallel does not become complicated, and can be achieved by simply adding a hardware path.

Generally, in the architecture of an information processing device, an arithmetic unit has a width of 8 bytes or more for data transfer from memory to memory or decimal operation. Furthermore, since the transfer instruction between the memory and the register handles 4-byte wide data, the remaining 4 bytes of the arithmetic unit are not effectively used in this transfer instruction. Therefore, even if the data path circuit according to the present invention is added, the amount of hardware in the arithmetic unit structure will not increase.

〔Example〕

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

FIG. 1 is a block diagram showing the configuration of an information processing apparatus according to an embodiment of the present invention. In FIG. 1, ■ is the main storage device. The instruction sequence read from the main memory device 1 is transferred to the instruction buffer 2 through the instruction transfer path 1a and stored therein. The instruction sequence stored in instruction buffer 2 is
Furthermore, the preceding instruction is extracted into the X instruction register 3, and the subsequent instruction is extracted into the Y instruction register 4, and decoded by an instruction decoder (not shown). Each instruction (
(preceding instructions, subsequent instructions) are decoded and determined, and instruction processing is controlled according to the content of each instruction. That is, if the instruction is an instruction that requires memory data, the memory address is sent to the main storage device 1 via the memory address buses 33 and 43, and a read request is issued. In response to a read request, the main memory contents are read from the main memory device 1, and the data path lb
, lc. If the instruction in question requires the contents of a general-purpose register, the required general-purpose register number is notified to the general-purpose register group 5 via paths 32 and 42, and the contents of the register with the general-purpose register number are read. data path 5 from general register group 5
a and data path 5b. In this way, the operands required for processing each instruction can be read for each of the instructions in the X instruction register 3 (hereinafter referred to as the X instruction) and the instruction in the Y instruction register 4 (hereinafter referred to as the Y instruction). It is configured to have a mechanism that independently executes instructions.

In addition, the type of each instruction (X instruction and Y instruction) set in the X instruction register 3 and Y instruction register 4 is transferred to the instruction parallelism determination circuit 6, and the instruction parallelism determination circuit 6 uses , M commands) and data transfer only commands (hereinafter referred to as S commands).

As a result of the determination, if the instruction parallelism determination circuit 6 determines that the X instruction and the Y instruction are an M instruction and S' all instruction pair, the control line 6a determines which of the X instruction and the Y instruction is the M instruction. is transmitted to the selector 20 by the signal on the control line 6a.
selects the M instruction side. The start address of instruction processing is set in the control storage address register 10 according to the instruction code of the instruction selected by the selector 20,
Microprograms are sequentially read from the control storage device 8 and their contents are set in the control storage data register 11. The microinstruction set in the control storage data register 11 controls the arithmetic unit 9 to execute the instruction.

On the other hand, a parallel correspondence signal indicating the correspondence between the X instruction/Y instruction and the M instruction/S instruction is transmitted from the instruction parallel determination circuit 6 to the operand control circuit 7 via the signal line 6b. The operand control circuit 7 receives the parallel correspondence signal, receives the operand signals from the X instruction register 3 and the Y instruction register 4 (signals from paths 32, 33, and 42, 43), and performs the operations necessary for the X and Y instructions. Knowing the operands to be used as
WBR) 13 generates a select signal for data to be set. The generated select signal is sent to the selector 21. by the signal lines 7b and 7C. is supplied to the selector 22, and the selector 2
1 and selector 22.

As described above, data from the general-purpose register group 5 is provided to the selectors 21 and 22 through the data paths 5a and 5b, and data read from the main memory 1 is provided to the selectors 21 and 22 through the data paths lb and lc, respectively. ing. others'
Therefore, by controlling selectors 21 and 22 with select signals, the operands of the M instruction are set to WAR12 and WBR1.
The operand of the S instruction is set to the second half (lower bit part) of WAR12.WBR13. The operand data of the M instruction set in WAR12 and WBR13 is transferred to the data path 12a,
The signal is supplied to the arithmetic unit 9 by 13a. Also, in the arithmetic unit 9.

As a control signal for calculation, a microinstruction is supplied from the control storage data register 11 via a control line 11a,
The microinstructions control the arithmetic unit 9 to control the execution of instructions using the arithmetic unit. The calculated result data is
It is input to the selector 23 via the data line 9a.

On the other hand, the operand of the S instruction placed in the latter half of the WAR 12 and WBR 13 is directly input to the selector 23 by bypassing the arithmetic unit 9 through the data paths 12b and 13b. In the selector 23, the operation result of the M instruction and the data of the S instruction are outputted to the operation output register 14 by the control signal from the operand control circuit 7 via the control line F a, and the general-purpose register group 5 and Main storage device 1
The result of instruction processing is stored in . Note that write requests to the general-purpose register group 5 and the main memory bag gil are issued independently, and data write operations are independently controlled for the general-purpose register group 5 and the main memory device 1, respectively.

In this way, when it is determined that the X and Y instructions decoded in parallel can be paired as the M and S instructions, the instruction processing is controlled as described above.
It is possible to execute instruction processing in parallel as an instruction and an S instruction.

If the decoded X and Y instructions cannot be paired with M and S instructions and become M and M instructions, the instructions are not executed in parallel and the X and Y instructions are Execute independently. In this case, under the control of the instruction parallelism determination circuit 6, the X instruction is made into an M instruction, and the operand control circuit 7

By controlling the instruction so that the data of the Y instruction is not selected, one instruction can be executed independently. Further, if the decoded X instruction and Y instruction cannot be made into a pair of M instruction and S instruction but become S instruction and S instruction, they can be executed in parallel as an instruction pair of S instruction. In this case, by executing one of the S instructions through the arithmetic unit, it can be treated as the execution of an M instruction and an S instruction, and parallel execution can be performed.

Even if instructions are controlled to be executed in parallel, the arithmetic unit usually has a data width of 8 bytes or more for decimal operations and transfer from memory to memory. Parallel execution of instructions can be controlled without changing circuits for setting condition codes based on calculation results, overflow detection, etc.

In this embodiment, the input register of the arithmetic unit is set up in the order of 1M instruction and then S instruction, and the input register of the arithmetic unit with a width of 8 bytes or more, which is set up for decimal instructions, is used as is. However, other registers may be used for the instruction set-up order and the register for setting up data for the S instruction.

5 In this embodiment, two data paths, data path 12b and data path 13b, which bypass the arithmetic unit 9 are provided for parallel execution of S instructions, but the actual processing of S instructions is as follows. Since the only function is data transfer, the S instruction requires only one data as an operand. Therefore, by setting data to the WAR12°WBR13 in one of the registers, for example, the WAR12, it is possible to omit the negative data path 13b.

In this way, S instructions that do not require an arithmetic unit, such as register data transfer instructions, memory register load instructions, register memory store instructions, etc., have lower processing power than M instructions that perform operations. Since it is easy to execute, by providing a function that can simultaneously execute M instructions and S instructions, it is possible to shorten the processing time of S instructions, which appear relatively often in normal programs. This makes it possible to speed up instruction processing.

As described above, according to the information processing apparatus of this embodiment, the execution of the M instruction is controlled by microprogram control or the like in the same way as normal instruction execution. By limiting the S instruction to an instruction that only has the function of transferring data, it is executed so as not to affect the execution of the M instruction. In this case, in the input register of the arithmetic unit, a pair of M and S instructions is determined and set up in the order of M and S instructions, regardless of the order in which the instructions are decoded. Regardless of the presence or absence of the S instruction, the execution control of the arithmetic unit of the M instruction is performed using the same control as the execution of instructions that use the arithmetic unit alone, and the compatibility with instructions with long execution cycles such as firmware is different. Never.

In this way, by executing instructions that do not use an arithmetic unit, such as a load instruction or a store instruction 2-intermediate instruction, in parallel with instructions that use other arithmetic units, the execution cycle of the instruction can be reduced to an apparent 0. It can be done. This speeds up instruction processing. In addition, by limiting the pairs of instructions that are executed in parallel to instructions that use arithmetic units and transfer-type basic instructions, the execution of instructions that use arithmetic units can be executed by microprograms in the same way as when parallel execution is not performed. This is done under the control of As a result, the amount of hardware for controlling parallel execution does not particularly increase. Additionally, an execution control mode that does not involve parallel execution can be easily set up.

The present invention has been specifically described above based on examples.
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

As described above, according to the present invention, load instructions and store instructions that do not use an arithmetic unit.

By executing instructions such as branch instructions in parallel with instructions that use other arithmetic units, instruction execution speed is increased.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an information processing device according to an embodiment of the present invention.
・・X instruction register, 4 ・・Y instruction register, 5 ・
General-purpose register group, 6... Instruction parallelism determination circuit, 7...
Operand control circuit, 8. Control storage device, 9. Arithmetic unit, 10. Control storage address register, 11.
Control storage data register, 12...A input register,
13...B input register, 14...output register,
20.21.22.23...Selector.

Claims (1)

[Claims] 1. An instruction decoder that decodes multiple instructions in an instruction sequence in parallel, an arithmetic unit, a data path that bypasses the arithmetic unit and sends the lower bits of the operation input register to the lower bits of the operation output register, and the instruction decoder. an instruction control unit that determines an instruction decoded by the processor, and uses the data path to execute an instruction that does not use an arithmetic unit in parallel with an instruction that uses an arithmetic unit when executing an instruction that uses an arithmetic unit; An information processing device comprising: