JPH0218732B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a microprogram-controlled information processing device, and more particularly to an information processing device in which the number of microinstruction steps is shortened by advance control.

[Prior art]

A microprogram-controlled information processing device is programmed with a set of microinstructions that specify the basic operations of the processing device, stores this in a control storage device, and sequentially reads and executes the microinstructions to control the operations of the processing device. Realize. A microprogram control unit for realizing machine language instructions of a processing device is mainly composed of three parts. That is, as follows.

(1) Read machine language instructions from main memory.

(2) Decipher the read machine language instructions.

(3) Execute the decoded machine language instructions.

In (2), there is a process of decoding the machine language instruction and branching to the microinstruction execution routine corresponding to each instruction, and in (3), after calculating the address of the operand description section common to each instruction, the operation section There is a process that performs the following.

Machine language instructions are prepared to perform efficient processing depending on their use and purpose, and here, as shown in FIG. 1, examples of two formats are shown.

In both formats 1 and 2, the attributes of the operands differ depending on the operation code part, and the operands are divided into register contents, contents calculated by registers and displacement, or contents of the main storage device. Format 1 differs from Format 2 in that the first operand is implicitly determined to be the contents of a specific register or the contents of the main memory indicated by the register. This example is an instruction that performs an operation on the first and second operands. Format 1 is a branch instruction, and format 2 is for an instruction in which operand description part 2 uses the result of register and displacement operations as an address. In this example, the contents of the storage device are designated as the second operand, and the operand description part 1 is designated as the contents of the register, which is designated as the first operand.

A time chart of the operation flow of a microinstruction that implements Format 2 machine language instructions with one arithmetic unit is shown below.
It is shown in FIGS. 2 and 3. Figure 2 shows the processing of a machine language instruction: read IF of the machine language instruction, decoding D of the read machine language instruction, address calculation A of the contents shown in operand description part 2, read OF of the second operand, and IF of the read machine language instruction. This is an operation flow in which operation E of the second operand is repeatedly performed. In this operation flow, address calculation A, operation between operands E
Otherwise, the arithmetic unit is not operating.

Fig. 3 shows an improved version of this method that enables high-speed processing. FIG. 3 shows the operation flow of a microinstruction in which three machine language instructions are processed at the same time with two machine cycles shifted, thereby making it possible to efficiently read out the main memory and use the arithmetic unit. In order to achieve this, the hardware needs at least three instruction registers to store machine language instructions, and after decoding machine language instructions, to perform operations between the previously read machine language operands. This requires an arithmetic storage control circuit.

As is clear from FIG. 3, the processing time for three instructions is reduced from 15 machine cycles to 10 machine cycles. If the information processing device that operates according to the operational flow shown in FIG. 3 uses a format 1 branch instruction, it operates according to the operational flow shown in FIG. 4. That is, if the second read machine language instruction is a branch instruction, the third read instruction must not be executed and the program must continue from the branch destination machine language instruction. This causes a disturbance in the operational flow and reduces the processing speed of calculations.

When one arithmetic unit is operated optimally, Format 2
If you execute this machine language instruction n times in succession, it should take 2n machine cycles. However, as shown in FIG. 3, a conventional information processing device using one arithmetic unit takes 2n+4 machine cycles when executing Format 2 machine language instructions n times in succession. The information processing device could not be operated optimally.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing apparatus capable of solving such conventional problems and operating one arithmetic unit optimally to improve processing efficiency.

[Summary of the invention]

In order to achieve the above object, an information processing device of the present invention includes a single arithmetic unit, a plurality of instruction registers that store a plurality of instructions successively read from a main memory, and a In a microprogram-controlled information processing device that is equipped with a decoder for decoding and a decoder for address calculation and performs advance control, a plurality of instructions successively read from the main memory are separately selected, and each of the instructions is The address of the operand is controlled by a plurality of first selectors sent to either the decoder for decoding or the decoder for address calculation, and the contents of the address calculation advance control designation field in the microinstruction read from the control memory. A second selector selects whether or not to send the output control signal of the address calculation decoder to the arithmetic unit in order to perform the calculation, and a second selector that sets the address calculation result of the operand in the program counter at the time of a branch instruction. A feature of the present invention is that it is equipped with a branch instruction selection decoder that controls the branch instruction selection decoder.

[Embodiments of the invention]

An embodiment of the present invention will be described below.

FIG. 5 is an operation flowchart of a microinstruction of the Format 2 machine language instruction, and FIG. 6 is a schematic configuration diagram of the hardware of the present invention that implements this microinstruction. FIG. 5 is an operational flow in which two instructions are processed simultaneously with a shift of one machine cycle.

In the present invention, (i) when executing the Format 2 instruction, decoding D of the operation code and address calculation A of the operand description part are performed on the same machine.
By executing in parallel in cycles, one instruction can be executed in four
(ii) When executing Format 1 (that is, a branch instruction), address calculation A of the operand description section is performed before decoding D, and the main memory of the branch destination is By calculating the address first, it is possible to read the branch destination instruction in the next machine cycle and execute it in one machine cycle less time than if there were no branch.

In FIG. 6, 1 is a main memory, 2 and 3 are operation registers on the A side and B side, respectively, 4 is a memory address register, 5 is a program counter, 6 is a memory buffer register, 7, 8
are first and second instruction registers, respectively, 9 is a calculation selector, 10 is a selector for machine language instruction decoding, 11 is an address calculation decoder, 12 is a machine language instruction decoder, 13 is an arithmetic unit, 14 is a microprogram addition circuit, 15
16 is a microinstruction address selector, 16 is a microinstruction address register, 17 is a control storage device, 18 is a microinstruction register, 19 is a selector for arithmetic control signals, and 20 is a branch instruction selection decoder.

In FIG. 6, the decoding D shown in (i) above is
To execute address calculation A of the operand description section in parallel, select the second instruction read out of the two instructions held in instruction registers 7 and 8, and decode it. means 9 for controlling address calculation of the operand description section;
11 and 19, and control storage device 1.
An address calculation advance control designation field C is provided in the microinstruction read from 7 to control the selector 19. In addition, in order to shorten the steps for the branch instruction shown in (ii) above,
Furthermore, a branch instruction selection decoder 20 is newly provided,
The previously obtained address calculation result of the operand description part is controlled to be set in the program counter 5 without being set in the memory address register 4. This prevents processing speed from slowing down due to branch instructions, and is even faster than normal.
Reduces machine cycle processing.

The operation shown in FIG. 6 will be explained in detail.

Microinstruction reads machine language instruction (instruction 1
IF), program counter 5
Reads the instruction 1 corresponding to the main memory 1 from the main memory 1,
Set to instruction register 7.
Next, when the microinstruction specifies machine language instruction reading (IF of instruction 2), decoding D of instruction 1, and address calculation A of the operand description part of instruction 1, instruction register 8 is set for advance control.
The instruction 2 read from the main memory 1 is set to In addition, the instruction register 7 in which the instruction to be executed is currently set is selected by the selector 10, and based on this, a microinstruction address is created in order to branch to the first address of the microinstruction execution group of instruction 1. The operation code of instruction 1 is decoded by the decoder 12, and the output thereof is selected by the microinstruction address selector 15 and set in the microinstruction address register 16. Reference numerals 16, 17, and 18 constitute a microprogram control unit, which accesses the control storage device 17 using the contents of the microinstruction address register 16 as an address, reads out the microinstruction from the address area, and writes the microinstruction register 18 to the microinstruction register 18. Set to . The microinstruction set in the microinstruction register 18 has three special fields a, b, and c; one is field a, which specifies the address for reading the next microinstruction, and the other field is Field b outputs a control signal for executing an operation, and the last one is field C that specifies advance control of address calculation for the next instruction.

When the microinstruction is set in the microinstruction register 18, at the same time, the instruction register 7 in which instruction 1 was set is set to the selector 9.
is selected, decoded by the decoder 11 that specifies the operation register and operation contents, and outputs a control signal for calculating the address of the operand description section. At this time, the microinstruction specifies advance address calculation (A of instruction 2), and the selector 19 selects the arithmetic control signal as the output of the decoder 11.
Next, when the microinstruction specifies read operand (OF) of instruction 1 and address calculation A of the operand description section of instruction 2, the contents corresponding to address register 4, where the operand address of instruction 1 is set, are stored in main memory. It is read from the device 1 and set in the memory buffer register 6. In addition, the instruction register 8 in which the instruction 2 is set is selected by the selector 9, and the instruction register 8 is set to the instruction 2 as described above.
A control signal for performing address calculation A of the operand description portion of is output from the selector 19, and address calculation is performed. When the selector 9 specifies machine language instruction decoding D in the previous microinstruction, the instruction register 7 sets the machine language instruction read next.
Select.

Next, when the microinstruction specifies execution of operation E of instruction 1, operand reading (OF) of instruction 2, and decoding D of instruction 2, the selector 19 selects the operation control signal (b) output from the microinstruction register 18. )
and select the memory where the operand is set.
Buffer register 6 and register 2 perform an operation according to the operation code of instruction 1. Also,
The contents corresponding to the address register 4 to which the operand address of the instruction 2 is set are read from the main memory 1 and set in the memory buffer register 6. At the same time, instruction 2 is decoded D, and the first microinstruction of the microinstruction group corresponding to instruction 2 is set in the microinstruction register 18 as described above.

Next, when the microinstruction specifies reading of the next machine language instruction (IF of instruction 3) and execution of operation E of instruction 2, the microinstruction sets instruction 3 in the instruction register 7 as described above, and at the same time Operation control signal (b) output from the instruction register 18
is selected by the selector 19, and operation E of instruction 2 is performed. Repeat this operation below.

The time chart for repeating this operation is shown in the 7th
Shown in Figure b. In other words, Figure 7b shows the case where instructions of Format 2 are executed consecutively, and the total time to execute instructions 1 and 2 is 5 machine cycles, that is, 2n + 1 (n is the number of instructions) machine cycles. However, since the arithmetic unit 13 is not available for instruction 3,
It will be read out with a delay of 3 machine cycles, and the total time for instructions 1 to 3 will be 8 machine cycles, that is, 2n+2 machine cycles. However, if two computing units 13 are provided,
It can be executed in 2n machine cycles. As described above, according to this embodiment, by calculating the address of the operand description part using a microinstruction before decoding the operation code of the machine language instruction, the instruction of the Format 2 is executed n times in succession. So, 2n
It can be executed in machine cycle time and has the effect of increasing the efficiency of processing equipment.

Next, using the hardware of this example, format 1
The operation flow of a microinstruction that executes a machine language instruction is shown in FIG. 7a. The difference between FIG. 7a and FIG. 7b is that instruction 2 is a branch instruction, which disrupts the operational flow. What is unique to the branch instruction in the hardware that implements FIG. 7a is that the branch instruction selection decoder 20 shown in FIG. Rather than setting the address calculation result in memory address register 4, the program
This decoder 20 controls so that the counter 5 is set and the read operand is set in the instruction register 7. This allows the reduction in processing speed due to branch instructions to be kept to a minimum.

That is, as shown in FIG. 7a, branch instruction 2
If so, the total execution time of instructions 1 through 3 is 7 machine cycles, which is 2n+1 machine cycles.

〔Effect of the invention〕

According to the present invention, the address of the operand description part can be calculated before decoding the operation code of the machine language instruction and branching to the microinstruction group corresponding to the machine language instruction. Since a single arithmetic unit is used to perform memory access, register/memory operations can be performed n times in succession in approximately 2n machine cycles, which has the effect of speeding up the processing unit.

[Brief explanation of drawings]

Fig. 1 is a diagram showing examples of two formats of machine language instructions, Fig. 2 is a microinstruction operation flow diagram that realizes the format 2 machine language instruction in Fig. 1, and Fig. 3 is a diagram showing examples of two formats of machine language instructions. Improved microinstruction operation flow diagram, 4th
The figure is an operation flow diagram of a microinstruction that implements the Format 1 machine language instruction in Figure 1, Figures 5 and 7 are operation flow diagrams of a microinstruction that implements the present invention, and Figure 6 is an embodiment of the present invention. FIG. 1 is a schematic configuration diagram of an information processing device. 1: Main memory, 2: A-side register for calculation,
3: Operation B-side register, 4: Memory address register, 5: Program counter, 6: Memory buffer register, 7: Instruction register 1, 8: Instruction register 2, 9:
Selector for address calculation, 10: Selector for decoding machine language instructions, 11: Decoder for address calculation, 1
2: Decoder for decoding machine language instructions, 13: Arithmetic unit,
14: Microprogram addition circuit, 15: Microinstruction address selector, 16: Microinstruction address register, 17: Control storage device, 1
8: microinstruction register, 19: arithmetic control signal selector, 20: branch instruction selection decoder.

Claims (1)

[Claims] 1 Equipped with a single arithmetic unit, a plurality of instruction registers for storing a plurality of instructions successively read from the main memory, a decoder for decoding the read instructions, and a decoder for calculating addresses, In a microprogram-controlled information processing device that performs control, a plurality of instructions that are sequentially read out from a main memory are separately selected and sent to one of the instruction decoding decoder or address calculation decoder, respectively. The output control signal of the address calculation decoder is controlled by the first selector of , and the contents of the address calculation advance control designation field in the microinstruction read from the control memory to calculate the address of the operand. a second selecting whether or not to send the data to the arithmetic unit;
1. An information processing device comprising: a selector; and a branch instruction selection decoder for controlling the address calculation result of the operand to be set in a program counter at the time of a branch instruction.