JP2522564B2 - Programmable controller - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a programmable controller for sequence-controlling a load based on a preset program.

[Prior Art] Conventionally, in a programmable controller of this type, which performs sequence control of a load based on a preset program, instructions are reduced (Reduced Instruction).
The RISC architecture has been proposed as a method for executing high speed execution. Here, in the conventional RISC architecture, an arithmetic logic operation unit (hereinafter referred to as ALU) is used to calculate the effective data address. For example, in the case of an addition instruction, it is executed in 10 cycles as shown in FIG. You can do it. In other words, for an instruction (LOAD / STORE) that requires memory access that references data, the IF reads the instruction, the RF decodes the instruction, the ALU calculates the effective address of the data, and the MEM reads the data from the data memory. (Or write), WB is used to write to the register. Next, an instruction that does not refer to the data memory (for example, add / subtract logical operation instruction AD
In D), the instruction is read by IF, the instruction is decoded and the register is read by RF, the operation is executed by ALU, the dummy cycle is MEM, and the register is written by WB. So anyway
The execution cycle of IF, RF, ALU, MEM, and WB is single. Three NOP (non-operation) instructions are inserted after the two LOAD instructions here because it is necessary to wait until the data necessary for the next ADD instruction is written in the register. That is, the RF cycle of the ADD instruction can be executed after the data read by the second LOAD instruction is written in the register. In the case of a general-purpose RISC computer, it is common to insert an instruction that can be executed after the next instruction first instead of this NOP to reduce the execution time, but the problem is that the compiler design becomes complicated. There is. Also, there may be no instruction that can be inserted instead of NOP depending on the combination of instructions. The three NOPs between the ADD instruction and the STORE instruction are also inserted for the same reason. Therefore, in the worst case, the instruction execution cycle is
You will need 10 cycles.

[Problems to be Solved by the Invention] In the above-described conventional example, many NOPs are included in the instruction execution cycle, which unnecessarily increases the instruction execution cycle, resulting in an inefficient instruction execution cycle. There was a problem that it would end up.

The present invention has been made in view of the above points, and an object thereof is to eliminate useless NOP cycles to reduce execution cycles, improve pipeline efficiency, and achieve high-speed execution. It is to provide a programmable controller that can.

[Means for Solving the Problems] A programmable controller according to the present invention calculates contact data of a data memory based on a program memory in which a program for sequence-controlling a load is stored and an instruction of the program read from the program memory. A RISC arithmetic processor which is provided with an arithmetic processor for processing, sequentially executes basic instructions and application instructions of the program to control the load, and uses the RISC arithmetic processor as the arithmetic processor to reduce application instructions to arithmetic processing. Pipeline processing by using the RISC arithmetic processor and general-purpose register group, arithmetic logic unit (ALU)
In the programmable controller formed using the ALU input register and the ALU output register, tag information indicating at which stage in the pipeline processing the contents of the data stored in the general-purpose register group is added to the data of each general-purpose register. In addition to this, a feedback path from the ALU output register to the ALU input register and a path from the data bus directly to the ALU input register are provided as a data bus.

[Operation] The present invention is configured as described above. The RISC arithmetic processor executes application instructions reduced in size by pipeline processing to control the load in sequence.
In a programmable controller that is a RISC processor that is composed of a general-purpose register group, an arithmetic and logic unit (ALU), and an ALU input register and an ALU output register, the contents of the data stored in the general-purpose register group are undergoing pipeline processing. In addition to adding tag information that indicates at which stage the data is in each general-purpose register, a feedback path from the ALU output register to the ALU input register and a path from the data bus directly to the ALU input register are provided as a data bus. It is possible to eliminate unnecessary NOP cycles, reduce the number of execution cycles, improve pipeline efficiency, and achieve high-speed execution.

[Embodiment] FIG. 1 shows an embodiment of the present invention, in which a program memory 1 in which a program for sequence-controlling a load is stored, a data memory 2 in which data is stored, and a program memory 1 read out. RISC arithmetic processor 3 for arithmetically processing data in the data memory 2 based on the instruction code of the program, and a main controller for fetching contact data, writing the contact data into the data memory 2, controlling the RISC arithmetic processor 3 and the like. In the programmable controller including 8 and prefetching the instruction code and pipeline processing, the data bus 4a of the program memory 1 and the data bus 4b of the data memory 2 are separately provided, and both memories 1 and 2 are provided. Address buses 5a and 5b are also provided separately to read instruction codes, set addresses, and Process is what was to be executed in parallel. In the figure, 6 is a control bus and 7 is an interface. Here, in the embodiment, the program memory 1 is composed of a source instruction memory 1a for storing a source instruction (CISC type) and a RISC instruction memory 1b for storing a RISC instruction. Only the instruction code of the multi-bit operation is taken out from it, reconstructed into the RISC instruction code and written in the RISC instruction memory 1b. Also, the basic instruction set (reduced instruction set) of the RISC processor 3 is defined so that the instruction execution cycles are the same, and the instruction code is reconfigured.
The source instruction memory 1a stores source instructions (CISC type), and the RISC instruction memory 1a stores reduced instructions (RISC type).

FIG. 2 is a block circuit diagram showing the configuration of the RISC arithmetic processor, which includes an ALU 10, a bit arithmetic processing unit 11,
It is composed of a dedicated data address generator 12 and a controller 13 including a decoder, a timing generator and a program counter. M ₁ ~M ₄ multiplexer, R ₁ ~Rn general purpose registers, R ₁₀ is an input buffer register, R _11, R ₁₂ is ALU input registers, R ₁₃ is an output buffer register, R ₁₄ is an instruction register, R ₁₅ is ALU It is an output register. The bit operation unit 11 executes a sequence basic instruction, and various construction methods are conceivable. However, since it is not directly related to the present invention, it is simplified and shown as a block. Further, the internal structures of the dedicated data address generator 12 and the controller 13 are not directly related to the present invention and are therefore simplified and shown in blocks.

In the embodiment, as well as additional tag information indicating whether the contents of data stored in the general-purpose register R ₁ ~Rn is in any stage of the pipeline process on the data of each general register R ₁ ~Rn, data As a bus, ALU output register R ₁₅
To ALU input registers R ₁₁ and R ₁₂ feedback path C
And a direct input path B from the data bus 4b directly to the AL input registers R ₁₁ and R ₁₂ . FIG. 3 shows a storage unit (several bits) for storing tag information corresponding to register data provided in the general-purpose registers R _{1 to} Rn, and FIG. 4 shows tags showing the data contents of the general-purpose registers R _{1 to} Rn. It has a register scoreboard SB that stores information collectively.

The operation of the embodiment will be described below. FIG. 5 shows an execution procedure of an addition instruction (ADD instruction) according to the present invention. First, data is read from the data memory 2 into the general-purpose register R ₁ and then from the data memory 2 into the general-purpose register R ₂ . Read the data. The processing up to this point is the same as in the conventional example. Next, in order to execute the ADD instruction, it is necessary that data be prepared in the general-purpose register before the RF cycle. Therefore, in the present invention, the ALU
Set data in input registers R ₁₁ and R ₁₂ .

i) The data in general-purpose register R ₁ is the input buffer register.
Since in the R ₁₀ can be seen by the information in the tag register in the WB cycle, stores the contents of the input buffer register R ₁₀ directly ALU input registers R ₁₁ via the path A.

ii) The data in the general-purpose register R ₂ is stored in the ALU input register R ₁₂ directly from the data bus 4b via the path B because it is known from the information of the register tag that the memory cycle is in progress.

iii) Furthermore, when writing the operation result to the data memory, the ALU output is directly stored in the output buffer register.
In this case, general-purpose register R ₃
Stores the data via path C since it is known to be in the ALU cycle.

As described above, during the register read cycle (RF or ADRS), the information of the register tag is used to: i) read from normal general-purpose registers R _{1 to} Rn; general-purpose register → ALU input register or output buffer register ii ) ALU10 output read, ALU output → ALU input register or output buffer register iii) Direct reading of data on data bus 4b, and data bus → ALU input register or output buffer register three types of data read control are possible . As a result, the add instruction (ADD instruction) can be executed in four execution cycles.

At this time, needless to say, it is necessary to define a data flow between each cycle so that pipeline processing can be performed consistently. That is, in the same cycle, the storage from the input buffer in the WB cycle to the general-purpose register must be performed at a timing earlier than that from the general-purpose register in the RF cycle to the ALU input register. Similarly, the storage from the general-purpose register to the ALU input register in the RF cycle must be performed earlier than the storage from the data memory to the input buffer register in the MEM cycle. As a result, the data reading control by the register tag is performed without contradiction.

In the embodiment, since the dedicated data address generator 12 is provided, the data address can be calculated in parallel while the ALU 10 is operating. Therefore, two types of application instructions (memory reference instruction, memory non-reference instruction) The NOP can be reduced, the basic execution cycle can be reduced, and the pipeline efficiency can be increased, enabling high-speed execution.

[Advantages of the Invention] The present invention is configured as described above. The RISC arithmetic processor executes application instructions that have been reduced in size by pipeline processing to sequence control the load.
In a programmable controller that is a RISC processor that is composed of a general-purpose register group, an arithmetic and logic unit (ALU), and an ALU input register and an ALU output register, the contents of the data stored in the general-purpose register group are undergoing pipeline processing. In addition to adding tag information that indicates at which stage the data is in each general-purpose register, a feedback path from the ALU output register to the ALU input register and a path from the data bus directly to the ALU input register are provided as a data bus. Therefore, there is an effect that wasteful NOP cycles can be removed to reduce the number of execution cycles, the pipeline efficiency can be improved, and high-speed execution can be achieved.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of an embodiment of the present invention, FIG. 2 is a block circuit diagram of essential parts of the same, FIGS. 3 to 5 are operation explanatory diagrams of the same, and FIG. 6 is an operation explanatory diagram of a conventional example. Is. 1 is program memory, 2 is data memory, 3 is arithmetic processor, 4a is instruction data bus, 4b is data bus, 5a is instruction address bus, 5b is data address bus, 6 is control bus, 8 is main controller, 12 is It is a data address generator.

Claims (1)

(57) [Claims] 1. A program memory, which stores a program for sequence-controlling a load, and an arithmetic processor, which arithmetically processes contact data of a data memory based on an instruction of the program read from the program memory,
The basic instructions and the application instructions of the program are sequentially executed so that the load is sequence-controlled, and pipeline processing is performed using the RISC arithmetic processor that reduces the application instructions to the arithmetic processing as the arithmetic processor,
The RISC arithmetic processor has a general-purpose register group, an arithmetic logic unit (ALU), an ALU input register, and an ALU.
In a programmable controller formed using output registers, tag information indicating at which stage in the pipeline processing the contents of the data stored in the general-purpose register group is added to the data of each general-purpose register, and as a data bus A programmable controller characterized by providing a feedback path from the ALU output register to the ALU input register and a path from the data bus directly to the ALU input register.