JP2988965B2 - Pipeline information processing circuit - Google Patents

Description

The present invention relates to a pipeline information processing circuit that performs data processing by a pipeline processing method.

(Prior art) In recent years, RISC (Reduced Insruction Set Computer)
Processor is becoming popular. A feature of the RISC processor is that processing is performed in a pipeline.

An example of a typical RISC instruction execution pipeline will be described. FIG. 4 is a block diagram of a conventional pipeline information processing circuit.

This pipeline information processing circuit includes an instruction fetch (F
Stage), decode (D stage), process execution (E stage), and write-back to register file 31 (W stage).

Source data read from the register file 31 in the D stage is latched in the input registers 35a and 35b of the arithmetic unit 33 at the end of this stage. The operation result is output to the output register 37 at the end of the E stage, and the operation result is written back to the register file 31 at the end of the W stage.

In addition, the output of the arithmetic unit 33 and the data from the output register 37 are bypassed one by one via the data buses 301 and 303. This bypass is controlled by the bypass control unit 39. FIG. 5 is a block diagram of the bypass control unit 39.

The processing of the bypass controller 39 will be described with reference to the timing chart shown in FIG.

In the execution flow 1, in the D stage, the input registers 35a, 35
b, the data of the register numbers F0 and F1 are read, and the operation result performed in the E stage is stored in the register file 31 in the W stage.
Write back to register number F2. In the execution flow 2, the data of the register number F2 is read into the input register 35a,
The data of the register number F3 in the register file 31 is read into the input register 35b. Then, the operation result is written back to the register number F4 in the register file 31.

When reading the data of the register number F2 in the execution flow 2, one data of the register number F2 of the E stage of the execution flow 1 is bypassed to the input register 35a via the data bus 301. At this time, the registers 41E and 41W hold register numbers (hereinafter, referred to as target register numbers) in the register file 31 in which the operation results of the execution flow 1 are written back. The target register number 305 of the E stage held in the register 41E is compared with the register number 307 of the data to be latched in the D stage of the execution flow 2 by the comparator 43.

Both target register number 305 and register number 307
Since it is F2, the match signal 309 is output from the priority determination unit 45.
Output to Priority judgment unit 45 and selector
By 47, the bypass data 301 of the E stage is selected and bypassed to the input register 35a.

As described above, when data having the same register number exists in the current pipeline, the processing can be started in the execution flow 2 before the operation result of the execution flow 1 is written back to the register file 31.

On the other hand, the configurations of the arithmetic unit 33, the input registers 35a and 35b, and the output register 37 are as shown in FIGS. 7 (A) and 7 (B).

FIG. 7A shows a case where a plurality of data are processed collectively, and FIG. 7B shows a case where one data read into each of the input registers 35a and 35b is processed. ing. Japanese Patent Application Laid-Open No. 64-14636 discloses an example of the arithmetic unit 33 for processing a plurality of data at once.

The arithmetic unit 33 used in the conventional pipeline information processing circuit can only process one data at a time.

(Problem to be Solved by the Invention) In a conventional pipeline information processing circuit, when bypassing data, only one data can be transferred in one transfer. For this reason, a plurality of data cannot be processed collectively by the arithmetic unit. Also, a plurality of registers have to be accessed when data is supplied from a register file to an arithmetic unit or when an operation result is stored in a register file. As a result, there is a problem that the efficiency of the pipeline processing is low.

In order to solve this problem, when transferring a plurality of data at a high speed, there is a method of transmitting a plurality of data in parallel by increasing the number of data buses by using a register holding a target register number as a multi-bus port. However,
This method has the drawback that the circuit of the register becomes complicated, the number of bypasses increases, and the number of comparators increases in proportion to the number of data.

Therefore, the present invention has been made in view of such a conventional situation, and an object of the present invention is to allow a plurality of data to be simultaneously transferred, so that a plurality of data can be operated collectively. It is to provide a pipeline information processing circuit.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, a first invention of the present application provides a register control means for outputting a plurality of data held in a register at once, and a plurality of data Means for calculating the data in a batch, and comparing the operation result output from the operation means with the data output from the register control means, selecting data to be subjected to the next operation and selecting the operation means And a bypass control unit for performing a bypass transfer to the bypass control unit, wherein the bypass control unit holds, for each of the plurality of data input for the operation, a valid flag indicating whether or not the data is used for the operation. It is configured to have means.

Further, in the second invention of the present application, the bypass means further includes a comparing means for comparing a register number of an operation result of the operation means with a register number to be operated next time,
If the comparison result of the comparison means is the same register number and the valid flag indicates that the data is used for the calculation, the calculation result output from the calculation means is used as data to be subjected to the next calculation. And selecting means for selecting.

Further, the third invention of the present application provides a register file including a plurality of registers represented by register numbers for storing a plurality of data, and a first file and a second file having a plurality of fields that can independently receive single-precision data items. An output port having a plurality of fields each of which can independently output a single-precision data item, corresponding to each of the input ports and one of the fields of the first and second input ports, respectively; Independent arithmetic operations are performed on the single-precision data item input from the corresponding field of the input port and the single-precision data item input as operation result data from the corresponding field of the second input port. Accordingly, a plurality of single precision arithmetic operations can be performed in parallel, and the operation result data is stored in the plurality of output ports of the output port. And a plurality of fields connected to the output port of the calculator and the register file, and each of the plurality of fields of the output port corresponding to one of the plurality of fields. An output register configured to store the operation result data, transferring the operation result data to a register file as write-back data, connected to the register file, the operation unit, and the output register;
A bypass control unit that supplies a plurality of selectors, wherein the plurality of selectors are configured to store the operation result data and the write-back data in at least the field of the output port or at least the field of the output register. From one of the first and second input ports of the computing unit, by-passing and transferring the data in the register file from the register file to the one of the computing unit. It is configured to transfer to any of the fields of the first and second input ports without bypassing.

Further, in the fourth invention of the present application, the arithmetic unit is configured to include a plurality of independent portions that can independently perform the first arithmetic operation and the second arithmetic operation.

Further, in the fifth invention of the present application, the bypass control unit may further include, from a field of an output port, a register number of a register storing a calculation result of the arithmetic unit transferred to the output register, or a field of the output register. The register number of the register in which the previous operation result of the operation unit is transferred to the register file, and the operand is used therefrom for the next operation of the operation unit, but is not actually obtained yet. It is configured to have a comparator for comparing the input data with the register number of the register.

Further, in the sixth invention of the present application, each of the selectors may be configured such that a register number of a register storing an operation result in the arithmetic unit is a register number of a register from which an operand is obtained for a next arithmetic operation in the arithmetic unit. If the same as the register number, in parallel with another selector transferring a data item from one register to one of the fields of the first and second input ports, the operation result in the operation unit is It is configured so that it can be directly transferred to one of the fields of the first and second input ports of the arithmetic unit.

Further, in the seventh invention of the present application, the bypass control unit further includes, when the comparison result indicates a match for each register number, an operand selected as the operation result data among the register numbers. It is configured to have a priority determiner for deciding to use the write-back data as the next highest priority, use the write-back data as the next highest priority, and use the data received from the register file as the third highest priority. ing.

Also, the eighth invention of the present application is directed to a fetch stage for fetching an instruction, a decode stage for decoding and loading the instruction, an execution stage for executing the instruction, and writing back data based on the execution of the instruction to a register file. A write-back stage, at least four pipeline stages, the data is latched at an input port of the arithmetic unit at a decode stage, and operation result data is output from an output port of the arithmetic unit to an output register at an execution stage. The write-back data is transferred from the output register to the register file in the write-back stage, and the plurality of selectors determine the register number required by the instruction acquired in the fetch stage and at least the The operation result received from the output port Data, and a register number corresponding to any one of the register numbers corresponding to the write-back data received from the output register. In order to use the data as the register number data of the fetch stage, the operation result data received from the output port of the arithmetic unit has priority over the write-back data received from the output register. If none of the register numbers corresponding to the write-back data and the register numbers corresponding to the operation result data respectively received from the fetch stage match the register numbers required by the instruction acquired in the fetch stage, The register number data used by the stage is selected from the register file. It is configured to.

Further, in a ninth invention of the present application, the bypass control unit includes:
Further, it is configured to have storage means for storing a valid flag indicating whether each of the operation result data transferred from the output port of the logic device and the write-back data transferred from the output register is valid. ing.

(Operation) In the above configuration, the present invention uses a comparator to compare the register number of the result calculated by the calculator with the register number of the data to be calculated next time. In the comparison result, when these register numbers are the same register number and the valid flag held in the valid flag holding means indicates that the valid flag was used in the current calculation, the result of the current calculation is The data is selected as the data to be calculated next time, and is bypass-transferred to the calculating means.

However, if the comparison result indicates that the register number is not the same register number or that the valid flag is not used in the current operation, the register with the register number of the data to be operated next time Are selected as data to be calculated next time and output to the calculating means.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of one embodiment of a pipeline information processing circuit of the present invention.

The pipeline information processing circuit shown in the figure includes an F (instruction fetch) stage, a D (instruction decode) stage,
(Process execution) stage and W (write back) stage are performed in four stages of pipeline processing.

This pipeline information processing circuit includes an instruction supplier 1, a bypass controller 3, a register file 5, selectors 7a to 7
d, an arithmetic unit 9, an input data register A, an input data register B, and an output data register 11. The output of the arithmetic unit 9 is provided with bypasses 101 and 103, and the output data register 11 is provided with bypasses 105 and 107, which are connected to the selectors 7a to 7d.

The arithmetic unit 9 also has an input data register A
And a second input port for the input data register B. Further, the arithmetic unit 9 is provided with an output port for the output data register 11.

The instruction supplier 1 sends the operation instruction signal 109 to the operation unit 9 at the D stage of each cycle, and outputs the target register number 111,
The high-side valid flag 113a, the low-side valid flag 113b, and the output data register numbers 115a and 115b are
And output data register numbers 115a and 115b to the register file 5.

The bypass control unit 3, which is the center of the present invention, will compare the register number of data to be operated next time with the register number of data currently on the pipeline, as will be described in detail later. Further, based on the comparison result, the bypass control unit 3 determines whether the data on the pipeline should be bypassed and used as data to be calculated next time,
Alternatively, selector control signals 117a to 117d indicating whether to use data in the register file 5 are given to the selectors 7a to 7d. The bypass control unit 3 also stores the register number 119 for writing to the register file 5 and the valid flags 121a and 121b of the W stage data in the register file 5.
Output to

According to selector control signals 117a to 117d provided from the bypass control unit 3, the selectors 7a to 7d perform data bypassed from the arithmetic unit 9 via the bypasses 101 and 103, and data bypassed from the output data register 11 via the bypasses 105 and 107. , Or one of the data in the register file 5. Further, the selectors 7a to 7d transfer the selected selection data 123a to 123d to the input data register A or the input data register B.

The register file 5 is a file composed of a plurality of registers, and a register number is added to each register. This register file 5 has a three-port configuration having an output port 5A, an output port 5B, and an input port 5C. The register width and each port width are 64 bits.
(Double precision). All 64 bits are used to hold double-precision data in each register constituting the register file 5, and higher order (high side) is used to hold single-precision data.
It has a function of dividing into 32 bits and lower (low side) 32 bits and holding them. The width of the data bus connected to the output port 5A, output port 5B and input port 5C is 64
bit. Data buses 108a to 108d connected to the output ports 5A and 5B are input to the selectors 7a to 7d.

Arithmetic unit 9 operates on data supplied from input data register A and input data register B, and outputs the operation result to output data register 11. The arithmetic unit 9 has a function of performing two single-precision (32-bit) operations, double-precision (64-bit) operations, and two single-precision operations simultaneously (hereinafter, referred to as a single-precision double-speed operation).

The arithmetic unit 9, the input data register A, the input data register B, and the output data register 11 have the configuration shown in FIG. 7 (B). The input data register A, the input data register B, and the output data register 11 are 64 bi
t, 32 bits for high side and 32 bits for low side
Is divided into

The single-precision double-speed operation performs an operation on the high-side data (32 bits) of the input data register A and the high-side data (32 bits) of the input data register B. At the same time, the low side data (32 bits) of the input data register A and the low side data (32 bits) of the input data register B are operated. Then, the operation result of the high side of the input data is output to the high side of the output data register 11, and the operation result of the low side of the input data is output to the low side of the output data register 11. I have.

Data is latched to the input data registers A and B at the D stage of the pipeline, and is latched to the output data register 11 at the E stage.

FIG. 2 shows a detailed block diagram of the bypass control unit 3.

The bypass control unit 3 shown in FIG.
Registers 15a to 15d, comparators 17a to 17d, AND circuits 19a to 19h
And priority determiners 21a to 21d. The selectors 7a to 7d are the selectors shown in FIG.
These are the same as 7a to 7d.

Register 13E is an input data register A for the E stage.
Alternatively, it is a register for holding a target register number corresponding to a processing result of the data stored in the input data register B. The register 13W is a register that holds a target register number corresponding to the data stored in the output data register 11 of the W stage.

The registers 15a and 15b are provided for the data register of the E stage, the high side (32 bits) and the low side (32 bits) of the data.
Is a register for holding a valid flag of the data. Similarly, the registers 15c and 15d are registers for holding high-side and low-side data valid flags of the data stored in the output data register 11 of the W stage. The valid flag is high
A valid bit is set on the side used in the operation between the side data and the low side data.

The registers 13E and 13W and the registers 15a to 15d are E and W
Each stage holds a target register number and a data valid flag flowing through the pipeline in the same manner as the processing data. Each register latches at the end of each stage.

The comparators 17a to 17d compare the register number of the register file 5 of the input data used in the next operation sent from the instruction supplier 1 during the D stage with the target register number of the data currently on the pipeline. It has a function to compare. Thus, the comparators 17a to 17d determine whether the data currently on the pipeline is data to be used in the next operation.

The comparator 17a compares the register number 115a of the source data to the input data register A with the target register number 125E of the E stage. Comparator 17b
Compares the register number 115b of the source data to the input data register B with the target register number 125E. Similarly, the comparators 17c and 17d compare the target register number 125W with the register number 115a or 115b.

AND circuits 19a to 19h output a match signal 1 from comparators 17a to 17d.
This is where the logical product of 27a to 127d and the data valid flags 129a to 129d is obtained. That is, the AND circuits 19a to 19h
When the register number of the register file 5 matches the target register number of the data currently on the pipeline, it is further determined whether or not the data on the high side or the low side is used. For example, the AND circuit 19a calculates the logical product of the coincidence signal 127a from the comparator 17a and the high-side data valid flag 129a of the E stage. If this result is valid, it means that the bypass condition for bypassing the E-stage data to the input data register A on the high side has been satisfied. The AND circuit 19h calculates the logical product of the match signal 127d and the low-side data valid flag 129d of the W stage. If this result is valid, the W stage data
This means that the bypass condition for bypassing the low side to the input data register B is satisfied.

Further, the AND circuits 19a to 19h output a bypass request signal 131a to 131h indicating whether or not the condition has been satisfied to a priority determination unit.
Send to 21a-21d.

The priority determiners 21a to 21d output a bypass request signal
Data in the register file 5 based on 131a to 131h,
The priority of three data, that is, the data of the E stage currently on the pipeline and the data of the W stage currently on the pipeline is to be determined. The priority is such that the data in the E stage is the highest, the data in the W stage is the next highest, and the data in the register file 5 is the lowest. Further, the priority determiners 21a to 21d select the selectors 7a to 7d in order to select one of the three data based on the determination result.
And selector control signals 117a to 117d.

For example, if the bypass request signal 131a from the E stage is valid, the priority determiner 21a outputs to the selector 7a a selector control signal 117a for preferentially selecting the high-side bypass data 101 of the E stage. However, if the bypass request signal 131a is invalid and the bypass request signal 131e from the W stage is valid, the selector control signal 117a for selecting the high side bypass data 105 of the W stage is output. Further, when the bypass request signals 131a and 131e are both invalid, a selector control signal for causing the data 108a in the register file 5 to be selected.
Outputs 117a. Similarly, the other priority determiners 21b to 21d output selector control signals 117b to 117d based on the determined priority to the selectors 7b to 7d.

The selectors 7a to 7d select one of the data in the register file 5, the data of the E stage, and the data of the W stage according to the selector control signals 117a to 117d. Further, the selectors 7a to 7d send the selected data 123a to 123d to the input data register A or the input data register B. For example, the selector 7a receives the read data from the output port 5A of the register file 5 according to the selector control signal 117a.
high side data 108a, E stage high side data 101, W
One of the high side data 105 of the stage is selected. Then, the selected data 123a is transmitted to the high side of the input data register A. Similarly, selectors 7b to
7d stores the selected data 123b to 123d in the input data register A.
The signal is sent to the low side, the high side of the input data register B, and the low side of the input data register B, respectively.

Thus, the pipeline information processing circuit of the present invention is configured, and an execution example of the bypass will be described next.

As an execution example, execution flow 1 currently in the pipeline
Then, register number F2 to be stored in E stage by single precision operation
Flow 2 for performing single-precision double-speed operation with data
Then, an example will be described in which an operation is performed using the data stored in the register numbers F2 and F3 as a source, and the operation result is written back to the register number F4 of the register file 11. At this time, in execution flow 2, a case is considered where the data of register number F2 is used in input data register A. It is assumed that the instruction before execution flow 1 is NOP.

 FIG. 3 shows a timing chart of this execution example.

In the figure, the upper timing chart shows an execution flow 1 for performing a single-precision operation, and the lower timing chart shows an execution flow 2 for performing a single-precision double-speed operation. Each timing chart is divided into F, D, E, and W stages. Data 201 to 207 are high-side data of the input data register A and data of the input data register A, respectively.
low side data, high side data of input data register B,
And low-side data of the input data register B. Data 209 and 211 represent high-side data and low-side data of the E stage, and data 213 and 215 represent high-side data and low-side data of the W stage. further,
These timing charts show that the low-side data 211 of the register number F2 of the E stage in the execution flow 1 is bypassed to the low side of the D stage in the execution flow 2.

When performing such a bypass, the register number F2 of the input data register A of the execution flow 2 is sent from the instruction supplier 1 to the register number 115a of the bypass control circuit 3. Similarly, the register number F3 of the input data register B is sent to the register number 115b. In the next stage, the instruction supplier 1 transfers the register number F4 as the target register number 111 latched in the E stage of the bypass controller 3.

As the data valid flags 113a and 113b of the output data,
Since the operation of execution flow 2 is a single-precision double-speed operation,
A valid signal is sent to both sides.

The execution flow 1 has already been stored in the register 13E of the E stage.
The target register number F2, which is the result of the operation described above, is held. Further, since the execution flow 1 is a single-precision operation only on the low side, a valid bit is set only in the register 15b.

In such a state, first, the register number 115a and the target register number 125E of the E stage are
Compared by 17a. Since the register number 115a and the target register number 125E are both F2, the comparator 17a
Output a match signal 127a indicating validity to the AND circuits 19a and 19b.

At the same time, comparisons by the comparators 17b to 17d are performed. Since register number 115b is F3, comparator 17b
The match signal 127b output to the AND circuits 19c and 19d is invalidated. Further, since the W stage is a NOP, the comparator 17
The match signals 127c and 127d output from c and 17d are also invalidated.

Next, the coincidence signal 127a is ANDed with the data valid flag 129a or 129b by the AND circuits 19a and 19b. Since only the low-side data valid flag 129b of the data valid flags 129a and 129b is valid, the result of the logical product in the AND circuit 19b is valid, but the result of the logical product in the AND circuit 19a is invalid. As a result, a bypass request signal 131a indicating invalidity is output from the AND circuit 19a to the priority determining unit 21a, and a bypass request signal 131b indicating validity is output from the AND circuit 19b to the priority determining unit 21b.

Since the match signals 127b to 127d output from the comparators 17b to 17d are all invalid, the bypass request signals 131c to 131h output from the AND circuits 19c to 19h are all invalid.

The priority determiners 21a to 21d determine the priority of the data based on the bypass request signals 131a to 131h. Since both the bypass request signals 131a and 131e are invalid, the priority determiner 21a determines that the priority of the data in the register file 5 is the highest. Further, a selector control signal 117a for selecting the data 108a in the register file 5 is output from the priority determiner 21a to the selector 7a. Since the bypass request signal 131b is valid, the priority determiner 21b preferentially determines that the low-side data of the E stage is the highest. As a result, the selector control signal 117b for selecting the low bypass data 103 of the E stage is output to the selector 7b.

Also, since the bypass request signals 131c, 131g, 131d, and 131h are all invalid, the selectors for allowing the priority determiners 21c and 21d to select the data 108c and 108d in the register file 5 similarly to the priority determiner 21a. Control signals 117c and 117d are output to selectors 7c and 7d.

By the selector 7a that receives the selector control signal 117a,
The high-side data 108a of the register number F2 read from the output port 5A of the register file 5 is selected. Further, the selector 7a sends the selection data 123a to the high side of the input data register A. In the selector 7b, the E-stage low-side bypass data 103 is selected by the selector control signal 117b, and the selected data 123b is sent to the low side of the input data register A.

In the selectors 7c and 7d, the high-side data 10 of the register number F3 read from the output port 5B of the register file 5
8c, low side data 108d is selected. Then, the selection data 123c and 123d are sent to the high side and the low side of the input data register B.

By the selection data 123a to 123d being sent, the data bypassed from the output port A of the register file 5 to the high side of the input data register A of the execution flow 2 and the data bypassed from the low side of the E stage to the low side. The latched data is latched. The input data register B latches read data from the output port 5B of the register file 5 on both the high side and the low side.

As described above, the bypass is performed by the bypass control circuit 3.

On the other hand, at the end of the pipeline processing, data is written back to each register in the register file 5. On this occasion,
Which register in the register file 5 is to be written back is determined by the target register number 125W (119 in FIG. 1) of the W stage, the high-side and low-side valid flags 129c and 129.
It is determined with reference to d (121a, 121b in FIG. 1). In the execution flow 1, only the low side is operated, so the contents of the register of the register number F2 are held as they are on the high side,
The low side is written back to the new data calculated in execution flow 1.

As described above, the bypass control unit 3 controls the high side and the low side.
Side data can be bypassed at the same time.

[Effect of the Invention] According to the pipeline information processing circuit of the present invention, only when the register numbers match and the data is used for the operation, the operation result is sent to the operation unit as the data to be operated next time. Added bypass transfer. As a result, a plurality of data can be simultaneously transferred by bypass with a slight increase in the number of circuits, and a plurality of data can be collectively operated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a pipeline information processing circuit of the present invention, FIG. 2 is a block diagram showing one embodiment of a bypass control unit and a selector shown in FIG.
The figure is a timing chart showing one embodiment of the pipeline processing by the pipeline information processing circuit of the present invention,
4 and 5 are block diagrams showing a conventional pipeline information processing circuit, a bypass control unit and a selector, FIG. 6 is a timing chart showing pipeline processing of the conventional pipeline information processing circuit, and FIG. FIG. 5 is a model diagram of the arithmetic unit shown in FIGS. 1 and 4. 3 ... Bypass control unit 5 ... Register files 7a-7d ... Selector 9 ... Calculator A, B ... Input data register 11 ... Output data register 13E, 13W, 15a-15d ... Registers 17a-17d ... … Comparator 19a ～ 19h …… AND circuit 21a ～ 21d …… Priority decision unit

────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Masato Nagamatsu 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba Research Institute (72) Inventor Junji Mori 1 shareholder, Komukai-Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Inside Toshiba Research Institute, Inc. (72) Inventor Toshi Yamazaki 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki City, Kanagawa Prefecture Inside Toshiba Research Institute, Inc. (56) References 108632 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 7/00 G06F 9/38 310

Claims (9)

(57) [Claims] 1. A register control means for outputting a plurality of data held in a register at once, an operation means for operating a plurality of data collectively, an operation result output from the operation means, and the register control Means for comparing data output from the means, selecting data to be subjected to the next calculation, and bypass-transferring the data to the calculation means, wherein the bypass control means is input for calculation. A pipeline information processing circuit, comprising: valid flag holding means for holding, for each of a plurality of data, a valid flag indicating whether or not the data is used for calculation. 2. The comparison device according to claim 1, wherein said bypass control means further compares the register number of the operation result of said operation means with a register number to be operated next time. And selecting means for selecting the calculation result output from the calculating means as data to be calculated next time, when the valid flag indicates that the data is used for calculation. The pipeline information processing circuit according to claim 1, wherein 3. A first and a second input port each having a register file including a plurality of registers represented by register numbers storing a plurality of data, and a plurality of fields each capable of independently receiving a single-precision data item. Corresponding to one of the fields of the first and second input ports, respectively, and an output port having a plurality of fields each capable of independently outputting a single precision data item; and a correspondence of the first input port By performing independent arithmetic operations on the single-precision data item input from the corresponding field and the single-precision data item input as operation result data from the corresponding field of the second input port, parallel operations are performed. To perform a plurality of single precision arithmetic operations, and the operation result data is stored in a plurality of fields of the output port. A computing unit for supplying the computing unit, the computing unit having a plurality of fields connected to the output port and the register file of the computing unit, and each of the computations from the plurality of fields of the output port corresponding to one of the plurality of fields. An output register configured to store result data and transferring the operation result data to a register file as write-back data; anda plurality of selectors connected to the register file, the operation unit, and the output register. A bypass control unit for supplying the operation result data and the write-back data, at least one of the fields of the output port or at least one of the fields of the output register. From one of them, to one of the fields of the first and second input ports of the computing unit Transferring the data in the register file from the register file to any of the fields of the first and second input ports of the arithmetic unit without bypassing the pipeline. Information processing circuit. 4. The pipe according to claim 3, wherein said arithmetic unit comprises a plurality of independent portions capable of independently performing a first arithmetic operation and a second arithmetic operation. Line information processing circuit. 5. The bypass control unit further transfers, from a field of an output port, a register number of a register in which an operation result of a computing unit to be transferred to an output register is stored, or a register file from a field of an output register. The register number of the register in which the previous operation result of the operation unit is stored, and the operand from which the operand is used for the next operation of the operation unit, 4. The pipeline information processing circuit according to claim 3, wherein a comparator for comparing a register number with a register number is provided. 6. The selector according to claim 1, wherein a register number of a register storing an operation result in said operation unit is equal to a register number of a register from which an operand is obtained for a next operation in said operation unit. In the case, in parallel with another selector transferring a data item from one register to one of the fields of the first and second input ports, the operation result in the arithmetic unit is The pipeline information processing circuit according to claim 5, wherein the data can be directly transferred to one of the fields of the first and second input ports. 7. The bypass control unit further, when the comparison result indicates a match for each register number, among the register numbers, an operand selected as the operation result data has the highest priority. And a priority determiner for deciding to use the write-back data as the next highest priority and to use the data received from the register file as the third highest priority. 5) The pipeline information processing circuit according to the above. 8. A fetch stage for fetching instructions,
A decoding stage for decoding and loading the instruction, an execution stage for executing the instruction, and a write-back stage for writing back data based on the execution of the instruction to a register file; and Data is latched at an input port of the arithmetic unit at a decode stage, and operation result data is transferred from an output port of the arithmetic unit to an output register at an execution stage.
The write-back data is transferred from an output register to a register file in a write-back stage, and the plurality of selectors register numbers required by an instruction acquired in a fetch stage, and at least, from the output port of the arithmetic unit. A priority number determiner for determining a match with a register number corresponding to the received operation result data and a register number corresponding to the write-back data received from the output register; If this occurs, the operation result data received from the output port of the arithmetic unit takes precedence over the write-back data received from the output register so that it can be used as the register number data of the fetch stage. Each received from the output port of the container If neither the register number corresponding to the data nor the register number corresponding to the operation result data matches the register number required by the instruction acquired in the fetch stage, the register number used by the fetch stage 6. The pipeline information processing circuit according to claim 5, wherein said data is selected from a register file. 9. The bypass control unit further includes a validity flag indicating whether each of the operation result data transferred from the output port of the logic device and the write-back data transferred from the output register is valid. The pipeline information processing circuit according to claim 3, further comprising storage means for storing.