JPH0233173B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention particularly relates to an arithmetic control device that controls arithmetic operations in an information processing device.

Generally, a processor of an information processing device executes operations according to instruction codes fetched from a storage device. Generally, operations are performed regardless of the state of the data, such as whether the data to be operated on is a positive number, a negative number, or an overflow number. If you want to change the process depending on the state of the data, first execute an instruction to check the state of the data, and then execute a conditional branch instruction that branches depending on the state. This conditional branch realizes processing branching.

For example, when executing "A+|B|", first determine whether B is positive or negative, and if B is positive, "A+
If B is negative, it is necessary to branch to a routine that executes A-B.

Further, for example, an example in which "if the calculation data A read from the storage device is equal to the constant "T", the constant "S" is added thereto; if they are not equal, the calculation data A is output as is" will be described below.

In this case, first, the calculation data A
Execute the Load instruction to load into the input register.

Next, a COMPARE instruction is executed to compare the calculated data A with the constant "T".

Next, a conditional branch instruction is executed to jump if the comparison results do not match.

Finally, if there is no branching, an ADD instruction is executed to add the constant "S" to the operation data A.

Thus, the above example requires four instructions to execute.

In conventional arithmetic control methods, there is no information indicating the state of the data itself, but there are flags (for example, sign flag, carry flag, parity flag, etc.) that indicate the state after computation, and these flags can be referred to. A conditional branch is being executed. However, this flag is typically reset each time the instruction is executed, independent of the previous state. Therefore, an instruction that refers to this flag must be executed after the flag is set by the desired instruction and before the flag is changed by another instruction.

In this way, in conventional arithmetic control methods, when processing differs depending on the state of the data, the overhead required for state judgment and conditional branching that refers to it occupies more than the processing that is actually performed on the data. It has the disadvantage that the ratio becomes quite large.

An object of the present invention is to provide an arithmetic and control device that can reduce the overhead required for conditional branching.

The arithmetic control device of the present invention includes a storage means for storing data including arithmetic data and a state variable associated with the data, and an instruction code of an instruction to be executed and the state variable of the data to be operated. an instruction decoding means for specifying an arithmetic process for the arithmetic data of data; an arithmetic unit for executing an arithmetic process for the arithmetic data of the data to be operated based on the arithmetic process specified by the means; generating means for generating a state variable to be attached to the operation result from the operation unit in response to the operation state of the operation unit; and means for storing the operation result and the state variable attached to the result in the storage means. It is characterized by being prepared. That is, the arithmetic control device of the present invention is an information processing device in which a computation is performed using an instruction code and duplicated data to be operated on, in which a group of flags for arithmetic control, that is, a group of flags with state variables added to the computed data, is provided. Equipped with a storage device for storing data, the processing to be performed by the arithmetic unit is determined based on the instruction code and a group of flags read from the storage device, and after the arithmetic processing, the group of flags modified according to the calculation result is converted into the calculation output data. is configured to be appended to and written to the storage device.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, and is a schematic block diagram of an arithmetic and control device in which the state variable is one bit, and FIG. FIG. 3 is a state variable explanatory diagram for explaining the operating conditions of the state variable generation circuit in the arithmetic and control device.

In the embodiment shown in FIG. 1, the instruction includes an instruction code and a state variable designation code for generating a state variable output.

The arithmetic control device shown in FIG. 1 includes an arithmetic unit 1 for performing binary operations, an instruction decoder 2, a state variable generation circuit 3, a storage device 14, an instruction register 4, input registers 5 and 6, Output buffer 7 and
It is configured to include an address generation circuit 8, a multiplexer 9, control signal lines 10-13, and buses 100-117.

In Figure 2a, the operation to be executed is determined by the result of the exclusive OR of the instruction code OPC and the two input state variables C _A and C _B (for the JUMP instruction, the state variable of input register 5). It is shown that. FIG. 2b shows the calculation result X output from the calculation unit 1 after the calculation determined in FIG. 2a is executed.

Also, Figure 3 shows the state variable output generated by the state variable specification code SC and the state of the calculation result X.
This shows that C _X is determined.

The operation of the arithmetic and control device shown in FIG. 1 will be explained below.

When an instruction is executed, data read from the storage device 14 and placed on the data bus 114 is first latched into the instruction register 4, input registers 5 and 6 via the buses 101, 102, and 103.

In other words, the instruction code is stored in instruction register 4.
An instruction including OPC and a state variable designation code SC is stored, and input registers 5 and 6 store state variables C _A and C _B and operation data A and B, respectively.
The state variables C _A and C _B are read out from the storage device 14 (or other registers) in pairs with the calculation data A and B.

The instruction code OPC and two state variables C _A and C _B are:
The commands are input to the instruction decoder 2 via buses 104, 105, and 106, respectively. These three types of parameters determine the processing instructions for the arithmetic unit 1 and the control for the address generation circuit 8 under the conditions shown in FIG. 2a.

First, the arithmetic unit 1 receives a processing instruction determined under the conditions shown in FIG. Tsute bus 110 and 11
The calculation result X is output to 1. State variable generation circuit 3
generates a state variable _C X to be output based on the calculation result X, the overflow signal V output from the arithmetic unit 1, and the state variable designation code SC input via the bus 109. The generation condition is the third
As shown in the figure. The operation result
Driven by 14. In the case of a COMP instruction, the operation data A on the bus 116 is input to the output buffer 7. This switching signal for multiplexer 9 is generated by instruction decoder 2.

On the other hand, the control signal 11 output from the instruction decoder 2 is input to the address generation circuit 8 and controls the program counter. That is, the control signal 11
After the operation is completed, it is determined whether the program counter is incremented or set to the branch destination address.

The above operation will be explained using two simple examples.

As a first example, “If the calculation data A read from the storage device is “T”, add “S””
Let's take up the operation. The instructions listed in Figure 2a shall be used.

First, execute the LOAD instruction, read out the operation data A from the storage device 14, and input "T" into the input register 5 via the data bus.
latch on. In addition, the state variables C _A at this time,
C _B may be either "1" or "0".

Next, the COMPARE instruction compares the operation data A stored in the input register 5 with "T" stored in the input register 6.
The operation of the COMPARE instruction is to subtract the contents of input register 5 and input register 6 in the arithmetic unit.
The contents of the input register 5 (bus 117) and the modified state variable (signal line 112) are outputted to the output buffer 7 via the multiplexer 9, and then relatched to the input register 5. At this time, the state variable specification code SC is specified as "101". In other words, if the operation result X obtained by executing the COMPARE instruction is equal to "0", the state variable output C _X is set to "0", otherwise it is set to "1".
and relatches the result to input register 5. As a result, only the state variables of input register 5 are changed.

Next, execute the ADD instruction. Input register 6
"0" is set as the state variable C _B , and the calculation data B
Enter "S" as This ADD instruction compares two input state variables C _A and C _B , and if they are equal, performs addition, and if they are not equal, performs NOP. That is, if the state variable C _A obtained by executing the COMPARE instruction is "0", T+S is output as the operation result X, and if it is "1", the value of the input register 5 is output as is.

Thus, in the case of the first example, execution of three instructions is sufficient if the present invention is applied.

In the first example mentioned above, the process temporarily branches to execute either ADD or NOP depending on the value of calculation data A, but after execution, the same sequence will be executed again. . This is an operation
Other instructions combined with NOP (except JUMP)
The same is true for this, and the conventional branch operation using a conditional branch instruction is no longer necessary.

By the way, the comparison between the calculation data A and "1" has been performed in advance, and the comparison result is the state variable C _A
If the data has already been stored in the storage device 14 as (each address in the storage device 14 stores a pair of calculation data and a state variable, and is addressed at the same time), the data will be loaded immediately.
ADD command can be executed. That is,
Since the state of the computed data is stored in memory as a state variable, the COMPARE instruction is no longer necessary. State variables are regenerated when all operations are executed, not just the COMPARE instruction, so if you store the state variables generated as a result of some operation in the storage device along with the data, you can save them. The state can be retrieved at any time and used for other operations. Conventionally, this was only temporarily stored as the state after the calculation.

Next, the operation of a conditional branch instruction will be explained.

As shown in FIGS. 2a and 2b, whether or not to branch is determined by the value of the state variable C _A of the input register 5. That is, a signal indicating success or failure of the branch is generated based on the instruction code OPC and state variable _CA input to the instruction decoder 2, and is output as the control signal 11 to the address generation circuit 8.
In response to this, the address generation circuit 8 controls the value of the program counter.

Next, as a second example, the case of "branching to address "Z" if an overflow occurs as a result of addition" will be described.

First, execute the ADD instruction with the state variable specification code SC set to "111". At this time, the state variable output _C

Next, the conditional branch instruction “JUMP (OPC=0110)”
The success or failure of the branch is determined by the instruction code of and the value of the state variable C _A stored in the input register 5. In this case, the sequence of "operation" → "conditional branch" is essentially the same as the conventional method. However, as in the first example described above, the calculation result
When the data and state variable output _C This was not possible with conventional methods.

Although one embodiment of the present invention has been described above, it is clear that by using a plurality of bits as a state variable and expanding the state variable specification code, it becomes possible to perform even more diverse conditional operations. In cases where processing differs depending on the state of data, the present invention makes it possible to omit conditional branching, reduce the setting of conditional determiners, and shorten processing time. Therefore, the performance of the information processing device can be significantly improved.

By adding a state variable generation circuit, the arithmetic control device of the present invention writes the generated state variables as a pair with the calculation data in the storage device, and calculates the calculation data according to the instruction code and the state variable during calculation. Since the conditional branching operation and the arithmetic operation can be integrated and processed with one instruction, the overhead required for the conditional branching can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
Figures 2a and b are operation explanatory diagrams for explaining the operation of the arithmetic unit shown in Figure 1, and Figure 3 is a state variable explanatory diagram for explaining the operation of the state variable generation circuit shown in Figure 1. be. 1... Arithmetic unit, 2... Instruction decoder, 3... State variable generation circuit, 4... Instruction register, 5, 6...
...Input register, 7...Output buffer, 8...Address generation circuit, 9...Multiplexer, 10-
12...Control signal, 14...Storage device, 100~
117...bus, OPC...instruction code, SC...
State variable specification code, A, B...calculation data, X
...Arithmetic results, C _A , C _B ...state variables, C _X ...state variable outputs.

Claims (1)

[Scope of Claims] 1. Storage means for storing data including operation data and state variables associated with the data, and the data to be calculated from the instruction code of the instruction to be executed and the state variables of the data to be calculated. an instruction decoding means for specifying an arithmetic process on the arithmetic data of the data to be operated on, an arithmetic unit that executes an arithmetic process on the arithmetic data of the data to be operated based on the arithmetic process specified by the means, and this arithmetic unit. generating means for generating a state variable to be attached to the operation result from the arithmetic unit in response to the operation state of the operation unit; and means for storing the operation result and the state variable attached to the result in the storage means. An arithmetic control device characterized by: 2. The patent to be characterized in that the instruction to be executed further includes a state variable designation code, and the generating means generates the state variable to be attached in response to the state variable designation code as well as the calculation state of the arithmetic unit. An arithmetic control circuit according to claim 1.