JPH0226252B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory content check control method, particularly a memory content check control method that enables checking of memory contents accurately and at low cost in a circuit having two or more memory ICs. It is related to.

As a conventional method for checking the contents of a memory, for example, there is a method that includes a memory for parity bits and performs a parity check for each address of the memory.

FIG. 1 shows an example of a conventional method. In the figure, 1 is a microprocessor, 2 is a first read-only memory (ROM), 3 is a second ROM, and 4 is a third ROM.
ROM, 5 is the nth ROM, 6 is the address bus,
7 represents a data bus, 8 a parity ROM, 9 a parity checker, and 10 a flip-flop. First ROM2, second ROM3,...
The n-th ROM 5 is composed of memory ICs each having a capacity of 2 Kbytes with 8 bits per byte, for example, and stores control programs for the microprocessor 1 and the like. Since there is no room to add a parity bit to each byte of these ROMs 2 to 5, one bit of parity ROM 8 is associated with each byte, and according to the contents of each byte of ROMs 2 to 5, even parity or parity is added. Each bit value of the parity ROM is set in advance at the stage when the contents of the ROMs 2 to 5 are determined to have odd parity. Check the memory contents from ROM2 to each address.
Contents of 1 byte of 5 and its corresponding parity
The 1-bit value of the ROM 8 is taken into the parity checker 9 and executed by the parity checker 9. If a parity error is detected, flip-flop 10 is set so that the parity check signal is turned on.

According to the conventional method described above, a parity ROM for parity bits and its peripheral circuits are required, which inevitably increases costs and also increases the cost of parity bits.
It takes time and effort to write to ROM.

Another conventional method is to add up the contents of the memory in order, for example, and compare the addition result with a preset value. That is, a check program and check data are stored in advance in a part of the memory, and the data in the memory is sequentially read and operated by the check program, and the results are compared with the check data to check the contents of the memory. This is a method to do so.

However, this method has the disadvantage that it cannot be correctly checked if the contents of the check program are corrupted, and it lacks accuracy.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks and to provide a method for checking memory contents accurately and at low cost. Therefore, the memory content check control method of the present invention is implemented by the microprocessor in a circuit including a microprocessor and a plurality of memories in which instructions fetched and executed by the microprocessor are stored. A check program for checking the normality of the memory contents is provided by storing it in two or more of the above-mentioned memories, and each of the above-mentioned check programs is executed respectively, and the check program read from one memory is used to check the normality of the memory contents. The present invention is characterized in that one memory is checked by a check program read from another memory, and the other memories are mutually checked. This will be explained below with reference to the drawings.

Figure 2 shows the configuration of one embodiment of the present invention, and Figure 3 shows the configuration of the second embodiment.
A time chart for explaining the operation of the illustrated embodiment is shown.

In the figure, numerals 1 to 7 correspond to those in FIG.
12 is a check program for checking the memory contents; 13 is an address decoder; 14 is an address decoder;
is a flip-flop, 15 is a selector, 16 is a
Represents the MPU reset signal line.

In Figure 2, the first ROM2, the second
The ROM 3, . . . , the n-th ROM 5 store control programs for the microprocessor 1, and the microprocessor 1 fetches and executes them and performs control according to their contents. In particular, the first
ROM2 includes, for example, second ROM3 to nth ROM3.
A check program 11 for checking the memory contents of the ROM 5 is stored.
A check program 12 for checking the memory contents of the first ROM 2 is stored in the ROM 3 . Both the check program 11 and the check program 12 have the same content as the conventional check program described above, and each consists of instructions of about several tens of steps, for example. Therefore, if a memory IC has a capacity of, for example, 2K bytes, the check program occupies a small proportion of it. Also, the first
The ROM 2 and the second ROM 3 store the check program 11 or the check program 12 as well as check data (not shown) for other memories, respectively.

When power is applied to the circuit shown in Figure 2, the microprocessor 1 enters the reset state (T shown in Figure 3).
1), then the reset is completed and the 3rd state is reached.
When the state T2 shown in the figure is reached, the microprocessor 1 specifies a certain specific address (vector address) and executes the program at the address specified by the vector address. This vector address is, for example, initially set to "0" by the flip-flop 14.
When , the first ROM2 is selected by the selector 15.
The check program 11 of the first ROM 2 is pointed to, and the check program 11 of the first ROM 2 is operated first.

Microprocessor 1 is check program 1
1, the data in the second ROM 3 to the n-th ROM 5 are sequentially calculated,
The calculation result is compared with check data that has been calculated in advance and is stored in the first ROM 2 and indicates a correct result. As a result of the comparison, if they match, it means that the memory contents of the second ROM 3 to n-th ROM 5 are correct. If the values do not match, it is determined that there is an error in the second ROM 3 to n-th ROM 5, and the error is detected.

When the execution of the check program 11 is completed, a reset circuit (not shown) operates, and a reset signal is supplied to the microprocessor 1 via the reset signal line 16, so that the microprocessor 1 enters the state shown in T3 in FIG. . Further, in response to this reset signal, the output of the flip-flop 14 is changed from "0" to "1" as shown in FIG. At the end of the reset, the microprocessor 1 points to the vector address and enters the state T4 shown in FIG.
Since 4 is "1", selector 1
5, the check program 12 in the second ROM 3 is pointed to, and the check program 12 is activated.

By executing the check program 12, the data in the first ROM 2 is sequentially calculated as in the case of executing the check program 11.
The calculation result and the check data in the second ROM 3 are compared, and the normality of the memory contents of the first ROM 2 is checked.

As mentioned above, the first ROM2 and the second ROM2
The check programs stored in the ROM 3 are themselves checked by other check programs, making it possible to check the memory contents more accurately.

In the above embodiment of the present invention, the check program to be executed is switched by the reset signal, but since it is sufficient that two or more check programs are executed alternately, the above-mentioned For example, the following may be used. Instead of a second reset, input a signal to the microprocessor's interrupt pin, etc., and transfer the branch destination address to other memory.
Leave it as IC. In this way, the check program in the memory IC is activated and the contents of the memory IC having the original vector address are checked. In this way, the flip-flop 14 and selector 15 shown in FIG. 2 are not required, so
Furthermore, it becomes possible to check the memory contents with simpler hardware.

As explained above, according to the present invention, a memory content check circuit can be realized at low cost without requiring memory for parity bits or its peripheral circuits, and even if the check program of one memory IC is corrupted. Even if the damaged memory IC cannot be checked correctly because of the broken memory IC, the damaged memory IC can be checked using the check program for other memory ICs, so it is possible to correctly check the contents of all memories.

[Brief explanation of drawings]

FIG. 1 shows an example of a conventional system, FIG. 2 shows the configuration of an embodiment of the present invention, and FIG. 3 shows a time chart for explaining the operation of the embodiment shown in FIG. 1 is a microprocessor, 2 to 5 are
ROM, 6 is address bus, 7 is data bus,
8 is parity ROM, 9 is parity checker,
10 is a flip-flop, 11 and 12 are check programs, 13 is an address decoder,
14 is a flip-flop, 15 is a selector, 1
6 represents a reset signal line.

Claims (1)

[Claims] 1. In a circuit having a microprocessor and a plurality of memories in which instructions fetched and executed by the microprocessor are stored, the normality check of the memory contents is executed by the microprocessor. The check programs to be performed are stored in two or more of the above-mentioned memories, and each of the above-mentioned check programs is executed respectively.
A check program read from one memory checks another memory, and a check program read from another memory checks the one memory, so that they mutually check the other memories. A memory content check control method characterized by: