JPH10164837A - Power supply - Google Patents

Power supply

Info

Publication number
JPH10164837A
JPH10164837A JP8315049A JP31504996A JPH10164837A JP H10164837 A JPH10164837 A JP H10164837A JP 8315049 A JP8315049 A JP 8315049A JP 31504996 A JP31504996 A JP 31504996A JP H10164837 A JPH10164837 A JP H10164837A
Authority
JP
Japan
Prior art keywords
mos
voltage
fet
power supply
coil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8315049A
Other languages
Japanese (ja)
Inventor
Akihiko Kikuchi
昭彦 菊池
Masanobu Takahama
昌信 高濱
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP8315049A priority Critical patent/JPH10164837A/en
Publication of JPH10164837A publication Critical patent/JPH10164837A/en
Pending legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

PROBLEM TO BE SOLVED: To significantly reduce loss by using MOS-FETs for secondary-side rectification. SOLUTION: The positive end of a direct current 100 obtained by rectifying an AC input is connected with the negative end through the collectors and emitters of switching transistors 1, 2. The middle point is connected with one end of the primary-side coil 5A of voltage changing transformer 5 through the coil 3A of a saturable reactor transformer 3 and a resonance capacitor 4. One and the other ends of the secondary-side coil 5B of the voltage changing transformer 5 are connected with each other through the sources and drains of N-channel MOS-FETs 19, 20, respectively. A capacitor 21 for smoothing is connected between the connecting point and the middle tap of the secondary- side coil 5B. The MOS-FETs 19, 20 are on/off-controlled by drive circuits 24, 25, respectively, and synchronously controlled, so that they will be on only when current flows from the capacitor 21 side to the coil 5B, for example.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、例えばAC入力を
整流したDCで駆動されるパーソナルコンピュータの電
源等に使用して好適な電源装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply device suitable for use as, for example, a power supply of a personal computer driven by DC obtained by rectifying an AC input.

【0002】[0002]

【従来の技術】例えばAC入力を整流したDCで駆動さ
れるパーソナルコンピュータの電源においては、内部で
必要な駆動電圧を得るために、いわゆるDC−DCコン
バータ等の電源装置が用いられている。すなわち図9に
は、そのような電源装置の一例の構成を示す。
2. Description of the Related Art For example, in a power supply of a personal computer driven by DC in which an AC input is rectified, a power supply device such as a so-called DC-DC converter is used in order to obtain a necessary driving voltage internally. That is, FIG. 9 shows a configuration of an example of such a power supply device.

【0003】この図9において、DC70の+端が、直
列に接続された2石のスイッチングトランジスタ71、
72のコレクタ・エミッタ間を通じてDC70の−端に
接続される。これらのトランジスタ71、72の中点が
過飽和リアクタトランス73のコイル3A、共振コンデ
ンサ74を通じて電圧変換トランス75の1次側コイル
5Aの一端に接続される。またこの1次側コイル5Aの
他端がDC70の−端に接続される。さらにトランジス
タ71、72の中点がコンデンサ76を通じてDC70
の−端に接続される。
In FIG. 9, the positive terminal of a DC 70 has two switching transistors 71 connected in series,
It is connected to the negative terminal of the DC 70 through the collector-emitter 72. The midpoint between these transistors 71 and 72 is connected to one end of the primary coil 5A of the voltage conversion transformer 75 through the coil 3A of the saturable reactor transformer 73 and the resonance capacitor 74. The other end of the primary coil 5A is connected to the negative end of DC 70. Further, the midpoint between the transistors 71 and 72 is
Is connected to the negative end of

【0004】また、トランジスタ71のコレクタが抵抗
器77を通じてトランジスタ71のベースに接続され、
このトランジスタ71のベースが順方向のツェナーダイ
オード78と逆方向のダイオード79の直列回路を通じ
てトランジスタ71のエミッタに接続される。さらにト
ランジスタ71のベースが抵抗器80、コンデンサ81
と、過飽和リアクタトランス73のコイル3B及びコン
デンサ82の並列回路との直列回路を通じてトランジス
タ71のエミッタに接続される。
Further, the collector of the transistor 71 is connected to the base of the transistor 71 through a resistor 77,
The base of the transistor 71 is connected to the emitter of the transistor 71 through a series circuit of a zener diode 78 in the forward direction and a diode 79 in the reverse direction. Further, the base of the transistor 71 is a resistor 80, a capacitor 81
Is connected to the emitter of the transistor 71 through a series circuit of a coil 3B of the saturable reactor transformer 73 and a parallel circuit of the capacitor 82.

【0005】さらにトランジスタ72のコレクタが抵抗
器83を通じてトランジスタ72のベースに接続され、
このトランジスタ72のベースが順方向のツェナーダイ
オード84と逆方向のダイオード85の直列回路を通じ
てトランジスタ72のエミッタに接続される。さらにト
ランジスタ72のベースが抵抗器86、コンデンサ87
と、過飽和リアクタトランス73のコイル3C及びコン
デンサ88の並列回路との直列回路を通じてトランジス
タ72のエミッタに接続される。
Further, the collector of the transistor 72 is connected to the base of the transistor 72 through a resistor 83,
The base of the transistor 72 is connected to the emitter of the transistor 72 through a series circuit of a zener diode 84 in the forward direction and a diode 85 in the reverse direction. Further, the base of the transistor 72 includes a resistor 86 and a capacitor 87.
Is connected to the emitter of the transistor 72 through a series circuit of a parallel circuit of the coil 3C of the saturable reactor transformer 73 and the capacitor 88.

【0006】また、上述の電圧変換トランス75の2次
側コイル5Bの一端及び他端が、それぞれ整流用の順方
向のダイオード89、90を通じて互いに接続される。
さらにこの接続点と2次側コイル5Bの中間タップとの
間に平滑用のコンデンサ91が接続される。そしてこの
コンデンサ91の両端から出力端子92の+端及び−端
が導出される。さらにこの出力端子92の+端がエラー
アンプ93を通じて過飽和リアクタトランス73の制御
コイル3Dに接続される。
[0006] One end and the other end of the secondary coil 5B of the voltage conversion transformer 75 are connected to each other through forward diodes 89 and 90 for rectification.
Further, a smoothing capacitor 91 is connected between the connection point and the intermediate tap of the secondary coil 5B. The positive terminal and the negative terminal of the output terminal 92 are led out from both ends of the capacitor 91. Further, the positive terminal of the output terminal 92 is connected to the control coil 3D of the saturable reactor transformer 73 through the error amplifier 93.

【0007】そしてこの装置において、上述のスイッチ
ングトランジスタ71、72が自励発振によって交互に
オンオフされることによって、電圧変換トランス75の
1次側コイル5Aには略正弦波の電流が流され、2次側
コイル5Bには所望の電圧が取り出される。さらにこの
取り出された電圧がダイオード89、90を通じて両波
整流され、整流された電圧がコンデンサ91で平滑され
て出力端子92に取り出される。
In this device, the switching transistors 71 and 72 are turned on and off alternately by self-excited oscillation, so that a substantially sine-wave current flows through the primary coil 5A of the voltage conversion transformer 75. A desired voltage is extracted from the secondary coil 5B. Further, the extracted voltage is subjected to double-wave rectification through diodes 89 and 90, and the rectified voltage is smoothed by a capacitor 91 and extracted to an output terminal 92.

【0008】また、出力端子92の+端に取り出された
電圧の、所望の電圧からの変動分がエラーアンプ93で
検出され、この変動分が過飽和リアクタトランス73の
制御コイル3Dに供給される。これによってこの過飽和
リアクタトランス73のコイル3A〜3Cに取り出され
る信号の波形が変化され、トランジスタ71、72のス
イッチング周波数が変化されて、出力端子92の+端に
取り出される電圧が所望の電圧に等しくなるように制御
が行われる。
[0008] Further, a variation from a desired voltage of the voltage taken out at the + terminal of the output terminal 92 is detected by the error amplifier 93, and the variation is supplied to the control coil 3 D of the saturable reactor transformer 73. As a result, the waveforms of the signals extracted to the coils 3A to 3C of the saturable reactor transformer 73 are changed, the switching frequencies of the transistors 71 and 72 are changed, and the voltage extracted to the positive terminal of the output terminal 92 is equal to the desired voltage. Control is performed so that

【0009】このようにして、上述の装置において、安
定化された所望の電圧を出力端子92に取り出すことが
できる。そしてこの取り出された電圧は、例えばDCで
駆動されるパーソナルコンピュータの電源として使用さ
れるものである。
Thus, in the above-described device, a stabilized desired voltage can be taken out to the output terminal 92. The extracted voltage is used as, for example, a power source of a personal computer driven by DC.

【0010】[0010]

【発明が解決しようとする課題】ところが上述の電源装
置において、電圧変換トランス75の2次側整流用のダ
イオード89、90の順方向降下電圧Vf によって損失
が発生する。すなわちこのようなダイオードの順方向降
下電圧Vf は、一般的0.45V程度であるが、この順
方向降下電圧Vf によって上述の装置では、 1.11×Io ×Vf 〔W〕 (但し、Io は出
力電流〔A〕) の損失が発生する。
However, in the power supply device described above, a loss occurs due to the forward drop voltage Vf of the diodes 89 and 90 for rectification on the secondary side of the voltage conversion transformer 75. That is, the forward drop voltage Vf of such a diode is generally about 0.45 V, and the forward drop voltage Vf causes the above-described device to be 1.11 × Io × Vf [W] (where Io is Output current [A]) is lost.

【0011】そしてこのような2次側整流用のダイオー
ド89、90による損失が、例えば出力電流Io が10
〔A〕では5〔W〕、20〔A〕では10〔W〕にもな
ってしまい、特にパーソナルコンピュータのように低電
圧、大電流が要求される電源では、出力に対する損失の
割合が大きくなってしまうものである。
The loss due to the secondary side rectifying diodes 89 and 90 is, for example, when the output current Io is 10
In [A], it becomes 5 [W], and in 20 [A], it becomes as much as 10 [W]. In particular, in a power supply requiring a low voltage and a large current such as a personal computer, the ratio of loss to output becomes large. It will be.

【0012】この出願はこのような点に鑑みて成された
ものであって、解決しようとする問題点は、従来の装置
では、特にパーソナルコンピュータのように低電圧、大
電流の電源が要求される場合に、2次側整流用ダイオー
ドの順方向降下電圧によって、出力に対する損失の割合
が大きくなってしまうというものである。
The present invention has been made in view of the above points, and the problem to be solved is that a conventional apparatus requires a power supply of a low voltage and a large current, particularly like a personal computer. In this case, the ratio of the loss to the output increases due to the forward drop voltage of the secondary-side rectifier diode.

【0013】[0013]

【課題を解決するための手段】このため本発明において
は、電圧変換用トランスの2次側整流としてMOS−F
ETを用いて同期整流を行うようにしたものであって、
これによれば、特に低オン抵抗のMOS−FETを用い
ることで、2次側整流での損失を大幅に減少させること
ができる。
Therefore, in the present invention, a MOS-F is used as a secondary rectifier of a voltage conversion transformer.
ET is used to perform synchronous rectification,
According to this, the loss due to rectification on the secondary side can be greatly reduced by using a MOS-FET having a low on-resistance.

【0014】[0014]

【発明の実施の形態】すなわち本発明においては、スイ
ッチング素子を2石用いたハーフブリッジ構成を有し、
2石のスイッチング素子の中点に共振コンデンサと電圧
変換用トランスが設けられると共に、電圧変換用トラン
スの2次側整流としてMOS−FETを用いて同期整流
を行うものである。以下、図面を参照して本発明を説明
するに、図1は本発明を適用した電源装置の一例の構成
を示すブロック図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS That is, the present invention has a half bridge configuration using two switching elements,
A resonance capacitor and a voltage conversion transformer are provided at the midpoint of the two switching elements, and synchronous rectification is performed using a MOS-FET as secondary rectification of the voltage conversion transformer. Hereinafter, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an example of a power supply device to which the present invention is applied.

【0015】この図1において、AC入力を整流したD
C100の+端が、直列に接続された2石のスイッチン
グトランジスタ1、2のコレクタ・エミッタ間を通じて
DC100の−端に接続される。これらのトランジスタ
1、2の中点が過飽和リアクタトランス3のコイル3
A、共振コンデンサ4を通じて電圧変換トランス5の1
次側コイル5Aの一端に接続される。またこの1次側コ
イル5Aの他端がDC100の−端に接続される。さら
にトランジスタ1、2の中点がコンデンサ6を通じてD
C100の−端に接続される。
In FIG. 1, D is obtained by rectifying the AC input.
The positive terminal of C100 is connected to the negative terminal of DC100 through the collector and emitter of two switching transistors 1, 2 connected in series. The middle point of these transistors 1 and 2 is the coil 3 of the supersaturated reactor transformer 3.
A, one of the voltage conversion transformers 5 through the resonance capacitor 4
It is connected to one end of the secondary coil 5A. The other end of the primary coil 5A is connected to the negative end of DC100. Further, the midpoint between the transistors 1 and 2 is
Connected to the minus end of C100.

【0016】また、トランジスタ1のコレクタが抵抗器
7を通じてトランジスタ1のベースに接続され、このト
ランジスタ1のベースが順方向のツェナーダイオード8
と逆方向のダイオード9の直列回路を通じてトランジス
タ1のエミッタに接続される。さらにトランジスタ1の
ベースが抵抗器10、コンデンサ11と、過飽和リアク
タトランス3のコイル3B及びコンデンサ12の並列回
路との直列回路を通じてトランジスタ1のエミッタに接
続される。
The collector of the transistor 1 is connected to the base of the transistor 1 through a resistor 7, and the base of the transistor 1 is connected to a zener diode 8 in the forward direction.
Is connected to the emitter of the transistor 1 through a series circuit of a diode 9 in the opposite direction. Further, the base of the transistor 1 is connected to the emitter of the transistor 1 through a series circuit of a resistor 10, a capacitor 11, and a parallel circuit of a coil 3B of the saturable reactor transformer 3 and a capacitor 12.

【0017】さらにトランジスタ2のコレクタが抵抗器
13を通じてトランジスタ2のベースに接続され、この
トランジスタ2のベースが順方向のツェナーダイオード
14と逆方向のダイオード15の直列回路を通じてトラ
ンジスタ2のエミッタに接続される。さらにトランジス
タ2のベースが抵抗器16、コンデンサ17と、過飽和
リアクタトランス3のコイル3C及びコンデンサ18の
並列回路との直列回路を通じてトランジスタ2のエミッ
タに接続される。
Further, the collector of the transistor 2 is connected to the base of the transistor 2 through a resistor 13, and the base of the transistor 2 is connected to the emitter of the transistor 2 through a series circuit of a forward Zener diode 14 and a reverse diode 15. You. Further, the base of the transistor 2 is connected to the emitter of the transistor 2 through a series circuit of the resistor 16 and the capacitor 17 and the parallel circuit of the coil 3C of the saturable reactor transformer 3 and the capacitor 18.

【0018】また、上述の電圧変換トランス5の2次側
コイル5Bの一端及び他端が、それぞれNチャンネルの
MOS−FET19、20のソース・ドレイン間を通じ
て互いに接続される。さらにこの接続点と2次側コイル
5Bの中間タップとの間に平滑用のコンデンサ21が接
続される。そしてこのコンデンサ21の両端から出力端
子22の+端及び−端が導出される。さらにこの出力端
子22の+端が制御回路23を通じて過飽和リアクタト
ランス3の制御コイル3Dに接続される。
One end and the other end of the secondary coil 5B of the voltage conversion transformer 5 are connected to each other through the source and drain of N-channel MOS-FETs 19 and 20, respectively. Further, a smoothing capacitor 21 is connected between the connection point and an intermediate tap of the secondary coil 5B. The positive terminal and the negative terminal of the output terminal 22 are led out from both ends of the capacitor 21. Further, the positive terminal of the output terminal 22 is connected to the control coil 3D of the saturable reactor transformer 3 through the control circuit 23.

【0019】そしてこの装置において、上述のスイッチ
ングトランジスタ1、2が自励発振によって交互にオン
オフされることによって、電圧変換トランス5の1次側
コイル5Aには略正弦波の電流が流され、2次側コイル
5Bには所望の電圧が取り出される。さらにこの取り出
された電圧が、MOS−FET19、20を通じて互い
に接続される。
In this device, the switching transistors 1 and 2 are alternately turned on and off by self-excited oscillation, so that a substantially sine-wave current flows through the primary coil 5A of the voltage conversion transformer 5, and A desired voltage is extracted from the secondary coil 5B. Further, the extracted voltages are connected to each other through MOS-FETs 19 and 20.

【0020】ここでこれらのMOS−FET19、20
はそれぞれ駆動回路24、25によってオンオフが制御
され、例えば図示の例ではコンデンサ21側からコイル
5Bに向かって電流が流れている期間にのみオンされる
ように同期制御される。これによって2次側コイル5B
に取り出された電圧が両波整流され、整流された電圧が
コンデンサ21で平滑されて出力端子22に取り出され
る。
Here, these MOS-FETs 19, 20
Are turned on and off by drive circuits 24 and 25, respectively. For example, in the example shown in the drawing, synchronous control is performed such that the transistor is turned on only during a period in which a current flows from the capacitor 21 toward the coil 5B. Thereby, the secondary coil 5B
Is rectified in both directions, and the rectified voltage is smoothed by the capacitor 21 and output to the output terminal 22.

【0021】また、出力端子22の+端に取り出された
電圧の、所望の電圧からの変動分が制御回路23で検出
され、この変動分が過飽和リアクタトランス3の制御コ
イル3Dに供給される。これによってこの過飽和リアク
タトランス3のコイル3A〜3Cに取り出される信号の
波形が変化され、トランジスタ1、2のスイッチング周
波数が変化されて、出力端子22の+端に取り出される
電圧が所望の電圧に等しくなるように制御が行われる。
The control circuit 23 detects a variation of the voltage taken out at the positive terminal of the output terminal 22 from the desired voltage, and supplies the variation to the control coil 3D of the supersaturated reactor transformer 3. As a result, the waveforms of the signals taken out to the coils 3A to 3C of the saturable reactor transformer 3 are changed, the switching frequency of the transistors 1 and 2 is changed, and the voltage taken out at the positive terminal of the output terminal 22 is equal to the desired voltage. Control is performed so that

【0022】このようにして、上述の装置において、安
定化された所望の電圧を出力端子22に取り出すことが
できる。さらにこの取り出された電圧は、例えばDCで
駆動されるパーソナルコンピュータの電源として使用さ
れるものである。
In this manner, in the above-described device, a desired stabilized voltage can be taken out to the output terminal 22. Further, the extracted voltage is used as a power source of a personal computer driven by, for example, DC.

【0023】そして上述の装置において、電圧変換トラ
ンス5の2次側の整流が、MOS−FET19、20の
それぞれ同期制御による同期整流によって行われてい
る。従ってこの場合には、2次側整流用のMOS−FE
T19、20のオン抵抗Ronによって損失が発生する。
In the above-described apparatus, rectification on the secondary side of the voltage conversion transformer 5 is performed by synchronous rectification by synchronous control of the MOS-FETs 19 and 20, respectively. Therefore, in this case, the MOS-FE for secondary side rectification is used.
Loss occurs due to the on-resistance Ron of T19 and T20.

【0024】すなわちこのようなオン抵抗Ronは、例え
ば低オン抵抗のMOS−FETでは7mΩ程度である。
そしてこのオン抵抗Ronによって上述の装置では、 1.11×Io ×1.11×Io ×Ron〔W〕 の損失が発生する。
That is, such an on-resistance Ron is about 7 mΩ for a low on-resistance MOS-FET, for example.
In the device described above, a loss of 1.11 × Io × 1.11 × Io × Ron [W] occurs due to the on-resistance Ron.

【0025】そしてこのような2次側整流用のMOS−
FET19、20による損失は、例えば出力電流Io が
10〔A〕では約0.86〔W〕、20〔A〕では約
3.45〔W〕に留めることができ、特にパーソナルコ
ンピュータのように低電圧、大電流が要求される電源
で、出力に対する損失の割合を大幅に削減することがで
きるものである。
The secondary side rectifying MOS-
The loss caused by the FETs 19 and 20 can be kept at about 0.86 [W] when the output current Io is 10 [A] and about 3.45 [W] when the output current Io is 20 [A], and particularly low as in a personal computer. It is a power supply that requires a large voltage and a large current, and can greatly reduce the ratio of loss to output.

【0026】すなわち図2において、直線Aは、従来の
2次側整流用の素子に例えば順方向降下電圧Vf =0.
45Vのダイオードを用いた場合の、電流〔A〕に対す
る損失〔W〕の発生の状況を示す。また、曲線Bは、2
次側整流用の素子に例えばオン抵抗Ron=7mΩのMO
S−FETを用いた場合の、電流〔A〕に対する損失
〔W〕の発生の状況を示している。
That is, in FIG. 2, a straight line A represents, for example, a forward drop voltage Vf = 0.
The situation in which a loss [W] with respect to a current [A] occurs when a 45 V diode is used is shown. Curve B is 2
For the element for rectification on the secondary side, for example, an MO having an on-resistance Ron = 7 mΩ
This shows a situation in which a loss [W] with respect to a current [A] occurs when an S-FET is used.

【0027】従ってこの装置において、電圧変換用トラ
ンスの2次側整流としてMOS−FETを用いて同期整
流を行うことによって、特に低オン抵抗のMOS−FE
Tを用いることで、2次側整流での損失を大幅に減少さ
せることができる。
Therefore, in this device, synchronous rectification is performed by using a MOS-FET as a secondary rectifier of the voltage conversion transformer, so that a MOS-FE having a low on-resistance can be obtained.
By using T, the loss in the secondary side rectification can be greatly reduced.

【0028】これによって、従来の装置では、2次側整
流用ダイオードの順方向降下電圧によって、出力に対す
る損失の割合が大きくなっていたものを、本発明によれ
ば、特にパーソナルコンピュータのように低電圧、大電
流の電源が要求される場合に、2次側整流での損失を大
幅に減少させ、効率の良いスイッチング電源を実現する
ことができるものである。
Thus, in the conventional device, the ratio of the loss to the output is increased due to the forward drop voltage of the secondary-side rectifier diode. When a power supply of a voltage and a large current is required, the loss in the secondary side rectification can be greatly reduced, and an efficient switching power supply can be realized.

【0029】ところで上述の装置において、2次側整流
素子は、本来は電圧変換用トランス5の2次側コイル5
Bから平滑用コンデンサ21を充電する方向のみに電流
を流さなければならない。ところが上述の装置におい
て、MOS−FETは、ゲートにオン電圧が印加される
とドレイン・ソース間は抵抗体と同等になるため、電流
は双方向に流れることができる。
In the above-described apparatus, the secondary-side rectifying element is originally a secondary-side coil 5 of the transformer 5 for voltage conversion.
A current must flow only in the direction from B to charge the smoothing capacitor 21. However, in the above-described device, when an ON-voltage is applied to the gate of the MOS-FET, the current between the drain and the source becomes equivalent to that of a resistor, so that current can flow in both directions.

【0030】従って上述の装置において、MOS−FE
Tのゲートにオン電圧を印加するタイミングを悪くする
と、コンデンサ21から2次側コイル5Bへ放電電流が
流れ、負荷側にエネルギーを有効に伝達できないばかり
か、逆電流によるMOS−FETの発熱やノイズの発
生、1次側スイッチング損失の増大にもつながる恐れが
ある。
Therefore, in the above device, the MOS-FE
If the timing of applying the on-voltage to the gate of T is deteriorated, a discharge current flows from the capacitor 21 to the secondary coil 5B, so that not only energy cannot be effectively transmitted to the load side, but also heat generation and noise of the MOS-FET due to the reverse current. This may lead to an increase in primary-side switching loss.

【0031】そこで、このようなMOS−FETのゲー
トにオン電圧を印加するタイミングを正確に制御するた
めに、例えば図3に示すような回路が用いられる。なお
以下の説明では、2次側整流用のMOS−FET19、
20の下側の片方の回路についてのみ示すが、上下両方
のMOS−FETについての回路構成、及びその作用動
作は同じである。
In order to accurately control the timing of applying the ON voltage to the gate of such a MOS-FET, for example, a circuit as shown in FIG. 3 is used. In the following description, the MOS-FET 19 for secondary rectification,
Although only one of the lower circuits 20 is shown, the circuit configuration and the operation of the upper and lower MOS-FETs are the same.

【0032】この図3において、MOS−FET20に
直列に電流検出用トランス31の1次側コイル31Aが
設けられる。そしてこの電流検出用トランス31の2次
側コイル31Bの両端間に検出用の抵抗器32が接続さ
れ、この抵抗器32の電圧がコンパレータ33で検出さ
れる。
In FIG. 3, a primary coil 31A of a current detecting transformer 31 is provided in series with the MOS-FET 20. A resistor 32 for detection is connected between both ends of the secondary coil 31B of the transformer 31 for current detection, and the voltage of the resistor 32 is detected by the comparator 33.

【0033】すなわち上述の抵抗器32の一端が電圧源
34に接続され、この電圧源34の電圧と抵抗器32の
他端の電圧がコンパレータ33で比較されて、他端の電
圧が所定値以上になったときに検出が行われる。そして
この検出信号がバッファ回路35を通じてMOS−FE
T20のゲートに供給される。
That is, one end of the resistor 32 is connected to a voltage source 34. The voltage of the voltage source 34 and the voltage of the other end of the resistor 32 are compared by a comparator 33, and the voltage of the other end is equal to or more than a predetermined value. Detection is performed when This detection signal is supplied to the MOS-FE through the buffer circuit 35.
It is supplied to the gate of T20.

【0034】従ってこの回路において、例えば上述の1
次側のトランジスタ1のコレクタ電流IC が、図4のA
に示すようであった場合には、電圧変換用トランス5の
2次側コイル5Bには図4のBの電圧が誘起される。そ
してこの電圧がコンデンサ21の充電電圧より大きくな
ると、MOS−FET20の寄生ダイオード20Aを通
じてコンデンサ21に充電電流が流される。
Therefore, in this circuit, for example,
The collector current I C of the transistor 1 on the next side is A
4, the voltage B in FIG. 4 is induced in the secondary coil 5B of the voltage conversion transformer 5. When this voltage becomes higher than the charging voltage of the capacitor 21, a charging current flows to the capacitor 21 through the parasitic diode 20A of the MOS-FET 20.

【0035】さらにこの充電電流が電流検出用トランス
31の1次側コイル31Aを流れることによって、2次
側コイル31Bには電圧が誘起される。そしてこの出力
電圧がコンパレータ33で検出され、この出力電圧が所
定値以上になると、即座にバッファ回路35を通じて例
えば図4のCに示すようなゲート電圧VgsがMOS−F
ET20に印加される。
Further, when the charging current flows through the primary coil 31A of the current detecting transformer 31, a voltage is induced in the secondary coil 31B. The output voltage is detected by the comparator 33, and when the output voltage becomes equal to or higher than a predetermined value, the gate voltage Vgs as shown in FIG.
Applied to ET20.

【0036】また、上述の充電電流が減少すると、コン
パレータ33の出力が反転され、バッファ回路35を通
じてMOS−FET20のゲート容量が放電されて、M
OS−FET20がオフされる。なおこの時点でコンデ
ンサ21の充電電流はゼロにはなっていないが、この電
流はMOS−FET20の寄生ダイオード20Aを通じ
て流される。
When the charge current decreases, the output of the comparator 33 is inverted, the gate capacitance of the MOS-FET 20 is discharged through the buffer circuit 35, and M
OS-FET 20 is turned off. At this point, the charging current of the capacitor 21 has not become zero, but this current flows through the parasitic diode 20A of the MOS-FET 20.

【0037】これによって、MOS−FET20には、
例えば図4のDに示すようなドレイン電流ID が流され
る。すなわちこのMOS−FET20は、コンデンサ2
1への充電電流が流れ始めた後でオンされ、充電電流が
ゼロになる前にオフされる。そしてこのMOS−FET
20がオンされている期間に、低オン抵抗を介して損失
の少ない充電が行われるものである。
Thus, the MOS-FET 20 has
For example the drain current I D as shown in D of FIG. 4 is flowed. That is, this MOS-FET 20 is
It is turned on after the charging current to 1 starts flowing, and turned off before the charging current becomes zero. And this MOS-FET
During the period when the switch 20 is turned on, charging with low loss is performed via the low on-resistance.

【0038】なお、上述のMOS−FET19において
も作用動作は全く同じに行われる。すなわち例えば図5
のA、Bに示すMOS−FET20の動作に反転した形
で、図5のC、Dに示すようにMOS−FET19の動
作が行われる。そしてこの場合も、MOS−FET19
は、コンデンサ21への充電電流が流れ始めた後でオン
され、充電電流がゼロになる前にオフされるものであ
る。
The operation of the MOS-FET 19 is exactly the same. That is, for example, FIG.
The operation of the MOS-FET 19 is performed as shown in FIGS. 5C and D in a form inverted from the operation of the MOS-FET 20 shown in FIGS. Also in this case, the MOS-FET 19
Is turned on after the charging current to the capacitor 21 starts flowing, and turned off before the charging current becomes zero.

【0039】従ってこの回路において、MOS−FET
は充電電流がゼロになる前にオフされるので、例えばタ
ーンオフのタイミングが遅れて逆電流が流されるような
ことがない。これにより、いかなる動作条件でもMOS
−FETのオン期間が充電電流の方向のみの電流だけ流
せるようにでき、逆電流の発生による不具合を解消する
ことができる。
Therefore, in this circuit, the MOS-FET
Is turned off before the charging current becomes zero, so that, for example, the turn-off timing is delayed and a reverse current does not flow. This allows the MOS to operate under any operating conditions.
-The ON period of the FET can flow only the current in the direction of the charging current, and the problem caused by the generation of the reverse current can be solved.

【0040】さらに図6、図7は、MOS−FETのゲ
ートにオン電圧を印加するタイミングを正確に制御する
ための回路の他の例を示す。すなわち図6は充電電流の
検出方法として検出抵抗41を用いる場合であって、こ
の検出抵抗41で検出された電圧をコンパレータ42で
電圧源43の電圧と比較し、この比較出力をバッファ回
路44を通じてMOS−FET20のゲートに印加して
いる。
FIGS. 6 and 7 show another example of a circuit for accurately controlling the timing of applying the ON voltage to the gate of the MOS-FET. That is, FIG. 6 shows a case where the detection resistor 41 is used as a method of detecting the charging current. The voltage detected by the detection resistor 41 is compared with the voltage of the voltage source 43 by the comparator 42, and the comparison output is supplied through the buffer circuit 44. The voltage is applied to the gate of the MOS-FET 20.

【0041】また、図7は検出抵抗としてMOS−FE
T20のオン抵抗を用いるものである。すなわちこの例
では、MOS−FET20のオン抵抗で検出された電圧
をコンパレータ51で電圧源52の電圧と比較し、この
比較出力をバッファ回路53を通じてMOS−FET2
0のゲートに印加している。なおこの図7の回路は、も
っとも損失が少なくなる構成である。
FIG. 7 shows a MOS-FE as a detection resistor.
The on-resistance of T20 is used. That is, in this example, the voltage detected by the on-resistance of the MOS-FET 20 is compared with the voltage of the voltage source 52 by the comparator 51, and this comparison output is output through the buffer circuit 53 to the MOS-FET 2.
0 is applied to the gate. The circuit shown in FIG. 7 has a configuration in which the loss is minimized.

【0042】こうして上述の電源装置によれば、スイッ
チング素子を2石用いたハーフブリッジ構成を有し、2
石のスイッチング素子の中点に共振コンデンサと電圧変
換用トランスが設けられると共に、電圧変換用トランス
の2次側整流としてMOS−FETを用いて同期整流を
行うことにより、2次側整流での損失を大幅に減少さ
せ、効率の良いスイッチング電源を実現することができ
るものである。
Thus, according to the power supply device described above, the power supply device has a half-bridge configuration using two switching elements,
A resonance capacitor and a voltage conversion transformer are provided at the middle point of the stone switching element, and synchronous rectification is performed by using a MOS-FET as the secondary rectification of the voltage conversion transformer, so that the loss in the secondary rectification is reduced. Can be greatly reduced, and an efficient switching power supply can be realized.

【0043】なお、上述の説明では、いずれも2次側整
流用のMOS−FET19、20を電圧変換トランス5
の2次側コイル5Bの−側に設ける場合について行った
が、例えば従来の装置で述べたダイオードのように+側
に設けても同様の作用効果を得ることができる。ただ
し、−側に設けた方がMOS−FETの駆動には適正で
ある。
In the above description, each of the secondary-side rectifying MOS-FETs 19 and 20 is connected to the voltage conversion transformer 5.
However, the same effect can be obtained by providing the diode on the + side as in the diode described in the conventional device. However, the provision on the negative side is more appropriate for driving the MOS-FET.

【0044】また、例えば図8に示すように1次側のス
イッチング素子が他励発振によってオンオフ駆動される
場合においても本発明を適用することができる。すなわ
ち図8においては、コントロール回路60からの制御信
号がドライブ回路61、62を通じてそれぞれスイッチ
ング素子63、64に供給され、これらのスイッチング
素子63、64がオンオフ駆動されて、上述の電圧変換
トランス5の1次側コイル5Aに略正弦波の電流が流さ
れる。
The present invention can also be applied to a case where the primary-side switching element is driven to be turned on and off by separately excited oscillation as shown in FIG. That is, in FIG. 8, the control signal from the control circuit 60 is supplied to the switching elements 63 and 64 through the drive circuits 61 and 62, respectively, and these switching elements 63 and 64 are driven on and off to drive the voltage conversion transformer 5 described above. A substantially sinusoidal current flows through the primary coil 5A.

【0045】さらにこの装置において、出力端子22の
+端に取り出された電圧の、所望の電圧からの変動分が
フィードバック回路65を通じてコントロール回路60
に供給され、これによってスイッチング素子63、64
のスイッチング周波数が変化されて、出力端子22の+
端に取り出される電圧が所望の電圧に等しくなるように
制御が行われる。
Further, in this device, the variation of the voltage taken out at the + terminal of the output terminal 22 from the desired voltage is supplied to the control circuit 60 through the feedback circuit 65.
And the switching elements 63, 64
Of the output terminal 22 is changed.
Control is performed so that the voltage taken out at the end is equal to the desired voltage.

【0046】そしてさらにこの装置においても、電圧変
換用トランスの2次側整流としてMOS−FETを用い
て同期整流を行うことによって、特に低オン抵抗のMO
S−FETを用いることで、2次側整流での損失を大幅
に減少させることができ、効率の良いスイッチング電源
を実現することができるものである。
Further, in this apparatus, synchronous rectification is performed by using a MOS-FET as secondary rectification of the voltage conversion transformer, so that a particularly low on-resistance MO is realized.
By using the S-FET, the loss in the secondary side rectification can be greatly reduced, and an efficient switching power supply can be realized.

【0047】[0047]

【発明の効果】この発明によれば、電圧変換用トランス
の2次側整流としてMOS−FETを用いて同期整流を
行うことによって、特に低オン抵抗のMOS−FETを
用いることで、2次側整流での損失を大幅に減少させる
ことができるようになった。
According to the present invention, synchronous rectification is performed by using a MOS-FET as a secondary rectifier of a voltage conversion transformer, and in particular, by using a low on-resistance MOS-FET, a secondary rectifier is used. The rectification loss can be greatly reduced.

【0048】これによって、従来の装置では、2次側整
流用ダイオードの順方向降下電圧によって、出力に対す
る損失の割合が大きくなっていたものを、本発明によれ
ば、特にパーソナルコンピュータのように低電圧、大電
流の電源が要求される場合に、2次側整流での損失を大
幅に減少させ、効率の良いスイッチング電源を実現する
ことができるものである。
Thus, according to the present invention, the ratio of the loss to the output is increased due to the forward drop voltage of the diode for secondary rectification. When a power supply of a voltage and a large current is required, the loss in the secondary side rectification can be greatly reduced, and an efficient switching power supply can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の適用される電源装置の一例の構成図で
ある。
FIG. 1 is a configuration diagram of an example of a power supply device to which the present invention is applied.

【図2】その説明のための図である。FIG. 2 is a diagram for explaining this.

【図3】本発明の適用される電源装置の要部の一例の構
成図である。
FIG. 3 is a configuration diagram of an example of a main part of a power supply device to which the present invention is applied.

【図4】その動作の説明のための図である。FIG. 4 is a diagram for explaining the operation.

【図5】その動作の説明のための図である。FIG. 5 is a diagram for explaining the operation.

【図6】本発明の適用される電源装置の要部の他の例の
構成図である。
FIG. 6 is a configuration diagram of another example of a main part of a power supply device to which the present invention is applied.

【図7】本発明の適用される電源装置の要部の他の例の
構成図である。
FIG. 7 is a configuration diagram of another example of a main part of a power supply device to which the present invention is applied.

【図8】本発明の適用される電源装置の他の例の構成図
である。
FIG. 8 is a configuration diagram of another example of a power supply device to which the present invention is applied.

【図9】従来の電源装置の構成図である。FIG. 9 is a configuration diagram of a conventional power supply device.

【符号の説明】[Explanation of symbols]

100 AC入力を整流したDC、1,2 スイッチン
グトランジスタ、3過飽和リアクタトランス、4 共振
コンデンサ、5 電圧変換トランス、6 コンデンサ、
7 抵抗器、8 ツェナーダイオード、9 ダイオー
ド、10 抵抗器、11,12 コンデンサ、13 抵
抗器、14 ツェナーダイオード、15ダイオード、1
6 抵抗器、17,18 コンデンサ、19,20 M
OS−FET、21 コンデンサ、22 出力端子、2
3 制御回路、24,25 駆動回路
100 DC rectified AC input, 1, 2 switching transistor, 3 supersaturated reactor transformer, 4 resonance capacitor, 5 voltage conversion transformer, 6 capacitor,
7 resistor, 8 Zener diode, 9 diode, 10 resistor, 11, 12 capacitor, 13 resistor, 14 Zener diode, 15 diode, 1
6 resistors, 17 and 18 capacitors, 19 and 20 M
OS-FET, 21 capacitor, 22 output terminal, 2
3 control circuit, 24, 25 drive circuit

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 スイッチング素子を2石用いたハーフブ
リッジ構成を有し、 上記2石のスイッチング素子の中点に共振コンデンサと
電圧変換用トランスが設けられると共に、 上記電圧変換用トランスの2次側整流としてMOS−F
ETを用いて同期整流を行うことを特徴とする電源装
置。
1. A half-bridge configuration using two switching elements, wherein a resonance capacitor and a voltage conversion transformer are provided at a midpoint of the two switching elements, and a secondary side of the voltage conversion transformer. MOS-F as rectification
A power supply device that performs synchronous rectification using ET.
【請求項2】 請求項1記載の電源装置において、 上記2次側整流用のMOS−FETの駆動信号として上
記MOS−FETを流れる電流を検出した信号を用いる
ことを特徴とする電源装置。
2. The power supply device according to claim 1, wherein a signal obtained by detecting a current flowing through the MOS-FET is used as a drive signal of the secondary-side rectification MOS-FET.
【請求項3】 請求項2記載の電源装置において、 上記MOS−FETに直列に電流検出トランスを接続し
て上記MOS−FETを流れる電流を検出することを特
徴とする電源装置。
3. The power supply device according to claim 2, wherein a current detection transformer is connected in series with said MOS-FET to detect a current flowing through said MOS-FET.
【請求項4】 請求項2記載の電源装置において、 上記MOS−FETに直列に電流検出抵抗を接続してそ
の電圧降下により上記MOS−FETを流れる電流を検
出することを特徴とする電源装置。
4. The power supply device according to claim 2, wherein a current detection resistor is connected in series to said MOS-FET, and a current flowing through said MOS-FET is detected by a voltage drop.
【請求項5】 請求項2記載の電源装置において、 上記MOS−FETのオン抵抗による電圧降下により上
記MOS−FETを流れる電流を検出することを特徴と
する電源装置。
5. The power supply device according to claim 2, wherein a current flowing through the MOS-FET is detected by a voltage drop due to an on-resistance of the MOS-FET.
JP8315049A 1996-11-26 1996-11-26 Power supply Pending JPH10164837A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8315049A JPH10164837A (en) 1996-11-26 1996-11-26 Power supply

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8315049A JPH10164837A (en) 1996-11-26 1996-11-26 Power supply

Publications (1)

Publication Number Publication Date
JPH10164837A true JPH10164837A (en) 1998-06-19

Family

ID=18060824

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8315049A Pending JPH10164837A (en) 1996-11-26 1996-11-26 Power supply

Country Status (1)

Country Link
JP (1) JPH10164837A (en)

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JP2008301680A (en) * 2007-06-04 2008-12-11 Fuji Electric Systems Co Ltd Dc-dc converter
JP2010187478A (en) * 2009-02-12 2010-08-26 Shindengen Electric Mfg Co Ltd Means for controlling series resonant converter
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