JP2012133752A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microcomputer capable of measuring time required for various processing by minimizing an increase of circuit scale and without changing a description of a user program when the microcomputer comprises an on-chip debug function.SOLUTION: A debug circuit unit of a microcomputer comprises a measurement permission circuit 23 outputting measurement permission signals to a timer 28 which measures time between two events occurring during a CPU program execution period, according to prescribed conditions of a user. The measurement permission circuit 23 comprises: an interruption level setting register 21 for setting an interruption level to permit or inhibit a measurement operation of the timer 28; and a comparator 22 for determining whether a level of interruption processing executed by a CPU 2 is equal to or more than the interruption level set by the interruption level setting register 21. The measurement permission circuit 23 is configured to be able to designate a determination result by the comparator 22 as the measurement permission signal.

Description

  The present invention relates to a microcomputer having an on-chip debugging function.

Conventionally, when debugging a program of a microcomputer, in order to measure a specific processing time in the program, for example, as in Patent Document 1, an address for starting measurement of a processing time and an address for ending the measurement are set. However, there is a technique for measuring the processing time between addresses. However, the microcomputer may also execute a subroutine such as function processing and various interrupt processing during execution of the main routine, and an interrupt may occur during processing of the subroutine. Therefore, in order to measure them individually, it is necessary to prepare a register for setting a measurement start address and a measurement end address for each process and a register for holding a measurement result, as in Patent Document 2, for example. .
Japanese Patent Laid-Open No. 3-118644 Japanese Patent No. 2595728

  Here, when a microcomputer emulator is prepared for debugging a program, the circuit scale is relatively small. However, in recent years, a microcomputer having a so-called on-chip debugging function in which a function for debugging a program is mounted in advance has been used. In this case, since the restriction on the circuit scale becomes large, it is desirable to reduce the redundant configuration as much as possible. For example, assuming that the time required for a specific process is measured using the technique of Patent Document 1, a register for setting start addresses and end addresses of all interrupt processes that can occur is provided, It is necessary to change the software (user program) to be debugged so that interrupts other than processing are temporarily prohibited or the level of interrupts to be permitted is temporarily set high.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to perform various processes without increasing the circuit scale as much as possible and without changing the description of the user program when an on-chip debugging function is provided. An object of the present invention is to provide a microcomputer capable of measuring the time required for the operation.

  According to the microcomputer of claim 1, the on-chip debug circuit unit is provided with a timer whose time is to be measured between two events that occur during the program execution period of the CPU according to a condition specified by the user. Measurement permission signal output means for outputting a measurement permission signal is provided. The timer performs a measurement operation during a period when the measurement permission signal is active. Thereby, according to the event which a user designates, and the output conditions of a measurement permission signal, the time which various processes require by one timer can be measured flexibly. Therefore, an increase in circuit scale due to the on-chip debug circuit portion can be suppressed as much as possible, and it is possible to avoid changing the description of the user program.

  According to the microcomputer of the second aspect, the measurement permission signal output means can designate an interrupt processing signal indicating that the CPU is in interrupt processing as the measurement permission signal. Therefore, for example, the length of the period during which the CPU executes the interrupt process or the period during which the interrupt process is not executed between two events can be measured by the timer.

  According to the microcomputer of claim 3, the measurement permission signal output means includes an interrupt level setting register for setting an interrupt level for permitting or prohibiting a measurement operation by the timer, and an interrupt processing level executed by the CPU. And a determination unit that compares and determines the level relationship between the interrupt level set in the interrupt level setting register and the determination result by the determination unit can be specified as a measurement permission signal. Therefore, between two events, the timer measures the period when the level of interrupt processing being executed by the CPU is higher or lower than the level set in the interrupt level setting register. Can do.

  According to the microcomputer of claim 4, the interrupt hold signal output means outputs an interrupt hold signal indicating that the CPU is holding the lower level interrupt processing generated during the upper level interrupt processing, and performs measurement. The permission signal output means can designate an interrupt hold signal as the measurement permission signal. Therefore, it is possible to measure the time during which the CPU holds the interrupt processing between two events by using the timer.

  According to another aspect of the microcomputer of the present invention, the interrupt prohibition signal output means outputs an interrupt prohibition signal that becomes active during a period when interrupt to the CPU is prohibited, and the measurement permission signal output means interrupts as a measurement permission signal. The prohibition signal can be specified. Therefore, it is possible to measure the time during which interrupt processing for the CPU is prohibited between the occurrences of two events by the timer.

  According to the microcomputer of the sixth aspect, the comparing means compares the start address setting register and the end address setting register with the value of the program counter of the CPU. Then, the on-chip debug circuit unit uses the comparison result by the comparison means as an event. Therefore, for example, if the start address and end address of a subroutine program for performing a specific process are set in the corresponding registers, the execution time of the subroutine program can be measured by a timer.

  According to the microcomputer of the seventh aspect, the on-chip debug circuit unit can designate an edge at which the level of the interrupt processing signal changes as an event. That is, the time required for the interrupt process can be measured by the timer by using the edge of the interrupt process signal that changes as the interrupt process starts and ends as an event.

  According to the microcomputer of the eighth aspect, the on-chip debug circuit unit can designate the edge of the determination signal output by the determination unit for determining the interrupt level as an event. Therefore, the processing time of the interrupt processing to be measured can be selectively measured according to the level set in the interrupt level setting register.

  According to the microcomputer of the ninth aspect, the on-chip debug circuit unit can designate an edge at which the level of the interrupt pending signal changes as an event. Therefore, it is possible to measure the time during which the interrupt processing has been suspended by the timer.

  According to the microcomputer of the tenth aspect, the on-chip debug circuit unit can designate an edge at which the level of the interrupt inhibition signal changes as an event. Therefore, the timer can measure the time during which the interrupt processing is prohibited.

  According to the microcomputer of the eleventh aspect, the maximum value register holds the maximum value of the measurement result by the timer, and when the measurement operation by the timer is completed, the maximum value updating means The maximum value held in the value register is compared. If the former value is large, the measurement result is written in the maximum value register and updated. Therefore, if the maximum value register is accessed, the maximum value of the measurement result by the timer can be obtained.

  According to the microcomputer of the twelfth aspect, the minimum value register holds the minimum value of the measurement result by the timer, and when the measurement operation by the timer is completed, the minimum value updating means The minimum value held in the value register is compared. If the former value is small, the measurement result is written in the minimum value register and updated. Therefore, if the minimum value register is accessed, the minimum value of the measurement result by the timer can be obtained.

  According to the microcomputer of the thirteenth aspect, the measurement number counter counts the number of executions of the measurement operation by the timer, and accumulates and holds the measurement result in the accumulated value register at the end of the measurement operation by the timer. Therefore, the average value of the measurement results by the timer can be obtained by dividing the cumulative value of the measurement results by the timer held in the cumulative value register by the count value of the measurement number counter.

  According to the microcomputer of the fourteenth aspect, it is configured to be able to shift to the low power consumption mode by stopping the supply of the system clock signal to the CPU, and in a state in which the function of the on-chip debug circuit unit is made effective, Even during the transition to the power consumption mode, the system clock signal is supplied to the on-chip debug circuit unit. Therefore, for example, the length of the period can be measured by the on-chip debug circuit unit even during the period in which the microcomputer shifts to the low power consumption mode.

Functional block diagram showing the configuration of the microcomputer according to the first embodiment The figure which shows the detailed structure of a time measurement function part and an event function part Flowchart showing the setting procedure when measuring a specific processing time with a timer when debugging a user program Timing chart showing four different processing time measurement patterns Partial equivalent diagram of FIG. 2 showing the second embodiment Timing chart showing processing time measurement pattern Partial equivalent diagram of FIG. 2 showing the third embodiment 6 equivalent diagram FIG. 5 or FIG. 7 equivalent view showing the fourth embodiment Equivalent to FIG. 6 equivalent diagram Timing chart showing the minimum time measurement pattern between interrupts FIG. 5 is a diagram schematically illustrating only a clock signal supply path portion of a microcomputer according to a fifth embodiment.

(First embodiment)
The first embodiment will be described below with reference to FIGS. FIG. 1 is a functional block diagram showing the configuration of the microcomputer. The microcomputer 1 includes a CPU 2, an interrupt control circuit (interrupt processing signal output means, interrupt hold signal output means, interrupt prohibition signal output means) 3, a memory 4, a peripheral circuit 5, a debug circuit section (on-chip debug circuit section) ) 6 etc. The CPU 2 to the peripheral circuit 5 are components of a general microcomputer, and these are connected via an address bus 7 and a data bus 8.

The interrupt control circuit 3 monitors various interrupt signals output to the CPU 2 and generates, for example, the following signals.
-A signal indicating the interrupt level indicating the importance level of the interrupt-An interrupt processing signal that is active while the CPU 2 is performing interrupt processing-An interrupt with a lower level occurs while the CPU 2 is performing higher level interrupt processing Occurs when the latter interrupt processing is pending Interrupt pending signal • Writes to the interrupt control register (not shown), active during periods when interrupt output to CPU 2 is prohibited Interrupt disable signal

  The debug circuit unit 6 is stored in a memory 4 including a non-volatile memory such as a flash ROM, and is used when debugging a user program executed by the CPU 2. The debug circuit unit 6 communicates with an external debug tool 9, and registers or work memory (RAM included in the memory 4) when the CPU 2 executes a user program according to a monitor program executed by the tool 9. It operates to monitor the state of).

  The debug circuit unit 6 includes an execution control function unit 10, a built-in break function unit 11, a trace function unit 12, an event function unit 13, a debug DMA function unit 14, a time measurement function unit 15, and the like. The execution control function unit 10 is a part that comprehensively controls the debug function executed by the debug circuit unit 6, and the built-in break function unit 11 is a break that stops the execution of the CPU 2 while the user program is being executed. This is the part that realizes the function. The trace function unit 12 realizes a trace function for tracking the execution state of the user program by the CPU 2. The event function unit 13 is a function for monitoring in order to use a specific event set by the user as a trigger, and the debug DMA function unit 14 is for transferring data in the memory 4 and reading it on the debug tool 9 side, for example. used.

  The time measurement function unit 15 is a part for measuring the execution time of various processes by the CPU 2, and its detailed configuration is shown in FIG. 2 together with the event function unit 13. An interrupt level is written and set in the interrupt level setting register 21 by the user via the debug tool 9, and the register value is compared with the interrupt level given from the interrupt control circuit 3 in the comparator 22 (determination means). The comparator 22 outputs a signal that becomes active when the interrupt level (B) is higher than the register value (A) to the selector 24 that constitutes the measurement permission circuit (measurement permission signal output means) 23. In addition, the above-described interrupt processing signal, interrupt hold signal, interrupt prohibition signal, and the like are given to the selector 24 from the interrupt control circuit 3.

  The selection of the input signal in the selector 24 is performed by the register value written in the measurement permission condition selection register 25. In the measurement permission condition selection register 25, which one of the output signal of the comparator 22, the interrupt processing signal, the interrupt hold signal, and the interrupt prohibition signal is selected by the user via the debug tool 9 is written. The output signal of the selector 24 is given to the selector 26 at the next stage.

  The selector 26 selects either the output signal of the selector 24 or its negative logic signal according to the register value written in the measurement permission setting register 27, and the timer 28 sets a measurement permission / pause signal (measurement permission signal). Output as. The measurement permission setting register 27 is written by the user via the debug tool 9 as in the measurement permission condition selection register 25. The timer 28 performs a timing operation during a period when the measurement permission / pause signal is at a high level, and temporarily stops the timing operation when the signal is at a low level.

The timer 28 is given a measurement start signal and a measurement end signal from the two selectors 29 and 30, respectively. Various signals are input to the selectors 29 and 30 from the event function unit 13. The rising / falling edge detection unit (edge detection means) 31 of the event function unit 13 receives the output signal of the comparator 22, the interrupt processing signal, the interrupt hold signal, and the interrupt prohibition signal. When the rising / falling edge detection unit 31 detects the rising edge and the falling edge of each input signal, the rising / falling edge detection unit 31 generates, for example, a one-shot pulse signal for each signal and outputs it to the selectors 29 and 30 (that is, a measurement start signal). , The measurement end signal being activated corresponds to “occurrence of event”).
For convenience of illustration, the output line of the rising / falling edge detector 31 is four. However, in actuality, the rising edge and the falling edge are individually detected for each signal. Will be eight. Each of the selectors 29 and 30 can individually select a rising edge input and a falling edge input.

  The event function unit 13 includes a start address setting register 32, an end address setting register 33, and comparators 34 and 35 (comparison means). The comparator 34 compares the register value of the start address setting register 32 with the value of the program counter (not shown) of the CPU 2, and the comparator 35 compares the register value of the end address setting register 33 and the value of the program counter. When both of them match, a match signal is output to the selectors 29 and 30, respectively. Selection of input signals in the selectors 29 and 30 is performed by register values written in the measurement start condition selection register 36 and the measurement end condition selection register 37, respectively. In the registers 36 and 37, which of the signals to be input to the selectors 29 and 30 is selected by the user via the debug tool 9 is written.

  Next, the operation of this embodiment will be described with reference to FIGS. FIG. 3 is a flowchart showing a setting procedure when a specific processing time is measured by the timer 28 during debugging of the user program. While the user program is being executed by the CPU 2 (step P1), the debug tool 9 breaks and the monitor program is executed. Then, when the timer 28 and the time measurement data register (not shown) to which the timer value measured by the timer 28 is transferred are cleared (step P2), the address at which the timer 28 starts measurement (event occurrence) And the address (event occurrence) at which the measurement is to be ended are written and set in the start address setting register 32 and the end address setting register 33 of the event function unit 13, or the measurement start condition selection register 36 and the measurement end condition selection register are set. 37 is set (step P3).

  Next, the interrupt level to be measured is set in the interrupt level setting register 21, and the measurement permission condition selection register 25, the measurement permission selection register 27, etc. are set (step P4). Then, when the execution of the monitor program is terminated and returned to the user program (step P5), a break is again caused by the debug tool 9 during the execution, and the monitor program is executed. Then, the timer value of the timer 28 and the number of measurements described later are read (step P6). If necessary, the process returns to Step P2, and the setting for measuring the processing time is performed again.

FIGS. 4A to 4D are timing charts showing four different processing time measurement patterns. FIG. 4A shows a measurement state when each register is set as follows. Yes. The broken line in the figure is the period during which measurement by the timer 28 is stopped (the start event has not occurred), the thick line is the period during which the measurement by the timer 28 is being executed, and the thin line is the measurement by the timer 28 being suspended Corresponds to the period that is being used.
Interrupt level setting register 21: Interrupt level “X (arbitrary)”
・ Measurement permission condition selection register 25: Interrupt processing signal ・ Measurement permission selection register 27: “0” (stop)
Start address register 32: 0xA00000
End address register 33: 0xB00000
Measurement start condition selection register 36: comparator 34
Measurement end condition selection register 37: comparator 35
Here, the value of the measurement start condition selection register 36 corresponds to the start address of the function process (subroutine process), and the value of the measurement end condition selection register 37 corresponds to the end address of the function process. When an interrupt occurs during the execution of function processing, the interrupt processing signal becomes active. Since the selector 26 outputs the inverted signal to the timer 28, the timing operation by the timer 28 is stopped during the period when the interrupt processing signal is active. As a result, the timer 28 measures only the execution time of the function process.

FIG. 4B is a timing chart showing a measurement state when each register is set as follows.
Interrupt level setting register 21: Interrupt level “1”
Measurement permission condition selection register 25: comparator 22
Measurement permission selection register 27: “1”
Start address register 32: 0x000000
End address register 33: 0xFFFFFE
Measurement start condition selection register 36: comparator 34
Measurement end condition selection register 37: comparator 35
Here, the value of the measurement start condition selection register 36 corresponds to the start address of the main routine process, and the value of the measurement end condition selection register 37 corresponds to the end address of the main routine process. Then, when the interrupt level is higher than “1”, the timing operation by the timer 28 is permitted, so that an interrupt of level “2” or higher occurs during the execution of the function processing, and the time during which the interrupt processing is executed Only will be measured. Note that the same measurement is performed when an interrupt occurs during the execution of the main routine process.

FIG. 4C is a timing chart showing a measurement state when each register is set as follows.
Interrupt level setting register 21: Interrupt level “X”
Measurement permission condition selection register 25: Interrupt processing signal Measurement permission selection register 27: “1”
Start address register 32: 0x000000 (or any)
End address register 33: 0xFFFFFE (or any)
Measurement start condition selection register 36: rising edge of interrupt hold signal Measurement end condition selection register 37: falling edge of interrupt hold signal Measurement start condition selection register 36 and measurement end condition selection register 37 are shown in FIG. The same as or may be arbitrary. In this case, a level “1” interrupt is generated while a level “2” interrupt is generated and the processing is being performed, and the interrupt hold signal becomes active during a period in which the latter processing is held. Therefore, measurement by the timer 28 is started at the rising edge of the interrupt hold signal, and measurement by the timer 28 is ended at the falling edge of the interrupt hold signal. In addition, the timer 28 is allowed to measure during the period when the interrupt process is being performed. As a result, the time during which interrupt processing at level “1” is suspended is measured.

  In this case, the interrupt processing signal and the interrupt hold signal can be interchanged to perform the same measurement. In other words, the measurement by the timer 28 is started at the rising edge of the interrupt processing signal, the measurement by the timer 28 is ended at the falling edge of the interrupt processing signal, and the measurement of the timer 28 is permitted during the period when the interrupt pending signal is active. You may do it.

FIG. 4D is a timing chart showing a measurement state when each register is set as follows.
Interrupt level setting register 21: Interrupt level “X”
• Measurement enable condition selection register 25: Interrupt disable signal • Measurement enable selection register 27: “1”
Start address register 32: 0x000000
End address register 33: 0xFFFFFE
Measurement start condition selection register 36: comparator 34
Measurement end condition selection register 37: comparator 35
The values of the measurement start condition selection register 36 and the measurement end condition selection register 37 are the same as those in FIG. While level 1 and level 2 interrupts are generated during the execution of function processing, the interrupt processing is prohibited and measurement by the timer 28 is permitted during the period when the interrupt disable signal is active. Is done. As a result, the time during which interrupt processing is prohibited is measured.

  In this case, as in FIG. 4C, the measurement by the timer 28 is started at the rising edge of the interrupt prohibition signal, and the measurement by the timer 28 is ended at the falling edge of the interrupt prohibition signal. By permitting the measurement of the timer 28 during the active period, the same measurement can be performed.

  As described above, according to the present embodiment, the debugging circuit unit 6 of the microcomputer 1 sets the time measurement target between two events that occur during the program execution period of the CPU 2 in accordance with the conditions specified by the user. A measurement permission circuit 23 that outputs a measurement permission signal to the timer 28 is provided. The timer 28 performs a measurement operation during a period when the measurement permission signal is active. Thereby, the time required for various processes can be flexibly measured by one timer 28 according to the event specified by the user and the output condition of the measurement permission signal. Therefore, it is possible to suppress an increase in circuit scale as much as possible by installing the debug circuit unit 6 in the microcomputer 1 and to avoid changing the description of the user program.

  Specifically, the measurement permission circuit 23 includes an interrupt level setting register 21 for setting an interrupt level for permitting or prohibiting the measurement operation by the timer 28, the level of interrupt processing executed by the CPU 2, and an interrupt level setting. A comparator 22 for comparing and determining the level relationship with the interrupt level set in the register 21 is provided, and a determination result by the comparator 22 can be specified as a measurement permission signal. Therefore, during the occurrence of two events, the timer 28 can measure the period during which the level of interrupt processing executed by the CPU 2 is equal to or higher than the level set in the interrupt level setting register 21.

  The comparators 34 and 35 compare the start address setting register 32 and the end address setting register 33 with the value of the program counter of the CPU 2. Since the debug circuit unit 6 uses the comparison result of the comparators 34 and 35 as an event, for example, the start address and end address of the function processing program for performing a specific process are set in the corresponding registers 32 and 33, respectively. By doing so, the execution time of the function processing program can be measured by the timer 28.

  Therefore, even when an interrupt occurs during the execution of the function processing by the CPU 2, only the execution time of the function processing or the execution time of the interrupt processing is determined according to the setting in the measurement permission setting register 27. It becomes possible to measure from 28 to a common timer. As a result, the execution time of the function processing or the execution time of the interrupt can be measured without increasing the circuit scale of the debug circuit unit 6 as much as possible and without making a significant change to the user program to be debugged. Even when the interrupt level (importance) is set in a plurality of stages, the measurement target of the execution time can be changed by designating the level.

  In addition, the measurement permission circuit 23 holds, as the measurement permission signal, an interrupt processing signal indicating that the CPU 2 is in interrupt processing, and that the CPU 2 is holding down the lower level interrupt processing generated during the upper level interrupt processing. The interrupt hold signal shown, and the interrupt disable signal that is active during the period when the interrupt to the CPU 2 is prohibited can be designated to be a measurement enable / pause signal. The timer 28 can measure the length of the period during which the interrupt processing is executed or the period during which the interrupt processing is not executed, the length of the interrupt suspension / interrupt disable period, and the like.

  The debug circuit unit 6 also includes an edge at which the level of the interrupt processing signal changes, an edge of the comparison signal (determination signal) output from the comparator 22 that determines the interrupt level, an edge at which the level of the interrupt pending signal changes, and an interrupt. An edge at which the level of the inhibition signal changes can be designated as an event by the selectors 29 and 30. Therefore, the timer 28 can measure the time when the interrupt processing is suspended, the time when the interrupt processing is prohibited, and the like.

(Second embodiment)
5 and 6 show a second embodiment. The same parts as those in the first embodiment are denoted by the same reference numerals and the description thereof will be omitted. Hereinafter, different parts will be described. FIG. 5 is a partial equivalent diagram of FIG. 2, and a rising edge detector 41 that detects a rising edge of the output signal of the selector 29, and a measurement number counter 42 that counts the number of outputs of the output signal of the rising edge detector 41. With. The rising edge detector 41 outputs a one-shot pulse signal each time a rising edge of the output signal of the selector 29 is detected.

  FIG. 6 is a timing chart showing the measurement state when each register is set in the same manner as in the case of FIG. 4A of the first embodiment. In the case of the second embodiment, the execution of the function processing is started, and measurement is performed by the timer 28 every time the value of the program counter of the CPU 2 indicates the start address 0xA00000. Even when the end address 0xB00000 is reached, the measurement value of the timer 28 is not reset and the measurement result is accumulated.

  The measurement number counter 42 stores how many times the timer 28 has started measurement. Therefore, a break is made after the user program is executed for a predetermined period, and the former value is divided by the latter value by referring to the measured value of the timer 28 and the counted value of the measured number counter 42 by the monitor program. The average execution time of function processing can be obtained.

  As described above, according to the second embodiment, the measurement number counter 42 for counting the number of execution times of the time measurement by the timer 28 is provided, and the timer 28 continues the period in which the function processing is continuously executed a plurality of times. To measure. Therefore, if the measured value of the timer 28 at a certain point is divided by the number of executions, the average execution time of the function processing can be obtained.

(Third embodiment)
FIGS. 7 and 8 show a third embodiment, and the differences from the first embodiment will be described. FIG. 7 is a partial equivalent diagram of FIG. 2. When the rising edge detector 43 detects the rising edge of the output signal of the selector 26, it outputs a one-shot pulse as a detection signal. Is output as a reset signal. The measurement data of the timer 28 is given to the comparator 44 and the selector 45. A maximum value holding register 46 is connected to the output side of the selector 45, and the register value of the maximum value holding register 46 is also given to the comparator 44 and the selector 45. That is, the comparator 44 compares the measured data value of the timer 28 with the register value of the maximum value holding register 46, and if the former value is larger than the latter value, the selector 45 sends the measured data of the timer 28 to the selector 45. A value is selected and written to the maximum value holding register 46.

  Next, the operation of the third embodiment will be described with reference to FIG. FIG. 8 shows a case where each register setting is measured in the same manner as in the case of FIG. 4B. When the interrupt level is “2” or higher, the measurement operation by the timer 28 is permitted. This corresponds to a time (dead zone) in which an interrupt of level “2” or lower cannot newly generate an interrupt. The timer 28 is reset every time an interrupt of level “2” or higher occurs. In the case shown in FIG. 8, the maximum value “5” of the measurement data by the timer 28 is held in the maximum value holding register 46.

  As described above, according to the third embodiment, when the timer 26 performs measurement when the selector 26 outputs the measurement permission signal, the execution time data measured by the timer 28 is held in the maximum value holding register 46. The timer 28 is reset every time the measurement permission signal becomes active, and the comparator 44 determines that the current data value measured by the timer 28 is higher than the past data value held in the maximum value holding register 46. When the value is larger, the data value is stored in the maximum value holding register 46 and updated. Therefore, it is possible to measure the maximum value of the time corresponding to the dead zone in which a predetermined level of interrupt cannot newly generate an interrupt.

(Fourth embodiment)
9 to 12 show a fourth embodiment. In the second embodiment, the configuration for obtaining the average execution time of the function processing is individually shown, and in the third embodiment, the configuration for measuring the maximum value of the time corresponding to the dead zone is individually shown. The example shows a configuration example in which these can be realized by a common configuration and the minimum time of an interval at which an interrupt occurs can be measured. FIG. 9 corresponds to FIG. 5 or FIG. 7, and rising edge detectors 51 and 52 are arranged at the output terminals of the selectors 29 and 30, respectively. The output signal of the rising edge detection unit 51 is given to the measurement number counter 53 to count the number of outputs, and is given to the timer 28 as a reset signal. The output signal of the rising edge detection unit 52 is given to the maximum value holding register 46 as a holding timing signal for data output from the selector 45 (maximum value updating means).

  The comparator 54, the selector 55, and the minimum value holding register 56 are connected by the same connection relationship as the comparator 44 (maximum value updating means), the selector 45, and the maximum value holding register 46. Then, the comparator 54 (minimum value updating means) compares the timer value of the timer 28 with the data value held in the minimum value holding register 56, selects the smaller value, and enters the minimum value holding register 56. A selection switching signal is output to the selector 55 (minimum value updating means) so as to be output.

  Further, an adder 57 and a cumulative value holding register 58 are provided, and the timer value of the timer 28 and the register value held in the cumulative value holding register 58 are given to the input terminal of the adder 57. Yes. The adder 57 outputs the addition result of the data values given to both input terminals to the accumulated value holding register 58. The output signal of the rising edge detection unit 52 is given to the minimum value holding register 56 and the cumulative value holding register 58 as a data holding timing signal.

Next, the operation of the fourth embodiment will be described with reference to FIGS. FIG. 10 is a timing chart when the maximum time of the dead zone, which is a time during which an interrupt of level “2” or lower cannot newly generate an interrupt, is obtained as in the third embodiment. Each register in this case is set as follows.
Interrupt level setting register 21: Interrupt level “1”
Measurement permission condition selection register 25: comparator 22
Measurement permission selection register 27: “1”
Start address register 32: Arbitrary End address register 33: Arbitrary Measurement start condition selection register 36: rising edge of comparator 22 Measurement end condition selection register 37: falling edge of comparator 22

  By setting as described above, the timer 28 measures the period during which an interrupt of level “2” or higher is processed. When the falling edge of the comparator 22 is detected, the timer 28 passes through the selector 30 and the rising edge detection unit 52. The holding timing signal is output to the maximum value holding register 46. As a result, the larger of the timer value measured by the timer 28 at that time and the data value held in the maximum value holding register 46 is held in the maximum value holding register 46. Next, when the rising edge of the comparator 22 is detected, a reset signal is output to the timer 28 via the selector 29 and the rising edge detector 51. In the example shown in FIG. 10, the maximum value held in the maximum value holding register 46 changes from “0” → “3” → “5”.

FIG. 11 is a timing chart in the case of obtaining the average value of the function processing time as in the second embodiment. Each register in this case is set as follows.
Interrupt level setting register 21: Interrupt level “0”
Measurement permission condition selection register 25: comparator 22
Measurement permission selection register 27: “0”
Start address register 32: 0xA00000
End address register 33: 0xB00000
Measurement start condition selection register 36: comparator 34
Measurement end condition selection register 37: comparator 35

  By setting as described above, every time the execution of the function process is started and the value of the program counter of the CPU 2 indicates the start address 0xA00000, the measurement is started after the timer 28 is reset. When the end address 0xB00000 is reached, the measured value of the timer 28 is cumulatively held in the cumulative value holding register 58 via the adder 57. In addition, since the measurement number counter 53 stores how many times the measurement by the timer 28 has been started, the user program is executed for a predetermined period, and then a break is applied to the accumulated value holding register 58 by the monitor program. By referring to the stored value and the count value of the measurement number counter 53 and dividing the former value by the latter value, the average execution time of the function processing can be obtained. In the example shown in FIG. 11, the cumulative value held in the cumulative value holding register 58 changes from “0” → “5” → “9”, and the count value of the measurement number counter 53 is “0” → “1” → It has changed to “2”.

FIG. 12 is a timing chart in the case where the minimum time of interrupt generation intervals of level “2” is acquired. Each register in this case is set as follows.
Interrupt level setting register 21: Interrupt level “0”
Measurement permission condition selection register 25: comparator 22
Measurement permission selection register 27: “0”
Start address register 32: 0xD00000
End address register 33: 0xC00000
Measurement start condition selection register 36: comparator 34
Measurement end condition selection register 37: comparator 35
Here, address 0xC00000 is the start address of a subroutine that processes interrupts of level “2” or higher, and address 0xD00000 is the end address of the subroutine.

  By setting as described above, the timer 28 is reset when the value of the program counter reaches the end address 0xD00000, and starts measurement, and when it reaches the start address 0xC00000, the measurement ends. The smaller one of the timer value at that time and the data value held in the minimum value holding register 56 is held in the minimum value holding register 56. In the example shown in FIG. 12, the minimum value held in the minimum value holding register 56 changes from “F” → “7” → “5”.

  As described above, according to the fourth embodiment, the maximum value of the measurement result by the timer 28 is held in the maximum value holding register 46. When the measurement operation by the timer 28 ends, the comparator 44 The measurement result is compared with the maximum value held in the maximum value holding register 46, and if the former value is large, the measurement result is written into the maximum value holding register 46 via the selector 45 and updated. Therefore, if the maximum value holding register 46 is accessed, the maximum value of the measurement result by the timer 28 can be obtained.

  Further, the minimum value holding register 56 holds the minimum value of the measurement result by the timer 28, and the comparator 54 holds the measurement result at that time and the minimum value holding register 56 when the measurement operation by the timer 28 is completed. When the former value is small, the measurement result is written into the minimum value holding register 56 via the selector 55 and updated. Therefore, if the minimum value holding register 56 is accessed, the minimum value of the measurement result by the timer 28 can be obtained.

  Further, the measurement number counter 53 counts the number of executions of the measurement operation by the timer 28, and accumulates and holds the measurement result by the adder 57 in the accumulated value holding register 58 at the end of the measurement operation by the timer 28. did. Therefore, the average value of the measurement results obtained by the timer 28 can be obtained by dividing the cumulative value held in the cumulative value holding register 58 by the count value of the measurement number counter 58.

(5th Example)
FIG. 13 shows a fifth embodiment. In the fifth embodiment, the microcomputer 61 having the on-chip debug function shifts from the normal operation mode to the sleep mode or the standby mode (low power consumption mode) in which the supply of the clock signal (CPU clock) to the CPU 2 or the like is stopped. It is assumed that it is configured to be possible. FIG. 13 schematically shows only the clock signal supply path portion of the microcomputer 61. The oscillation circuit 62 is configured by, for example, a CR oscillation circuit, an oscillation circuit using a crystal oscillator, or the like, and outputs a reference clock signal having a frequency of, for example, the order of kHz.

  The reference clock signal is input to two multiplier / divider circuits 63 and 64, which are analog or digital PLL (Phase Locked Loop) circuits, for example. The multiplier / divider circuits 63 and 64 generate, for example, a multiplied clock signal (system clock signal) whose frequency is in the order of MHz in accordance with a value set in a register (not shown) for setting the multiplier / divider ratio. Generate and output. The multiplied clock signal output from the multiplier / divider circuit 63 is supplied as a CPU clock to the CPU 2, the interrupt control circuit 3, the peripheral circuit 5, etc. (also to the memory 4 as necessary). On the other hand, the multiplied clock signal output from the multiplier / divider circuit 64 is supplied to the debug circuit unit 6.

  The multiplier / divider circuit 63 stops the oscillation operation when a signal for setting the microcomputer 61 to the low power consumption mode (low power consumption mode signal) becomes active. The low power consumption mode signal is output, for example, by the CPU 2 every predetermined transition period set in advance, and becomes inactive when the period is counted by a timer that counts the transition period of the low power consumption mode. The low power consumption mode signal is also given to one input terminal of the AND gate 65. A signal for enabling the function of the debug circuit section 6 (debug function enable signal) is given as a stop control signal to the multiplication / frequency division circuit 64 via the NOT gate 66, and the AND gate 65 The output signal of the AND gate 65 is given to the other input terminal, and is given to the oscillation circuit 62 as a stop control signal.

With the above configuration, the conditions under which the oscillation circuit 62 and the multiplier / divider circuits 63 and 64 stop operating according to the states of the low power consumption mode signal and the debug function enable signal are as follows. In addition, (circle) shows active and x shows inactive.
Low power consumption mode signal Debug function enable signal
Oscillation circuit 62 ○ ×
Multiplier / divider circuit 63 ○ −
Multiplication / frequency division circuit 64-×

  Therefore, the oscillation circuit 62 outputs the reference clock signal during the period when the debug function valid signal becomes active and the debug circuit unit 6 operates even when the microcomputer 61 shifts to the low power consumption mode. Since 63 stops, the CPU clock is not output. On the other hand, the multiplier / divider circuit 64 operates when the debug function enable signal is active, so that the multiplied clock signal is supplied to the debug circuit unit 6. Then, when the debug function enable signal becomes inactive, the operation of the multiplier / divider circuit 64 stops.

  As described above, according to the fifth embodiment, when the microcomputer 61 is configured to be able to shift to the low power consumption mode by stopping the supply of the multiplied clock signal to the CPU 2 or the like, the function of the debug circuit unit 6 In the state in which is activated, the multiplied clock signal is supplied to the on-chip debug circuit section 6 even during the period of shifting to the low power consumption mode. Therefore, even during the period of shifting to the low power consumption mode, the debug circuit unit 6 can measure the length of the period, for example. In addition, since the measurement executed by adopting the individual configurations in the second and third embodiments can be realized by the common configuration in the fifth embodiment, the versatility can be improved and the increase in circuit scale can be suppressed. .

The present invention is not limited to the embodiments described above or shown in the drawings, and the following modifications or expansions are possible.
The configuration shown in FIG. 2 may be appropriately selected from signals necessary for measurement according to individual design, and is not necessarily configured similarly to FIG.
The comparator 22 may output an active signal when B <A. In that case, the selection of “1, 0” in the selector 26 may be reversed.
The second to fourth embodiments may be applied to measurement of other processes, such as measurement of interrupt processing time, interrupt hold time, and interrupt prohibition time.
In the fourth embodiment, the adder 57 and the accumulated value holding register 58 may be constituted by an accumulator.
The fifth embodiment may be executed in combination with other embodiments as appropriate.

  In the drawings, 1 is a microcomputer, 2 is a CPU, 3 is an interrupt control circuit (interrupt processing signal output means, interrupt hold signal output means, interrupt inhibition signal output means), 6 is a debug circuit section (on-chip debug circuit section), 22 is a comparator (determination unit), 23 is a measurement permission circuit (measurement permission signal output unit), 28 is a timer, 31 is a rising / falling edge detection unit (edge detection unit), 32 is a start address setting register, and 33 is End address setting register, 34 and 35 are comparators (comparison means), 44 is a comparator (maximum value update means), 45 is a selector (maximum value update means), 46 is a maximum value holding register, 53 is a counter for the number of times of measurement, 54 is a comparator (minimum value updating means), 55 is a selector (minimum value updating means), 56 is a minimum value holding register, 57 is an adder, and 58 is a cumulative value holding register. , 61 denotes a micro-computer.

Claims (14)

In a microcomputer provided with an on-chip debug circuit unit having a debugging function,
In the on-chip debug circuit section,
A timer that is designated by the user and that measures the time between two events that occur during the period in which the CPU is executing the program;
A measurement permission signal output means for outputting a measurement permission signal for allowing a measurement operation by the timer according to a condition designated by a user,
The microcomputer is configured to perform a measurement operation during a period in which the measurement permission signal is active. An interrupt processing signal output means for outputting an interrupt processing signal indicating that the CPU is in interrupt processing;
The microcomputer according to claim 1, wherein the measurement permission signal output unit can designate the interrupt processing signal as the measurement permission signal. The measurement permission signal output means includes an interrupt level setting register for setting an interrupt level for permitting or prohibiting the measurement operation by the timer,
A determination means for comparing and determining the level relationship between the level of interrupt processing executed by the CPU and the interrupt level set in the interrupt level setting register, and outputting a determination signal;
3. The microcomputer according to claim 1, wherein a determination result by the determination unit can be designated as the measurement permission signal. The CPU comprises an interrupt hold signal output means for outputting an interrupt hold signal indicating that a lower level interrupt process generated during an upper level interrupt process is being held,
4. The microcomputer according to claim 1, wherein the measurement permission signal output means can designate the interrupt hold signal as the measurement permission signal. An interrupt prohibition signal output means for outputting an interrupt prohibition signal which becomes active during a period in which an interrupt to the CPU is prohibited;
5. The microcomputer according to claim 1, wherein the measurement permission signal output means can designate the interrupt prohibition signal as the measurement permission signal. A start address setting register in which a measurement start address is set;
An end address setting register in which a measurement end address is set;
Comparing means for comparing the start address setting register and the end address setting register with the value of the program counter of the CPU,
6. The microcomputer according to claim 1, wherein the on-chip debug circuit unit sets the comparison result obtained by the comparison unit as the event. An interrupt processing signal output means for outputting an interrupt processing signal indicating that the CPU is in interrupt processing;
Edge detecting means for detecting an edge where the level of the interrupt processing signal changes,
The microcomputer according to claim 1, wherein the on-chip debug circuit unit can designate the edge as the event. The measurement permission signal output means includes an interrupt level setting register for setting an interrupt level for permitting or prohibiting the measurement operation by the timer,
A determination means for determining whether the process being executed by the CPU is equal to or higher than the interrupt level set in the interrupt level setting register or less than the interrupt level, and outputting a determination signal;
Edge detecting means for detecting an edge where the level of the determination signal changes,
The microcomputer according to claim 1, wherein the on-chip debug circuit unit can designate the edge as the event. An interrupt hold signal output means for outputting an interrupt hold signal indicating that a lower level interrupt process generated during an upper level interrupt process is held;
Edge detecting means for detecting an edge where the level of the interrupt pending signal changes,
9. The microcomputer according to claim 1, wherein the on-chip debug circuit unit can designate the edge as the event. An interrupt prohibition signal output means for outputting an interrupt prohibition signal that is active during a period in which an interrupt to the CPU is prohibited;
Edge detecting means for detecting an edge where the level of the interrupt prohibition signal changes,
The microcomputer according to any one of claims 1 to 9, wherein the on-chip debug circuit unit can designate the edge as the event. A maximum value register for holding the maximum value of the measurement result by the timer;
When the measurement operation by the timer is completed, the measurement result at that time is compared with the maximum value held in the maximum value register, and if the former value is large, the measurement result is written to the maximum value register and updated. The microcomputer according to claim 1, further comprising a maximum value updating unit configured to update the microcomputer. A minimum value register for holding the minimum value of the measurement result by the timer;
When the measurement operation by the timer is completed, the measurement result at that time is compared with the minimum value held in the minimum value register, and if the former value is small, the measurement result is written in the minimum value register. 12. The microcomputer according to claim 1, further comprising a minimum value updating means for updating. A measurement number counter for counting the number of executions of the measurement operation by the timer;
13. The microcomputer according to claim 1, further comprising a cumulative value register that accumulates and holds measurement results obtained by the timer at the end of the measurement operation by the timer. A clock signal output circuit for generating and outputting a system clock signal is provided.
It is possible to shift to the low power consumption mode by stopping the supply of the system clock signal to the CPU,
When the function of the on-chip debug circuit unit is enabled, the system clock signal is supplied to the on-chip debug circuit unit even during the transition to the low power consumption mode. The microcomputer according to any one of claims 1 to 13, characterized in that:

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