JPH1165897A - Microprocessor with debugger built-in - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microprocessor with debugger built-in with high easiness/ convenience. SOLUTION: The operating state of a CPU 2 is inputted as data to be detected, an input/output part 3 outputs the detected result of these data to be detected, and a prescribed held reference value is compared with the data to be detected. Two event detecting parts 4 and 5 output the result of this comparison, and the outputted result is counted by a counter 7. In this counting, a counter control part 6 sets a countable state based on one detected result and sets a count stopped state based on the other detected result, and a debugging function part for debugging the program operation of the CPU 2 is constituted on one semiconductor. Thus, since RAM is not required, a circuit size is made compact so that the microprocessor can be mounted in one semiconductor. Further, counting can be started/ended at any arbitrary address, accuracy is improved and convenience is improved as well.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a microprocessor with a built-in debugger, and more particularly, to a microprocessor with a built-in debugger having a built-in debugger for software development.

[0002]

2. Description of the Related Art In recent years, microprocessors with a built-in debugger have been receiving attention, especially in recent years. The reason is that in multimedia applications such as voice, sound, image, data communication, etc., one processor is used to execute various applications to reduce the cost of the system. Such debugging of processor software needs to be performed from various viewpoints. For example, confirmation of the logic of the program, confirmation of the validity of the data, and the like. This is because in such a confirmation process, the microprocessor with a built-in debugger has utility value, convenience, and the like.

[0003] However, there is a difference between conventional software and software for new multimedia applications. This is a multimedia application
Various processes need to be performed within a certain fixed cycle. For example, in a sound application, 44.
Execute various applications within about 20 μsec to sample at 1 KHz. Normally, programming is performed using a real-time OS so that switching of applications is as little as possible when designing software.

[0004] However, not all solutions can be obtained by using this real-time OS. This is because, in the case of the sound-based application described above, it is necessary to confirm whether or not all processing is completed within 20 μsec. The real-time OS is unaware of this. If the processing is not completed, the next processing will be affected. For this reason, in software debugging, it is necessary to check the processing time in addition to the confirmation of the logic and the validity of the data described above.

[0005] As a method for confirming the processing time, several methods have conventionally been proposed. For example, there are a method of measuring by using a software simulator, a method of actually operating a program in real time by using a hardware emulator, and a method of measuring.

A method using a debugger such as a hardware emulator will be described below. Normally, a hardware debugger is configured by combining some semiconductors with a function for debugging. Again, each element is a dedicated semiconductor.

An operation example of the conventional technique will be described with reference to FIG. FIG. 3 shows an example of a circuit configuration for debugging a conventional debugged CPU. The debug circuit of the conventional example includes a debugged CPU 31, a register 32, a trace RAM 3
3, bidirectional buffer 34, inverter 35, buffer 3
6, AND element 37, AND element 38, main memory 39, system bus 40, address register 41, main memory 42 of the debugged device, address bus 43 of the debugged device,
It comprises a system bus 44, a program development device host processor bus 45, an address information output timing signal 46, a mapping information signal 47, a counter 52, a flip-flop 53, an AND element 54, a clock signal 55, and other components and a signal system. You.

In the conventional debug circuit having the above configuration,
When the address information is output from the debugged microprocessor (CPU) 31 to the bus 44 and subsequently the address information output timing signal 46 is output, first, the address information output timing signal 46 is input to the write signal terminal of the RAM 33. The contents of the counter at that time are RA
Written to M33. The address information output timing signal 46 is applied to the clock terminal of the register 32,
4 is stored in the register 32 and stored in the RAM 3
The address input 3 changes. The corresponding contents of the RAM 33 are read out by the updated address, and the counter 5
2 and is taken into the counter 52 by the address information output timing signal 46.

On the other hand, the debugger sets a flip-flop (F / F) 53 connected to a host processor bus (simply referred to as a bus) 45 of the program development apparatus in order to start measuring the operating characteristics of the developed program. A
The gate of the ND element 54 opens and the unit time clock signal 55
Is applied to the count-up terminal of the counter 52. The counter 52 starts counting up from a value preset by the RAM 33. This count-up operation is continued until the next address information output timing signal 46 is output from the microprocessor 31 to be debugged.

When the timing signal 46 is output,
At that time, the value of the counter 52 is written to the same storage location of the RAM 33, and the same operation as described above is repeated with the updated address after the writing. Therefore, assuming that the debugged microprocessor 31 accesses the addresses A, B, and A and the main memory by the program, the storage location corresponding to the address A in the RAM 33 is accessed by the above operation. The accumulated time is stored as a count value. Furthermore, RAM3
3 is a part of the address output of the register 32, for example, only the upper 8 bits, so that 256
The program execution time can be measured with the subsequent blocks.

As another conventional example having a technical field similar to that of the present invention, a "program development device" disclosed in Japanese Patent Application Laid-Open No. S59-57355 discloses a register for storing address information output from a microprocessor, a storage device, and a counter. And the counter measures the elapsed time from when the address information is output, and stores the content in the storage device every time the address is updated. Thus, the execution time of each disposal of the program is detected. This function corresponds to the conventional example shown in FIG.

[0012]

However, these methods have several disadvantages. Using a software simulator on a personal computer or workstation and using software alone to measure it takes an enormous amount of time to execute. In the sound system, data must be input for at least a few seconds and measured. A typical software simulator requires 1000 hours of actual operation.
Since it takes about 1 to 10000 times, it takes more than 5000 seconds to execute data for 5 seconds, for example. This would take an enormous amount of time to debug. It is also difficult to create input data. Such a system causes the following problem.

First, in order to measure the processing execution time, the value counted by the address information timing signal is stored in a RAM.
It is written in. This indicates that RAM is essential. The larger the address range, the more memory is needed.

Further, such a system cannot be applied to a very high-speed CPU these days. Because the CPU
Due to the work of counting outside the CPU and writing it to the RAM based on the output of
This processing cannot be performed within one instruction execution time of U. In other words, when the measurement is performed, a state occurs in which the real-time operation of the CPU has to be delayed for the measurement.

[0015] In the case of a high-speed CPU, especially a signal processor called a DSP, this problem is particularly remarkable.
Some recent DSPs have a simple program debugging function inside the device. When realizing such a function inside a semiconductor, such a delay is generally not a problem compared to a case where a dedicated device is combined.

Further, in order to reduce the amount of memory and perform measurement, the width of the address must be limited as described above. This means that measurement can be performed only in block units. In the prior art example, measurement is performed in units of 256 words.
They are organized in 256 word blocks and are not neatly placed. Therefore, when trying to measure all applications, it is necessary to measure all blocks in which the application is located.
This would be less rigorous.

In order to correctly measure such a module, it is necessary to measure the addresses of all the modules to determine the processing time, which requires an enormous amount of memory. Further, since the means for starting the execution is only from the program development device, it is not possible to detect the state of a certain CPU and start it by using the state as a trigger, which is inconvenient.

An object of the present invention is to provide a microprocessor with a built-in debugger which is simple and convenient.

[0019]

In order to achieve the above object, a microprocessor with a built-in debugger according to the present invention inputs an operation state of a predetermined CPU as detected data and outputs a detection result of the detected data. An output unit, two event detectors for comparing a predetermined held reference value with the detected data and outputting the result of the comparison, a counter for counting the output result, and a counter for detecting one of the events. A counter control unit that sets a countable state based on the result of the unit, and sets a count stop state based on the detection result of the other event detection unit, wherein a predetermined CPU and a debug function unit that debugs a program operation of the CPU are provided. It is characterized by being formed on one semiconductor.

The above-described counter control detection section causes the counter to perform a count operation based on a count clock which is a count-up signal, and outputs the count-up signal.
It is good to be the execution clock of CPU.

The event detecting section compares the reference value with the count number of the counter, and outputs a count end signal to the counter control section when the comparison result matches. It is preferable that a holding unit for holding the data is provided, and the holding unit holds the reference value input through the input / output unit.

Furthermore, the microprocessor with a built-in debugger has at least two sets of event detectors, one set of two event detectors, a holding circuit for holding the count value of the counter, and a reading circuit for reading the count value. , The execution period of the CPU may be grasped.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a microprocessor with a built-in debugger according to the present invention will be described in detail with reference to the accompanying drawings. Referring to FIGS. 1 and 2, there is shown an embodiment of a microprocessor with a built-in debugger of the present invention.

<Embodiment> FIG. 1 is a block diagram showing a circuit configuration of an embodiment of a microprocessor with a built-in debugger according to the present invention. The microprocessor with a built-in debugger (hereinafter, also simply referred to as a semiconductor 1) of the present embodiment includes a CPU 2 and a debugger. The debugger includes an input / output unit 3, event detection units 4 and 5, a counter control unit 6, a counter 7,
It consists of each part of.

The signal relations of the main parts of the semiconductor 1 of this configuration include a count-up signal 8, CPU execution state data 9,
Execution state data 10, count start signal 11, count end signal 12, data bus 13, data bus 14, counter control line 15, data bus 16, reset signal 17,
Count start control signal 18, count end control signal 1
9, a data bus 20, an operation clock 21, and the like. The semiconductor 1 is configured so that predetermined data can be input / output to / from the debugger via the input / output unit 3 from the outside via the data bus 20.

First, the condition for starting the counting is set as reference data in the event detecting unit 4 through the input / output unit 3 described above. Various conditions can be considered for this condition, but they are not specified here. For example, the CPU generates an interrupt or accesses a specific address. Similarly, a condition for terminating the count is set in the event detection unit 5. These event detectors are CP
The state of U1 is input as CPU execution state data. The reference data set in the event detection unit 4 and the event detection unit 5 are compared with CPU execution state data input from the CPU 1.

The counter control section 6 has a function of controlling the counter 7. Commands for controlling the counter 7 are input through the input / output unit 3. The counter 7 is controlled by a reset signal 17 for resetting the counter 7, a control line 15 for presetting data, a data bus 16, and the like.

First, the event detector 4,
Then, a reference value is set in the event detection unit 5. Next, a command to make the counter 7 countable is issued from outside the semiconductor 1 through the bus 13 to the counter control unit 6. This may be a control signal instead of a command. In such a state, the event detection unit 4 compares the state of the CPU 2 with the set reference value.
If they match, the event detection unit 4 outputs the count start signal 11 to the counter control unit 6. When output, the counter control unit 6 outputs a count start signal 18 to the counter 7.

As a result, the counter 7 performs a counting operation based on a count clock 8 which is a count-up signal. As this count-up signal, usually, the CPU
2 are input. Further, the event detector 5 compares the state of the CPU 2 with a set reference value. If they match, the event detection section 5 outputs the count end signal 12 to the counter control section 6. When output, the counter control unit 6 outputs a count end signal 19 to the counter 7. When the end signal 19 is input, the counter 7 stops counting. Thereafter, the data of the counter 7 is read via the input / output unit 3.

How this is used for measuring the execution time of an application will be described below. First, the execution start address of the application to be measured is set in the event detection unit 4, and the execution end address is set in the event detection unit 5. For example, starting an application on a real-time OS is usually an interrupt,
What is necessary is just to set the address of a certain interrupt process. CPU
When 2 accesses the execution start address, the counter 7 starts counting and continues until the end condition is satisfied by the event detection unit 5. By reading the value of the counter 7, it is possible to know how long it took.

<Application Example of Embodiment> FIG. 2 is a circuit configuration block diagram of an application example using the microprocessor with a built-in debugger of the above embodiment. In this application example, the event detection unit 104 is added to the semiconductor 1 described in the embodiment.
And 105, counter value holding circuits 108 and 10
9, a readout circuit 112.

In the above embodiment, the event detectors 4 and 5 are provided as one set. However, in this application example, one set of the event detectors 104 and 105 is further added. , 105, and a reading circuit 112 for reading the values held by the counter holding circuits 108, 109 are added.

The event detectors 104, 10 of the above components
In 5, in the same manner as in the event detection units 4 and 5 described in the first embodiment, CPU execution state data is input from the CPU 2 through the signal line 100. Similarly, the condition for starting the count is set to the signal line 1 through the input / output unit 3 described above.
01 and 103 are set as reference data in the event detection units 104 and 105.

The counter value holding circuits 108 and 109 hold the counter values based on the event coincidence signals 106 and 107 output from the event detectors 104 and 105. For example, the first address of the module in the event detection unit 104 is set as a comparison value, and the last address of this module is set in the event detection unit 105 as a comparison value. First, the counter 7 starts operating.
Thereafter, when the CPU enters the state set by the event detection unit 104, an event coincidence signal 106 is output from the event detection unit 104, and the counter value at that time is held in the holding circuit 108 based on this signal. When the processing in the CPU further proceeds and reaches the value set in the event detection unit 105,
A match signal 107 is output from the event detection unit 105,
The counter value at that time is held in the holding circuit 109 based on this signal.

Next, the data set in the holding circuits 108 and 109 are read through the reading circuit 112.
By looking at the difference between these values, it is possible to grasp the period of execution.

The above embodiment is an example of a preferred embodiment of the present invention. However, it is not limited to this.
Various modifications can be made without departing from the spirit of the present invention.

[0037]

As is apparent from the above description, the microprocessor with a built-in debugger of the present invention inputs the operation state of a predetermined CPU as data to be detected, outputs the detection result of the data to be detected, The stored reference value is compared with the detected data, and the result of the comparison is output. A debug function unit that controls the count of the output result and debugs the program operation of the CPU is formed on one semiconductor. According to this configuration, since the RAM is not required, the circuit size is compact, so that it can be mounted in one semiconductor. In addition, counting can be started and stopped at an arbitrary address, and the accuracy and usability are improved.

[Brief description of the drawings]

FIG. 1 is a circuit configuration block diagram of an embodiment of a microprocessor with a built-in debugger of the present invention.

FIG. 2 is a circuit configuration block diagram of an application example.

FIG. 3 shows a circuit configuration example of a conventional debugger for debugging a debugged CPU.

[Explanation of symbols]

 Reference Signs List 1 semiconductor 2 CPU 3 input / output unit 4 event detection unit 5 event detection unit 6 counter control unit 7 counter 8 count-up signal 9 CPU execution state data 10 CPU execution state data 11 count start signal 12 count end signal 13 data bus 14 data bus 15 Counter control line 16 Data bus 17 Reset signal 18 Count start control signal 19 Count end control signal 20 Data bus 21 Operation clock 104, 105 Event detector 106, 107 Event coincidence signal 108, 109 Counter holding circuit 112 Reading circuit

Claims (6)

[Claims] An input / output unit for inputting a predetermined CPU operation state as detected data and outputting a detection result of the detected data, comparing a predetermined held reference value with the detected data. Two event detectors that output the result of the comparison, a counter that counts the output result, and a counter that can count based on the result of the one event detector, and the other event detector A built-in debugger, comprising: a counter control unit for setting a count stop state according to a detection result of the above; and the predetermined CPU and a debug function unit for debugging a program operation of the CPU are formed on one semiconductor. Microprocessor. 2. The apparatus according to claim 1, wherein the counter control detection section causes the counter to perform a count operation based on a count clock that is a count-up signal.
A microprocessor with a built-in debugger as described. 3. The CPU according to claim 2, wherein the count-up signal is supplied to the CPU.
3. The microprocessor with a built-in debugger according to claim 1, wherein the clock is an execution clock. 4. The apparatus according to claim 1, wherein the event detector compares the reference value with a count number of the counter, and outputs a count end signal to the counter controller when the comparison result matches. The microprocessor with a built-in debugger according to claim 1. 5. The event detection unit according to claim 1, further comprising a holding unit for holding the reference value, wherein the holding unit holds the reference value input via the input / output unit. The microprocessor with a built-in debugger according to any one of 1 to 4. 6. The microprocessor with a built-in debugger includes a pair of the two event detectors as at least two.
2. The system according to claim 1, further comprising: a set of event detectors, a holding circuit for holding the count value of the counter, and a reading circuit for reading the count value, so that the execution period of the CPU can be grasped. 6. The microprocessor with a built-in debugger according to any one of items 1 to 5.