JP2001297012A - Processor and emulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide technology which performs emulation in a state as close to actual operation as possible. SOLUTION: A microprocessor (212) is formed including a 1st CPU (101) which can execute a user program, a 2nd CPU (119) which can execute a program for emulation independently of the 1st CPU, a 1st bus (I-BUS) which is connected to the 1st CPU, a 2nd bus (E-BUS) which is connected to the 2nd CPU, and a bus connecting means (111) which can connect the 1st and 2nd buses. Even if a break condition is met during the emulation, the execution of the user program by the 1st CPU is not stopped to put the emulation closer to the actual operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emulation technology, and more particularly to a technology effective when applied to, for example, a microprocessor and an emulator equipped with an emulation processor.

[0002]

2. Description of the Related Art In order to develop an application system using a single-chip microcomputer, a microcomputer development apparatus called an in-circuit emulator is used. The microcomputer development device includes a system development device such as a personal computer and an application system (user system) under development.
Is connected via a cable or the like, and acts as a debugger while acting as a single-chip microcomputer (target microcomputer) to be mounted on the application system. Support development. This microcomputer development device is equipped with an evaluation emulation processor called an evaluation chip corresponding to the single-chip microcomputer. The emulation processor facilitates development of microcomputer development equipment by adding functions dedicated to outputting the internal state of the microcomputer and controlling the operation of the microcomputer to the functions including the single-chip microcomputer. To be.

[0003] As for the in-circuit emulator,
For example, "LS" issued by Ohmsha on November 30, 1984
I Handbook "P562 and P563, and the emulation processor
For example, it is described in JP-A-63-106840.

A function dedicated to the emulation processor is that when a central processing unit (abbreviated as “CPU”) accesses a predetermined address, the CPU is stopped.
It has a break function for transferring control to the emulator side, and at the time of such a break, executes a program dedicated to emulation, and performs processing necessary for desired debugging under this program.

[0005] Examples of processing necessary for debugging include displaying a user's memory after a break once,
There is a function to change. This is called a memory command.

There is also a function of intermittently sampling and displaying the contents of the memory of the user system during execution of the user program. This is called a window function. These features actually break at regular intervals,
This is realized in such a procedure that, when a desired memory is monitored, execution of the user program is continued.

[0007]

The present inventor has studied such an emulator and an emulation processor, and found the following problems.

First, there are the following problems with the break.

When a break occurs, a program dedicated to emulation is executed, and execution of the user program is stopped. Since a break waits for a user to input a command, the break lasts longer than the operation of the user system. The user program has various tasks and the like, and there is also a task of performing mechanical control such as driving a motor of a user system. The task is switched by an interrupt or the like. If these do not operate due to a break, inconvenience may occur in the mechanical part of the user system.

For this reason, it is desirable that the execution of the user program can be continued even if a break occurs. In other words, it is desirable that a desired debugging process can be executed during the execution of the user program.

As in the above window function, there is a procedure in which a break is performed once, a predetermined debugging process is executed, and then the execution of the user program is resumed. In this case, the following overhead occurs.

Since a break is executed as an exception process of a CPU (central processing unit), a stack or vector read,
Alternatively, it is necessary to cancel the prefetched instruction. In the break processing routine, it is necessary to save general-purpose registers in preparation for resuming execution of the user program. Since it is difficult to use a vector according to the type of the debugging process, it is necessary to perform a process of determining which debugging process is to be performed. Since the debugging process is implemented by executing a predetermined instruction, it involves a larger number of instruction read operations than required data read or write operations. After the end of the debugging process, it is necessary to restore the saved general-purpose register. In order to resume the execution of the user program, it is necessary to execute a return (return) instruction and perform processing such as unstacking. The program at the time of such a break is often executed on a relatively low-speed memory dedicated to emulation, but this further increases the processing time at the time of a break.

In the case of controlling a device such as a motor, it is necessary to perform control so that a process corresponding to a predetermined event is completed within a predetermined time due to restrictions on a device to be controlled. Further, it is necessary to complete required processing within the time constraints of the entire system. Further, since events may occur simultaneously, in such a case, the respective constraints must be satisfied. For this reason, even if it is temporary, it is not preferable to interrupt the execution of the user program by a break.

As described above, although it is necessary to minimize the overhead and the time for the debugging process, the related art has not sufficiently improved the above.

Second, analyzing the operation of the CPU has the following problems.

The dedicated functions of the emulation processor include a signal indicating operation of the CPU, a signal for identifying instruction read / data access, a signal indicating that the read instruction has been loaded into the CPU, and the start of execution of the loaded instruction. And a function for outputting a signal indicating the start of execution of exception processing, a CPU status signal indicating the start of exception processing, and the like, to enable analysis on the emulator. These CPU status signals are described, for example, in Japanese Patent Application Laid-Open No. 9-198272.

The operation of a CPU, which is a main object of debugging, is complicated by speeding up by various methods such as a multi-stage pipeline. Due to the complicated operation of the CPU, it becomes difficult to analyze the operation with a limited number of CPU status signals. Although it is possible to output all the internal states of the CPU from the emulation interface and use it for such operation analysis, the number of terminals of the emulation processor is increased.

As a programming model, the internal registers of the CPU usable on the user program, that is, the states of the general-purpose registers and the condition code registers, exist only inside the CPU as a functional module and can be monitored or monitored. Cannot be the condition of a break. In order to monitor such contents, there is no alternative but to output the contents of the general-purpose register and the condition code register by executing a program for emulation by breaking. Although it is possible to output all registers inside the CPU from the emulation interface and use them for monitoring and breaks,
That would increase the number of terminals of the emulation processor. In particular, the number of bits of the general-purpose register is large, for example, 32 bits × 8, and it is not practical to output all of them.

Third, there are the following problems in the form of the emulator.

When an emulator is connected to an application system (user system) under development via a cable or the like, and the function of a single-chip microcomputer (target microcomputer) to be mounted on the application system is substituted, the cable must be connected. This may cause noise or an undesired delay in the analog signal. In particular, for example, in a servo control of a VTR (video tape recorder) or an optical disk, an analog signal is detected, processed, and analog output is performed. Loss of control, single-chip microcomputer (target microcomputer)
Function cannot be substituted. If servo control cannot be performed, data cannot be read, and debugging of other tasks becomes difficult.

For this reason, it is necessary to use the emulation processor in a state where it is mounted on the user system or the like, and to make analog signals and the like equivalent to the actual use state. Since it is not preferable to change the substrate of the user system, the package shape and the number of terminals of the emulation processor need to be equivalent to those of a single-chip microcomputer.

In a portable device such as a camera or a camera-integrated VTR, there is little room for connecting a cable because the user system itself is small. Furthermore, in order to debug them in the actual use state, that is, in the outdoors, it is necessary to reduce the size of the housing of the emulator.

An object of the present invention is to provide a technique for performing emulation as close to actual operation as possible.

Another object of the present invention is to facilitate CPU analysis in emulation.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0026]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, a first CPU capable of executing a user program, a second CPU capable of executing an emulation program independently of the first CPU, a first bus coupled to the first CPU, and a second CPU. A microprocessor is formed including the coupled second bus and bus connecting means capable of coupling the first bus and the second bus.

According to the above means, the second CPU is
The emulation program is executed independently of the first CPU. Therefore, even when the break condition is satisfied, there is no need to stop the execution of the user program in the first CPU, and the execution state of the user program in the first CPU is as close to the actual operation as possible. And emulation in a state as close to actual operation as possible.

At this time, in order to make it possible to read or write the resources arranged in the address space managed by the first CPU while minimizing the operation stop time of the first CPU, it is necessary to connect to the first bus. And the first CP
U enables access from the first CPU by being arranged in an address space managed by U, and allows access from the second CPU by being arranged in an address space managed by the second CPU. It is also advisable to provide enabled resources.

In order to suppress the increase in the number of terminals in the microprocessor having the emulation function as described above, the microprocessor is connected to the second bus and exchanges data for emulation between the second CPU and the outside in a serial format. It is good to provide a debug interface for performing this.

Resources that do not exist in the address space managed by the first CPU, such as general-purpose registers and instruction registers in the first CPU, are transferred to the second CP.
By arranging in the address space managed by U, it is possible to monitor and trace general-purpose registers and instruction registers in the first CPU without increasing the number of terminals of the microprocessor, and to display them on a system development device. Further, by enabling setting of break and trace conditions, analysis of the first CPU is facilitated.

An emulator including the microprocessor having the above-described configuration and a host interface for enabling signal exchange between the microprocessor and the system development device can be configured.

[0033]

FIG. 2 shows an example of the configuration of an emulator according to the present invention.

The microcomputer development device (emulator) shown in FIG. 2 includes a microcomputer development device main body (emulator main body) 204 and an interface cable 203. The microcomputer development device main body 204 is connected via an interface cable 203 between a system development device 213 such as a personal computer and a microcomputer application system (user system) 200 under development, and the microcomputer application system 200 It acts as a debugger while acting on behalf of the function of the target microcomputer to be mounted on the microcomputer, and supports the development of software executed by the target microcomputer and the microcomputer application system 200.

Microcomputer development device main body 204
A connector 202 that can be connected to the target microcomputer mounting area 201 in the microcomputer application system 200 is attached to the end of the interface cable 203 pulled out from the connector cable 202. The connector 202 is connected to the target microcomputer mounting area 201. Thus, various signals can be exchanged between the microcomputer application system 200 and the microcomputer development device main body 204.

Microcomputer development apparatus main body 204
Although not particularly limited, the emulation microcomputer 212, the emulation memory 206,
Real-time trace circuit 207, break control circuit 2
08, a host interface 210, and a control processor 211.

The emulation processor 212 includes:
Connected to emulation bus 205. The emulation bus 205 transmits a status signal, a control signal, and the like (not shown). From the emulation processor 212 to the emulation bus 205,
Information and the like according to the internal states of the microcomputer application system 200 and the emulation processor 212 are output. Further, various control signals for emulation are taken into the emulation processor 212 from the emulation bus 205. When the emulation mode terminal (not shown) of the emulation processor 212 is fixed at the power supply level, the emulation mode is set inside the emulation processor 212.

Further, the emulation bus 205
Although not particularly limited, an emulation memory 206 such as a RAM serving as a substitute for the built-in memory of the microcomputer application system 200 or the target microcomputer is provided. The emulation memory 206 includes a high-speed memory unit to act as a substitute for the built-in ROM, and a lending memory unit to be released to the user.

When a user's program is created, a design is often made with sufficient capacity, and the program itself may not fit in a built-in ROM or the like. In such a case, the user can use the lending memory unit in the emulation memory 206 to substantially expand the program memory and perform debugging. As the debugging progresses, the program can be optimized so as to fit in a predetermined capacity. The rental memory unit does not necessarily require high speed due to its characteristics.

The break control circuit 208 monitors the control state of the emulation processor 212 and the state of the emulation bus, and when the state reaches a preset state, asserts an emulator-dedicated interrupt and causes the CPU to execute the interrupt. The execution of the user program is stopped, and a transition is made to the emulation program execution state.

The break control circuit 208 outputs a break (B
RK) signal to an emulation processor. The break may be requested by a break control circuit inside the emulation processor 212 in addition to the BRK signal. The break function built into the emulation processor 212 is high-speed because a signal inside the microcomputer can be used, but is fixed for each emulation processor 212. On the other hand, the break control circuit 208 can generally realize various functions. Also, the number of channels and the like can be arbitrarily set.

The real-time trace circuit 207 has a CP
U based on a signal indicating a read or write operation of U, a signal indicating an instruction read operation, etc.
Real-time tracing that sequentially stores addresses, data, and control information given to 05 is enabled.

The emulation memory 206, break control circuit 208, real-time trace circuit 207
Are connected to a control bus 209 and are controlled by the control processor 211 via the control bus 209. Control bus 2
09 denotes an emulation memory 206, a real-time trace circuit 207, a break control circuit 208, a control processor 211, and a host interface 2
10 This host interface 210
Is connected to the system development device 213, and various signals can be exchanged between the microcomputer development device main body 204 and the system development device 213.
For example, a program input from the system development device 213 is transferred to the emulation memory 206. This program, which should normally be located on the built-in ROM, is sequentially read from the emulation memory 206 and executed by the emulation processor 212. In addition, a break condition and a real-time trace condition in the execution of the program are also provided from the system development device 213 via the host interface 210.

The control processor 211 uses a dedicated debugging interface (DBGIF) to
Communication can be performed with the emulation processor 212.

The system development device 213 is, for example, a personal computer, and includes an appropriate input device 215 such as a keyboard and a mouse, and a display device 214 for displaying various information.

FIG. 1 shows a configuration example of the emulation processor 212.

The emulation processor 212 shown in FIG. 1 is not particularly limited, but includes a microcomputer unit 100, an emulation buffer 122, a break interface (BRK) 116, a trace interface (TRC) 115, a monitor interface (MON) 114, Data replacement circuit (CHM) 113,
Emulator dedicated interrupt control circuit (IRQCR) 11
7. Debugging interface (serial communication interface for debugging: DBGIF), emulation CPU (EMLCPU) 119, emulation program memory (EMLROM) 12
0, emulation data memory (EMLRAM) 1
21 and is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

The microcomputer unit 100 has a CPU
101, direct memory access controller (DM
AC) 102, ROM 103, RAM 104, interrupt controller (INT) 105, bus arbiter (BAR)
B) 112, I-BUS controller (I-BSC) 1
11, P-BUS controller (P-BSC) 109,
An external bus controller (EX-BSC) 110 and an input / output unit 106 are included.

Although not shown, a clock signal generated by a single clock oscillator is widely used by the emulation processor 212. For example, CPU 101
And the EMLCPU 119 operate on a common clock.
The ROM 103 and the RAM 104 are not used during emulation, and their functions are replaced by an emulation memory 206 in the microcomputer development device main body 204 via an emulation interface. The input / output unit 106 is an I / O (input / output circuit)
107 and a buffer (BUF) 108. I / O
(I / O circuit) 107 is a timer, SCI (serial
Communication interface), A / D (analog / digital) circuits, and input / output ports. The buffer (BUF) 108 buffers an address bus, a data bus, and a bus control signal.

Although not particularly limited, the CPU 101, the EM
The instruction of the LCPU 119 is performed in units of 16 bits, and data access is also performed in units of 8/16 bits.

As circuits for controlling the bus, a bus arbiter (BARB) 112, an I-BUS controller (I-BSC) 111, a P-BUS controller (P-BSC) 109, an external bus controller (EX)
-BSC) 110 and the like, which are collectively referred to as a bus controller. Although not shown, the bus controller 17 includes a module select (MS) and a bus control register.

The interrupt controller (INT) 105
Receives an interrupt signal output from an I / O (timer, SCI, input / output port) 107, outputs an interrupt request signal and a vector number to the CPU 101,
02 is output as a start request.

As an internal bus, I-BUS (IAB, I-BUS
DB), P-BUS (PAB, PDB), E-BUS
(EIAB, EIDB) are provided, and various signals can be exchanged between the functional modules. Each of the internal data buses IDB, EIDB, and PDB has a 16-bit configuration.

CPU 101, ROM 103, RAM
100 is connected to I-BUS (IAB, IDB),
EMLCPU119, EMLROM120, EML
The RAM 1021 is an E-BUS (EIAB, EIDB)
It is connected to the.

E-BUS is a bus controller (IB)
SC), connection to the I-BUS is enabled and
-BUS can be connected to P-BUS via a bus controller (P-BSC). P-BS
C controls a peripheral bus (P-BUS) composed of PAB and PDB.

CPU for emulation (EMLCP
U) 119, emulation program memory (EM
LROM) 120, emulation data memory (E
An MLRAM 121 and a debugging interface 118 are provided as dedicated blocks for emulation. Further, a break interface (BRK) is provided for interfacing with the microcomputer unit 100.
116, a trace interface (TRC) 115, a monitor interface (MON) 114, and a data replacement circuit (CHM) 113 are provided. Break interface (BRK) 116, trace interface (TR)
C) 115 and the monitor interface (MON) 114 are supplied with CPU internal information such as the contents of general-purpose registers. In particular, the monitor interface (MON) 114
Displays the contents of a general-purpose register, a program counter (PC), a condition code register (CCR) or an instruction register (IR) in an address space managed by the EMLCPU 119, and
9 is possible. In addition, an emulation-dedicated control register (not shown) is provided to perform break control, bus control, module selection control, and the like.

An emulation CPU (EMLCP
U) 119 is an emulation program memory (E)
The emulation is controlled by executing a program stored in the MLROM (120). At this time, an emulation data memory (EMLRAM) 121 is used as a work area, and commands are input and status is displayed by a debugging interface (DBGIF) 118. The debugging interface 118 includes a data line (transmission and reception, or transmission / reception), and uses several signals as an interface, such as a synchronous clock and a transmission request, as necessary.

Further, as necessary, resources such as an internal I / O register of the CPU 101 to be emulated are read or written via the bus controller (I-BSC) 111. The bus right (BAK) at this time is output to the emulation interface.

A break / monitor interface (not shown) can display resources (such as general-purpose registers of the CPU 101) that do not exist in the address space managed by the CPU 101, change data at a desired address, and the like. .

An emulator-specific interrupt EMLIRQ is input, and an interrupt is requested to the EMLCPU 119. Enabling or disabling of the emulator dedicated interrupt EMLIRQ is performed by the emulator dedicated interrupt control circuit (I
RQCR) 117.

Normally, the bus state of the target CPU 101 is output to the emulation bus.

As a part of the emulation interface, EMLBUF1 for controlling the emulation bus
22 are provided.

The EX-BSC controls an external bus,
At this time, the bus width and the number of access states are appropriately selected according to the contents of the bus control register.

The EMLBUF 122 controls an emulation bus included in the emulation interface. At this time, if an emulation bus cycle is selected, the contents of the bus control register and the like are ignored, and access is performed according to the bus specifications of the emulation bus. The emulation bus cycle is executed by the CPU 101
Is performed when a break occurs or when an address corresponding to an external address is read or written by setting a predetermined control bit. These are specified by a predetermined emulation control register setting and a break acknowledge signal (BRKAK), and control the user bus and the emulation bus, and permit or prohibit a wait request from the emulation side.

P-BSC109, EX-BSC110,
When the EMLBUF 122 is activated, an address bus and various strobe signals are output at a predetermined timing,
Data bus input / output is performed.

The bus arbiter 112 includes the CPU 101 and D
By inputting a bus right request signal of the MAC 102 and the EMLCPU 119 and performing arbitration of the bus right, any one of the bus masters (the CPU 101, the DMAC 102, the EMLCPU 1
19) The bus right is given.

The address is determined based on the bus command of the bus master to which the bus right has been given and the bus IAB, and the bus control register, the emulation control register (MEMC / EWTCR registers, WD1,
0 bit), the access destination and the access method are determined, and the I-BSC 111, P-BSC 109, EX-B
The SC 110 and the EMLBUF 122 are activated. P-B
Even if SC109 and EX-BSC110 are activated,
EMLBUF 122 is activated for signal output.

That is, when the CPU 101 reads a program from the ROM 103 or reads or writes data from / to the RAM, the operation is performed using the I-BUS. When data is read or written via I / O, P-BUS is used via I-BUS and bus controller. EMLCPU 119 is EM
When reading a program from the LROM 120, or when reading or writing data from / to the EMLRAM 1021 or the debug interface, the E-BUS is used.

At this time, the EMLCPU 119 sets the E-BU
As long as the operation is performed using S, the operation can be performed in parallel with the CPU 101, and the operation of the user program of the CPU 101 is not affected.

The EML CPU 119 can use the IAB and IDB, and further, the emulation bus by acquiring the bus right. Bus arbiter 11
2 is a CP via the emulation interface.
A bus right indication signal indicating which of the U101 and the EMLCPU 119 is in use is output.

When the EML CPU 119 attempts to read or write an address corresponding to the address space managed by the CPU 101, a bus right is requested to the bus controller. The bus controller is a CPU 1
01 or DMAC 102, the bus right is arbitrated and the EML CPU 119 is given a bus right,
Using B and IDB, read or write of the address space managed by the CPU 101 is permitted. EML
When the CPU 119 reads or writes an address corresponding to an internal I / O register or an external address in the address space managed by the CPU 101, similarly to the CPU 101, the P-BUS (PAB, PB
DB) or EX-BUS (external address bus, external data bus).

During the operation of CPU 101, EMLCPU 1
Emulation operation 19 can be performed using independent buses EIAB and EIDB. This allows the CPU
101 is capable of executing a user process without a break. For example, when the SCI reception process is being performed, the reception of the SCI is not undesirably interrupted. Can be avoided. Further, for the same reason, when the pulse output processing is being performed, the pulse output is not undesirably interrupted, so that, for example, the inconvenience that the motor drive of the user system cannot be performed during the emulation can be avoided. it can.

The emulation interface further includes a break interrupt signal BRK and an emulator wait signal EMLWAIT (not shown) as input signals at the interface to the CPU 101, and a break acknowledge signal BRK as an output signal.
AK, CPU status signal, etc. exist.

The break request includes a BRK interrupt signal, a bus cycle designation register, a break address register (BAR), and a break address mask register (B
AMR), and a register break request by a general-purpose register designation register, a data register, and a data mask register. The address break request and the register break request are transmitted to the CPU via a break control register (BRKCR).

As described in, for example, Japanese Patent Application Laid-Open No. 3-271834, a block dedicated to the emulation processor designates the prohibition of functions built into the emulation processor or the change of operation, and specifies one block. Emulation of a plurality of microcomputers can be performed by the emulation processor. The module selection control is specified by a module selection register (not shown). By setting the module selection register, the microcomputer to be emulated is selected, and the function built in the emulation processor is prohibited or the operation is changed. I do. For example, the number of usable channels of the timer or the SCI is specified, or a valid IOP is specified. Also, the capacity of the built-in ROM and RAM is specified.

FIG. 14 shows a specific configuration example of a main part of the microcomputer unit 100.

The DMAC 102 shares a bus with the CPU 15, and performs data transfer in place of the CPU 15. DMA
The C102 performs data transfer based on transfer information such as a source / destination address and a transfer counter held in an internal I / O register included therein, and writes the data to a transfer destination. In this example, the DMAC 102
Although connected only to the I-BUS (IAB, IDB), when data transfer is being performed by the DMAC 102 (functioning as a bus master), a period during which an internal I / O register inside the DMAC 102 is set (functioning as a bus slave) ), The bus connection state may be switched. For example, when data transfer is performed by the DMAC 102, I-BUS (IAB, IDB) is used, and when setting an internal I / O register inside the DMAC 102, P-BUS (PAB, PDB) is used. The connection state of the bus can be switched in such a manner as to make the connection.

The internal bus includes, in addition to the address bus and the data bus, a bus right request signal, a bus acknowledge signal, a bus command, a ready signal, a read / write signal, and a bus size signal, not shown. The internal address bus includes IAB and PAB. The internal data bus includes IDB and PDB.

These buses are interfaced by a bus controller 17. Bus controller 1
7 is I-BSC111, P-BSC109, EX
-Corresponds to BSC110.

The I-BUS (IAB, IDB) is a CPU
15, DMAC102, ROM103, RAM102,
The IAB is connected to a bus controller 17, and furthermore, IAB is connected to IOPA-C to make it an address bus of an external bus, and IDB is made to a data bus of an external bus
Connected to IOPD, E.

The P-BUS (PAB, PDB) includes a bus controller 17, a timer 20, a pulse output circuit 21,
I18, A / D converter 19, interrupt controller 1
6. Input / output ports IOPA to IOPF and IOP1 to IOP
Connected to OP5.

The bus controller 17 has a function as a bus arbiter and a control function for an I-BUS, a P-BUS, and an external bus (EX-BUS).
Further, a refresh timer or the like may be provided.

The CPU 101 and the DMAC 102 can use the internal bus as an internal bus master.
7 (bus arbiter) arbitrates.

ROM 103, RAM 102, timer 2
0, pulse output circuit 21, SCI 18, A / D converter 1
9. Input / output ports IOPA to IOPF and IOP1 to IOP
The OP5, each functional block of the interrupt controller 16, and the internal I / O register of the DMAC 102 are read or written by the CPU 15 or the DMAC 102 as an internal bus slave.

The interrupt controller 16 controls the timer 2
0, an interrupt signal from the SCI 18, the A / D converter 19, and the input / output port, and outputs an interrupt request signal to the CPU 15 and a start request signal to the DMAC 102. The interrupt controller 16
Captures a clear signal output from the DMAC 102 and outputs an interrupt clear signal.

Input / output ports IOPA to IOPF and IO
P1 to IOP5 are also used for input and output of different signals. For example, the input / output ports IOPA to IOPC are also used for address output, and the input / output ports IOPD, IOPE
Is also used for data input / output, and the input / output port IOPF is also used for bus control signal input / output. The external address bus and the external data bus are respectively I-BUS (IAB, IDB) via buffer circuits included in the input / output ports.
It is connected to the.

The P-BUS (PAB, PDB) is used to read or write a register included in the input / output port 107, and has no direct relationship with an external bus. The bus control signal output includes an address strobe, a high / low data strobe, a read strobe, a write strobe, a bus acknowledge signal, and the like. The bus control input signal includes a wait signal, an external bus request signal, and the like. These input / output signals are omitted in the drawing.

IOP1 is a timer input / output, IOP2
Is a pulse output, IOP3 is an SCI input / output, IOP4 is an analog input, and IOP5 is also used as a DMAC input / output and an external interrupt request (IRQ) input. DMAC10
2. Timer 20, SCI 18, pulse output circuit 21, A
Input / output signals between the / D converter 19 and the input / output ports IOP1 to IOP5 and internal interrupt request signals are omitted in the drawing.

In addition, power supply terminals Vcc and Vss, analog power supply terminals AVcc and AVss, reset input RES,
Standby input STBY, interrupt input NMI, clock inputs EXTAL, XTAL, operation mode input MD0,
Input terminals such as MD1 and MD2 are provided.

FIG. 7 shows an address map in the emulation processor 212. The address is shown in hexadecimal.

The CPU 101 has a 16 Mbyte address space, and the EMLCPU 119 has a 4 Gbyte address space. EMLROM 120, EMLRAM 1021, E
The MLI / O exists only in the address space managed by the EML CPU 119. The EMLI / O includes a control register and a data register included in a break interface, a trace interface, a monitor interface, a data replacement circuit, and the like, and a DBGIF control register and a data register. ROM, RAM, and I / O existing in the address space managed by the CPU 101 are:
It also exists in the address space (H'01000000 to H'01FFFFFF) managed by the EMLCPU 119, and can be accessed when the EMLCPU 119 acquires the bus right of the CPU 101. That is, these are:
Each physical address has a unique logical address in an address space managed by each CPU. These addresses are associated with each other by an address. Specifically, an address obtained by adding H′01 to the upper address of the address of the CPU 101 is the EMLCPU 119.
Address. For example, the start address of the ROM of the target microcomputer is H'000000 in the CPU 101 and H'010 in the EMLCPU 119.
00000.

The EMLCPU 119 receives the address H'01
When an attempt is made to access data from 000000 to H'01FFFFFF, a bus right request is given to the bus arbiter (BARB) 112. The EML CPU 119 is kept in a wait state until the bus right can be acquired. E
By acquiring this bus right, the MLCPU 119 obtains addresses H'01000000 to H'01FFFF.
FF data access becomes possible.

FIG. 13 shows a register configuration of the CPU 101.

The CPU 101 has 32 general-purpose registers having a 32-bit length. All general-purpose registers have the same function, and can be used as both an address register and a data register.

As a data register, 32 bits,
Can be used as 16-bit and 8-bit registers. The address register and the 32-bit register are collectively used as general-purpose registers ER (ER0 to ER7). As the 16-bit register, the general-purpose register ER is divided and used as general-purpose registers E (E0 to E7) and general-purpose registers R (R0 to R7). These have the same function, and up to 16 16-bit registers can be used. As an 8-bit register, the general-purpose register R is divided into general-purpose registers RH (R0H to R7
H), used as general-purpose registers RL (R0L to R7L). These have equivalent functions and can use up to 16 8-bit registers. The method of use can be selected independently for each register.

The general-purpose register ER7 is assigned a function as a stack pointer (SP) in addition to the function as a general-purpose register, and is used implicitly in exception processing and subroutine branching. Exception processing includes the above-described interrupt processing.

PC is a 24-bit counter that indicates the address of an instruction to be executed next by the CPU.

CCR is an 8-bit register that indicates the internal state of the CPU. Interrupt mask bit (I), half carry (H), negative (N), zero (Z),
8 including each flag of overflow (V) and carry (C)
Consists of bits.

EXR is an 8-bit register that controls exception processing such as interrupts. It includes interrupt mask bits (I2 to I0) and trace (T) bits.

FIG. 12 shows a configuration example of the CPU 101 in the emulation processor 212.

The CPU 101 basically includes a control unit 1201
And an execution unit 1202.

Control unit 1201 includes an instruction register IR and an instruction decoder CONT. The instruction decoder CONT
The contents of the instruction register IR are decoded, and a control signal for the execution unit, a bus command output and a CP for emulation are output.
Outputs a U status signal and the like. In addition, other control signals such as reset and interrupt are taken in, and the operation is changed according to the control signal.

The execution unit 1202 includes ER0 to ER7 as general-purpose registers 31 as shown in FIG.
C, a condition code register CCR, and an extended register EXR. Further, the execution unit 1202
Arithmetic logic unit ALU, incrementer INC, read data buffer RDB, write data buffer WDB,
An address buffer AB and the like are provided. These blocks are interconnected by a GB bus, a DB bus, and a WB bus.

Although not shown, each section of the execution section 1202 has a 32-bit configuration, and has a general register E (16).
Bit), H (8 bits), and L (8 bits).

The general-purpose register, program counter,
Other than the condition code register, it cannot be referred to in programming the CPU, and is used only for the operation inside the microcomputer. That is, the read data buffer RDB, write data buffer WDB, address buffer AB, and the like temporarily latch data in order to interface with the internal buses IAB, IDB.

The read data buffer RDB is a ROM,
Instruction codes and data read from a RAM, an internal I / O register, or an external memory (not shown) are temporarily stored. The write data buffer WDB is a ROM,
It temporarily stores write data to a RAM, an internal I / O register, or an external memory.

The address buffer AB temporarily stores an address to be read or written by the CPU.

The arithmetic and logic unit ALU uses various operations specified by instructions and calculation of effective addresses.
The operation result flag is reflected in the condition code register.

The incrementer INC is mainly used for adding the program counter PC.

The target CPU 101 of the emulation processor 212 outputs the contents of a general-purpose register, a program counter, a condition code register, and an instruction register via independent signal lines. These are supplied to the break interface, trace interface, monitor interface, and the like as CPU internal information.

The contents of the WB bus and a selection signal for a general-purpose register may be output to detect the contents of the general-purpose register when it changes.

FIG. 8 shows a trace interface (TRC) built in the emulation processor 212.
A configuration example of 115 is shown.

As shown in FIG. 8, the trace interface 115 is not particularly limited, but may be an R or R such as an SRAM.
It comprises an AM unit 804, a trace control circuit 801, an address selection circuit 807, and a counter 808.

The trace control circuit 801 monitors a predetermined signal in the CPU internal information, and when a write signal of a designated general-purpose register is generated, asserts a trace enable signal (TRCE) to the RAM unit 804. Of the light. Further, the address of the RAM unit 804 can be updated by incrementing the counter 808. The counter 808 is an EMLCP
A predetermined initial value is set by the control of U119.

At the time of tracing, a general-purpose register (32 bits × 8), a program counter (24 bits), a condition code register (8 bits), and an instruction register (1 bit)
6 bits) (including 304 bits)
To be writable. Such writing is performed, for example, in row address units. The row address is a counter 80
8 is specified.

In the break mode (BRKAK = 1), tracing is prohibited. At this time, the trace control circuit 8
Since the operation of the address selection circuit 807 is controlled by 01, the address is not fetched.

Although the RAM section 804 is not particularly limited,
A memory cell array 804 in which a plurality of static memory cells are arranged in an array, an address decoder 806 for decoding an address signal (row address and column address) captured via the address selection circuit 807, An input / output circuit 803 for selecting a data line of the memory cell array 804 based on a decoding result of the column address. RAM section 80
The bus width of the EMLCPU 11 is not particularly limited.
At the time of reading by No. 9, the width is 16 bits in accordance with the data bus width of the EMLCPU 119. Reading is performed according to an E-BUS address (EAB) and a read signal (E-RD). A column address is designated by the address decoder 806, and data is selected by the input / output circuit 803. The contents of the read trace are output to the system development device 213 via the control processor 211 and displayed on the display device 214.

In the state at the time of tracing, a trace acquisition signal (TRCE) is output from the emulation interface. Real-time trace circuit 20
7 stores only this trace acquisition signal. EMLC
Read the contents of the internal trace memory from PU 119,
By displaying it along with the corresponding bus cycle,
The trace list can be displayed.

FIG. 9 shows a configuration example of the break control circuit 208.

The following three factors can be given as break requests to the CPU 101.

The first is a break request from the BRK terminal, the second is an address break, and the third is a register break.

The address break has two channels A and B, and the comparator 913 compares the addresses based on the output values of the bus cycle designation register 910, the address designation register 911, and the address mask bit register 912, respectively. Instruction reading, data reading or writing, and designation of a bus master are performed by the bus cycle designation register 910, and bus control information is to be compared.
The output value of the address designation register 911 is
Is compared with the address (IAB). The address mask bit register 912 does not compare a desired bit (it always regards it as a match). FIG. 9 shows only the channel A. The channel B is similarly configured, and the logic of the address comparisons A and B and the ABIEA and ABIEB bits of a break control register (not shown) is determined by AND gates 914, 915 and OR gate 916. I have.

To enable a register break, a register selection register 901 and a data designation register 902
Then, register comparison is performed based on the register holding the mask bit register 903. A register number and a size (selection of general-purpose registers ER / E / R / RH / RL) are designated by a register selection register 901, and CPU internal information is selected by a selector 905. In addition to general-purpose registers, a program counter (PC),
The condition code register (CCR) and instruction register (IR) can also be specified. The selected CPU internal information, data designation and data mask bit register 9
Twelve output values are compared by a comparator 904. Again, only channel A is shown. The channel B is similarly configured. The register comparisons A and B and break control registers RBIEA and RBIEB (not shown) are performed.
Logic with bits is taken by AND gates 906 and 907 and OR gate 908.

Then, in the OR gate 917, the output logic of the NOR gates 908 and 916 and the OR logic of the break signal BRK are taken to form a break request signal (BRK request signal).

A control register such as the address designation register 911 is connected to the EMLCPU 119 via the E-BUS.
Is set from

FIG. 10 shows a data replacement circuit (CHM) 1
13 shows a configuration example.

As shown in FIG. 10, although this data replacement circuit (CHM) 113 is not particularly limited, it has an address designation register 1131 and an alternative data designation register 113.
3 and a comparator 1132. The address designation register 1131 and the substitute data designation register 1133 are
Writing from the EMLCPU 119 is enabled. EM
When the target CPU 101 reads the address specified by the address register by the LCPU 119, the data register is selected and output instead of the actual address.

The value held in address designation register 1131 is compared with address bus (IAB) in comparator 1132. If the two match in this comparison, the fact is notified to the bus controller (I-BSC) 111. The bus controller 111 refers to the bus control information and refers to the data bus (IDB) of the substitute data designation register.
To control the I-BUS so as to instruct output to the P-BSC 109 and EX
And controlling the BSC 110.

The address designation register 1131 has, for example, 16 sets. I-BUS and P-B
The US may have a predetermined number of sets.

In any of the examples of the emulation processor and the emulator, the program and the like can be changed and tuned without stopping the operation of the emulation processor (target CPU). For example, debugging can be performed while changing parameters on the ROM as needed using a data replacement circuit without changing the ROM, and the debugging efficiency can be improved.

FIG. 11 shows a flow of the operation of the emulator.

After the power is turned on, the EMLCPU 119
The emulation program is executed (S11), and the setting of which microcomputer to operate as the emulation processor (S12), the configuration of the lending memory, and the like are input from the system development device (S11).
13), are set in the respective emulation control registers via the host interface 210 and the control processor 211.

When processing for a desired emulator is performed and execution of a user program is requested based on a command or the like input from the system development device 213, EML is executed.
The CPU 119 permits the operation of the target CPU 101 (S14). The CPU 101 starts the operation from the reset (S21) and executes the user program (S2).
2).

Even when a predetermined user program is being executed, the EML
Since the CPU 119 performs an emulation control operation (input of an emulation command, display of an internal state of the target microcomputer, and the like), the CPU 101
There is no need to break.

When the CPU 101 terminates the user program to be executed or satisfies the condition set by the user, the execution of the user program is interrupted (break), the emulation program is executed, and the CPU 101 enters a standby state (S23). , S24).

When the user program is restarted, the start address of the program is set to the holding address of the returning program counter, and the return instruction (RT
B) is executed (S25).

The target CPU 101 may transition to a low power consumption state depending on the operation state of the system to be controlled. In the low power consumption state, for example, C
There is a sleep mode in which only the PU 101 stops, and a standby mode in which the entire microcomputer stops.

The mode shifts to the sleep mode by execution of the dedicated low power consumption (sleep) instruction. At this time, CPU1
01 is stopped. When an interrupt is requested, the sleep mode is released.

When a low power consumption (sleep) instruction is executed while a predetermined control bit is set to 1,
Transition to software standby mode. At this time,
The clock supplied to the entire microcomputer unit 100 is stopped. When a given external interrupt is requested,
The software standby mode is released.

At this time, even when the microcomputer is stopped, the emulator itself continues to operate.

FIG. 15 shows a configuration example of the low power consumption state control circuit in the target CPU 101.

Although not particularly limited, the target CPU 1
01, the low power consumption state control circuit 151 includes three flip-flops SLPF1, SLPF2, SSBY
F, and three logic gates 51 to 53. The flip-flop SLPF1 has a SLEEP instruction 1
And reset by a CPU interrupt request. The flip-flop SSBYF is SLEE
It is set by the AND logic of the P instruction 1 and the control bit SSBY, and is reset by an external interrupt request. The flip-flop SLPF2 has a SLEEP instruction 2
And reset by an EMLCPU interrupt request. When EMLMOD is a logical value “0”, the EMLCPU stop signal is asserted.
The operation of the LCPU 119 is stopped. When EMLMOD is a logical value “1”, the CPU 101 and the EMLCPU 119
Is operated.

The flip-flop SLPF1 is set when the target CPU executes the SLEEP instruction. At this time, when the CPU stop signal is asserted, the CPU 101 enters a sleep state. CPU101
Is cleared when an interrupt request is issued.

The flip-flop SSBYF is set when the target CPU executes the SLEEP instruction while the control bit SSBY (not shown) is set to the logical value “1”.

When the microcomputer transits to the software standby mode, the operation of all functions including the clock oscillator is stopped. However,
As long as the specified voltage is applied, the contents of the RAM are retained. The state of the input / output port is also maintained. When an external interrupt request occurs, the state is cleared.

In the emulation processor 212,
In the emulation mode (EMLMOD = 1), when trying to transition to the software standby mode, at least the clock oscillator, the bus controller, and the EMLC
PU 119 continues to operate. The other function blocks are supplied with a module stop signal, and are stopped as in the actual software standby mode.

Therefore, the EMLCPU can operate even in the software standby mode, and the emulator can input commands, change programs and data, and the like.

FIG. 4 shows another configuration example of the microcomputer development device main body 204.

The microcomputer development apparatus main body 204 shown in FIG. 4 is largely different from that shown in FIG. 2 in that it has a first emulation bus 1 and a second emulation bus 2. The emulation memory 206 has a first storage unit corresponding to the first emulation bus 1 and a second storage unit corresponding to the second emulation bus 2. The first storage unit and the second storage unit are readable or writable independently of each other.

The first emulation bus 1 transmits status signals and control signals for tracing and breaking. Through the first emulation bus 1, information corresponding to the application system and the internal state of the emulation processor can be obtained from the emulation processor.

The second emulation bus 2 transmits a required control signal for reading or writing. The emulation processor 212 can read various control programs for emulation using the second emulation bus 2.

The break control circuit 208 and the real-time trace circuit 207 are the same as those shown in FIG. 2, and are connected to the first emulation bus 1 and controlled by the control processor 211 to break the target CPU 101. And do a trace.

FIG. 3 shows an example of the configuration of the emulation processor 212 when the configuration shown in FIG. 4 is adopted.

The emulation processor 212 shown in FIG. 3 is significantly different from that shown in FIG.
As an emulation interface, an emulation buffer (EML) corresponding to the second emulation bus 2 is provided separately from the emulation buffer (EMLBUF) 122 corresponding to the first emulation bus 1.
(LBUF) 123 is provided.

The first emulation bus 1 is connected to the target CPU 101 via an emulation buffer (EMLBUF) 122, while the second emulation bus 2 is connected to an emulation buffer (EML buffer).
(LBUF) 123 to the EML CPU 119. That is, the first emulation bus 1
US (IAB, IDB), and the second emulation bus 2 corresponds to E-BUS (EIAB, EIDB).

Since the program of the EMLCPU 119 can be stored in the emulation memory 206, even if the emulation function is large and the program capacity is large, it can be easily handled. EMLCPU
The reading or writing of the emulation memory 2 by 119 is performed by the EMLROM 120 or the EMLRAM 10.
As in the case of accessing the program 21, execution of the user program in the CPU 101 is not restricted.

FIG. 6 shows another example of the configuration of the emulator according to the present invention.

In FIG. 6, the emulator includes an emulation processor 212, a debugging interface cable 602, and a microcomputer development device main body 204.

The emulation processor 212
It is mounted on the microcomputer application system 200.

Microcomputer development apparatus main body 204
Although not particularly limited, is a card form by PCMCIA, and is detachably mounted in a card slot 604 provided in the system development device 213. A debug interface cable 602 is pulled out from the host interface 603, and a connector is provided at the tip of the bag interface cable 602, and a debugging interface (SCI for debugging) connector area 60 is provided.
1 can be connected to the connector attached thereto.

Microcomputer development apparatus main body 204
Is provided with a host interface 603,
Control processor, emulation memory,
There is no real-time trace circuit or break control circuit. As the emulation memory, a ROM or a RAM built in the emulation processor 212 is used. Breaks and traces are limited to those built in the emulation processor 212.

The emulation processor 212
Dedicated debugging interface connector area 601
Signals can be exchanged with the system development device 213 via the connector attached to the.

The dedicated debug interface (debug SCI) may be a terminal shared with the general-purpose SCI of the target CPU 101. When emulation is executed, it cannot be used as SCI.
The CI can be used in a wide variety of ways, such as an interface with a test jig, which is not always necessary for software debugging. The terminal can be used effectively by making the terminal double.

FIG. 5 shows an example of the configuration of the emulation processor 212 when the configuration shown in FIG. 6 is employed.

The emulation processor 212 shown in FIG. 5 is largely different from that shown in FIG. 1 in that the emulation interface is a debugging interface only.

As the ROM 103 and the RAM 104, those having a built-in emulation processor 212 are used. As the ROM 103, such as a flash memory,
Use an electrically rewritable one. EMLCPU1
With the control of 19, rewriting of the flash memory can be enabled. At this time, the program is loaded from the debugging interface. Further, the RAM 104 may be enabled to perform an overlap operation.

FIG. 16 shows a still camera as an example of the microcomputer application system 200.

An MCU (microcomputer) 160 is provided, and the MCU 160 controls the operation of the whole still camera. Switches and keys 161, dial 162, EEPROM (electrically erasable and programmable read only memory) 163, LED (light emitting diode) 164, LCD
(Liquid crystal display panel) 165 are provided,
Coupled to CU 160. Further, another microcomputer 166 and a debug test circuit 167 are connected to the MCU 1
60. Lens 171, aperture 170, C
A CD 169 and a filter 168 are provided. Further, a motor 173, a driver 172, and an encoder 174 are provided for focus adjustment.

The switches and keys 161 are input to an input / output port (IOP), and detect depression of the switches and keys. The input from the dial 162 or the like is counted by a timer as a two-phase encoder pulse. These inputs are analyzed by the MCU 160 and predetermined control is performed. Depending on the output of the input / output port, the LED 164
And the LCD 165 are controlled. EE via SCI
A PROM (Electrically Releasable Programmable ROM) 163 is connected, and the MCU 160
Via I, desired data can be written or read.

The SCI also provides an interface for another microcomputer (not shown) (not shown).

The light incident from the lens 171 passes through the stop (A
The signal is input to the CCD 171 via the (PT) 170 and is photoelectrically converted. After the unnecessary frequency components are removed by the filter 168 from the CCD 169 output signal, the A / D
It is converted to a digital signal by the converter. Integration is performed for each of the divided areas of the screen, and based on this result, control of autofocus and aperture control is performed. To control the focus, the driver 172 for driving the motor 173
It is controlled based on the timer output. These are PWM
The output may be (pulse width modulation) output, or a combination of a plurality of waveform outputs that can drive a stepping motor by a pulse output circuit. Further, the movement amount of the lens is captured as a two-phase encoder pulse by the encoder 174, and is counted by a timer. Aperture 17
Control of 0 is performed by the output of the input / output port (IOP).

In addition, the camera-integrated VTR only needs to input video data to the above system and add a display function, a recording / reproducing function, and the like.

As is well known, the size of a still camera or a camera-integrated VTR has been reduced, and a package such as a chip size package (CSP) may be used for a semiconductor integrated circuit applied thereto. In such a case, it is difficult to attach a user cable or draw out a wiring. In the present invention, since the debugging interface may be performed using the SCI, it is easy to make the same package with the same pin function as the target microcomputer, and it is easy to use the same package as the CSP. , Can be implemented and evaluated in the same way as the target.

As shown in FIG. 6, since it is only necessary to pull out the SCI wiring from the microcomputer application system 200, it is easy to operate and debug or tune it in an actual use environment such as outdoors. it can. For example, the data substitution circuit can change the control parameters of the focus and zoom movement amounts, and confirm them by actual operation. With a camera-integrated VTR, it is possible to confirm the gain adjustment of video data and the like in actual operation.

In portable equipment such as a still camera and a camera-integrated VTR, the microcomputer frequently transitions to and returns from a low power consumption state in order to reduce power consumption. In the above, by having the EMLCPU 119 for emulation, the transition of the low power consumption state of the target CPU 101 and the return from the state can be performed similarly to the actual microcomputer, and the debugging efficiency can be improved.

An example in which emulation is performed by incorporating a plurality of CPUs is described in Japanese Patent Application Laid-Open No. H10-222395. However, these plurality of CPUs are to be debugged. Emulation cannot be controlled without interrupting the execution of the program. Further, this example describes that a debug port is provided to monitor or change desired data in response to an instruction such as a packet command. Only the functions can be realized, and after all, it is necessary to interrupt the processing to be debugged and perform processing for emulation.

According to the above example, the following operation and effect can be obtained.

(1) Emulation processor 21
2, emulation CPU 119 is built in, and emulation control is performed by emulation CPU 119.
In this case, it is possible to cope with an increase in the speed of the microcomputer and to improve the usability. In addition, the halt of the operation of the target CPU can be minimized, the emulation operation in actual operation can be facilitated, and the debugging efficiency can be improved.

(2) Emulation processor 21
2, the emulation CPU 119, which can operate independently of the target CPU 101, is built in. The emulation CPU 119 has a dedicated debugging interface, and interfaces with the system development device 213, etc.
It is not necessary to stop the program execution at 01.

The emulation CPU 119
By acquiring the bus right of the target CPU 101 and enabling the resources in the address space managed by the target CPU 101 to be readable or writable,
The resources arranged in the address space can be displayed or changed for debugging while minimizing the time during which the operation of the U101 is stopped, and so-called memory commands and window functions can be realized. Since the interruption of the operation of the target CPU can be minimized,
It is closer to actual operation, without impairing real-time performance,
Debugging can be performed.

(3) Resources that do not exist in the address space managed by the CPU 101, such as general-purpose registers in the CPU 101, are transferred to the emulation CP.
To enable monitoring and tracing without increasing the number of terminals of the emulation processor, to display them on the system development device, and to set break and trace conditions without increasing the number of emulation processor terminals As a result, software debugging efficiency can be improved. Since these need not be output to the outside, the number of terminals of the emulation processor does not increase undesirably.

(4) The trace memory 115 is incorporated in the emulation processor 212 so that the operation of resources that do not exist in the address space managed by the CPU 101, such as general-purpose registers and instruction registers, can be stored in the trace memory. The target CPU 101
In addition to improving the efficiency of emulator development, it is possible to further improve the software debugging efficiency.

(5) Emulation processor 21
2 is controlled by the emulation processor 212 so that appropriate information in the emulation processor 212 can be used. In addition, signal delay from the emulation processor 212 to the emulator and emulation can be performed. From the delay to the emulation processor. Then, the emulation processor 212 can be controlled easily and at high speed without increasing the number of input / output signals between the emulation processor 212 and the outside. The time required for determination and control can be shortened. For example, for break control, it is easy to break in a desired instruction execution state,
It is possible to prevent the execution of a few extra instructions.

(6) Even when the target CPU 101 transitions to the low power consumption state and the microcomputer stops, the emulation CPU 119 can operate and the emulator itself continues to operate.
Debugging is continued without requesting a break interrupt from the emulator, and the transition or release of the low power consumption state can be emulated in the same manner as the actual operation of the microcomputer.

(7) Conventionally, an emulation system including a control processor and a break control circuit is realized by one emulation processor 212, so that the system can be downsized.

(8) By having a debugging interface 118 such as an SCI, the terminal configuration of the emulation processor is such that a small number of terminals for the interface are added to the target microcomputer or are used alternately. In addition, the emulation processor and the target microcomputer have the same external shape such as a package, and can be mounted on the same board, thereby enabling debugging in a mounted state. Since a debugging interface consisting of a small number of pins only needs to be prepared on the application system, there is no need to use a so-called interface cable (user cable), which is closer to actual operation and minimizes noise to analog signals. Then, debugging can be performed. Even small devices such as a still camera and a camera-integrated VTR perform debugging in the actual operating environment, that is, while controlling the application system by the target microcomputer, and further change desired parameters. It can be performed. This can contribute to improving the development efficiency of users.

Controllable from the emulation CPU,
By having a circuit that substitutes data at a desired address of the target CPU, the tuning can be further facilitated.

The debugging interface can be changed to a general-purpose SC.
It can be used by switching to a general-purpose SCI, which does not necessarily affect actual use such as equipment control for testing, etc. by using it also as I, and the terminal is effective without greatly reducing usability and debugging efficiency Can be used for

The host interface may be in the form of a PCMCIA card or the like so that it can be directly connected to a system development device such as a personal computer, and the application system and the system development device can be connected. Thus, the emulation system can be reduced in size. Application system,
Debugging and tuning can be easily performed while operating in an actual operating environment such as outdoors.

Although the invention made by the present inventor has been specifically described above, the present invention is not limited to this, and it goes without saying that various modifications can be made without departing from the gist of the invention.

For example, the dedicated debugging interface (SCI for debugging) may be a dual-port RAM. Alternatively, the EML CPU may have an input / output port or the like to realize an arbitrary protocol.

The emulation CPU may make the target CPU compatible and use a common emulation program. The development efficiency of emulation processors and emulators can be improved.

The specific configurations of the CPU 101 and the EML CPU 119 can be variously changed. The number of bits and number of general-purpose registers, the configuration of the condition code register, and the like can be arbitrarily set. Break conditions can also be variously changed. A desired signal or state can be detected by being provided inside the semiconductor integrated circuit. For example, if the program bus and the data bus are independent, such as in the Harvard architecture, storing the data bus in the built-in trace memory allows the data read or write value to be stored without increasing the number of emulation interface terminals. It can be displayed on the trace list, and the debugging efficiency can be improved. Alternatively, if the contents of the instruction register and the program counter are stored in the built-in trace memory, the operation can be easily analyzed even when a plurality of instructions such as superscalar are executed simultaneously.

The size of the address space and the specific circuit configuration of the bus can be variously changed. EMLCPU
The method by which the 119 accesses the address space managed by the CPU 101 may be specified by a control bit such as a window bit without depending on the address. CPU
After setting the upper address or all the addresses of the address space managed by the CPU 101 in a predetermined emulation control register, and reading or writing another predetermined emulation control register, a desired address in the address space managed by the CPU 101 is set. It may be possible to read or write. In this case, E
The address space managed by the MLCPU 119 is
The address space does not need to be wider than the address space managed by the CPU 101. If the logical and physical scale of the EMLCPU is reduced, the emulation processor can be used as a microcomputer. By making the functions of the EMLCPU unnecessary for the microcomputer relatively small, it may be acceptable in comparison with an increase in development costs for developing the emulation processor and the microcomputer as separate semiconductor integrated circuits. So-called system LSI
In cases where many functions of individual systems are incorporated, and therefore the number of products is small and large, developing a separate emulation processor and microcomputer is considered undesirable in terms of development cost and development period. .

The number and types of control signals of the emulation interface can be arbitrarily changed. The input detection of the emulator dedicated interrupt can also be changed. A bit for selecting input detection may be provided.

A plurality of CPUs can be emulated. A microcomputer in which a plurality of CPUs to be emulated simultaneously operate may be used, or an emulation processor in which one of a plurality of CPUs to be emulated exclusively operates. These may be combined. E independently of the CPU to be emulated
What is necessary is just to enable the MLCPU.

The EMLROM 120 has a mask RO
M, PROM, EEPROM, flash memory, etc.
Or even if it is something like a RAM, EMLC
Any memory that stores the program to be executed by the PU 119 may be used.

The number and type of the built-in functional blocks and modules, the number of pins, and the like are not limited at all. A functional block for requesting an interrupt such as a timer and SCI;
Alternatively, there is no restriction on the method of selecting these, such as the type, function, and number of functional blocks to be subjected to interrupt processing such as a pulse output circuit.

The interface cable 203 only needs to connect the microcomputer application system 200 and the emulation processor 212, and any form and connection method can be used.

In the above description, the case where the invention made by the present inventor is mainly applied to an emulation processor, which is a field of application as the background, has been described. However, the present invention is not limited to this. It can also be applied to

The present invention can be applied on condition that at least a target CPU for executing a user program is included.

[0202]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, since the second CPU executes the emulation program independently of the first CPU, there is no need to stop the execution of the user program in the first CPU even when the break condition is satisfied. The execution state of the user program is as close as possible to the actual operation.

Also, the first CP is connected to the first bus.
By arranging in the address space managed by U, access from the first CPU is enabled, and by arranging in the address space managed by the second CPU, access from the second CPU is also enabled. By providing such resources, the resources arranged in the address space managed by the first CPU can be read or written while the operation stop time of the first CPU is minimized.

By providing a debug interface coupled to the second bus for exchanging data for emulation between the second CPU and the outside in a serial format, an increase in the number of terminals in the microprocessor can be suppressed. it can.

By allocating resources that do not exist in the address space managed by the first CPU, such as general-purpose registers and instruction registers in the first CPU, to the address space managed by the second CPU, the number of terminals of the microprocessor can be reduced. Without increasing the CPU
Simplifies the analysis of the first CPU by enabling monitoring and tracing of general-purpose registers and instruction registers, and displaying them on a system development device and setting break and trace conditions. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of an emulation processor used in an emulator according to the present invention.

FIG. 2 is a block diagram showing a configuration example of the emulator.

FIG. 3 is a block diagram illustrating another configuration example of the emulation processor.

FIG. 4 is a block diagram illustrating another configuration example of the emulator.

FIG. 5 is a block diagram illustrating another configuration example of the emulation processor.

FIG. 6 is a block diagram illustrating another configuration example of the emulator.

FIG. 7 is an explanatory diagram of an address map in the emulation processor.

FIG. 8 is a block diagram showing a configuration example of a trace interface built in the emulation processor.

FIG. 9 is a block diagram illustrating a configuration example of a break control circuit in the emulator.

FIG. 10 is a block diagram showing a configuration example of a data replacement circuit built in the emulation processor.

FIG. 11 is a flowchart of a basic operation of the emulator.

FIG. 12 is a block diagram illustrating a configuration example of a target CPU in the emulation processor.

FIG. 13 is an explanatory diagram of a configuration example of a register included in a target CPU in the emulation processor.

FIG. 14 is a detailed configuration example block diagram of a microcomputer unit in the emulation processor.

FIG. 15 is a block diagram illustrating a configuration example of a low power consumption state control circuit in the target CPU.

FIG. 16 is a block diagram illustrating a configuration example of a still camera as an example of a microcomputer application system.

DESCRIPTION OF SYMBOLS 101 CPU 118 DBGIF 119 EMLCPU 111 I-BSC 200 Microcomputer application system 204 Microcomputer development device main body 212 Emulation processor 213 System development device 214 Display device 215 Input device IAB, IDB, EAB, EIDB, PAB, PDB
Internal bus

Claims (5)

[Claims] A first central processing unit capable of executing a user program; a second central processing unit capable of executing an emulation program independently of the first central processing unit; and a first central processing unit. A first bus coupled to the second central processing unit; a bus connection unit capable of coupling the first bus and the second bus; A microprocessor characterized in that it is formed. 2. The communication device according to claim 1, further comprising an address space connected to the first bus and arranged in an address space managed by the first central processing unit. 2. The microprocessor according to claim 1, further comprising resources arranged in an address space managed by the central processing unit so as to enable access from the second central processing unit. 3. A debug interface according to claim 1, further comprising a debug interface coupled to said second bus, for exchanging data for emulation between said second central processing unit and an external device in a serial format. Microprocessor. 4. A resource according to claim 1, wherein resources not existing in the address space managed by said first central processing unit are arranged in an address space managed by said second central processing unit. The microprocessor according to the item. 5. An emulator comprising: the microprocessor according to claim 1; and a host interface for enabling signal exchange between the microprocessor and a system development device. .