JP2001084161A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily generate arbitrary interruption from the outside part of a semiconductor chip. SOLUTION: This data processor is provided with an AUD(advanced user debug) control register 125 which can set information related with an interruption request from the outside part of a semiconductor chip and an interruption control circuit 126 which judges whether or not an interruption condition is fulfilled based on the information set in the AUD control register 125, and generates an interruption request signal based on the judged result. In this case, the information related with the interruption request is set in the AUD control register 125 so that the interruption request signal can be generated by the interruption control circuit 126. Thus, it is possible to simplify the generation of interruption from the outside part of the semiconductor chip.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a data processing device,
Furthermore, regarding the on-chip debug technology in that,
For example, the present invention relates to a technology that is effective when applied to a single-chip microcomputer (referred to as “microcomputer”).

[0002]

2. Description of the Related Art A microcomputer includes a central processing unit (abbreviated as "CPU") and one peripheral circuit.
ROM (Read Only Memory) which is included in a single semiconductor substrate and holds the operation program
Built-in. In microcomputer application equipment, for example, in an engine control device of an automobile, a microcomputer is often directly soldered to a printed circuit board, and in such a case, software cannot be debugged by replacing a real chip with an evaluation chip. . Therefore, a function for tracing the execution state of software in real time and an on-chip debug function for reading / writing data to / from a built-in RAM (random access memory) for debugging are provided. A provided microcomputer is provided.

As an example of a document describing a microcomputer, there is JP-A-55-131848.

[0004]

As means for realizing the on-chip debug function, there is an advanced user debugger. This advanced user debugger has a trace mode for tracing the execution state of a user program by a microcomputer and a RAM monitor mode for monitoring / tuning the operation state of a module connected to an internal bus or an external bus of the microcomputer. And In the RAM monitor mode, the inventors of the present invention have examined the case where an interrupt is generated from outside the microcomputer. As a result, it is necessary to change the interrupt enable bit of the control register corresponding to the desired interrupt and the value of the related internal register It was found to be troublesome.

For example, in order to perform a manual reset from outside the microcomputer, it is necessary to give the following command from a host computer for instructing the operation of the advanced user debugger via a RAM monitor (product).

#M FFFFEC12 5A7F; W (RET) #M FFFFEC12 A59F; W (RET) # M FFFFEC10 5A00; W (RET) # M FFFFEC10 A5F8; W (RET) "RET" indicates a return, and "M" indicates a return.
Indicates a memory display and change command on the RAM monitor.
"FFFFEC10", "FFFFEC12"
Indicates the addresses of arbitrary built-in peripheral modules and registers of the microcomputer. For example, FFFF
Address EC10 is a timer control / status register, and address FFFFEC12 is a reset control / status register. Furthermore, “5A7
F "," A59F "," 5A00 "," A5F8 "
Each shows a write value to an arbitrary built-in peripheral module.

As described above, in order to generate an arbitrary interrupt from the outside, it is necessary to set a plurality of interrupt enable bits of the control register and a plurality of related internal register values, so that the operator has to perform a troublesome operation.

An object of the present invention is to provide a technique for easily generating an arbitrary interrupt from outside a semiconductor chip.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, signals can be exchanged between a central processing unit for performing arithmetic processing according to a predetermined program, a built-in peripheral module disposed in an address space of the central processing unit, and an external device. And an on-chip debug module for supporting debugging of a program executed by the central processing unit, the on-chip debug module includes an interrupt generated from the built-in peripheral module. A register capable of setting an enable bit for the interrupt request from the external device corresponding to the request; and an interrupt control circuit for generating the interrupt request signal based on the enable bit set in the register. .

According to the above-described means, information relating to an interrupt request from outside the chip can be set in the register, and the interrupt control circuit has established an interrupt condition based on the information set in the register. Is determined, and an interrupt request signal is generated based on the determination result. This makes it easy to generate an interrupt from outside the semiconductor chip.

At this time, the register contains, as information relating to the interrupt request, an arbitrary interrupt request enable bit for instructing an arbitrary interrupt request to the central processing unit and a manual reset of the central processing unit. And a user debugger cycle select bit for designating a user debugger cycle.

Further, the data processing device includes a built-in peripheral module, and an interrupt control unit for determining the priority of an interrupt request signal from the built-in peripheral module and an interrupt request output from the interrupt control circuit. Can be provided.

[0015]

FIG. 4 shows an AUD including a microcomputer as an example of a data processing apparatus according to the present invention.
An (Advanced User Debugger) system is shown.

The user board 43 is not particularly limited.
This is an engine control device mounted on an automobile. The user board 43 has a microcomputer 44 and peripheral circuits (not shown) mounted thereon. The microcomputer 44 has a built-in AUD module as described later in detail, and enables on-chip debugging from outside. AUD built in the microcomputer
The plurality of input / output terminals connected to the module are drawn out to the user board 43 via external terminals of the microcomputer, and further connected to the connector 45 and the cable 46 via the connector 46.
It is coupled to the AM monitor 42. This RAM monitor 4
Numeral 2 is arranged between the host computer 41 and the user board 43, and enables monitoring and tuning of all modules connected to the internal bus or the external bus of the microcomputer 44. Although not particularly limited, the host computer 41 and the RAM monitor 42 are connected by a serial cable 47.

FIG. 5 shows an example of the configuration of the RAM monitor 42.

Although not particularly limited, this RAM monitor 4
2 includes an emulation board 51, an interface board 52, a power supply board 53, and an analog board 54. When connected to the user board 43, the emulation board 51 performs the same operation as the microcomputer mounted on the user board 43. The emulation board is coupled to the interface board 52 via the AUD interface, so that signals can be exchanged with the interface board 52.

The interface board 52 has a program correcting function, a built-in RAM monitor function, and an interface function with the host computer 41. According to the program correction function, it is possible to refer to and change data such as a built-in emulation memory, a built-in RAM, and a built-in I / O (input / output) during execution of a user program. The analog board 54 is connected to the interface board 52 to output information such as a built-in RAM in an analog manner, or to convert analog input data into digital data and display it on a monitor. Power supply board 53
Reduces the DC voltage of 6 to 16 V supplied from the battery 55 to form a DC voltage of 5 V. The formed 5V voltage is supplied to the emulation board 51, the interface board 52, and the analog board 54 as operating power supply voltages for them.

FIG. 6 shows the emulation board 51.
Is shown.

A user interface 521 is provided,
This user interface 521 allows the user board 4
3, various signals can be exchanged. Switches SW1 and SW2 are provided, and the user interface 5 is provided as a clock signal supplied to the CPU 512 or a clock signal supplied to each unit as an AUD clock.
It is possible to select whether to use the clock signal transmitted from the user board 43 through the internal circuit 21 or to use the internal clock signal generated by the clock signal generation circuit 511. A CPU (Central Processing Unit) 512 is a so-called emulation chip, and the CPU 512 enables execution of a user program. The above CPU
512 is connected to a data bus, an address bus, and a control bus. A decoder 518 for decoding an address signal transmitted from CPU 512 via the address bus is provided. CPU 51
2 is decoded by the decoder 518, and then the emulation memory 515, the user ROM (read only memory) 516, the firmware R
It is supplied to the OM 517 or the control register 519. Programs executed by the CPU 512 are stored in the user ROM 516 and the firmware ROM 517. The emulation memory 515 stores a program to be emulated. The operation of each unit is controlled according to the flag information set in the control register 519. The control register 51
9 and the CPU 512 are coupled to the interface board 52 via the input / output circuit 520 and the AUD interface 521.

FIG. 7 shows a configuration example of the interface board 52.

A system CPU 526 is provided, and the system CPU 526 controls the operation of the entire system. Firm RAM 532, Firm RAM 53
3 and a trace RAM 534 are provided. The system RAM is stored in the firmware RAM 532 and the firmware RAM 533.
The program executed in U526 is stored. Trace information for system debugging is written in the trace RAM 534. An address signal for accessing the firm RAM 532, the firm RAM, and the trace RAM 534 is decoded by the decoder 529. Information stored in the firmware RAM 533 and the trace RAM 534 can be transmitted to the host computer 41 via the input / output circuit 530 and the host interface 531 for data analysis. An AUD interface logic 524 for the AUD interface and a control register 525 for holding various operation control information are provided. AUD interface logic 524 is coupled to emulation board 51 via I / O circuit 523 and AUD interface 522. Further, an analog board interface logic 526 for interfacing with the analog board 54 is provided. The analog board interface logic 526 is coupled to the analog board 54 via the input / output circuit 527 and the analog board interface 528.

FIG. 1 shows a configuration example of a microcomputer 44 mounted on the user board 43.

As shown in FIG. 1, the microcomputer 44 includes a bus controller 11 for setting a wait control bus width, a central processing unit (hereinafter referred to as a CPU) 13 for arithmetic processing, a user break controller 21, and a built-in microcomputer. Memory 14 and built-in peripheral module 1
5 is connected to the internal bus 16 or the peripheral bus 17 so that signals can be exchanged. Further, in order to set the priority order of a plurality of interrupt requests, the interrupt control unit 19 and the internal bus 16 and the peripheral bus 17 have a CPU 1
An AUD module 12 as a module (on-chip debug module) for enabling on-chip debugging of the program executed in 3 is connected via the bus controller 11.

The built-in memory 14 includes, but is not limited to, a random access memory (RAM) that can be randomly accessed by the CPU 13, a read-only memory (ROM) storing a program, and the like.

The built-in peripheral module 15 is arranged in an address space managed by the CPU 13, and is not particularly limited. However, a timer for measuring time in program execution, a serial module for exchanging information in a serial format, and the like. -Includes a plurality of functional modules such as a communication interface (SCI) and a direct memory access control (DMAC) circuit that enables the exchange of information without passing through the CPU 13. The plurality of interrupt requests INreq1 to INreq1 from such functional modules are input to the interrupt control unit 19. Here, the plurality of interrupt requests INreq1 to nreqn from the built-in peripheral module 15 include a timer, an SCI, and a DM included in the built-in peripheral module 15.
An interrupt request generated from an AC or the like is included.

When a break condition is set in advance, the user break controller 21 generates a user break interrupt according to the content of the bus cycle generated by the CPU 13. The user break controller 21 includes, but is not limited to, a plurality of user control registers for setting a user break condition, a plurality of comparators for comparing the setting information of the user control register with a state of a bus cycle, and the like. . The comparison result is used as a user break trap request signal as C
It is input to PU13. With this signal, the execution of the program in the CPU 13 is stopped. Here, the plurality of user control registers include a plurality of registers for setting a break condition, for example, a break address register, a break address mask register, an AUD cycle bit register, and the like.

Although not particularly limited, the AUD module 12 includes a PC output circuit 121 for externally outputting various signals, and a mode control circuit 12 for AUD mode control.
2. Data buffer 123 for data output, address buffer 123 for address output, AUD control register 125 having any interrupt request enable bit and advanced user debugger cycle bit, and based on setting information of AUD control register 125 And an interrupt control circuit 126 for performing an interrupt request process for the CPU 13.

An external terminal of the microcomputer 44 has A for inputting or outputting various signals such as control signals.
An external terminal exclusively for UD is provided. For example, the dedicated external terminals include AUD buses AUDDATA3-0, AUD reset signal / AUDRST (/ indicates low active), synchronization signal / AUDSYNC, and clock signal AUD.
External terminals for CK and the mode signal AUDMD are provided.

In the AUD, a trace mode for tracing the execution state of the user program in real time, and reading and writing of data on modules connected to the internal bus and the external bus of the microcomputer 44 are enabled. RAM monitor mode.

The dedicated external terminal functions as follows in the RAM monitor mode.

AUD buses AUDATA3-0 are used for input / output of monitor addresses or data. When a command is input from outside, data is output after transmitting the Ready signal. Data output is sync signal / AUDSY
It starts after NC is negated to high level. A
The buffer and logic in the AUD module 12 are initialized by setting the UD reset signal / AUDRST to low level. At the time of a low level input, the AUD is in a reset state, and the buffer and logic in the AUD are reset. By returning to the high level after the level of the mode signal AUDMD is determined, the operation is performed in the selected mode. The mode can be selected by switching the logic of the mode signal AUDMD. Mode signal AU
When the DMD is at the high level, the RAM monitor mode is designated. A clock used for debugging is input to the clock signal AUDCK.

The AUD control register 125 is readable and writable by various control signals in the AUD. AUD control register 12
5 is provided with an arbitrary interrupt request enable bit, a manual reset bit, and an advanced user debugger cycle bit. When an interrupt condition of an arbitrary interrupt request enable bit is satisfied, n interrupt signals EXT are transmitted via the interrupt control circuit 126.
When a corresponding signal among req1 to n is asserted, a predetermined interrupt request is issued to CPU13. When a manual reset bit is set and an interrupt request for the bit is set, resetting of a predetermined functional module is enabled. Also, A
When the UD cycle bit is set, it is used as a trigger for interlocking with a peripheral function built in the microcomputer 44. For example, when the AUD cycle bit register in the user break controller 21 is set and the AUD cycle select signal SEL is enabled, a user break is applied via the interrupt control circuit 226 according to the AUD cycle. be able to.

An interrupt control unit 19 for determining the priority of the interrupt request signal from the built-in peripheral module 15 and the interrupt request output from the interrupt control circuit is provided. Arbitration can be achieved when the internal interrupt signal and the various interrupt signals output from the interrupt control circuit 226 conflict with each other.

Here, the priority order is determined according to the contents of a priority order register in which priority order information is set. This priority register can be provided in the interrupt control unit 19, and its contents are A
Rewriting can be arbitrarily performed in the RAM mode of the UD module 121, thereby changing the priority order.

The RAM monitor mode will be described.

In the RAM monitor mode, the internal bus 16, the peripheral bus 17,
Data can be read and written from and to the modules connected to the external bus.

For example, the AUD reset signal / AUDRST
Is asserted, the mode signal AUDMD is set to the high level and then the AUD reset signal / AUDRST is negated to start the operation in the RAM monitor mode.

When the synchronizing signal / AUDSYNC is asserted, input from the AUD buses AUDATA3-0 starts. When a command, address, and data (only at the time of writing) are input in a predetermined format, reading / writing of the specified address is started. At this time,
Data can be read / written from / to the AUD control register 125. For example, data can be read and written from and to all the modules connected to the internal bus 16, the peripheral bus 17, and the external bus of the microcomputer 44. The setting in the AUD control register 125 is also performed in this RAM monitor mode. That is, the AUD control register 125 is set by the address, and the content of the AUD control register is updated by the subsequent data.

During the internal execution, the AUD module 12 returns a NotReady signal. Upon completion of execution, a Read flag is returned.

At the time of reading, if the synchronization signal / AUDSYNC is negated after detecting this flag, data of a designated size is output.

FIG. 2 shows a flow of an arbitrary interrupt generation.

The user creates an A interrupt routine and an B interrupt routine, which are arbitrary interrupts, that is, an interrupt routine control program. The means for generating the arbitrary interrupt is executed by controlling the advanced user debugger terminal. Will be In other words, the sync signal /
AUDSYNC is asserted and the AUD bus AUDAT
When input from A3 to A3 is started, a command, an address, and data (only at the time of writing) are input in a predetermined format, and reading / writing of a specified address is started.

For example, to generate an arbitrary interrupt, A
A flag may be set for an arbitrary interrupt bit in the UD control register 125, which is realized by giving the following command from the host computer 41.

#M FFFFxxxx xxxx; W (RET) As a result, a flag is set to an arbitrary interrupt bit in the AUD control register 125. An interrupt request is made by the interrupt control circuit 126 based on the set flag, and the interrupt control unit 19 in the subsequent stage controls the CP according to a predetermined priority.
A predetermined interrupt request is made to U13, and a predetermined interrupt process is performed.

For example, as shown in FIG. 2, when a user program is executed in the RAM monitor mode, if an arbitrary interrupt, A interrupt or B interrupt is requested, the previous program responds. By jumping to the corresponding interrupt routine, the corresponding interrupt routine process is performed. When the process is completed, the process returns to the original program process.

Here, according to the prior art, in order to generate an arbitrary interrupt from the outside, it is necessary to set a plurality of interrupt enable bits of a corresponding control register and a plurality of associated internal register values. 1 must be input from the host computer. In the case of the configuration shown in FIG. 1, the host computer 41 executes one command for setting information in the AUD control register 125 as described above. Just do it. This makes it possible to easily generate an interrupt from outside the semiconductor chip.

According to the above example, the following operation and effect can be obtained.

(1) AUD control register 12 capable of setting information on interrupt requests from outside the chip
And an interrupt control circuit 126 for determining whether or not an interrupt condition is satisfied based on the information set in the AUD control register 125 and generating an interrupt request signal based on the determination result. The AUD control register 125
If the information on the interrupt request is set in this step, an interrupt request signal is generated by the interrupt control circuit 126, so that an interrupt from outside the semiconductor chip can be easily generated.

(2) An interrupt control unit 19 for determining the priority of an interrupt request signal from the built-in peripheral module and the interrupt request output from the interrupt control circuit is provided. Arbitration can be achieved when the generated internal interrupt signal and various signals output from the interrupt control circuit 226 conflict with each other.

FIG. 3 shows another configuration example of the microcomputer according to the present invention.

The microcomputer shown in FIG. 3 is significantly different from that shown in FIG. 1 in that a Nexus module 212 is provided instead of the AUD module 12 as an on-chip debug module. The Nexus module 212 has a standard debug interface specification, and is compatible with JTAG (JointT).
est Action Group) circuit 227, a development tool register, an auxiliary terminal interface, a control circuit, and the like 228, and a Nexus control register 225 and an interrupt control circuit 2
26 are provided. As external terminals, JTAG terminals and auxiliary terminals are provided. JTAG terminal via JTAG terminal
Settings and status confirmation in the G protocol, access to a development tool register, read / write access during execution, capture of a packet type read message, and the like can be performed. Further, tracing of a program, writing of data, and the like can be performed via the auxiliary terminal.

Nexus control register 225
Is configured to be readable / writable via a JTAG terminal and an auxiliary terminal. The Nexus control register 225 is provided with an arbitrary interrupt enable bit, a manual reset bit, and a Nexus cycle bit.

Nex through the JTAG terminal and the auxiliary terminal
When an arbitrary interrupt request enable bit is set in the us control register 225, the interrupt control circuit 226 determines whether or not the interrupt condition is satisfied, and the interrupt control unit 19 determines the priority of the interrupt. After that, an interrupt request is made to the CPU 13. Then, as in the case of the configuration shown in FIG. 1, a predetermined interrupt process is performed by jumping to the corresponding interrupt routine.

Nex through the JTAG terminal and the auxiliary terminal
When a manual reset bit is set in the us control register 225, a manual reset signal MRST is asserted from the interrupt control circuit 226 to the CPU 13 in response thereto, whereby the CPU 1
3 is reset.

Further, Nexus control register 225 is connected to Nexus control register 225 via JTAG terminal and auxiliary terminal.
When the cycle bit is set, the CPU 1
For 3, the Nexus cycle signal SEL is asserted. This Nexus cycle signal SEL is
Can be used as a trigger for interlocking with peripheral functions in the microcomputer 44. For example, N
Exus cycle signal SEL is interrupted by CPU1.
3, the user break interrupt for stopping the program execution in the CPU 13 can be generated in synchronization with the input.

Although the invention made by the present inventor has been specifically described above, the present invention is not limited to this, and it goes without saying that various modifications can be made without departing from the gist of the invention.

In the above description, the case where the invention made by the present inventor is mainly applied to a microcomputer which is the field of application as the background has been described. However, the present invention is not limited to this, -It can be widely applied to various data processing devices such as processors.

The present invention can be applied on condition that at least a central processing unit is included.

[0061]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a control register in which information relating to an interrupt request from outside the chip can be set, and whether or not an interrupt condition is satisfied is determined based on the information set in the control register, and an interrupt is determined based on the determination result. By providing an interrupt control circuit for generating a request signal, if information on an interrupt request is set in the control register, an interrupt request signal is generated by the interrupt control circuit. Can be easily generated.

Further, an interrupt control unit for determining the priority of the interrupt request signal from the built-in peripheral module and the interrupt request output from the interrupt control circuit is provided, so that it is generated from the built-in peripheral module. Arbitration can be achieved when the internal interrupt signal and various signals output from the interrupt control circuit conflict.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a microcomputer according to the present invention.

FIG. 2 is an explanatory diagram of interrupt processing in the microcomputer.

FIG. 3 is a block diagram illustrating another configuration example of the microcomputer according to the present invention.

FIG. 4 is an explanatory diagram of an advanced user debugger system including the microcomputer.

FIG. 5 is a block diagram illustrating a configuration example of a RAM monitor in the advanced user debugger system.

FIG. 6 is a block diagram showing a configuration example of a main part of the RAM monitor.

FIG. 7 is a block diagram showing a configuration example of a main part in the RAM monitor.

[Explanation of symbols]

Reference Signs List 11 bus controller 12 AUD module 13 CPU 14 built-in memory 15 built-in peripheral module 16 internal bus 17 peripheral bus 19 interrupt control unit 41 host computer 42 RAM monitor 43 user board 44 microcomputer 121 PC output circuit 122 mode control circuit 123 data buffer 124 address Buffer 125 AUD control register 126 Interrupt control circuit 212 Nexus module 225 Nexus control register 226 Interrupt control circuit 227 JTAG circuit 228 Registers for development tools, auxiliary terminal interface and control circuit, etc.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Yujiro Kaneko 5-22-1, Kamisumihonmachi, Kodaira-shi, Tokyo Inside Hitachi Super LSI Systems Co., Ltd. (72) Inventor Yoshikazu Kabata Tokyo 5-22-1, Kamizuhoncho, Kodaira-shi, Tokyo F-term in Hitachi Ultra-SII Systems Co., Ltd. 5B042 GA13 GB08 GC01 GC07 HH03 5B048 AA14 DD08 5B062 AA00 CC01 DD10 EE10 JJ03 JJ08 5B098 BA05

Claims (3)

[Claims] 1. A central processing unit for performing arithmetic processing according to a predetermined program, a built-in peripheral module arranged in an address space of the central processing unit, and an external device capable of exchanging signals. And an on-chip debug module that supports debugging of a program executed by the central processing unit, wherein the on-chip debug module responds to an interrupt request generated from the built-in peripheral module. A register capable of setting an enable bit for an interrupt request from the corresponding external device, and an interrupt control circuit for generating the interrupt request signal based on the enable bit set in the register. A data processing device comprising: 2. The register includes an arbitrary interrupt request enable bit corresponding to an interrupt request from a built-in peripheral module, a manual reset bit indicating a manual reset of a main module, and a user debugger cycle select bit indicating a user debugger cycle. 2. The data processing apparatus according to claim 1, comprising: 3. An internal peripheral module, and an interrupt control unit for determining the priority of an interrupt request signal from the internal peripheral module and an interrupt request output from the interrupt control circuit.
Or the data processing device according to 2.