JP3323341B2 - Emulation processor and emulator equipped with it - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer and an emulator which is an apparatus for developing a microcomputer application system, and is effective when applied to, for example, a microcomputer emulation processor and an emulator equipped with the emulation processor. Technology.

[0002]

2. Description of the Related Art For example, in order to develop an application system using a single-chip microcomputer, a microcomputer development apparatus called an in-circuit emulator is used. This microcomputer development device is connected between a system development device such as a so-called personal computer and an application system (user system) under development (single chip microcomputer (target microcomputer)) to be mounted on the application system. It has the function of a debugger while acting on behalf of the function, and supports the development of software or application systems.

[0003] This microcomputer development device includes:
A function that includes a single-chip microcomputer in an emulation processor for evaluation called an evaluation chip corresponding to the single-chip microcomputer, and is dedicated to outputting the internal state of the microcomputer and controlling the operation of the microcomputer. By adding the function described above, the development of the microcomputer development device is facilitated.

[0004] Such a microcomputer development device or in-circuit emulator is described in, for example, "LSI" issued by Ohmsha on November 30, 1984.
Handbook ”P562 and P563
The emulation processor is known, for example, from JP-A-63-106840, and will not be described in detail.

[0005] Further, functions dedicated to the emulation processor include a function of stopping the CPU when the CPU accesses a predetermined address and transferring control to the emulator (break), and a program dedicated to emulation at the time of such a break. And monitor and modify the user's memory. What to do during a break is, for example,
No. 5,779, and the like.

[0006]

However, in the above-described emulation processor, it is difficult to design an external circuit for controlling the emulation processor due to the speeding up of the microcomputer. For example, when resetting the emulation processor, the emulation processor executes or changes the user program depending on whether the reset request is caused by the user or the emulator.

Although such a change is not a known technique, it has been performed by changing a vector (start address) read by the emulation processor by an external circuit external to the emulation processor. If the access time is shortened by the speeding up of the microcomputer, the time allowed for such vector change is also shortened.

An emulation memory is arranged in the address space of the CPU, but this overlaps with the user memory. It is necessary to determine whether to access the emulation memory or the user memory with respect to the address output from the CPU, and to enable the emulation bus and the user bus when the CPU has the emulation bus and the user bus. When the access time is shortened due to the speeding up of the microcomputer, the time allowed for such address determination and bus control is also shortened.

Further, C is set according to the access state of the CPU.
A break interrupt is requested to interrupt the execution of the PU program and transfer control to the emulation side (break). However, if the access state of the CPU is determined outside the emulation processor and the break interrupt is requested, It is difficult to break the CPU in a desired instruction execution state. For example, a break occurs when a command is executed by several instructions more than a desired instruction execution state. It becomes difficult to cause a break immediately after execution of a desired instruction such as a single step operation.

Further, the number of signals that can be input and output between the emulation processor and the emulator is limited by the number of terminals of the emulation processor as a semiconductor integrated circuit device. For this reason, it is not always possible to sufficiently output, for example, a signal indicating the instruction execution state of the CPU inside the emulation processor to the emulator. Also, it is not always possible to input a sufficient number of control signals to the emulation processor of the emulator.

Further, the increase in emulation signals increases the package size of the emulation processor. Further, it becomes difficult to increase the size of the emulator itself, for example, to put the application system into an actual operation state and evaluate the system.

Therefore, an object of the present invention is to reduce the load on external circuits without increasing the number of signals between the emulation processor and the emulator (without increasing the size of the emulator and enabling evaluation even in a mounted state). An object of the present invention is to provide an emulation processor that forms an emulator capable of realizing emulation by controlling the emulation processor quickly and easily without increasing the number of emulation processors, and to provide an emulator equipped with the emulation processor.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0014]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the emulation processor of the present invention is applied to a processor capable of emulating a microcomputer, and includes a break mode as a first mode in which an emulation program operates, and a user to be emulated. A user mode, which is a second mode in which the program operates, and a break reset and a user reset corresponding to each mode, and inputting whether to immediately transition to the break mode or to enter the user mode after the reset It can be selected depending on the state of the terminal.

Further, a memory selection register (MEMCR) is provided as a means for dividing an address space of a microcomputer to be emulated and specifying whether to access an emulation memory or a user memory for each area in a break mode. It has.

Further, a break condition is set in the emulation. In particular, when a control bit (SSTP) for requesting a single step process is provided, when the bit is in a predetermined state, each instruction of the user program is set. Automatically when a break interrupt control bit (BIEA, B) is provided, and a PC break is enabled when a multiple break interrupt control bit (BMBE) is provided. The interrupt is prohibited.

The emulator according to the present invention is provided with the emulation processor. When the reset signal of the user system is in the active state, the user reset is selected, and the reset signal of the emulator is in the active state. In some cases, the microcomputer has a break reset control circuit as a means for setting a state in which a break reset is selected, and further reads or writes the memory of the user system by a bus cycle specified by the microcomputer, and executes an emulator by a bus cycle for emulation. It enables reading or writing of the rental memory of the system.

[0019]

According to the emulation processor and the emulator equipped with the emulation processor, the information controlled outside the emulation processor is taken into the emulation processor, so that abundant information inside the emulation processor can be used. Also, it is not affected by the delay of the signal from the emulation processor to the emulator or the delay of the signal from the emulator to the emulation processor. The emulation processor can be controlled at high speed.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing an example of a microcomputer to be emulated by an emulation processor according to one embodiment of the present invention, FIG. 2 is a block diagram showing an emulation processor according to this embodiment, and FIGS. FIG. 20 is a detailed block diagram, timing diagram, or operation flowchart of the emulation processor. FIG. 21 is a block diagram of an emulator having the emulation processor according to the present embodiment.
7 is an operation flowchart of the emulator.

First, the configuration of a microcomputer to be emulated by the emulation processor of this embodiment will be described with reference to FIG.

The microcomputer in this embodiment is, for example, a single-chip microcomputer, and includes a central processing unit CPU, a data transfer controller DTC, a read-only memory ROM, a random access memory RAM, a timer, a serial communication interface SCI, and an A / D converter. A / D, input / output ports IOP1 to IOP11, an interrupt controller, a bus controller BSC, and a clock oscillator CPG function blocks (or modules), which are interconnected by an internal bus.

The bus controller includes a module select section MS for determining the contents of an address. Although not shown, the timer includes blocks for five channels and the SCI includes blocks for three channels.

The internal bus includes a read signal and a write signal in addition to an address bus and a data bus, and may further include a bus size signal or a system clock. IAB and PAB exist on the internal address bus. IDB and PDB exist in the internal data bus. IAB and PA
B, IDB and PDB are interfaced by a bus controller.

The internal data buses IDB and PDB have a 16-bit configuration. CPU instructions are in 16-bit units. The address space of the CPU is 16 MB. P
AB and PDB are bus controller, timer, SCI,
A / D converter, interrupt controller, connected to IOP1 to IOP11. The interrupt controller inputs a timer, an SCI, an interrupt signal output from an input / output port,
An interrupt request signal and a vector number are output to the TC.

The input / output port is also used as an external bus signal and an input / output signal of an input / output circuit. IOP1 to 3 are address bus outputs, IOP4 and 5 are data bus input / output,
OPs 6 and 7 are also used as bus control signal input / output signals. External addresses and external data are respectively transmitted to IAB, IAB via buffer circuits included in these input / output ports.
Connected to DB.

PAB and PDB are used to read / write the register of the input / output port, and have no direct relation to the external bus. The bus control signal output is chip select,
There are an address strobe, a high / low data strobe, a read strobe, a write strobe, a column address strobe, a bus acknowledge signal, and the like. The bus control input signal includes a wait signal, a bus request signal, and the like. These input / output signals are not shown. The extension of the external bus is selected depending on the operation mode and the like, and the functions of these input / output ports are also selected.

IOP8 is a timer input / output, IOP9
Is SCI input / output, IOP10 is analog input, IOP1
Reference numeral 1 is also used as an external interrupt request IRQ input. The input / output signals of the timer, SCI, A / D converter and IOP8 to IOP10 are not shown. In addition, power supply terminal Vc
c, Vss, analog power supply terminals AVcc, AVss, reset input terminal RES, standby input terminal STBY,
Interrupt input terminal NMI, clock input terminal EXTAL, X
There are input terminals such as TAL and operation mode input terminals MD0, MD1, and MD2.

Next, the configuration of the emulation processor will be described with reference to the block diagram of FIG.

The emulation processor is composed of the microcomputer part and a block dedicated to the emulation processor including a buffer circuit (not shown) and the like.
Formed on one semiconductor substrate. Signals and the like not directly related to the present invention in the microcomputer portion are omitted. I / O includes a timer, SCI, A / D, and IOP. BUF is a buffer portion of the address bus / data bus / bus control signals included in IOP1 to IOP7.

The emulation processor has a user interface for transmitting and receiving signals to and from the application system, and an emulation interface for transmitting and receiving signals to and from the microcomputer development device.

The emulation interface receives as input signals a break interrupt signal BRK, an emulator interrupt signal EMIRQ, and an emulator wait signal EML.
WAIT is present, and a break acknowledge signal BRKAK and trigger output signals TOA and TOB are present as output signals. In addition, an address bus, a data bus, a read signal, a write signal, and the like are included.

The emulation processor dedicated block has an emulation dedicated control register, and performs break control, bus control, module selection control, and the like. For example, as described in Japanese Patent Application Laid-Open No. 3-271834 or Japanese Patent Application No. 4-316068, prohibition of a function built into the emulation processor or change of operation is designated by one emulation processor. Emulation of a plurality of microcomputers can be performed.

The module selection control is specified by the module selection register MSELR, the microcomputer to be emulated is selected by setting the module selection register, and the prohibition of functions built into the emulation processor and the change of operation are specified. Is supplied to the module select circuit included in the bus controller BSC and other microcomputer parts.

For example, the number of available channels of the timer or the SCI is specified, or the number of valid IOPs is specified. Also, the capacity of the built-in ROM and RAM is specified. For the prohibited module, operations such as read / write are suppressed by fixing the module selection signal to an inactive state.

The bus control is performed by a memory control register MEMC.
R, the wait control register EWTCR, the window control bits WD1, 0, and the break acknowledge signal BRK.
AK, and instructs the bus controller to control the user bus and the emulation bus, and to permit / prohibit a wait request from the emulation side.
The bus controller controls the bus based on the address determination result of the module select circuit.

The break control is performed by a BRK interrupt signal, a break control register BRKCR, a break address register BAR, and a break address mask register BAMR. A break request and a single-step break request are made in accordance with information such as the register and the address. To the CPU.

An EMLWAIT signal is supplied to a bus controller and a reset control circuit. Although the reset control circuit is not particularly limited, it outputs a user reset RST signal and a break reset BRST signal, a microcomputer part is supplied with a user reset RST, and a user dedicated RST and a break reset BRST signal are supplied to a dedicated emulation processor block. Is supplied.

The emulator-specific interrupt control is performed by the EMLIR
Q signal and emulator dedicated interrupt control register IRQCR
And requests an interrupt to the CPU via an interrupt controller of the microcomputer part.

Next, the configuration of the emulator dedicated register included in the emulator dedicated block will be described with reference to the register configuration diagrams of FIGS.

The reset initial value differs between the user reset and the break reset. It is not initialized by a user reset and is held at the previous value. At the break reset, all the dedicated registers for emulation are initialized.

(1). The module select register MSELR is an 8-bit register, and specifies the enable / disable of DTC, the number of timer channels, the number of SCI channels, the package (number of input / output ports), the ROM capacity, and the RAM capacity. I do.

Reading / writing is possible only in the break mode. Such a designation method and a control method are described in Japanese Patent Application Laid-Open No. Hei.
It is described in Japanese Patent Application No. 271834 or Japanese Patent Application No. 4-316068, and a detailed description thereof will be omitted.

The module selection register is initialized by the BRES signal. Since the setting is retained by the user reset, once the setting is performed after the operation of the emulator starts, it is not necessary to reset the setting unless the target microcomputer is changed.

(2). The memory selection register MEMCR is 16
A register having a bit configuration, which corresponds to one obtained by dividing the address space into 16, specifies whether to allocate a user memory or an emulation memory (rental memory) to each area.

(3) The wait control register EWTCR is 1
A 6-bit register corresponding to the address space divided into 16 in the same manner as described above.
Specify whether to allow or prohibit AIT. In general, an area to which an emulation memory (lending memory) is allocated is allowed to have EMLWAIT so that a sufficient access time can be secured.

The bus control register / wait control register is initialized by the BRES signal. Since it is held by a user reset, if it is set once after the operation of the emulator starts, there is no need to reset it unless the target memory arrangement is changed. Read / write is possible only in the break mode.

(4) Emulator dedicated interrupt control register I
RQCR is an 8-bit register. The emulator interrupt request flag IRQF is
It is set to "1" when a predetermined input occurs at the IRQ terminal, for example, when a rising edge occurs.
When "0" is written after reading "1", "0"
Is cleared.

The emulator interrupt permission bit IRQE is
Allows emulator-specific interrupts. IRQF and IR
When both QEs are set to "1", an emulator-specific interrupt is requested. Emulator-specific interrupts are different from user interrupts, and do not transition to break mode when accepted. Treated in the same way as a user interrupt request. Such a register can be read / written regardless of the user mode or the break mode.

The emulator interrupt control register includes:
Read / write is enabled regardless of the user mode / break mode. When the debugger of the OS mounted on the emulator is executing the user program, it is suitable for the interrupt handler to check the state of the task or the like by interrupting the emulator. Since the OS operates even in the user mode, it is convenient to read / write the emulator interrupt control register in the user mode. Therefore, the resources of the microcomputer are not used.

When the OS is also initialized by the user reset, the emulator interrupt control register is set to U
Initialized by RES. The OS is described in "HI8-3X" issued by Hitachi, Ltd. in August 1991.

(5) The break control register BRKCR is 1
This is a 6-bit register. Window control bits WD0 and WD1 permit access to the user bus during the break mode. When the WD0 bit is set to “1”, the WD1 bit is set to “1” during read data access.
Is set, the user bus is accessed at the time of write data access. Ignored in user mode.

In the break mode, the access state is set to three states irrespective of the designation by the user, and the address multiplexing for the DRAM interface is not performed. At this time, if the WD0 and WD1 bits are set to "1", access is performed as specified by the user. It is preferable to read and display the user memory in the break mode by using a memory command of the emulator or to write a specified value to the user memory.

The address multiplex for DRAM access is described in “H8 / 3” issued by Hitachi, Ltd. in March 1993.
003 Hardware Manual ”p155-p194
And so on. Regarding memory commands, see “H8 / 300” issued by Hitachi, Ltd. in March 1994.
H Series Emulator E7000 User's Manual ”, pp. 12-56 to 12-57.

The window control bits are initialized with URES. The single step bit SSTP internally requests a BRK interrupt after executing one instruction of the user program. That is, a single-step BRK interrupt is required when the SSTP bit is set to "1" and BRKAK is inactive. However, after execution of the RTB instruction, such a single-step BRK interrupt request is ignored.

The SSTP bit is suitable for debugging because it does not affect the internal state of the CPU and is treated as a resource dedicated to the emulator. For the single step, see “H8 / 300” issued by Hitachi, Ltd. in March 1994.
H Series Emulator E7000 User's Manual ”, pp. 12-76 to 12-78.

The break interrupt enable bit BMBE is always initialized to a disabled state in the user mode. This makes it possible to prohibit multiple exception handling of a break when transitioning from the user mode to the break mode. In the multiple exception processing, for example, there is a conflict between the BRK instruction and the BRK interrupt. The BRK instruction is arranged, for example, next to the last instruction of the user program.

When the execution of the BRK instruction and the break condition are satisfied after the end of the user program and the BRK interrupt is requested, if the BRK interrupt is executed after the execution of the BRK instruction, that is, after the transition to the break mode, the emulator is activated. When a dedicated stack memory is provided, the contents once stacked may be destroyed by the second exception processing. This can be avoided by prohibiting multiple exception handling of a break at the time of transition from the user mode to the break mode using the break interrupt enable bit.

Since the BRK instruction is not used after the transition to the break mode, the BRK interrupt can be used even during the break mode if the break interrupt enable bit is set to the enable state thereafter.

The trigger output permission bit TOE permits the trigger output to the trigger output terminals BTOA and BTOA when the break condition is satisfied. Break condition A
Is satisfied, a one-state high-level pulse is output to the BTOA terminal when the break condition B is satisfied.

By observing such terminals, the time from the first desired step to the second desired step of the program can be easily measured. The address of the first desired step of the program is set to BARA and the address of the second desired step is set to BARB, and BIEA, B
The IEB bit is cleared to "0", the instruction execution is selected, and the program is executed in a state where the TOE bit is set to "1". After the high level of one state is output to the BTOA terminal, one state is output to the BTOB terminal. Can be measured until a high level is output. Alternatively, the number of executions of the program can be measured. Based on this result, a break can be requested by the BRK terminal.

Break interrupt A and B enable bits BIEA,
B permits a break request based on the break conditions A and B. Even in the disabled state, the break condition is determined and the BTO
Pulse output from the A and B terminals can be performed.

Condition selection bits CSA1, 0 and CSB
1, 0 sets a break condition. Instruction execution, read access, write access, read or write access can be selected. For example, when execution of an instruction is selected, the CPU fetches an instruction at an address specified by BAR and BAMR, a break is requested when the instruction is executed, and a break occurs after execution of the instruction. Regarding the break, "H" issued by Hitachi, Ltd. in March 1994
8 / 300H Series Emulator E7000 User's Manual ”, pp. 12-56 to 12-57. Such a register can be read / written only in the break mode.

(6) The address register BAR and the address mask register BAMR are 24-bit registers corresponding to the address space of the CPU. There are two channels A and B.

The address register specifies an address.
Of these, bits for which the corresponding bit of the address mask register is set to "1" are ignored. The specified address is compared with the address output by the CPU to determine whether they match. This determination is (CA23 / AR23 + @ CA23 / @ AR23 +
(AMR23) ···· (CAn · ARn + ｎCAn · ¬A
Rn + AMRn) ···· (CA0 · AR0 + ¬CA0 ·
¬AR0 + AMR0). ¬ indicates logical inversion. Note that CA23-0 is bit 23 output by the CPU.
−0.

(7) The emulator stack memory register EMLSTKR is used as a stack area at the time of a break. A capacity corresponding to one exception processing stack of the CPU, for example, 4 bytes is provided. For example, C
One byte of the condition code register CCR of the PU and three bytes of the program counter PC. For such a stack, see “H8 / 3003 Hardware Manual”, p. 79, issued by Hitachi, Ltd. in March 1993.
To p88.

At the time of a break, the stack pointer SP of the CPU is ignored, and the stack is always stored in the emulator stack memory. The break interrupt enable bit prevents the break from occurring multiple times and destroying the emulation stack memory. The reset initial value is not specified, but is undefined.

Next, the address space will be described with reference to the address map shown in FIG.

The address space of the CPU is 16 Mbytes, which is divided into 8 areas of 128 Kbytes, 1 area of 1 Mbytes, and 7 areas of 2 Mbytes, and the attribute of each area is specified by each bit of MEMCR and EWTCR. . The areas overlapping the internal ROM, the internal RAM, and the internal I / O register are the internal ROM, the internal RAM,
And the specification of the internal I / O register is prioritized, and the control bit is ignored.

The bus control designation register controls the bus controller. Specify the emulation memory area. This is enabled in user mode. It is convenient to be able to subdivide an area that is often connected to the built-in ROM and become a program area, and set a program lending memory.

It is convenient if the other area is set to 2 Mbytes and can be shared with the bus control setting on the user side.
The bus control on the user side is described in "H8 / 3003 Hardware Manual" published by Hitachi, Ltd., March 1993, p121 to p154.

In the break mode, access is basically made using an emulation bus. When the emulator monitors or changes the user memory, the user memory can be accessed using the window bits. This applies only to data access in order to monitor and change the user memory.

Next, the access method will be described with reference to the state diagrams of FIGS.

In the user mode, when the corresponding MEMCR is cleared to "0", a bus cycle of the microcomputer, for example, specified by a bus controller is performed. When accessing the external memory, the strobe signal on the user side becomes valid. The sequence output indicates that a strobe signal according to the specification of the microcomputer is output. The user side WAIT terminal is also enabled according to the specification of the microcomputer. Furthermore, EW
The TCR specifies whether EMLWAIT is allowed or prohibited.

In the user mode, when an external memory is accessed, the bus cycle specified by the microcomputer is invalidated when the corresponding MEMCR is set to "1", and the bus cycle becomes an emulation bus cycle. Read / write is performed via the emulation bus. The number of basic bus states is three. User side strobe signal is inactive (fixed to high level)
And the user side WAIT terminal is ignored. The strobe signal on the user side is read signal RD, write signal H
WR, LWR, column address strobe CAS and the like are included. EMLWAI by EWTCR as before
Whether T is permitted or prohibited is specified.

That is, even in the user mode, in the area where the corresponding MEMCR is set to “1”,
The memory on the emulator side can be read / written. Among the memories on the emulator side, the MEMCR corresponding to the address at which the memory (rental memory) permitted to be used by the user may be set to “1” in advance. If access is not possible without inserting a wait, EMLW
Allow AIT.

In the break mode, the bus cycle specified by the microcomputer is basically invalidated, and becomes a bus cycle for emulation. Read / write is performed via the emulation bus. The number of basic bus states is three. EMLWAIT is allowed. The user side strobe signal is deactivated, and the user side WAIT terminal is ignored.

When a data access specified by the WD1,0 bits occurs in the break mode, a bus cycle specified by the microcomputer occurs. If the external address is accessed, the strobe signal on the user side becomes valid. The user side WAIT terminal is also enabled according to the specification of the microcomputer.

For example, the condition for the emulation bus cycle is as follows: (ROM + RAM + IO). (BR
KAK ・ (PF + DRD ・ ¬WD0 + DWR ・ ¬WD
1) It is expressed as + · ・ BRAKAK · MCi). MCi
Indicates a MEMCR bit corresponding to the selected address. PF is instruction read, DRD is data read, DW
R indicates data write. ¬ indicates logical inversion.

Next, the bus configuration of the emulation processor will be described with reference to the block diagram of FIG.

The bus controller includes a P-BUF for controlling a bus composed of PAB and PDB, and a bus control register. The bus control register is disclosed in, for example, Japanese Patent Application No. Hei 4-1379.
No. 56. When the emulation bus cycle is selected, the contents of the bus control register and the like are ignored. The emulation interface includes an EMLBUF that controls the emulation bus.

The MS receives a start signal and IAB output from the CPU or DTC, and inputs a bus control register, MEMC
An access destination and an access method are determined based on each register of the R • EWTCR and the WD1,0 bits, and the P-BU
Activate any of the buffers F, user BUF, and EMLBUF.

Even if the P-BUF and the user BUF are activated, the EMLBUF activates for output. P-BUF,
When the user BUF and the EMLBUF are activated, an address bus and various strobe signals are output at a predetermined timing to input / output a data bus. When each buffer ends the bus cycle, it outputs an end signal to the MS. MS is CPU
Alternatively, an end signal is output to the DTC. CPU or DT
C starts the next bus cycle.

The bus control of each buffer and the bus control register are described in, for example, Japanese Patent Application No. 4-13795.
No. 6.

Next, an example of the bus timing will be described with reference to the timing chart of FIG. This is an example in which an external address specified in the two-state access space by the bus control register is read in the user mode.

If the MC bit is cleared to "0" and the bus cycle specified by the microcomputer is valid, access is made in two states, and the strobe signal A on the user side is accessed.
S, RD, etc. perform predetermined output and read data from the user data bus. The emulator strobe signal is valid, and read data of the user data bus is output to the emulation data bus.

When the MC bit is set to "1" and an emulation bus cycle is performed, the basic bus cycle is set to three states. If the WC bit is set to "1", a wait is requested by EMLWAIT, and, for example, one wait state is inserted and four-state access is performed. The strobe signal on the user side is fixed in an inactive state, and the user data bus is set to a high impedance state. The emulator strobe signal is valid, and data is read from the emulation data bus.

Next, the timing of the break reset will be described with reference to the timing chart of FIG.

When the EMLWAIT signal is active, R
When the ES signal becomes active, a break reset is performed,
BRK before the CPU executes reset exception handling
The AK signal is activated. While the BRKAK signal is in an active state, the CPU reads a vector (start address) and performs an instruction fetch following the read vector. Since the BRKAK signal is active, emulation memory is selected for vector and instruction fetch. Therefore, any program on the emulator side can be executed.

All memory accesses are three-state accesses, and waits including EMLWAIT are permitted. The BRKAK signal is activated, and the user-side strobe signal is fixed at an inactive state.

Next, the timing of the user reset will be described with reference to the timing chart of FIG.

When the EMLWAIT signal is inactive,
When the RES signal becomes active, the user is reset,
The CPU executes the reset exception processing while the BRKAK signal is in the inactive state. When the BRKAK signal is in an inactive state, the CPU reads a vector (start address) and fetches an instruction following the vector (start address). BRKA
Since the K signal is inactive, user memory is selected for vector and instruction fetch.

The memory access is an access according to the user's specification. Although not particularly limited, in FIG.
It is assumed that the vector and the first instruction exist in the built-in ROM, and are accessed in one state, and the wait including EMLWAIT is prohibited. When the vector or the first instruction exists in the external memory, the user-side strobe signal goes into a predetermined output state.

An emulation processor having two types of resets is described in Japanese Patent Application No. 4-316068. This is only considered for the initialization of the emulation dedicated register and the change of the number of bus states. In this example, the user bus and the emulation bus of the emulation processor are common. As registers dedicated to emulation, only registers that specify a microcomputer to be emulated have been studied.

In the present invention, the BRKAK signal is activated or deactivated in response to two types of resets, thereby facilitating control even when the user bus and the emulation bus are independent. it can. The trouble of transitioning to the break mode after reset can be saved.

Further, not only the register for designating the microcomputer but also registers relating to the entire emulator system, for example, MEMCR and EWTCR are held by user reset, so that the trouble of resetting by software can be saved. .

Next, the break reset control circuit will be described with reference to the block diagram of FIG.

EMLWAIT is requested from the bus controller as a wait request signal, and is used for reset control via a clocked buffer or three stages of flip-flops.

The reset signal RES generates an internal reset signal RST via a clocked buffer or three stages of flip-flops. Also, the internal reset signal R
ST and clocked buffer or flip-flop 3
The EMLWAIT signal passed through the stage is input to the AND circuit, and the output is inverted and the output is passed through a clocked buffer or a flip-flop to the AND circuit. Signal.

Therefore, BRS is changed according to the state of the EMLWAIT # signal when the RES # terminal transits to the inactive state.
Whether the T signal is activated or not is set. B
The RST signal is also used as a transition signal of the break acknowledge signal BRKAK. The part initialized by the user reset is initialized by the RST signal. The part initialized by the break reset is initialized by the BRST signal.

By referring to the state of the EMLWAIT # signal when the RES # terminal transitions to the inactive state, break reset is not erroneously made even if RES # is activated in any state. When the RES signal is activated, the emulator
When the T # signal is deactivated, the user is reset.
A significant portion of the emulator dedicated registers are retained. #
Indicates a negative logic signal.

Next, the break acknowledge BRKAK signal control circuit will be described with reference to the block diagram of FIG.

The BRKAK signal is controlled by a flip-flop circuit. The output of such a flip-flop circuit is BR
This is a KAK signal. The output of the AND circuit is provided as a set signal of the flip-flop. One input of the AND circuit is the clock φ2, the other input is the output of the OR circuit, and the input of the OR circuit is the B
An RST signal and a SETBRAKAK signal output at a predetermined timing when the CPU executes break exception processing.

Note that the break exception processing is performed when a break instruction BRK is executed, when a break interrupt is executed by a break request from the BRK terminal, and when BRKCR · B
This is performed when a break interrupt is executed by a break request due to the satisfaction of the AR / BAMR condition and when a single-step break is executed.

The output of the AND circuit is given as a set signal of the flip-flop. One input of the AND circuit is a clock φ2, and the other input is a CPU φ2.
Is a RESBRKAK signal output at a predetermined timing when a return instruction RTB from a break is executed.

Therefore, at the time of a break reset or when the CPU activates the break exception handling, the BRKAK
The signal goes active. When the CPU executes the break exception processing, the BRKAK signal becomes inactive.

Next, an example of the emulation-dedicated control register will be described with reference to the block diagram of FIG.

The control register is mainly composed of flip-flops. The output Q of such a flip-flop is used as a control signal. The output is connected to a data bus via a clocked buffer. The clock of the clocked buffer is an AND signal of the AND signal of the address decode signal and the break mode signal and the read signal.

The input D of the flip-flop is the data bus, and the clock C is a logical product signal of the logical product signal of the address decode signal and the break mode signal and the write signal. Such an address decode signal is C
When the address output by the PU becomes the address where the control register exists, the PU is activated. That is, read / write is enabled only in the break mode. IRQC
As for R, the break mode signal is removed by enabling read / write in the user mode.

A reset input R of the flip-flop is used as a break reset signal. Cleared to "0" at break reset. For a control register to be set to "1" at the time of a break reset, a break reset signal is input to the set input of the flip-flop.

Since the IRQCR is initialized by a user reset, the reset input R is a user reset signal. EMLSTKR does not have a reset input and is not initialized by a user reset or a break reset.

Next, the break interrupt control circuit will be described with reference to the block diagram of FIG.

There are three causes of a break request to the CPU. The first is a request by the BRK terminal. The second is a request by address comparison A, which is BRKCR B
Permitted by the IEA bit. The third is a request by address comparison B, which is granted by the BIEB bit of BRKCR.

Note that this address comparison is as described above.
(CA23 / AR23 + @ CA23 / @ AR23 + AM
R23) · · · (CAn · ARn + $ CAn · @ARn
+ AMRn) ···· (CA0 · AR0 + ¬CA0 · ¬A
R0 + AMR0). These OR signals are supplied to the CPU as a break request.

In the break mode, permission / prohibition of the break request by the BRK terminal is selected according to the state of the BMBE bit. That is, when the BMBE bit is cleared to "0" in the break mode, the break request is suppressed. Break requests due to address comparison are prohibited in break mode.

The BMBE bit is constituted by a flip-flop, and is cleared to "0" by an inverted signal of the BMKE signal. The input of the flip-flop is a bit of a predetermined data bus, and the clock is an AND signal of a break mode signal, an address decode signal, and a write signal. Such an address decode signal is activated when the address output from the CPU becomes the address where BRKCR exists. That is, writing is enabled only in the break mode. That is, immediately after the transition to the break mode, the break request is in the disabled state, and the multiple exception processing of the undesired break is prohibited.

Also, the SSTP bit of BRKCR and B
The logical product of the RKAK signal and the inverted signal is given to the CPU as a single step break request. The logical product signal of the single step break request, the RTB instruction execution signal, and the break request are recognized inside the CPU as a CPU break exception processing request. The contents of these exception processes are common. When executing the RTB instruction, the CPU ignores the single step break request.

Next, the outline of the emulator will be described with reference to the block diagram of FIG.

The connector part is an application system (user system) instead of a single-chip microcomputer.
Attached to. The emulation processor inputs and outputs signals to and from the application system using the target system interface via the connector section and the interface cable.

Although not particularly limited, the user system has a user bus and is connected to a user memory. The user memory is read / written according to a user strobe signal output from the emulation processor and supplied via the interface cable. The reset signal is supplied from the user system via the interface cable.

A logical sum signal with the emulator reset signal is supplied to the RES terminal of the emulation processor. As the emulator reset signal, a logical sum signal of the delay circuit and the emulator memory wait signal is supplied to the EMLWAIT terminal of the emulation processor. The emulator reset signal is generated when the entire emulator is reset, such as when the emulator is turned on. Further, a user reset can be given as a command of the emulator based on information input from the system development device.

On the other hand, an emulation processor is connected to an emulation bus using the above emulation interface. The emulation bus includes status signals and control signals (not shown). Using the emulation bus, information and the like according to the application system and the internal state of the emulation processor are output from the emulation processor, and various control signals for emulation are input to the emulation processor. An emulation mode terminal (not shown) of the emulation processor is fixed at the power supply level, and the emulation mode is set inside the emulation processor.

Further, the emulation bus includes:
Although there is no particular limitation, there is an emulation memory such as a RAM for substituting a memory built in an application system or a target microcomputer.
The emulation memory includes a high-speed memory that acts as a substitute for the built-in ROM and a lending memory that is released to the user.

When a user program is created, a design is often made with a margin in capacity, and may not fit in a built-in ROM or the like. Also in such a case, the user can use the lending memory of the emulator to substantially expand the program memory and start debugging. As the debugging progresses, the program can be optimized so as to fit in a predetermined capacity. The rental memory does not necessarily require high speed due to its characteristics.

The emulation processor monitors the control state and the state of the emulation bus, and when the state reaches a preset state, inputs the emulator-dedicated interrupt to stop the execution of the user program by the CPU. A break control circuit for causing a transition to an emulation program execution state (break), an address and data provided to an emulation bus based on a signal indicating a read operation or a write operation of the CPU, a signal indicating an instruction read operation, and the like. Is connected to a real-time trace circuit for sequentially storing control information. The emulation bus is connected to an emulation memory, a break control circuit, a real-time trace circuit, and the like.

The break control circuit supplies the BRK signal to the emulation processor.

The emulation memory, the break control circuit, and the real-time trace circuit are connected to a control bus, and are controlled by a control processor via the control bus. The control bus is connected to an emulation processor control circuit, and via an interface circuit.
Although not particularly limited, it is connected to a system development device such as a personal computer.

For example, a program input from the system development device is transferred to the emulation memory, and when the CPU reads such a program to be arranged in the built-in ROM, the program on the emulation memory is read. Further, break conditions, real-time trace conditions, and the like can also be given from the system development device.

The control processor has the EMIRQ
Supply the signal to the emulation processor. The EMIRQ can be requested at a desired timing to cause the emulation processor to execute a predetermined EMIRQ interrupt processing routine.

Next, the operation of the emulator will be described with reference to the operation flowchart of FIG.

After the power is turned on, a break reset is first performed, and the mode is immediately set to the break mode, and the emulation program is executed. Which microcomputer operates as the emulation processor is input from the system development device, and the host interface,
It is set in the module control register via the control processor and the emulation memory (S1 to S
3).

The processing for the desired emulator is performed, and based on the command input from the system development device, etc.
If the execution of the user program is requested, the emulation processor executes the return instruction RTB instruction, transits to the user mode, and executes the user program (S
4-S6).

In this state, if a reset is requested from the user system, the user program is reset. At this time, the emulation dedicated register is held. When the user program to be executed ends or the condition set by the user is satisfied, the execution of the user program is interrupted (break), and the emulation program is executed (S7, S8, S6 to S9).

As shown in FIG. 4, during the break mode, 3-state access and EMLWAIT are permitted except for the window regardless of the user's designation. Since all emulation programs are allowed to wait, there is no restriction on the access speed of the emulation memory or the arrangement on the emulator. This facilitates the design of the emulator.

According to the emulation processor and emulator configured and operated as described above, the following effects can be obtained.

(1) By specifying whether to set the break mode or the user mode after the reset by the control terminal, it is possible to execute a desired program after the reset without requiring the control of the emulator. Further, by making the control terminal an EMLWAIT signal, it is not necessary to increase the number of input / output terminals of the emulation processor.

Furthermore, since the emulator control register is initialized at the time of a break reset and not initialized at the time of a user reset, the operation after the power is turned on can be determined, and the software for performing the initial setting can be omitted.

(2) The address space is divided, and a bus control register corresponding to the divided address space is provided. The bus control register specifies whether access is to be made using a user bus or an emulation bus. Thus, the user memory and the emulation memory can be mixed in the address space of the CPU without requiring the address determination circuit and the bus control circuit on the emulator side. The control terminal can be omitted.

Further, the division of the address space is made asymmetric,
By setting the size of the minimum area to 128 kB or the like, it is possible to correspond to the capacity of the memory that can be connected to the outside, and the flexibility in arranging the rental memory (emulation memory) and the user memory can be improved.

(3) By incorporating a PC break function, a break can be requested without the need for an address determination circuit or instruction execution determination circuit on the emulator side. In addition, since no external circuit is required, the time required for determination and control can be reduced, and it is easy to cause a break in a desired instruction execution state, thereby preventing the execution of several extra instructions. it can.

By outputting the coincidence detection function, it is possible to easily measure the time from a predetermined execution state to a predetermined execution state. Measurement such as the number of executions of a predetermined program can be easily performed. By requesting a break interrupt based on the measurement result, the user program can be easily stopped at a desired number of times of execution of the user program.

Further, by providing a single step designation bit, a break can be requested without the need for an address determination circuit or an instruction execution determination circuit on the emulator side. In addition, the time required for determination and control can be reduced, and a break can be easily performed each time an instruction is executed.

(4) An emulator stack area is provided,
It is possible to specify whether multiple interrupts of the break are prohibited or permitted, and by setting the initial value to the prohibited state, the address to be returned is not lost.

By permitting multiple interrupts for breaks with such control bits, a break interrupt can be requested in the break mode, and the flexibility is improved.

(5) In addition to the break interrupt, by providing a general interrupt that can be requested from the emulator, the monitor software can be started without using resources on the user side.

As described above, the invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and can be variously modified without departing from the gist thereof. Needless to say.

For example, there is no limitation on the size of the address space, the number of divisions, or the number and type of function blocks or modules to be incorporated, the number of pins, and the like. The arrangement of the control registers, the specific configuration of the emulation processor dedicated block, the specific configuration of the emulator, and the like are not limited to the above-described embodiment, and may be variously modified.

The bus cycle specified by the microcomputer includes, in addition to the bus width, the number of bus states and the address multiplex, the number of valid address bits, the output of an address decode signal, the multiplex of data and address, and the like. be able to. Some of these can be shared by emulation bus cycles. The bus width and the like may be common. What is necessary is just to prevent the contents of the memory on the user side from being destroyed. Output of an address decode signal or the like may be performed.

Further, the basic external bus cycle and the bus cycle of the internal ROM, the internal RAM, and the internal I / O register can be arbitrarily set. The register initialized only by a break reset can be arbitrarily changed.
The initial value can also be set arbitrarily. For example, external ST
When a hardware standby mode using the BY terminal is provided, all control registers may be initialized in the hardware standby mode.

The number and types of control signals for the emulator can also be arbitrarily changed. The input detection of the emulator dedicated interrupt can also be changed. A bit for selecting input detection may be provided.

In the above description, the case where the invention made by the present inventor is mainly applied to an emulation processor and an emulator having the emulator, which are fields of application, has been described. However, the present invention is not limited to this. The present invention can be widely applied to a semiconductor integrated circuit device having at least two operation states and arranging memories twice in an address space.

[0153]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) Means enabling selection of the transition to the break mode immediately after reset or the user mode by the state of the input terminal, and the access to the emulation memory for each area in the break mode Means for designating whether to access the memory, setting a break condition inside the emulation, particularly having a bit for requesting single-step processing, and when such a bit is in a predetermined state, for each instruction of the user program By providing a means for automatically requesting a break interrupt, data controlled outside the emulation processor can be taken into the emulation processor, so that abundant information inside the emulation processor is used in emulation. It becomes possible.

(2) According to the above (1), what is controlled externally is taken into the emulation processor, so that a signal delay from the emulation processor to the emulator and a signal from the emulator to the emulation processor are delayed. The effect of the delay can be eliminated.

(3) According to the above (1), what is controlled externally is taken into the emulation processor, so that emulation can be performed easily and at high speed without increasing the number of input / output signals between the emulation processor and the emulator. It is possible to control the processor for use.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a microcomputer to be emulated by an emulation processor according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an emulation processor according to the embodiment.

FIG. 3 is an explanatory diagram showing a configuration of an emulator dedicated register in the embodiment.

FIG. 4 is an explanatory diagram showing a configuration of an emulator dedicated register (continued from FIG. 3) in the embodiment.

FIG. 5 is an explanatory diagram showing a configuration of an emulator dedicated register (continued from FIG. 4) in the embodiment.

FIG. 6 is an explanatory diagram showing a configuration of an emulator dedicated register (continued from FIG. 5) in the embodiment.

FIG. 7 is an explanatory diagram showing a configuration of an emulator dedicated register (continued from FIG. 6) in the embodiment.

FIG. 8 is an explanatory diagram showing a configuration of an emulator dedicated register (continued from FIG. 7) in the embodiment.

FIG. 9 is an explanatory diagram showing a configuration of an emulator dedicated register (continued from FIG. 8) in the embodiment.

FIG. 10 is an explanatory diagram showing an address map of an address space in the embodiment.

FIG. 11 shows a MEMCR, an EWTCR in this embodiment.
FIG. 7 is an explanatory diagram showing an access state by the STA.

FIG. 12 shows a MEMCR, an EWTCR in this embodiment.
FIG. 12 is an explanatory diagram showing an access state (continued from FIG. 11) according to FIG.

FIG. 13 is a block diagram illustrating a bus configuration of an emulation processor in the present embodiment.

FIG. 14 is a timing chart showing an example of bus timing in the present embodiment.

FIG. 15 is a timing chart of a break reset in the present embodiment.

FIG. 16 is a timing chart of a user reset in the present embodiment.

FIG. 17 is a block diagram of a break reset control circuit in the present embodiment.

FIG. 18 is a block diagram of a break acknowledge signal control circuit in the present embodiment.

FIG. 19 is a block diagram illustrating an example of an emulation-dedicated control register in the present embodiment.

FIG. 20 is a block diagram of a break control circuit in the present embodiment.

FIG. 21 is a block diagram of an emulator equipped with an emulation processor according to the present embodiment.

FIG. 22 is an operation flowchart of an emulator including an emulation processor according to the present embodiment.

[Explanation of symbols]

 CPU Central processing unit DTC Data transfer controller ROM Read only memory RAM Random access memory SCI Serial communication interface A / D A / D converter IOP1 to IOP11 I / O port BSC bus controller CPG clock oscillator MS module select section IAB, PAB Internal address bus IDB, PDB Internal data bus Vcc, Vss Power supply terminal AVcc, AVss Analog power supply terminal RES Reset input terminal STBY Standby input terminal NMI Interrupt input terminal EXTAL, XTAL Clock input terminal MD0, MD1, MD2 Operation mode input terminal MSELR Module selection register MEMCR Memory control register EWTCR Wait control register BRKCR Break control Register BAR break address register BAMR break address mask register IRQCR emulator dedicated interrupt control register EMLSTKR emulator stack memory register

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Tatsuya Suzuki 5-2-21-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Co., Ltd. (56) References JP-A-6-150026 (JP, A) JP-A-5-282471 (JP, A) JP-A-5-120053 (JP, A) JP-A-2-144733 (JP, A) JP-A-6-59909 (JP, A) JP-A-6-314213 ( JP, A) JP-A-2-50230 (JP, A) JP-A-1-145740 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 11/22 340 G06F 11 / 28

Claims (4)

(57) [Claims] 1. An emulation processor capable of emulating a microcomputer, comprising: means for selecting a first mode in which an emulation program operates or a second mode in which a user program to be emulated operates. The address space of the microcomputer to be emulated is divided, and in at least one of the divided areas, a bus cycle specified by the microcomputer is performed in the second mode, or a bus cycle for emulation is set. Means for specifying whether to perform the operation, comprising a memory control bit corresponding to at least one of the divided address spaces, wherein in the second mode:
An emulation processor wherein a bus cycle specified by a microcomputer is performed when the memory control bit is in a first state, and an emulation bus cycle is performed when the memory control bit is in a second state. 2. The emulation processor according to claim 1 , wherein an emulator wait is always valid in said emulation bus cycle. 3. The emulation processor according to claim 1 , wherein the address space is divided into three or more, and
An emulation processor characterized in that one divided area is different from at least two or more other divided areas in the size of an address space. 4. An emulator equipped with the emulation processor according to claim 1, 2 or 3 , wherein the emulation processor, a user system memory read / write, and an emulator system memory read / write. Read and write the memory of the user system by a bus cycle designated by the microcomputer,
An emulator for reading or writing a memory of an emulator system by the emulation bus cycle.