JP3199138B2 - Microprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus access system, and more particularly to a microprocessor having internal resources which cannot be accessed from the outside in a normal operation state, and a technique particularly effective when used in the bus access system. .

[0002]

2. Description of the Related Art There is an emulator that is effective for efficiently debugging hardware and software of a microprocessor and its application system and shortening the development period. As shown in FIG. 8, the emulator executes a user program by a target microprocessor MPU or an evaluation microprocessor having a function equivalent thereto, while the break controller BRC controls an external bus, that is, an emulation bus EBUS. The access state is monitored, and the break interrupt request signal BRRQ is selectively asserted when a pre-registered break condition is satisfied (hereinafter, for example, to set the break interrupt request signal BRRQ or the like to a valid level is referred to as assertion, and is set to an invalid level). Is referred to as negation) to selectively stop the operation of the microprocessor MPU. The microprocessor MPU receives the break interrupt request signal BRRQ of the emulator EMU, starts interrupt processing, and asserts a break interrupt confirmation signal BRAK for the emulator EMU.

On the other hand, in emulation of a system including a microprocessor, it is effective to directly read or rewrite the contents held in a storage device connected to a bus and the contents held in a control register of an input / output device from the emulator. For this reason, in the conventional emulator, a method is employed in which the normal operation of the microprocessor is stopped using the above-described break function, and then the control register of the storage device or the input / output device is accessed. However, when this method is adopted, so-called real-time emulation cannot be performed because the microprocessor is stopped, which is a barrier to more detailed debugging.
In order to cope with this, in recent years, the normal operation of the microprocessor is temporarily stopped only for a period during which access to the control register of the storage device or the input / output device is performed, and immediately after the access is completed, the normal operation before the stop is immediately returned to A so-called parallel mode has been devised, and an emulator having such a parallel mode has been realized.

An emulator having a parallel mode and its parallel mode are described in, for example, "Hitachi Microcomputer Support Hardware H8 / 570ASEmo" issued by Hitachi, Ltd. in February 1992.
del-1], pp. 33-36.

[0005]

In the parallel mode described above, the emulator EMU asserts a break interrupt request signal BRRQ in response to the input of a predetermined command from the keyboard KB, and interrupts the microprocessor MPU. Microprocessor MPU
Receives the break interrupt request signal BRRQ, starts interrupt processing, and executes access to a storage device or a control register of an input / output device in accordance with the input command. Then, when the necessary access is completed, restoration processing from the interruption is performed, and normal processing before the interruption is restarted.

However, the present inventors have found that the emulator having the above-mentioned parallel mode has the following problems as microprocessors become more highly integrated and multifunctional. That is, the microprocessor has been provided with an internal bus to which internal resources such as a read-only memory and a random access memory are connected and which cannot be accessed from the outside, with the increase in the degree of integration and the functions of the microprocessor. In the parallel mode, the emulator EMU is an external device of the microprocessor, and must access the internal resources of the microprocessor by interrupt processing by a break. For this reason, even in the parallel mode, monitoring and rewriting of the internal resources of the microprocessor, ie, the user space, cannot be realized in real time, which hinders effective emulation.

An object of the present invention is to provide an effective bus access method for an internal bus which cannot be accessed in a normal operation state. Another object of the present invention is to realize effective real-time emulation of a microprocessor or the like having an internal resource that cannot be accessed in a normal operation state.

[0008] The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a dedicated bus master coupled to an external emulator via a serial interface unit is provided in a microprocessor or the like having internal resources that cannot be accessed in a normal operation state, and a bus access request by this bus master is given the lowest priority. Accept.

[0010]

According to the above-mentioned means, an internal bus to which internal resources such as a read-only memory and a random access memory are connected is accessed without requiring much hardware addition and without hindering a normal operation of a microprocessor or the like. be able to. Thereby, the internal resources such as the microprocessor, that is, the user space can be monitored or rewritten in real time in the emulation execution state, so that the effective real-time emulation of the microprocessor or the like having the internal resources that cannot be accessed in the normal operation state can be realized. Can be realized.

[0011]

FIG. 1 shows a connection diagram of one embodiment of an emulation system employing a bus access system to which the present invention is applied. First, an outline of the emulation system of this embodiment and a connection form thereof will be described with reference to FIG.

Referring to FIG. 1, the emulation system of this embodiment includes a microprocessor MPU and an emulator EMU. The emulator EMU is coupled on one side to the microprocessor MPU via an emulation bus EBUS and on the other side to an external bus of the user system. Various storage devices represented by the main memory MM and various input / output devices (not shown) are coupled to the external bus. The emulator EMU further includes a break interrupt request signal line BRR.
Q, break interrupt confirmation signal line BRAK, serial clock signal line SCK, serial input signal line SI
And a microprocessor MPU via a serial output signal line SO, and a keyboard KB and a display device DP via an input / output controller IOC.

The microprocessor MPU is constituted by a microprocessor itself which is a basic component of the user system or an evaluation microprocessor (evaluation chip) having a function equivalent thereto. In addition, as described later, an internal bus MBUS is provided,
It has so-called internal resources such as a read only memory ROM and a random access memory RAM coupled to the internal bus MBUS. The microprocessor MPU executes predetermined arithmetic processing in accordance with a control program stored in advance in a read-only memory ROM, and further controls and supervises the entire user system. Microprocessor M
The PU includes a bus arbiter BABT coupled to the emulator EMU via a break interrupt request signal line BRRQ and a break interrupt confirmation signal line BRAK, and an emulator via a serial clock signal line SCK, a serial input signal line SI, and a serial output signal line SO. A SIF bus master SIB coupled to the EMU. The specific configuration of the microprocessor MPU will be described later in detail.

Next, the emulator EMU includes an emulation control unit EMC, an emulation control memory ECM, a break controller BRC, a trace memory TRM, an emulation memory EMM, and a user interface unit U which are coupled to the emulation bus EBUS.
It has an IF. It also has a stored program type host processor HCPU, and has a system memory SYM and an IO controller IOC coupled to the host processor HCPU via an internal bus IBUS. The emulation control unit EMC, emulation control memory ECM, break controller BRC, trace memory TRM, and emulation memory EMM are further coupled to the internal bus IBUS. Further, a keyboard KB and a display device DP are connected to the IO controller IOC.

An emulation control unit EMC constituting the emulator EMU manages and controls the emulation operation by the emulator EMU according to the instruction of the host processor HCPU. At this time, the control information necessary for the emulation operation is stored in the emulation control memory E
The result of the bus cycle monitoring is stored in the trace memory TRM. Further, a predetermined user space is allocated to the emulation memory EMM,
A corresponding user program or the like is stored. Further, the break controller BRC has an emulation bus E
An address or data transmitted through the BUS is monitored, and when the contents thereof match an address or data previously given as a break condition, an internal control signal (not shown) for the emulation control unit EMC is selectively asserted. I do. Emulation control unit EMC
Receives the internal control signal, asserts a break interrupt request signal BRRQ, and requests the microprocessor MPU to perform a break interrupt process. This interrupt processing request is accepted with the lowest priority operation as described later, and as a result, the break interrupt confirmation signal BR
AK is asserted. User interface UIF
Is the emulation bus EBUS and the user system U
Used for interface matching with SY.

In this embodiment, the emulator EMU
Is further connected to a serial interface unit ESI coupled to a host processor HCPU via an internal bus IBUS.
F is provided. The serial interface ESIF is coupled to the serial interface MSIF of the microprocessor MPU via the serial input signal line SI and the serial output signal line SO, and synchronizes information such as internal bus access conditions and bus access results with the serial clock signal SCK. To give and receive serially.

FIG. 2 is a block diagram showing one embodiment of the microprocessor MPU included in the emulation system of FIG. FIG. 3 shows an SIF bus master SI included in the microprocessor MPU of FIG.
A block diagram of one embodiment of the BM is shown. further,
FIG. 4 shows a bit configuration diagram of one embodiment of the address registers ADRH and ADRL, the data register DR and the control register CR included in the SIF bus master IBM of FIG. 3, and FIG. 5 shows the microprocessor MPU of FIG. An address map diagram of one embodiment is shown. With reference to these drawings, an outline of the configuration and operation of the microprocessor MPU included in the emulation system of this embodiment and its features will be described.

In FIG. 2, the microprocessor MPU of this embodiment has a central processing unit CPU as a basic component. The central processing unit CPU has an internal bus MBUS.
A read only memory ROM and a random access memory RAM, which are internal resources of the microprocessor MPU, are connected via the
C, a refresh controller REFC, an input / output port unit IOP, a bus controller BUSC, and an external bus interface unit EBIF. The internal bus M
The BUS includes, but is not limited to, a 16-bit address bus and an 8-bit data bus, and internal resources coupled thereto cannot be accessed from any external device in a normal operation state.

Here, the central processing unit CPU executes a predetermined logical operation according to a control program stored in the read-only memory ROM, and controls and supervises the operation of each unit of the microprocessor MPU. Also,
Read-only memory ROM is a mask ROM or EPR
OM (Erasable and Programma)
ble ROM) etc., and the central processing unit C
Stores programs and fixed data necessary for step control of the PU. Furthermore, random access memory RAM
Is composed of a dynamic RAM, and temporarily stores the operation result and control data of the central processing unit CPU.

On the other hand, the refresh controller REFC
Includes a timer circuit, an address generation circuit, and the like, and performs a refresh operation for all addresses of a dynamic RAM constituting a random access memory RAM at a predetermined cycle. Also, the DMA controller DMAC
Controls autonomously and at high speed to perform a series of data transfer between the random access memory RAM and the main memory MM coupled to the external bus. The bus controller BUSC controls execution of access to each bus. The input / output port unit IOP serves as an interface with a communication control device and the like, and the external bus interface unit EBI
F is an interface between the internal bus MBUS and the external bus, that is, the emulation bus EBUS.

In this embodiment, the microprocessor MPU is further provided with a dedicated bus master, that is, an SIF bus master SI provided for the external emulator EMU.
A BM and a bus arbiter BABT for selectively receiving a bus access request issued from each bus master. The bus arbiter BABT includes bus access request signal lines CBRQ, DBRQ, RBRQ, and SBRQ.
And bus access confirmation signal lines CBAK, DBAK,
Microprocessor MP via RBAK and SBAK
Each bus master in U, that is, central processing unit CPU, DMA
Controller DMAC, refresh controller RE
The emulator EM is coupled to the FC and SIF bus masters IBM respectively via a break interrupt request signal line BRRQ and a break interrupt confirmation signal line BRAK.
U is coupled to the emulation control unit EMC. The SIF bus master SIBM is coupled to the internal bus MBUS and the SIF dedicated bus SBUS, and is connected to the emulator EMU via the serial clock signal line SCK, the serial input signal line SI, and the serial output signal line SO.
Is connected to the serial interface section ESIF.

When the bus access request signal line CBRQ, DBRQ, RBRQ, or SBRQ is asserted, the bus arbiter BABT causes the central processing units CPU, DM
A controller DMAC, refresh controller R
A bus access request from the EFC or SIF bus master IBM is identified, and an external bus access request signal EBR
When Q is asserted, an external bus access request is identified. Then, these bus access requests are alternatively received in accordance with a predetermined priority, and the corresponding bus access confirmation signals CBAK, DBAK, RBA are received.
Selectively assert K or SBAK or EBAK.

On the other hand, the SIF bus master IBM
As shown in FIG. 3, the internal bus MBUS and various registers coupled to the SIF dedicated bus SBUS, that is, address registers ADRH and ADRL, a data register DR and a control register CR,
An F bus master control unit SBMC and a serial interface unit MSIF are provided. SIF bus master control unit SBM
C is coupled to a bus arbiter BABT via a bus access request signal line SBRQ and a bus access confirmation signal line SBAK, and the serial interface MSIF is connected via a serial clock signal line SCK, a serial input signal line SI, and a serial output signal line SO. Emulator EMU
Is connected to the serial interface section ESIF.

As shown in FIG. 4, address registers ADRH and ADRL constituting SIF bus master SIBM have 16-bit address signals A0 to A16 of the internal bus access conditions for accessing internal bus MBUS.
A15 is stored, and the data register DR stores 8-bit data D0 to D7. The control register CR includes a request bit REQ corresponding to the bus access request signal SBRQ, a read / write bit RW designating a bus access direction, and an end bit END indicating that the bus access has been completed.

The data stored in the data register DR is 8
Bit data D0 to D7 are stored in SIF bus master SIB.
If the internal bus access by M is in read mode,
Read data from a read-only memory ROM or random access memory RAM or read information from a control register such as a DMA controller DMAC or a refresh controller REFC. In the write mode, write data to the random access memory RAM or DMA controller DMAC or refresh data. This is write information for a control register such as the controller REFC. On the other hand, the internal bus MBUS designated by the 16-bit address signals A0 to A15, that is, the address space of the microprocessor MPU is shown in FIG.
As shown in the figure, the address "0000" in hexadecimal notation
To “FFFF”, of which addresses “0000” to “3FFF” are allocated to a read-only memory ROM built in the microprocessor,
Addresses “E000” to “EFFF” and “F
000 ”to“ FFFF ”are assigned to the built-in random access memory RAM and the input / output device IO, respectively, and the addresses“ 4000 ”to“ 7FF ”.
F ”is allocated to a relatively low-speed so-called three-state type external device, and has addresses“ 8000 ”to“ DFF ”.
F ″ is assigned to a relatively high-speed two-state type external device.

The SIF bus master IBMB takes in address signals A0 to A15, data D0 to D7, request bits REQ and read / write bits RW which are serially input as internal bus access conditions from the serial interface unit ESIF of the emulator EMU. Address registers ADRH and ADRL,
Data register DR and control register CR
To be stored. Further, in response to the request bit REQ being set, the bus access request signal SBRQ is asserted to request the bus right to the bus arbiter BABT, and to receive the bus access confirmation signal SBAK from the bus arbiter BABT to access the internal bus MBUS. And the internal bus MBUS according to the read / write bit RW
Execute read access or write access to.

FIG. 6 shows the SIF bus master SIB of FIG.
A processing flow diagram of one embodiment of microprocessor internal bus access by M is shown. With reference to the figure, a method of accessing the internal resources of the microprocessor of the emulator EMU in the emulation system of this embodiment and its characteristics will be described.

In FIG. 6, the access to the microprocessor internal bus by the emulator EMU is started by inputting an internal bus access command from the keyboard KB during execution of the emulation. In the emulator EMU, upon receiving the input of the internal bus access command, the generation of the internal bus access condition by the host processor HCPU is started, and based on the address, write information, operation mode and the like input as a part of the command from the keyboard KB. A series of internal bus access conditions are generated. These internal bus access conditions are controlled by the SIF of the microprocessor via the serial input signal SI from the serial interface ESIF of the emulator EMU.
The data is transferred to the bus master IBM and stored in the address registers ADRH and ADRL, the data register DR, and the control register CR. Then, the bus access request signal SBRQ is asserted in response to the setting of the request bit REQ of the control register CR, and the bus arbiter BAB is sent from the SIF bus master IBM.
A bus right request to T is made.

The bus arbiter BABT of the microprocessor MPU receives the assertion of the bus access request signal SBRQ, identifies the bus right request by the SIF bus master IBMB, and on the condition that the bus right requests from other bus masters are not congested. , Asserts a bus access confirmation signal SBAK to give the SIF bus master IBM an internal bus access right. Thereby, the SIF bus master SIB
M is an internal bus MBUS, that is, a read only memory ROM, a random access memory RAM, or a DMA.
Controller DMAC or refresh controller R
Executes access to the EFC control register and the like. At this time, in the case of a write access, the SIF bus master SIB
Data D0 to D7 stored in M data register DR
Is transmitted to the data bus of the internal bus MBUS as write data, and in the case of read access, read data output via this data bus is transmitted to the SIF bus master S.
It is stored in the IBM data register DR. In the control register CR, when the internal bus access ends, the end bit END is set. The internal bus access result held by each register is transmitted from the serial interface unit MSIF to the serial output signal SO.
Is transferred to the serial interface section ESIF of the emulator EMU via the
The microprocessor internal bus access by U ends.

As described above, the microprocessor MPU of this embodiment has the dedicated SIF bus master SIBM coupled to the external emulator EMU via the serial interface sections MSIF and ESIF. That is, during execution of the emulation, the internal bus M of the microprocessor MPU is used.
BUS access right temporarily acquired, read only memory ROM and random access memory RAM
And other internal resources of the microprocessor. As a result, the user space can be easily monitored or rewritten by the emulator EMU, so that an effective real-time emulation of a microprocessor MPU having internal resources that cannot be accessed in a normal operation state can be realized. Note that SI
Since the F bus master IBM and the emulator EMU are connected via the serial interface unit, the number of additional external terminals of the microprocessor due to the addition of the above function can be reduced. Also, the SIF bus master SI
By setting the BM bus priority to the lowest priority, the SIF
Since the influence of the internal bus access by the bus master IBM on other bus masters is suppressed, high-precision emulation can be realized without hindering the normal operation of the microprocessor MPU.

As shown in the above embodiment, the following effects can be obtained by applying the present invention to a microprocessor having an internal resource which cannot be accessed in a normal operation state and its bus access method. be able to. (1) A dedicated bus master coupled to an external emulator via a serial interface unit is provided in a microprocessor or the like having internal resources that cannot be accessed in a normal operation state, and a bus access request by this bus master is assigned to the lowest order. By receiving with priority, the internal bus of the microprocessor or the like to which the read-only memory and the random access memory are coupled is accessed without much hardware addition and without interrupting the normal operation of the microprocessor or the like. The effect that it can be obtained is obtained. (2) According to the above item (1), it is possible to monitor or rewrite the internal resources such as the microprocessor, that is, the user space in real time in the emulation execution state. (3) According to the above items (1) and (2), there is obtained an effect that effective real-time emulation of a microprocessor or the like having internal resources that cannot be accessed in a normal operation state can be realized.

Although the invention made by the present invention and the like has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say, there is. For example, in FIG. 1, it is not essential that the microprocessor MPU and the emulator EMU are coupled through a serial interface unit. That is, when there is a margin in the number of external terminals of the microprocessor MPU, for example, as shown in FIG. 7, the microprocessor MPU and the emulator EMU can be directly connected by the SIF dedicated bus SBUS. In this case, emulator EMU provides bus access request signal SB
The bus access right can be requested by asserting RQ, and the bus access right can be obtained by asserting the bus access confirmation signal SBAK. SIF
The bus master IBM can be effective only when the microprocessor MPU is used as an evaluation microprocessor for emulation. Further, the block configuration of the emulator EMU and the connection configuration as the emulation system are not restricted by this embodiment.

In FIG. 2, SIF bus master IBM
The priority of the bus right given to the server is not required to be the lowest priority. In addition, the microprocessor MPU
The internal resources and the number and types of bus masters and the block configuration of the microprocessor MPU can adopt various embodiments. The block configuration of the SIF bus master IBM shown in FIG. 3, the bit configuration of each register shown in FIG. 4, the address map shown in FIG. 5, and the internal bus access processing flow shown in FIG. Is not restricted by

In the above description, the case where the invention made by the present inventor is mainly applied to the microprocessor and the emulation system thereof, which are the field of application, has been described. However, the present invention is not limited to this. It can also be applied to various digital processing devices having various internal resources and emulation systems thereof. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a processing device having an internal resource that is inaccessible at least in a normal operation state and a bus access method thereof.

[0035]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a microprocessor or the like having internal resources that cannot be accessed in a normal operation state,
A dedicated bus master that is connected to an external emulator via the serial interface unit is provided, and the bus access request by this dedicated bus master is accepted with the lowest priority. And the like, and can access an internal bus to which internal resources such as a read-only memory and a random access memory are coupled. Thereby, the internal resources such as the microprocessor, that is, the user space can be monitored or rewritten in real time in the emulation execution state, so that the effective real-time emulation of the microprocessor or the like having the internal resources that cannot be accessed in the normal operation state can be realized. Can be realized.

[Brief description of the drawings]

FIG. 1 is a connection diagram showing one embodiment of an emulelan system adopting a bus access method to which the present invention is applied.

FIG. 2 is a block diagram illustrating a first embodiment of a microprocessor included in the emulation system of FIG. 1;

FIG. 3 is a block diagram showing one embodiment of an SIF bus master included in the microprocessor of FIG. 2;

FIG. 4 is a bit configuration diagram showing an embodiment of an address register, a data register, and a control register included in the SIF bus master of FIG. 3;

FIG. 5 is an address map diagram showing one embodiment of the microprocessor of FIG. 2;

FIG. 6 is a processing flowchart showing one embodiment of microprocessor internal bus access by the SIF bus master of FIG. 3;

FIG. 7 is a block diagram showing a second embodiment of the microprocessor included in the emulation system of FIG. 1;

FIG. 8 is a connection diagram showing an example of a conventional emulation system.

[Explanation of symbols]

MPU: Microprocessor, EMU: Emulator, EBUS: Emulation bus, IBU
S: emulator internal bus, EMC: emulation control unit, ECM: emulation control memory, BRC: break controller, TRM ...
Trace memory, EMM: Emulation memory, HCPU: Host processor, SYM: System memory, ESIF: Emulator serial interface unit, IOC: IO controller, UI
F: User interface unit, MM: Main memory, KB: Keyboard, DP: Display device. CPU: central processing unit, MBUS: microprocessor internal bus, SBUS: SIF dedicated bus, DMAC: DMA controller, REFC ...
・ Refresh controller, SIBM ・ ・ ・ SIF bus master, BABT ・ ・ ・ Bus arbiter, ROM ・ ・ ・
Read-only memory, RAM: Random access memory, IOP: Input / output port, BUSC:
Bus controller, EBIF ... External bus interface unit. SBMC: SIF bus master control unit, AD
RH, ADRL: Address register, DR: Data register, CR: Control register, MS
IF: microprocessor serial interface unit.

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-63-304334 (JP, A) JP-A-4-148343 (JP, A) JP-A-4-77833 (JP, A) JP-A 64-64 7235 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 11/22-11/277 G06F 15/78

Claims (4)

(57) [Claims] A plurality of function blocks including a central processing unit ; an internal bus connected to the plurality of function blocks; and a serial input / output interface connected to the internal bus.
A bus master and a chair circuit a first register, and arbitration means for arbitrating access to said internal bus is a microprocessor which is formed on the same chip, the emulation execution state of the microprocessor
Oite, wherein the bus master address for designating the address space of the microprocessor the Syrian
Input from the outside of the microprocessor via the input / output interface circuit and held in the first register.
And the first bus master communicates with the arbitration means.
Request access to the local bus, before the arbitration means
After obtaining the right to access the internal bus,
And accessing the address to input or output necessary internal data. 2. The first bus master according to claim 1, further comprising a second register for holding data for writing to the address or data read from the address. A microprocessor characterized in that: 3. An access request by the bus master according to claim 1, wherein the access request by the bus master has the lowest priority.
A microprocessor to which a degree is assigned . 4. A one of claims 1 to 3, the address inputted from outside of the microprocessor, the microprocessor, characterized in that an address supplied from the emulator.