JP2002514320A - Active matrix light emitting diode pixel structure and method - Google Patents

Active matrix light emitting diode pixel structure and method

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JP2002514320A
JP2002514320A JP54637898A JP54637898A JP2002514320A JP 2002514320 A JP2002514320 A JP 2002514320A JP 54637898 A JP54637898 A JP 54637898A JP 54637898 A JP54637898 A JP 54637898A JP 2002514320 A JP2002514320 A JP 2002514320A
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transistor
coupled
source
gate
drain
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JP4251377B2 (en
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ドーソン,ロビン,マーク,アドリアン
ケイン,マイケル,ギリス
スー,ジェイムズ,ヤ−コング
スー,フ−ラング
イプリ,アルフレッド,チャールズ
ステュワート,ロジャー,グリーン
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サーノフ コーポレイション
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • G09G3/325Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror the data current flowing through the driving transistor during a setting phase, e.g. by using a switch for connecting the driving transistor to the data driver
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/04Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions
    • G09G3/06Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions using controlled light sources
    • G09G3/10Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions using controlled light sources using gas tubes
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809Several active elements per pixel in active matrix panels
    • G09G2300/0819Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809Several active elements per pixel in active matrix panels
    • G09G2300/0842Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809Several active elements per pixel in active matrix panels
    • G09G2300/0842Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809Several active elements per pixel in active matrix panels
    • G09G2300/0842Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00Control of display operating conditions
    • G09G2320/04Maintaining the quality of display appearance
    • G09G2320/043Preventing or counteracting the effects of ageing

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of El Displays (AREA)

Abstract

(57)【要約】 ピクセル構造の「駆動トランジスタ」の電流不均一性及び閾値電圧変化を低減するLEDピクセル構造(200、300、400、600、700)を開示する。LEDピクセル構造は、電流源を組み込んでおり、データをピクセルにデータラインを通してロードする。代わりに、オートゼロの電圧は、駆動トランジスタデータのロードに先立って決定される。 Abstract: Disclosed are LED pixel structures (200, 300, 400, 600, 700) that reduce current non-uniformity and threshold voltage variation of a pixel structure "drive transistor". The LED pixel structure incorporates a current source to load data into the pixel through data lines. Instead, the auto-zero voltage is determined prior to loading the drive transistor data.

Description

【発明の詳細な説明】 アクティブマトリックス発光ダイオードピクセル構造及び方法 本出願は、1997年4月23日に出願された米国仮出願第60/044,174号の利 益を主張する。その内容は本明細書に援用されている。 本発明は、契約番号F33615-96-2-1944の下、米国政府の支持を得てなされた 。米国政府は、本発明において確かな(certain)権利を有する。 本発明は、アクティブマトリックス発光ダイオードピクセル構造に関する。更 に詳細には、本発明は、ピクセル構造の「駆動トランジスタ」において、電流不 均一性及び閾値電圧変化を低減するピクセル構造、及び前記アクティブマトリッ クス発光ダイオードピクセル構造を動作する方法に関する。 開示の背景 マトリックスディスプレイは当該技術においてかなり知られており、図1で示 すように、マトリックスアドレッシングを使用してピクセルが照明される(illu minate)。代表的なディスプレイ100は、行列(ロー及びカラム)に配置され た複数のピクチャ又は表示部材(ピクセル)160を含む。ディスプレイは、カ ラムデータ発生装置110及びローセレクト発生装置120を組み込んでいる。 動作中、各ローはローライン130を通して順に起動され、対応するカラムライ ン140を用いて対応するピクセルが起動させられる。パッシブマトリックスデ ィスプレイでは、ピクセルの各ローは順に1つずつ照明されるが、アクティブマ トリックスディスプレイでは、ピクセルの各ローは、最初にデータと共に連続し てロードされる。 例えばラップトップコンピュータといったポータブルなディスプレイの使用が 増加し、種々のディスプレイテクノロジー(例えば液晶ディスプレイ(LCD) 及び発光ダイオード(LED)ディスプレイ)が、採用されてきている。これら の2つの技術の重要な差異は、LEDが発光装置であって、非発光装置(LCD 等)よりもパワー効率上の利点を有することである。LCDにおいて、蛍光性の バックライトは、ディスプレイが使用中である持続時間全体でオンであり、ピク セルを「オフ」するためにさえパワーを消費する。これに対して、LED(又は OLED)ディスプレイは、起動されたピクセルのみを照明し、「オフ」ピクセ ルを照明しないことによってパワーを節約する。 OLEDピクセル構造を採用したディスプレイは、パワー消費量を低減するこ とができるが、このようなピクセル構造は強度に不均一性を示す可能性があり、 それは、製造による駆動トランジスタ及びトランジスタ不均一性の閾値電圧ドリ フトに起因している。しかし、OLEDの明るさがOLEDを通過する電流に比 例していることが判った。 従って、ピクセル構造の「駆動トランジスタ」における電流不均一性及び閾値 電圧変化を低減するピクセル構造及び付随する方法が、当該技術に必要である。 発明の概要 本発明の一実施形態では、電流源がLED(OLED)ピクセル構造の中に組 み込まれており、ピクセル構造の駆動トランジスタでの電流不均一性及び閾値電 圧変化を低減する。電流源はデータラインに結合されており、そこでは、一定の 電流が最初にプログラムされており、それから収集される。 代わりの実施形態では、オートゼロ(auto zero)電圧を決定して記憶するオ ートゼロフェーズで、基準電圧を最初に適用することによって一定の電流が達成 される。オートゼロの電圧は、駆動トランジスタの閾値電圧を効果的に説明する 。次に、同じ基準電圧に関連するデータ電圧が、ピクセルを照明するために、今 、適用される。 他の実施形態では、レジスタがLED(OLED)ピクセル構造内に組み込ま れており、駆動トランジスタの閾値電圧に対する、OLEDを通過した電流の依 存の感度を下げるようになっている。 図面の簡単な説明 本発明の教示内容は、添付図面に関連して、以下の詳細な説明を考慮すること によって容易に理解されることができる。 図1は、マトリックスアドレッシングインタフェースのブロック図である。 図2は、本発明のアクティブマトリックスLEDピクセル構造の回路図である 。 図3は、本発明のアクティブマトリックスLEDピクセル構造の代替の実施形 態の回路図である。 図4は、本発明のアクティブマトリックスLEDピクセル構造の他の代替の実 施形態の回路図である。 図5は、本発明の複数のアクティブマトリックスLEDピクセル構造を有する ディスプレイを使ったシステムのブロック図である。 図6は、図2のアクティブマトリックスLEDピクセル構造の代替の実施形態 の回路図である。 図7は、本発明のアクティブマトリックスLEDピクセル構造の代替の実施形 態の回路図である。 理解を容易にするために、図に共通の同一の部材を示すために可能なところで は同一の参照数字を使用した。 詳細な説明 図2は、本発明のアクティブマトリックスLEDピクセル構造200の回路図 を示す。好ましい実施形態において、アクティブマトリックスLEDピクセル構 造は、例えば、アモルファス又はポリシリコンを使用して製造されるトランジス タである薄膜トランジスタ(TFT)を使用して実行される。同じように、好ま しい実施形態において、アクティブマトリックスLEDピクセル構造は、有機発 光ダイオード(OLED)を組み込んでいる。本ピクセル構造は薄膜トランジス タ及び有機発光ダイオードを使用して実行されるが、本発明がトランジスタ及び 発光ダイオードの他のタイプを使用して実行されることができることが理解され なくてはならない。例えば、他の材料を使用して製造されるトランジスタが上述 したように閾値不均一性を示するならば、本発明は、照明部材を通して一定の電 流を提供するために使われることができる。 本発明を、単一のピクセル又はピクセル構造として下に示すが、ピクセルはデ ィスプレイを形成するために他のピクセルと(例えば配列で)使用することがで きることを理解しなければならない。更に、下の図は特定のトランジスタ形状を 示すが、トランジスタのソースが電圧サインに対応することを理解されなければ ならない。 図2について述べる。ピクセル構造200は、3つのPMOSトランジスタ2 40、250、260、NMOSトランジスタ270、コンデンサ280及びL ED(OLED)290(光部材)を含む。セレクトライン210は、トランジ スタ240、250及び270のゲートに結合されている。データラインはトラ ンジスタ250のソースに結合され、+VDDラインはトランジスタ270のドレ インに結合されている。OLED290の1つの電極は、トランジスタ240及 び260のドレインに結合されている。トランジスタ240のソースは、トラン ジスタ260のゲート及びコンデンサ280の1つのターミナルに結合されてい る。最後に、トランジスタ250のドレイン、トランジスタ270のソース、ト ランジスタ260のソース及びコンデンサ280の1つのターミナルは、全て1 つに結合されている。 本ピクセル構造200は、大きな閾値電圧(Vt)不均一性存在下で、均一な 電流駆動を提供する。言い換えると、OLEDを横切って均一な電流を維持し、 ディスプレイの強度の中で均一性を確保することが望ましい。 より詳細には、OLEDピクセル構造は、2つのフェーズ、ロードデータフェ ーズ及び連続照明フェーズにおいて動作される。 ロードデータフェーズ ピクセル構造200は、適当なセレクトライン210を駆動させることによっ てデータがロードされ得る。即ち、セレクトラインが「ロー」にセットされると 、トランジスタP4(240)は「オン」にされ、OLED290の陽極側の電 圧がトランジスタP2(260)のゲートに送られる。同時に、トランジスタP 1(250)も、「オン」にされ、データライン220からの一定の電流がトラ ンジスタP2(260)及びOLED290の両方を流れる。即ち、トランジス タ260は、電流源230によって駆動された電流を下げるためにオンにする。 データラインを駆動する電流源230は、外部のデータによってプログラムされ ている。トランジスタ260(駆動トランジスタ)のソース電圧へのゲートは、 次に電流を駆動するために必要な電圧に定まる。同時に、トランジスタN1(2 70)は「オフ」にされて、電源+VDDはOLED290から切り離される。一 定の電流源230も、ソースからゲートへの電圧を自己調整し、固定オーバドラ イブ値(電圧)をトランジスタ260に適応させ、ポリシリコンTFT260の 閾値変化を補う。オーバドライブ電圧は、データを示す。順番に、データは記憶 コンデンサCS280の上で、適切に記憶される。これでデータのためのロード 又はライトサイクルを完了する。 連続照明フェーズ セレクトラインが「ハイ」にセットされると、P1(250)及びP4(24 0)の両トランジスタは「オフ」にされ、トランジスタN1(270)は「オン 」にされる。トランジスタ260の電源電圧がわずかに変化する可能性があるが 、トランジスタ260のソースからゲートへの電圧が照明サイクル中の電流レベ ルを制御する。コンデンサ280を横切るトランジスタ270のVSGは、即座に 変わることができない。このように、トランジスタ260のゲート電圧はソース 電圧を追尾し、ソースからゲートへの電圧が、全体のロード及び照明フェーズを 通して維持される。ポリシリコンTFTの漏れ電流及びOLEDのグレースケー ル輝度に要求される電圧解像度は、フレームタイムの有効データを保持するため に必要な記憶コンデンサのサイズを決定する。好ましい実施形態において、コン デンサは0.25pfのオーダにある。即ち、トランジスタ260の電流漏れを 考慮するのにコンデンサは十分大きいであろう。これで照明フェーズピクセル動 作を完了する。 各データ/カラムライン220はそれ自身のプログラムされた一定の電流源2 30を有する点に留意する必要がある。照明フェーズ中に、データラインに後続 のプログラムされた電流源が送られ、全てのピクセルの次のローをロードして、 前のローのピクセルが照明フェーズの中で全フレーム時間動作している。このよ うに、図2のピクセル構造は、2.5のラインを有する1つのNMOSトランジ スタ及び3つのPMOSトランジスタのみを必要とする。(隣接のピクセルと共 有されうるVDD電圧供給、セレクトライン、データライン電流ソース)。 代替として、図6は、図2のピクセル構造が、全てのPMOSトランジスタを 有して実行される実施例を示し、それは、PMOS又はNMOSプロセスのみの どちらを使用しても経済的である。NMOSトランジスタN1は、PMOS P 3トランジスタ610で置換されている。しかし、追加のライン(制御ライン) 620はトランジスタ610のゲートに結合され、追加のPMOSトランジスタ をアドレッシングし、もって合計3.5のライン(即ち追加のPMOSゲートを 制御するための追加の電圧供給)を必要とする。 要するに、図2及び図6のピクセル構造は、トランジスタ260のVSG上での 自調整/トラッキング機構によって、またOLED290を通して一定の電流源 を供給することによって、ポリシリコンTFT及びOLEDの両方の閾値変化を 補うためように設計されている。実際、図2及び図6のピクセル構造は、ロード 及び照明フェーズの両方の最中に高電圧供給を有する適当な動作を達成すること ができる。これらのピクセル構造は、OLED又はピクセルポリシリコンTFT の両方での不安定にもかかわらず、良好なグレースケール均一性及び高いライフ タイムを有する高品質のOLEDディスプレイを設計するために実行されること ができる。 図3は、本アクティブマトリックスピクセル構造の代替の実施形態を示す。代 替の実施形態において、データライン電圧は、ピクセル構造内で電流に変換され 、図2及び図6で上述した電流源の実施のような電圧電流変換器を必要としない 。 図3について述べる。ピクセル構造300は、4つのPMOSトランジスタ( 360、365、370、375)、2つのコンデンサ350及び355及びL ED(OLED)380を含む。セレクトライン320は、トランジスタ360 のゲートに結合している。データライン310はトランジスタ360のソースに 結合され、+VDDラインはトランジスタ365のソース及びコンデンサ355の 1つのターミナルに結合されている。オートゼロライン330はトランジスタ3 70のゲートに結合され、照明ラインはトランジスタ375のゲートに結合 されている。OLED280の1つの電極は、トランジスタ375のドレインに 結合されている。トランジスタ375のソースは、トランジスタ365及び37 0のドレインに結合されている。トランジスタ360のドレインは、コンデンサ 350の1つのターミナルに結合されている。最後に、トランジスタ365のゲ ート、トランジスタ370のソース、コンデンサ350の1つのターミナル及び コンデンサ355の1つのターミナルは、全て結合されている。 より詳細には、図3は3つのフェーズの中で動作されるピクセル構造300を 示す。即ち、1)オートゼロフェーズ、2)ロードデータフェーズ、3)照明フ ェーズである。 オートゼロ オートゼロライン330及び照明ライン340が「ロー」にセットされると、 トランジスタP2(375)及びP3(370)は、「オン」に変わり、トラン ジスタP1(365)のドレイン側の電圧は、ゲートに送られ、一時的にダイオ ードに連結される。データライン310は「基準電圧」にセットされ、セレクト ライン320は「ロー」にセットされる。基準電圧は任意にセットされることが できるが、それは最高データ電圧より大きくなくてはならない。 次に、照明ライン340は「ハイ」にセットされ、トランジスタP2 375 が「オフ」にされる。ピクセル回路は、今、トランジスタP1 365(駆動ト ランジスタ)の閾値に定まり、もってデータラインの基準電圧とコンデンサCC 350のトランジスタP1 365の閾値電圧との間の差異である電圧(オート ゼロ電圧)を記憶する。これによって、ゲート電圧、又はより正確にはトランジ スタ365のVSGをトランジスタ365の閾値電圧にセットする。これは、次に 、トランジスタP1(365)上に、閾値電圧変化に関係なく固定オーバドライ ブ電圧を提供する。最後に、オートゼロライン330は「ハイ」にセットされ、 トランジスタP1 365のゲートを絶縁する。オートゼロの目的は、これから 達成される。 ロードデータフェーズ オートゼロフェーズの終わりに、セレクトラインは「ロー」にセットされ、デ ータラインは「基準電圧」であった。今、データライン310は、データ電圧に セットされる。データ電圧は、トランジスタP1(365)のゲート上にコンデ ンサCC350を通して送られる。次に、セレクトラインは、「ハイ」にセット される。このように、トランジスタ365のVSGは、一定の電流レベルを提供す るために、トランジスタ365に固定オーバドライブ電圧を提供する。これはロ ードデータフェーズを終了し、ピクセルは照明用となる。 デセレクト(deselect、選択から外す)ローフェーズ中の連続照明データフェー ズ データ電圧がトランジスタP1(365)のゲート上で記憶されると、照明ラ イン340が「ロー」にセットされ、トランジスタP2 375が「オン」にさ れる。トランジスタP1 365によって供給される電流は、OLED380を 通して流れることができるようになる。要するに、トランジスタ365は一定の 電流源のように機能する。これで照明フェーズが完了する。 図4に、本アクティブマトリックスピクセル構造の代替の他の実施形態を示す 。代替の実施形態において、データライン電圧はまた、ピクセル構造の内で電流 に変換され、電流源の図2及び6で上述したように、電流源での実施のような電 圧電流変換器を必要としない。 図4について述べる。ピクセル構造400は、3つのPMOSトランジスタ( 445、460、465)、2つのコンデンサ450及び455及びLED(O LED)470を含む。セレクトライン420は、トランジスタ445のゲート に結合している。データライン410はトランジスタ445のソースに結合され 、VSWPラインはトランジスタ460のソース、コンデンサ455の1つのタ ーミナルに結合される。オートゼロライン430は、トランジスタ465のゲー トに結合されている。OLED470の1つの電極は、トランジスタ465及び 460のドレインに結合されている。トランジスタ445のドレインは、コンデ ンサ450の1つのターミナルに結合されている。最後に、トランジスタ4 60のゲート、トランジスタ465のソース、コンデンサ450の1つのターミ ナル及びコンデンサ455の1つのターミナルは、全て結合されている。 より詳細に、図4は、3つのフェーズの中で動作されるピクセル構造400を 示す。即ち、1)オートゼロフェーズ、2)ロードデータフェーズ、3)照明フ ェーズである。 オートゼロ(VSWPによる)フェーズ VSWP(供給を切り換える電圧)は「ローワ(より低い、lower)電圧」に 量「ΔV」だけセットされる。ここで、ローワ電圧は、OLED470が少量の 電流(例えば、ナノアンプのオーダで、OLED特性に依存して)を少しずつ流 すように選択される。ローワ電圧は、コンデンサに結合されたCC(450)と トランジスタP4(445)との間の浮動ノード(fによるダイリューションな しでトランジスタP1(460)VG(P1)のゲートを通して結合される。オート ゼロライン430は、次に「ロー」セットされる。トランジスタP1(460) (駆動トランジスタ)は、トランジスタP3(465)を閉じることによってダ イオードとして一時的に連結される。セレクトライン420は次に「ロー」にセ ットされ、「基準電圧」はデータライン410に適用される。基準電圧は任意に セットされることができる、しかし、最高データ電圧より大きくなくてはならな い。ピクセル回路は、今、トランジスタP1 460の閾値に定まることができ る。最後に、オートゼロライン430は次に「ハイ」にセットされ、トランジス タP1 460のゲートを絶縁する。オートゼロフェーズの効果は、記憶装置に コンデンサCC450に電圧(オートゼロ電圧)を記憶することであり、それは データライン上基準電圧とP1 460のトランジスタ閾値電圧との間での差異 を表す。これはオートゼロフェーズを完了する。 ロードデータフェーズ オートゼロのフェーズの終わりで、セレクトラインは「ロー」にセットされ、 データラインは「基準電圧」であった。次に、データラインは、基準電圧から、 データにおける変化がデータに参照されるローワ電圧(データ電圧)まで切り換 えられる。順番に、データ電圧(データ入力)はロードされてコンデンサ450 及び455を通してトランジスタP1 460のゲートに結合される。トランジ スタ460の電圧VSGは、トランジスタP1(460)に、固定オーバドライブ 電圧を提供し、OLED470電流を駆動する。即ち、データ電圧は、トランジ スタP1 460の上でオーバドライブ電圧に変換される。コンデンサ450上 で記憶される電圧が、トランジスタP1 460の閾値電圧の原因であるので、 オーバドライブ電圧全体が、今、トランジスタP1の閾値電圧と独立である。セ レクトライン420は、次に「ハイ」にセットされる。これはロードデータフェ ーズを完了する。 デセレクトローフェーズ中に連続的に、データを照明する データロードフェーズの完了で、トランジスタP1 460のゲートが、今、 容量結合を除いて絶縁され、OLEDを駆動するためのオーバドライブ電圧がコ ンデンサCS455に記憶される。次に、VSWPは最初のハイア(より高い、h igher)電圧(照明電圧)に戻される。続いてVSWPが上がり、今、照明のた めにOLEDを駆動する十分な電圧が存在する。即ち、セレクトライン420が 「ハイ」にセットされると、トランジスタP3(465)及びP4(445)の 両方は「オフ」に変えられ、データ電圧は以前のようにトランジスタ460のVSG の上に記憶されたままである。ソースからゲートへの電圧VSG(P1)は同様に全 体の照明フェーズを通して維持され、それはOLEDを通しての電流レベルが一 定のことを意味する。これで照明サイクルを完了する。 要するに、図3は、4つのPMOSトランジスタ及び3と1/2ラインを有す る1つの結合コンデンサを使用するピクセル構造を開示する。(オートゼロライ ン及びVDDH電圧供給は、両方とも共有されることができる)。図4は、3つ のPMOSトランジスタ及び2と1/2ラインを有する1つの結合コンデンサだ けを使用したピクセル構造を開示する。(電源を切り換えるVSWPは、隣接の ピクセルと共用する)これらの2つのピクセル構造の両方を照明、及びVSG(P1) 上のオートゼロとリクエストリング電流機構によって、ポリシリコンTFT及び OLEDの閾値変化を補うことができる前記の2つの(2)ピクセル構造も 、ポリシリコンNMOSの中で及びアモルファスNMOS設計の中で実行される ことができる。 図3及び図4の2つの(2)ピクセル構造が、OLED又はピクセルポリシリ コンTFTにおける不安定にもかかわらず、良好なグレースケール均一性及び長 い寿命を有する高品質のOLEDを設計するために実行されることができる。 図7は、本発明のアクティブマトリックスLEDピクセル構造700の回路図 を示す。好ましい実施形態で、アクティブマトリックスLEDピクセル構造は、 薄膜トランジスタ(TFT)(例えばポリシリコン又はアモルファスシリコンを 使用して製造されるトランジスタ)を使用して実行される。同様に、好ましい実 施形態で、アクティブマトリックスLEDピクセル構造は、有機発光ダイオード (OLED)を組み込んでいる。本ピクセル構造は薄膜トランジスタ及び有機発 光ダイオードを使用して実行されるが、本発明がトランジスタ及び発光ダイオー ドの他のタイプを使用して実行されることができることは理解されなければなら ない。 本ピクセル構造700は、大きな閾値電圧(Vt)不均一性存在下で、均一な 電流駆動を提供する。換言すると、OLEDsを通して均一な電流を維持するこ とが望ましく、もってディスプレイ強度における均一性が確保される。 図7について述べる。ピクセル構造700は、2つのPMOSトランジスタ7 10及び720、コンデンサ730、レジスタ750及びLED(OLED)7 40(光部材)を含む。セレクトライン770は、トランジスタ710のゲート に結合されている。データライン760は、トランジスタ710のソースに結合 されている。レジスタ750の1つのターミナルはトランジスタ720のソース に結合され、OLED740の1つの電極はトランジスタ720のドレインに結 合されている。最後に、トランジスタ710のドレイン、トランジスタ720の ゲート及びコンデンサ730の1つのターミナルは、全て結合されている。 より詳細には、ピクセル構造を含むローがアクティブローとして選択されると き、セレクトライン770の論理的「ハイ」レベルは、トランジスタM1710 をオンにし、コンデンサC730がデータライン760から電圧Vgまで充電さ れることができるようになっている。ローがセレクトライン770で「ロー」レ ベルによってデセレクトされた後、トランジスタM1をオフにし、コンデンサ7 30の電圧がフレーム時間のために記憶される。電圧がトランジスタM2 72 0のゲートに現れるので、それは、電流を、トランジスタ720を通し、ドレイ ンに位置するOLED740も通り抜けるようにセットする。 更に重要なことは、レジスタ750が本ピクセル構造で実行されることである 。レジスタは、トランジスタ720のソースに結合されて、マイナスのフィード バック部材として機能する。個々の駆動トランジスタが異常に低い閾値電圧を有 するならば、トランジスタは、OLEDにより多くの電流を通過する傾向がある が、追加の電流は、レジスタ750を横切る追加の電圧低下を引き起こし、もっ て電流を低減する。 相補的な影響が、異常に高い閾値電圧を有する駆動トランジスタに起こる。全 体の影響は、電流の不均一性を低減することである。レジスタが、TFTで達成 される閾値電圧均一性より非常に良好な抵抗均一性を有して一般に形成されるこ とができることが判った。1つの理由はTFT閾値電圧がアクティブなシリコン 材料のトラップ密度に非常に敏感であるのに、レジスタの中で使用されるドープ された層の抵抗はトラップ密度に対してそれほど敏感でないことである。測定値 は、抵抗の百分率変化がポリシリコンディスプレイウェーハを横切って非常に小 さいことを示し、抵抗が変わる範囲で、トランジスタ閾値と違って滑らかに変化 することが予想される。 OLED740を通り抜ける電流は、輝度を決定する。しかし、TFTを使用 してピクセルが実行されるとき、TFTの閾値電圧も、上述のようライフにわた って変化することができることが観察された。加えて、TFT閾値電圧の初期不 均一性があるであろう。閾値がOLEDを通して確定される電流に関して、電圧 は強い影響を有しないので、トランジスタ710に関するそのような不均一性が 問題でない点に留意する必要がある。これに対して、駆動トランジスタ720の 閾値電圧における変化は、OLEDを通して直接に電流に影響を及ぼす。 より詳細には、電流、本ピクセル構造の中のOLEDを通り抜けるIOLDEは、 以下のように表されることができる K’はトランジスタM2の固有相互コンダクタンスパラメータ、W及びLはその 幅及び長さ、Vtは閾値電圧、Vgはデータラインからの電圧であり、レジスタ R750は好ましい実施形態で1Mの値を有する。しかし、抵抗値は、駆動トラ ンジスタ特性に従って、100K〜10Mであることができる。本ピクセル構造 が、電流変動を、以下で述べる本発明のレジスタなしで可能な変動の1/3に低 減することができることが、観察された。 より詳細には、トランジスタ720のソースに結合されたレジスタを備え、閾 感度は、以下の通りである。 可能な限りゲート電圧Vgを増やすことは有益であるが、トランジスタ720 が飽和内にとどまらなければならないという限界を有する。レジスタ(IOLDER )を横切って電圧降下をもたらすことによって、閾値電圧変化への感度は、レジ スタなしで達成可能なもの以下に低減されることができる。最終的に、項(IOL DE R)は(Vg-Vt)よりも大きくなることができない。理由は、そのような結 果がトランジスタ720がオフにされたこと意味するからである。従って、トラ ンジスタ720のソースの中でレジスタを置くことによって達成されることがで きる感度における最大の低減は、2のファクタである。 しかし、ソースの中にレジスタを置くことは、トランジスタ720の幅Wが増 加することを認め、そのような増加は閾値電圧の標準偏差を低減する。固定最大 ゲート電圧、Wは増加されることができるので、σVt内の統計的低減からより 多くの利益を引き出す。このようにレジスタをトランジスタ720のソースに置 くことによって、電流変動における低減は以下の(1)、(2)の影響の組合せ 減(2×又は50%の低減である理論上の最大利益に制限)、及び、(2)閾値 変化σVt自体の低減(幾何学的及びキャパシタンス制約を除いて限界がない)で ある。 図5は、本発明の複数のアクティブマトリックスLEDピクセル構造200、 300、400、600又は700を有するディスプレイ520を使ったシステ ム500のブロック図を示す。システム500は、ディスプレイコントローラ5 10及びディスプレイ520を含む。 より詳細には、ディスプレイコントローラは、汎用コンピュータとして実施さ れることができ、当該コンピュータは中央処理装置CPU512、メモリ514 及び複数のI/O装置416(例えば、マウス、キーボード、記憶装置、例えば 磁気及び光学の駆動装置、モデムなどを有している。ディスプレイ520を起動 させるソフトウェア命令は、メモリ514にロードされることができ、CPU5 12によって実行されることができる。 ディスプレイ520は、ピクセルインタフェース522及び複数のピクセル( ピクセル構造200、300、400、600又は700)を含む。ピクセルイ ンタフェース522は、ピクセル200、300、400、600又は700を 駆動するために必要な回路を含む。例えば、ピクセルインタフェース522は図 1で示したマトリックスアドレッシングインタフェースでありえる。 このように、システム500はラップトップコンピュータとして実行されるこ とができる。代わりに、ディスプレイコントローラ510は、他の方法において 実行することができ、それは、例えばマイクロコントローラ又はアプリケーショ ン特定の集積回路(ASIC)、又はハードウェア及びソフトウェア命令の組合 せである。要するに、システム500は、本発明のディスプレイを組み込んだよ り大きいシステム内で実行されることができる。 本発明はPMOSトランジスタを使用して記載したが、本発明がNMOSトラ ンジスタを使用して実行されることができることは理解されなければならない。 なお、そこでは、関連した電圧は逆にされる。即ち、OLEDは、今、NMOS 駆動トランジスタのソースに結合される。OLEDを裏返すので、OLEDのカ ソードは、透明な材料で作られなければならない。 本発明の教示内容を組み込んだ種々の実施形態を示して本明細書で詳細に記載 したが、当業者は、容易にこれらの教示内容を組み込んだ多くの他の様々な実施 形態を工夫することができる。DETAILED DESCRIPTION OF THE INVENTION         Active matrix light emitting diode pixel structure and method   This application claims the benefit of US Provisional Application No. 60 / 044,174, filed April 23, 1997. Claim profit. The contents of which are incorporated herein.   This invention was made with U.S. Government support under contract number F33615-96-2-1944. . The United States Government has certain rights in the invention.   The present invention relates to an active matrix light emitting diode pixel structure. Change More specifically, the present invention relates to a driving transistor having a pixel structure. A pixel structure for reducing uniformity and threshold voltage variations; The present invention relates to a method for operating a light emitting diode pixel structure.                                Background of disclosure   Matrix displays are well known in the art and are illustrated in FIG. Pixels are illuminated using matrix addressing (illu minate). A typical display 100 is arranged in rows and columns (rows and columns). A plurality of pictures or display members (pixels) 160. The display is A ram data generator 110 and a row select generator 120 are incorporated. In operation, each row is activated sequentially through the row lines 130, and the corresponding column lines are activated. The corresponding pixel is activated using the button 140. Passive matrix de In the display, each row of pixels is illuminated one by one, but the active In a trix display, each row of pixels is initially contiguous with the data. Loaded.   The use of portable displays such as laptop computers Increasingly different display technologies (eg liquid crystal display (LCD) And light emitting diode (LED) displays). these An important difference between the two technologies is that LEDs are light emitting devices and non-light emitting devices (LCDs). Etc.) has an advantage in power efficiency. In LCD, fluorescent The backlight is on for the entire duration the display is in use and It consumes power even to "turn off" the cell. In contrast, LEDs (or OLED) displays illuminate only the activated pixels and provide an "off" pixel. Saves power by not lighting the lamp.   Displays employing OLED pixel structures can reduce power consumption. However, such a pixel structure can exhibit non-uniformity in intensity, It is due to the threshold voltages of the drive transistors and transistor non-uniformity due to manufacturing Due to theft. However, the brightness of the OLED is less than the current passing through the OLED. It turned out to be an example.   Therefore, the current non-uniformity and threshold in the “drive transistor” of the pixel structure There is a need in the art for pixel structures and associated methods for reducing voltage changes.                                Summary of the Invention   In one embodiment of the present invention, the current source is assembled into an LED (OLED) pixel structure. Current non-uniformity and threshold voltage in the pixel structure driving transistor. Reduce pressure changes. The current source is coupled to the data line, where a constant Current is programmed first and then collected.   In an alternative embodiment, an auto-zero voltage is determined and stored. Constant current achieved by applying a reference voltage first in the zero-phase Is done. Auto-zero voltage effectively accounts for the threshold voltage of the driving transistor . Next, a data voltage associated with the same reference voltage is now applied to illuminate the pixel. , Apply.   In another embodiment, the resistor is embedded within an LED (OLED) pixel structure And the dependence of the current through the OLED on the threshold voltage of the driving transistor. To reduce the sensitivity of existence.                             BRIEF DESCRIPTION OF THE FIGURES   The teachings of the present invention will take into consideration the following detailed description in connection with the accompanying drawings. Can be easily understood by:   FIG. 1 is a block diagram of the matrix addressing interface.   FIG. 2 is a circuit diagram of the active matrix LED pixel structure of the present invention. .   FIG. 3 shows an alternative embodiment of the active matrix LED pixel structure of the present invention. It is a circuit diagram of a state.   FIG. 4 shows another alternative implementation of the active matrix LED pixel structure of the present invention. It is a circuit diagram of an embodiment.   FIG. 5 has a multiple active matrix LED pixel structure of the present invention It is a block diagram of a system using a display.   FIG. 6 shows an alternative embodiment of the active matrix LED pixel structure of FIG. FIG.   FIG. 7 illustrates an alternative embodiment of the active matrix LED pixel structure of the present invention. It is a circuit diagram of a state.   For ease of understanding, where possible to show identical parts common to the figures Used the same reference numbers.                                Detailed description   FIG. 2 is a circuit diagram of an active matrix LED pixel structure 200 of the present invention. Is shown. In a preferred embodiment, the active matrix LED pixel structure For example, transistors manufactured using amorphous or polysilicon This is performed using a thin film transistor (TFT) that is a data source. Like, like In a preferred embodiment, the active matrix LED pixel structure is organic Incorporates a photodiode (OLED). This pixel structure is a thin film transistor And the invention is implemented using transistors and organic light emitting diodes. It is understood that it can be implemented using other types of light emitting diodes Must-have. For example, transistors manufactured using other materials If the threshold non-uniformity is exhibited as described above, the present invention may provide a constant power through the illumination member. Can be used to provide flow.   The invention is shown below as a single pixel or pixel structure, where the pixels are Can be used with other pixels (eg, in an array) to form a display. You have to understand that you can. In addition, the figure below shows a specific transistor shape. Shown, but without understanding that the source of the transistor corresponds to the voltage sign No.   Referring to FIG. The pixel structure 200 includes three PMOS transistors 2 40, 250, 260, NMOS transistor 270, capacitor 280 and L ED (OLED) 290 (light member) is included. Select line 210 is Stars 240, 250 and 270 are coupled to the gates. The data line is a tiger + V connected to the source of transistor 250DDThe line is the drain of transistor 270 In. One electrode of OLED 290 is connected to transistor 240 and And 260 are connected to the drain. The source of transistor 240 is Coupled to the gate of transistor 260 and one terminal of capacitor 280 You. Finally, the drain of transistor 250, the source of transistor 270, The source of transistor 260 and one terminal of capacitor 280 are all 1 Are joined together.   The present pixel structure 200 has a large threshold voltage (Vt) In the presence of heterogeneity, uniform Provides current drive. In other words, maintaining a uniform current across the OLED, It is desirable to ensure uniformity in display strength.   More specifically, the OLED pixel structure has two phases, the load data phase It is operated in the dose and continuous lighting phases. Load data phase   Pixel structure 200 is driven by driving the appropriate select line 210. Data can be loaded. That is, when the select line is set to "low" , The transistor P4 (240) is turned “ON” and the voltage on the anode side of the OLED 290 is Pressure is sent to the gate of transistor P2 (260). At the same time, the transistor P 1 (250) is also turned “on” and a constant current from data line 220 is It flows through both transistor P2 (260) and OLED 290. That is, Transis The power 260 is turned on to reduce the current driven by the current source 230. The current source 230 for driving the data line is programmed by external data. ing. The gate to the source voltage of transistor 260 (drive transistor) Next, the voltage required for driving the current is determined. At the same time, the transistors N1 (2 70) is turned off and the power supply + VDDIs disconnected from the OLED 290. one The constant current source 230 also self-adjusts the voltage from the source to the gate, The Eve value (voltage) is adapted to the transistor 260 and the polysilicon TFT 260 Compensate for threshold changes. The overdrive voltage indicates data. In order, data is memorized Capacitor CS280 is stored appropriately. Now load for data Alternatively, the write cycle is completed. Continuous lighting phase   When the select line is set to "high", P1 (250) and P4 (24) 0) are turned off, and transistor N1 (270) is turned on. Is made. Although the power supply voltage of the transistor 260 may slightly change, The voltage from the source to the gate of transistor 260 is the current level during the lighting cycle. Control files. V of transistor 270 across capacitor 280SGImmediately I can't change. Thus, the gate voltage of transistor 260 is Tracks the voltage and the voltage from the source to the gate determines the entire load and lighting phase. Maintained throughout. Polysilicon TFT leakage current and OLED gray scale The required voltage resolution for the pixel brightness is to hold the effective data of the frame time. Determine the size of storage capacitor needed for In a preferred embodiment, the Densers are on the order of 0.25 pf. That is, the current leakage of the transistor 260 The capacitor will be large enough to take into account. Now the lighting phase pixel motion Complete the work.   Each data / column line 220 has its own programmed constant current source 2 Note that it has 30. Following the data line during the lighting phase Is programmed to load the next row of all pixels, The previous row of pixels has been active for the entire frame time during the illumination phase. This Thus, the pixel structure of FIG. 2 has one NMOS transistor with 2.5 lines. Only three transistors and three PMOS transistors are required. (Share with adjacent pixels V that can beDDVoltage supply, select line, data line current source).   Alternatively, FIG. 6 shows that the pixel structure of FIG. 4 illustrates an embodiment implemented with a PMOS or NMOS process only. Both are economical. The NMOS transistor N1 is a PMOS P It is replaced by three transistors 610. But additional lines (control lines) 620 is coupled to the gate of transistor 610 and includes an additional PMOS transistor To a total of 3.5 lines (ie, additional PMOS gates Additional voltage supply to control).   In short, the pixel structure of FIGS.SGOn Constant current source by self-adjustment / tracking mechanism and through OLED 290 By supplying the threshold voltage change of both the polysilicon TFT and the OLED. Designed to make up. In fact, the pixel structure of FIGS. And achieving proper operation with high voltage supply during both the lighting phase Can be. These pixel structures are OLED or pixel polysilicon TFT Good grayscale uniformity and high life despite instability in both What is done to design a high quality OLED display with time Can be.   FIG. 3 shows an alternative embodiment of the present active matrix pixel structure. Teens In an alternative embodiment, the data line voltage is converted to a current in the pixel structure. Does not require a voltage-to-current converter as in the current source implementation described above in FIGS. .   Referring to FIG. The pixel structure 300 has four PMOS transistors ( 360, 365, 370, 375), two capacitors 350 and 355 and L ED (OLED) 380 is included. Select line 320 is connected to transistor 360 Connected to the gate. Data line 310 is the source of transistor 360 Combined, + VDDThe line connects the source of transistor 365 and the capacitor 355 It is connected to one terminal. Auto zero line 330 is transistor 3 The illumination line is coupled to the gate of transistor 375 Have been. One electrode of OLED 280 is connected to the drain of transistor 375 Are combined. The source of transistor 375 is connected to transistors 365 and 37 0 is connected to the drain. The drain of the transistor 360 is a capacitor 350 to one terminal. Finally, the transistor 365 Gate, the source of transistor 370, one terminal of capacitor 350 and One terminal of the capacitor 355 is all coupled.   More specifically, FIG. 3 illustrates a pixel structure 300 operated in three phases. Show. That is, 1) auto-zero phase, 2) load data phase, 3) lighting It's a daze. Auto zero   When the auto zero line 330 and the illumination line 340 are set to "low", Transistors P2 (375) and P3 (370) turn "on" and the transistor The voltage on the drain side of the transistor P1 (365) is sent to the gate and is temporarily Connected to the code. Data line 310 is set to "reference voltage" and select Line 320 is set low. Reference voltage can be set arbitrarily Yes, but it must be greater than the highest data voltage.   Next, the illumination line 340 is set to "high" and the transistor P2 375 Is turned off. The pixel circuit now has a transistor P1 365 (drive transistor). Transistor) and thus the data line reference voltage and the capacitor CC The voltage which is the difference between the threshold voltage of transistor P1 365 at 350 (auto (Zero voltage). This allows the gate voltage, or more precisely, the transistor Star 365 VSGIs set to the threshold voltage of the transistor 365. This is then Fixed overdriving on transistor P1 (365) regardless of threshold voltage change To provide the voltage. Finally, the auto-zero line 330 is set to "high", The gate of the transistor P1 365 is insulated. The purpose of Auto Zero is now Achieved. Load data phase   At the end of the autozero phase, the select line is set low and the The data line was at the "reference voltage". Now, the data line 310 is connected to the data voltage. Set. The data voltage is provided on the gate of transistor P1 (365). Sensor CCSent through 350. Next, set the select line to “high”. Is done. Thus, the V of transistor 365SGProvides a constant current level To provide a fixed overdrive voltage to transistor 365. This is The code data phase ends, and the pixel is now for illumination. Continuous lighting data phase during low phase of deselect Z   When the data voltage is stored on the gate of transistor P1 (365), the illumination IN 340 is set low and transistor P2 375 is turned "ON". It is. The current supplied by transistor P1 365 turns on OLED 380 Will be able to flow through. In short, transistor 365 is a constant Acts like a current source. This completes the lighting phase.   FIG. 4 shows another alternative embodiment of the present active matrix pixel structure. . In an alternative embodiment, the data line voltage is also the current within the pixel structure. Into a current source, as described above in FIGS. 2 and 6 for the current source. No piezo-current converter is required.   Referring to FIG. The pixel structure 400 has three PMOS transistors ( 445, 460, 465), two capacitors 450 and 455 and an LED (O LED) 470. Select line 420 is the gate of transistor 445 Is bound to. Data line 410 is coupled to the source of transistor 445 , VSWP lines are connected to the source of transistor 460 and one of the capacitors 455. To the terminal. The auto zero line 430 is connected to the gate of the transistor 465. Connected to the One electrode of OLED 470 includes a transistor 465 and 460 is coupled to the drain. The drain of transistor 445 is Connected to one terminal of the sensor 450. Finally, transistor 4 60 gates, the source of transistor 465 and one terminator of capacitor 450 The null and one terminal of the capacitor 455 are all coupled.   More specifically, FIG. 4 illustrates a pixel structure 400 operated in three phases. Show. That is, 1) auto-zero phase, 2) load data phase, 3) lighting It's a daze. Auto zero (VSWP) phase   VSWP (voltage to switch supply) is set to "lower (lower) voltage" Only the quantity “ΔV” is set. Here, the lower voltage is such that the OLED 470 has a small amount. Current (eg, on the order of nanoamps, depending on OLED characteristics) Is selected as The lower voltage is equal to the C coupled to the capacitor.C(450) and A floating node between the transistor P4 (445) and the floating node (f The transistor P1 (460) VG (P1)Coupled through the gate of Auto Zero line 430 is then set "low". Transistor P1 (460) (Drive transistor) is closed by closing transistor P3 (465). Temporarily connected as an iod. Select line 420 then goes low. The "reference voltage" is applied to the data line 410. Any reference voltage Can be set, but must be greater than the maximum data voltage No. The pixel circuit can now be set to the threshold of transistor P1 460 You. Finally, the autozero line 430 is then set to "high" and the transistor The gate of P1 460 is insulated. The effect of the auto-zero phase is on the storage device Capacitor CCIs to store the voltage (auto zero voltage) at 450, which is Difference between reference voltage on data line and transistor threshold voltage of P1 460 Represents This completes the auto-zero phase. Load data phase   At the end of the auto-zero phase, the select line is set low and Data line was "reference voltage". Next, the data line is Switch to lower voltage (data voltage) where changes in data are referred to by data available. In turn, the data voltage (data input) is loaded and the capacitor 450 And 455 to the gate of transistor P1 460. Transi The voltage V of the star 460SGIndicates that the transistor P1 (460) has a fixed overdrive Provide voltage and drive OLED 470 current. That is, the data voltage is It is converted to an overdrive voltage on the star P1 460. Above capacitor 450 Is the cause of the threshold voltage of transistor P1 460, The overall overdrive voltage is now independent of the threshold voltage of transistor P1. C The rect line 420 is then set to "high". This is the load data Complete Illuminate data continuously during the deselect row phase   At the completion of the data load phase, the gate of transistor P1 460 is now Isolated except for capacitive coupling, the overdrive voltage to drive the OLED is Capacitor CS455. Next, VSWP is the first higher (higher, h igher) voltage (lighting voltage). Then the VSWP went up and now the lighting There is enough voltage to drive the OLED to operate. That is, the select line 420 When set high, the transistors P3 (465) and P4 (445) Both are turned "off" and the data voltage is changed as before by the VSG Remains stored on the Source-to-gate voltage VSG (P1)Is all Maintained throughout the body lighting phase, which means that the current level through the OLED is Means certain. This completes the lighting cycle.   In short, FIG. 3 has four PMOS transistors and three and half lines A pixel structure using a single coupling capacitor is disclosed. (Auto Zero Rye And the VDDH voltage supply can both be shared). Figure 4 shows three PMOS transistor and one coupling capacitor with 2 and 1/2 lines A pixel structure using a pixel structure is disclosed. (VSWP for switching the power supply Illuminate both of these two pixel structures (shared with pixels) and VSG (P1) With the above auto-zero and request ring current mechanism, polysilicon TFT and The above two (2) pixel structures that can compensate for the threshold change of the OLED also Implemented in polysilicon NMOS and in amorphous NMOS designs be able to.   The two (2) pixel structures of FIG. 3 and FIG. Good grayscale uniformity and length despite instability in the con TFT It can be implemented to design high quality OLEDs with long lifetime.   FIG. 7 is a circuit diagram of an active matrix LED pixel structure 700 of the present invention. Is shown. In a preferred embodiment, the active matrix LED pixel structure is Thin film transistor (TFT) (for example, polysilicon or amorphous silicon (Transistors manufactured using the same). Similarly, favorable fruit In an embodiment, the active matrix LED pixel structure comprises an organic light emitting diode (OLED). This pixel structure is based on thin film transistors and organic light emitting devices. It is implemented using photodiodes, but the invention is not limited to transistors and light emitting diodes. It must be understood that it can be implemented using other types of Absent.   The pixel structure 700 has a large threshold voltage (Vt) In the presence of heterogeneity, uniform Provides current drive. In other words, maintaining a uniform current through OLEDs It is desirable to ensure uniformity in display intensity.   Referring to FIG. The pixel structure 700 includes two PMOS transistors 7 10 and 720, capacitor 730, resistor 750 and LED (OLED) 7 40 (optical member). Select line 770 is the gate of transistor 710 Is joined to. Data line 760 is coupled to the source of transistor 710 Have been. One terminal of register 750 is the source of transistor 720 And one electrode of OLED 740 is connected to the drain of transistor 720. Have been combined. Finally, the drain of the transistor 710 and the transistor 720 The gate and one terminal of the capacitor 730 are all coupled.   More specifically, when the row containing the pixel structure is selected as the active row At this time, the logical “high” level of the select line 770 is Is turned on, and capacitor C730 is charged from data line 760 to voltage Vg. That can be done. Low is “Low” on select line 770 After being deselected by the bell, the transistor M1 is turned off and the capacitor 7 Thirty voltages are stored for the frame time. When the voltage is the transistor M2 72 Since it appears at the gate of 0, it draws current through transistor 720 and drains The OLED 740 is set so as to pass through.   More importantly, register 750 is implemented in the present pixel structure. . A resistor is coupled to the source of transistor 720 to provide a negative feed. Functions as a back member. Each drive transistor has an abnormally low threshold voltage If so, the transistor tends to pass more current to the OLED However, the additional current causes an additional brownout across resistor 750, To reduce the current.   Complementary effects occur on drive transistors with abnormally high threshold voltages. all The effect of the body is to reduce the non-uniformity of the current. Register achieved with TFT That is generally formed with much better resistance uniformity than the threshold voltage uniformity It turned out that I could do it. One reason is that the TFT threshold voltage is active silicon Dope used in resistors, even though it is very sensitive to the trap density of the material The resistance of the deposited layer is less sensitive to trap density. measured value Indicates that the percentage change in resistance is very small across the polysilicon display wafer Changes within the range where the resistance changes, unlike the transistor threshold It is expected to be.   The current passing through OLED 740 determines the brightness. But use TFT The threshold voltage of the TFT is also extended over the life as described above when the pixel is executed. It has been observed that the In addition, the initial threshold voltage of the TFT There will be uniformity. For a current whose threshold is determined through an OLED, the voltage Does not have a strong effect, such non-uniformity for transistor 710 It should be noted that this is not a problem. On the other hand, the driving transistor 720 Changes in the threshold voltage directly affect the current through the OLED.   More specifically, the current, I through the OLED in the pixel structureOLDEIs Can be represented as K 'is the intrinsic transconductance parameter of transistor M2, and W and L are Width and length, VtIs the threshold voltage, Vg is the voltage from the data line, R750 has a value of 1M in a preferred embodiment. However, the resistance value According to transistor characteristics, it can be 100K to 10M. This pixel structure Reduces the current variation to one third of the possible variation without the inventive register described below. It was observed that it could be reduced.   More particularly, a threshold value comprising a resistor coupled to the source of transistor 720 is provided. The sensitivities are as follows.   Although it is beneficial to increase the gate voltage Vg as much as possible, the transistor 720 Has the limitation that it must stay within saturation. Register (IOLDER By causing a voltage drop across the threshold voltage, the sensitivity to threshold voltage changes It can be reduced below what can be achieved without star. Finally, the term (IOL DE R) is (Vg-Vt) Cannot be larger than. The reason is that This is because the result means that the transistor 720 is turned off. Therefore, the tiger Can be achieved by placing a register in the source of transistor 720 The greatest reduction in sensitivity that can be achieved is a factor of two.   However, placing a register in the source increases the width W of transistor 720. And such an increase reduces the standard deviation of the threshold voltage. Fixed maximum Since the gate voltage, W, can be increased, σVtFrom statistical reduction within Bring out many benefits. Thus, placing the resistor at the source of transistor 720 Thus, the reduction in the current fluctuation is a combination of the following effects (1) and (2). Reduction (limited to a theoretical maximum benefit of 2 × or 50% reduction), and (2) threshold Change σVtWith its own reduction (no limits except geometric and capacitance constraints) is there.   FIG. 5 shows a plurality of active matrix LED pixel structures 200 of the present invention. System using display 520 having 300, 400, 600 or 700 FIG. 2 shows a block diagram of a program 500. The system 500 includes a display controller 5 10 and a display 520.   More specifically, the display controller is implemented as a general-purpose computer The computer may include a central processing unit CPU 512, a memory 514. And a plurality of I / O devices 416 (eg, a mouse, a keyboard, a storage device, for example, It has a magnetic and optical drive device, a modem, and the like. Activate display 520 The software instructions causing the CPU 5 to load 12 can be performed.   The display 520 includes a pixel interface 522 and a plurality of pixels ( Pixel structure 200, 300, 400, 600 or 700). Pixeli The interface 522 includes the pixels 200, 300, 400, 600, or 700. Includes circuits necessary for driving. For example, the pixel interface 522 1 may be the matrix addressing interface.   Thus, system 500 can be implemented as a laptop computer. Can be. Instead, the display controller 510 may be otherwise Can be implemented, for example, by a microcontroller or an application. Specific integrated circuit (ASIC) or combination of hardware and software instructions It is. In short, the system 500 incorporates the display of the present invention. It can be implemented in larger systems.   Although the invention has been described using PMOS transistors, the invention is not limited to NMOS transistors. It should be understood that it can be implemented using transistors. Note that the associated voltages are reversed there. That is, OLED is now NMOS It is coupled to the source of the driving transistor. Since the OLED is turned over, the OLED The sword must be made of a transparent material.   Various embodiments incorporating the teachings of the present invention are shown and described in detail herein. However, those skilled in the art will readily recognize many other various implementations that incorporate these teachings. The form can be devised.

───────────────────────────────────────────────────── フロントページの続き (31)優先権主張番号 09/064,697 (32)優先日 平成10年4月22日(1998.4.22) (33)優先権主張国 米国(US) (81)指定国 EP(AT,BE,CH,CY, DE,DK,ES,FI,FR,GB,GR,IE,I T,LU,MC,NL,PT,SE),JP,KR (72)発明者 スー,ジェイムズ,ヤ−コング アメリカ合衆国 ニュー ジャージー州 エディソン ハナ ロード 7107 (72)発明者 スー,フ−ラング アメリカ合衆国 ニュー ジャージー州 クランベリー キングレット ドライヴ サウス 14 (72)発明者 イプリ,アルフレッド,チャールズ アメリカ合衆国 ニュー ジャージー州 プリンストン コツウォルド レーン 7 (72)発明者 ステュワート,ロジャー,グリーン アメリカ合衆国 ニュー ジャージー州 ネシャニック ステーション スキー ド ライヴ 3────────────────────────────────────────────────── ─── Continuation of front page    (31) Priority claim number 09 / 064,697 (32) Priority date April 22, 1998 (April 22, 1998) (33) Priority country United States (US) (81) Designated country EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE), JP, KR (72) Inventors Sue, James, Yakong             United States New Jersey             Edison Hana Road 7107 (72) Inventor Sue, Furang             United States New Jersey             Cranberry Kinglet Drive             South 14 (72) Inventors Ipri, Alfred, Charles             United States New Jersey             Princeton Cotswold Lane 7 (72) Inventor Stewart, Roger, Green             United States New Jersey             Neshanic Station Skied             Live 3

Claims (1)

【特許請求の範囲】 1.複数のピクセルを含むディスプレイ(520)であって、各ピクセル(20 0)が、 ゲート、ソース及びドレインを有する第1のトランジスタ(250)であって 、該ゲートがセレクトライン(210)結合され、該ソースがデータライン(2 20)に結合された第1のトランジスタ(250)と、 ゲートソース及びドレインを有する第2のトランジスタ(270)であって、 該第2のトランジスタのゲートが前記セレクトラインに結合され、該第2のトラ ンジスタのドレインがVDDライン(295)に結合され、該第2のトランジスタ のソースが前記第1のトランジスタの前記ドレインに結合された第2のトランジ スタ(270)と、 ゲート、ソース及びドレインを有する第3のトランジスタ(240)であって 、前記第3のトランジスタのゲートが前記セレクトラインに結合された第3のト ランジスタ(240)と、 第1のターミナル及び第2のターミナルを有するコンデンサ(280)であっ て、前記第3のトランジスタの前記ソースが前記コンデンサの前記第1のターミ ナルに結合され、前記コンデンサの前記第2のターミナルが前記第1のトランジ スタの前記ドレインに結合されたコンデンサ(280)と、 ゲート、ソース及びドレインを有する第4のトランジスタ(260)であって 、該第4のトランジスタのソースが前記第1のトランジスタの前記ドレインに結 合され、該第4のトランジスタのゲートが、前記第3のトランジスタの前記ソー スに結合された第4のトランジスタ(260)と、 2つのターミナルを有する照明(light)部材(290)であって、前記第4 のトランジスタの前記ドレイン及び前記第3のトランジスタの前記ドレインが、 該照明部材の前記ターミナルのうちの1つに結合している照明部材(290)と 、 を含むディスプレイ(520)。 2.前記データラインに結合するための電流源(230)を更に含む請求項1記 載のディスプレイ。 3.複数のピクセルを含むディスプレイ(520)であって、各ピクセル(60 0)が、 ゲート、ソース及びドレインを有する第1のトランジスタ(250)であって 、該ゲートがセレクトライン(210)に結合され、該ソースがデータライン( 220)に結合された第1のトランジスタ(250)と、 ゲートソース及びドレインを有する第2のトランジスタ(610)であって、 該第2のトランジスタのゲートがコントロールライン(620)に結合され、該 第2のトランジスタのソースがVDDライン(295)に結合され、該第2のトラ ンジスタのドレインが前記第1のトランジスタの前記ドレインに結合された前第 2のトランジスタ(610)と、 ゲート、ソース及びドレインを有する第3のトランジスタ(240)であって 、該第3のトランジスタのゲートが前記セレクトラインに結合された第3のトラ ンジスタ(240)と、 第1のターミナル及び第2のターミナルを有するコンデンサ(280)であっ て、該第3のトランジスタのソースが前記コンデンサの前記第1のターミナルに 結合され、前記コンデンサの前記第2のターミナルが前記第1のトランジスタの 前記ドレインに結合された、コンデンサ(280)と、 ゲート、ソース及びドレインを有する第4のトランジスタ(260)であって 、該第4のトランジスタのソースが前記第1のトランジスタの前記ドレインに結 合され、該第4のトランジスタのゲートが前記第3のトランジスタの前記ソース に結合された第4のトランジスタ(260)と、 2つのターミナルを有する照明部材(290)であって、前記第4のトランジ スタのドレイン及び前記第3のトランジスタのドレインが前記照明部材の前記タ ーミナルのうちの1つに結合された照明部材(290)と、 を含むディスプレイ(520)。 4.各ピクセルが照明部材へのエネルギの適用を制御する回路を含み、該回路が 駆動トランジスタを含む複数のピクセルを有するディスプレイを照明する方法で あって、 (a)データラインに電流を適用することによって前記ピクセルにデータをロー ドするステップと、 (b)前記データを駆動トランジスタに結合されたコンデンサに記憶するステッ プと、 (c)前記記憶データに従って前記照明部材を照明するステップと、 を含む方法。 5.前記電流が電流源によって提供される請求項4記載の方法。 6.複数のピクセルを含むディスプレイ(520)であって、各ピクセル(30 0)が、 ゲート、ソース及びドレインを有する第1のトランジスタ(360)であって 該ゲートがセレクトライン(320)に結合され、該ソースがデータライン(3 10)に結合された第1のトランジスタ(360)と、 第1のターミナル及び第2のターミナルを有する第1のコンデンサ(350) であって、該第1のトランジスタのドレインが前記第1のコンデンサの前記第1 のターミナルに結合された第1のコンデンサ(350)と、 ゲート、ソース及びドレインを有する第2のトランジスタ(365)であって 、該第2のトランジスタのソースがVDDライン(390)に結合され、該第2の トランジスタのゲートが前記第1のコンデンサの前記第2のターミナルに結合さ れた第2のトランジスタ(365)と、 第1のターミナル及び第2のターミナルを有する第2のコンデンサ(355) であって、前記第2のトランジスタのゲートが該第2のコンデンサの該第1のタ ーミナルに結合され、前記第2のトランジスタのソースが該第2のコンデンサの 該第2のターミナルに結合された第2のコンデンサ(355)と、 ゲート、ソース及びドレインを有する第3のトランジスタ(370)であって 、該第3のトランジスタのゲートがオートゼロライン(330)に結合され、該 第3のトランジスタのソースが前記第2のトランジスタの前記ゲートに結合され 、該第3のトランジスタのドレインが、前記第2のトランジスタのドレインに結 合された第3のトランジスタ(370)と、 ゲート、ソース及びドレインを有する第4のトランジスタ(375)であって 、該第4のトランジスタのゲートが照明ライン(340)に結合され、該第4の トランジスタのソースが前記第3のトランジスタのドレインに結合された第4の トランジスタ(375)と、 2つのターミナルを有する照明部材(380)であって、前記第4のトランジ スタの前記ドレインが該照明部材のターミナルのうちの1つに結合された照明部 材(380)と、 を含むディスプレイ。 7.複数のピクセルを含むディスプレイ(520)であって、各ピクセル(40 0)が、 ゲート、ソース及びドレインを有する第1のトランジスタ(445)であって 、前記ゲートがセレクトライン(420)に結合され、前記ソースがデータライ ン(410)に結合された第1のトランジスタ(445)と、 第1のターミナル及び第2のターミナルを有する第1のコンデンサ(450) であって、該第1のトランジスタのドレインが該第1のコンデンサの第1のター ミナルに結合された第1のコンデンサ(450)と、 ゲート、ソース及びドレインを有する第2のトランジスタ(460)であって 、該第2のトランジスタのソースがVSWPライン(440)に結合され、該第 2のトランジスタのゲートが前記第1のコンデンサの前記第2のターミナルに結 合された第2のトランジスタ(460)と、 第1のターミナル及び第2のターミナルを有する第2のコンデンサ(455) であって、該第2のトランジスタのゲートが該第2のコンデンサの第1のターミ ナルに結合され、該第2のトランジスタのソースが該第2のコンデンサの第2の ターミナルに結合された第2のコンデンサ(455)と、 ゲート、ソース及びドレインを有する第3のトランジスタ(465)であって 、該第3のトランジスタのゲートがオートゼロライン(430)に結合され、該 第3のトランジスタのソースが前記第2のトランジスタのゲートに結合され、該 第3のトランジスタのドレインが前記第2のトランジスタのドレインに結合され た第3のトランジスタ(465)と、 2つのターミナルを有する照明部材(470)であって、前記第2のトランジ スタのドレインが該照明部材のターミナルのうちの1つに結合された照明部材( 470)と、 を含むディスプレイ。 8.複数のピクセルを有するディスプレイを照明し、各ピクセルが照明部材への エネルギの適用を制御するための回路を含み、前記回路が駆動トランジスタを含 む複数のピクセルを有するディスプレイを照明する方法であって、 (a)データラインに基準電圧を適用することによって、駆動トランジスタのた めのオートゼロの電圧を決定するステップと、 (b)前記基準電圧を前記データラインのデータ電圧に切り換えることによって 、ピクセルの上のデータをローディングするステップと、 (c)駆動トランジスタに結合されたコンデンサに前記データを記憶するステッ プと、 (d)前記記憶データに従って前記照明部材を照明するステップと、 を含む方法。 9.2つのターミナルを有する照明部材を駆動する回路(300)であって、 ゲート、ソース及びドレインを有する第1のトランジスタ(360)であって 、該ゲートはセレクトライン(320)を接続するためのものであり、該ソース はデータライン(310)を接続するためのものである第1のトランジスタ(3 60)と、 第1のターミナル及び第2のターミナルを有する第1のコンデンサ(350) であって、前記第1のトランジスタのドレインが該第1のコンデンサの第1のタ ーミナルに結合された第1のコンデンサ(350)と、 ゲートソース及びドレインを有する第2のトランジスタ(365)であって、 該第2のトランジスタのソースがVDDライン(390)に結合され、該第2のト ランジスタのゲートが前記第1のコンデンサの前記第2のターミナルに結合され た第2のトランジスタ(365)と、 第1のターミナル及び第2のターミナルを有する第2のコンデンサ(355) であって、前記第2のトランジスタのゲートが該第2のコンデンサの第1のター ミナルに結合され、前記第2のトランジスタのソースが該第2のコンデンサの第 2のターミナルに結合された第2のコンデンサ(355)と、 ゲート、ソース及びドレインを有する第3のトランジスタ(370)であって 、該第3のトランジスタの前記ゲートがオートゼロライン(330)結合される ためのものであり、該第3のトランジスタのソースは前記第2のトランジスタの ゲートに結合され、該第3のトランジスタのドレインは前記第2のトランジスタ の前記ドレインに結合されている第3のトランジスタ(370)と、 ゲート、ソース及びドレインを有する第4のトランジスタ(375)であって 、該第4のトランジスタのゲートが照明ライン(340)に結合されるものであ り、該第4のトランジスタのソースが前記第3のトランジスタのドレインに結合 されており、該第4のトランジスタのドレインが照明部材に結合されるためのも のである第4のトランジスタ(375)と、を含む回路(300)。 10.ディスプレイコントローラ(510)と、 前記ディスプレイコントローラに結合されたディスプレイ(520)と、 を含むシステム(500)であって、 前記ディスプレイが複数のピクセルを含み、該ピクセル(300)が、 ゲート、ソース及びドレインを有する第1のトランジスタ(360)であって 該ゲートがセレクトライン(320)に結合され、該ソースがデータライン(3 10)に結合された第1のトランジスタ(360)と、 第1のターミナル及び第2のターミナルを有する第1のコンデンサ(350) であって、前記第1のトランジスタのドレインが前記第1のコンデンサの第1の ターミナルに結合された第1のコンデンサ(350)と、 ゲート、ソース及びドレインを有する第2のトランジスタ(365)であって 、該第2のトランジスタのソースがVDDライン(390)に結合され、該第2の トランジスタのゲートが前記第1のコンデンサの前記第2のターミナルに結合さ れた第2のトランジスタ(365)と、 第1のターミナル及び第2のターミナルを有する第2のコンデンサ(355) であって、前記第2のトランジスタのゲートが該第2のコンデンサの第1のター ミナルに結合され、該第2のトランジスタのソースが該第2のコンデンサの第2 のターミナルに結合された第2のコンデンサ(355)と、 ゲート、ソース及びドレインを有する第3のトランジスタ(370)であって 、該第3のトランジスタのゲートがオートゼロライン(330)を結合し、該第 3のトランジスタのソースが前記第2のトランジスタのゲートに結合し、該第3 のトランジスタのドレインが前記第2のトランジスタのドレインに結合されてい る第3のトランジスタ(370)と、 ゲート、ソース及びドレインを有する第4のトランジスタ(375)であって 、該第4のトランジスタのゲートが照明ライン(340)に結合され、該第4の トランジスタのソースが前記第3のトランジスタのドレインに結合された第4の トランジスタ(375)と、 2つのターミナルを有する照明部材(380)であって、前記第4のトランジ スタのドレインが、前記照明部材の前記ターミナルのうちの1つに結合された照 明部材(380)と、 を含むシステム(500)。 11.複数のピクセルを含むディスプレイ(520)であって、各ピクセル(7 00)が、 ゲート、ソース及びドレインを有する第1のトランジスタ(710)であって 、該ゲートがセレクトライン(770)に結合され、該ソースがデータライン( 760)に結合された第1のトランジスタ(710)と、 ゲート、ソース及びドレインを有する第2のトランジスタ(720)であって 、前記第1のトランジスタのドレインが該第2のトランジスタのゲートに結合さ れた第2のトランジスタ(720)と、 2つのターミナルを有するレジスタ(750)であって、前記第2のトランジ スタのソースが該レジスタのターミナルのうちの1つに結合されたレジスタ(7 50)と、 2つのターミナルを有する照明部材(740)であって、前記第2のトランジ スタのドレインが該照明部材のターミナルのうちの1つに結合された照明部材( 740)と、を含むディスプレイ(520)。[Claims] 1. A display (520) comprising a plurality of pixels, wherein each pixel (200) is a first transistor (250) having a gate, a source and a drain, the gate being coupled to a select line (210); A first transistor (250) having a source coupled to the data line (220); and a second transistor (270) having a gate source and a drain, wherein the gate of the second transistor is the select line. And a second transistor (270) having a drain coupled to the VDD line (295) and a source coupled to the drain of the first transistor. A third transistor (240) having a gate, a source, and a drain, wherein the third transistor (240) comprises: A third transistor (240) having a gate coupled to the select line; and a capacitor (280) having a first terminal and a second terminal, wherein the source of the third transistor is the capacitor. A capacitor (280) coupled to the first terminal of the first transistor and the second terminal of the capacitor coupled to the drain of the first transistor; and a fourth transistor (260) having a gate, a source and a drain. ) Wherein a source of the fourth transistor is coupled to the drain of the first transistor and a gate of the fourth transistor is coupled to the source of the third transistor (260) and a light member (290) having two terminals, A lighting member (290), wherein the drain of the fourth transistor and the drain of the third transistor are coupled to one of the terminals of the lighting member. 2. The display of claim 1, further comprising a current source (230) for coupling to the data line. 3. A display (520) comprising a plurality of pixels, each pixel (600) being a first transistor (250) having a gate, a source and a drain, the gate being coupled to a select line (210). A first transistor (250) having a source coupled to the data line (220); and a second transistor (610) having a gate source and a drain, wherein the gate of the second transistor has a control line ( 620), the source of the second transistor being coupled to the VDD line (295), and the drain of the second transistor being coupled to the drain of the first transistor ( 610) and a third transistor (240) having a gate, a source, and a drain. A third transistor (240) having a gate coupled to the select line, and a capacitor (280) having a first terminal and a second terminal, the source of the third transistor being the capacitor. And a fourth transistor having a gate, a source and a drain, wherein the second terminal of the capacitor is coupled to the drain of the first transistor. 260) wherein a source of the fourth transistor is coupled to the drain of the first transistor and a gate of the fourth transistor is coupled to the source of the third transistor (260) and a lighting member (290) having two terminals, Display drains and the third transistor of the fourth transistor comprises an illumination member (290) coupled to one of said terminals of said illumination member (520). 4. A method of illuminating a display having a plurality of pixels including driving transistors, wherein each pixel includes a circuit for controlling application of energy to a lighting member, the method comprising: (a) applying a current to a data line; Loading the pixel with data; (b) storing the data in a capacitor coupled to a driving transistor; and (c) illuminating the lighting member according to the stored data. 5. 5. The method of claim 4, wherein said current is provided by a current source. 6. A display (520) comprising a plurality of pixels, each pixel (300) being a first transistor (360) having a gate, a source and a drain, the gate being coupled to a select line (320); A first transistor (360) having a source coupled to the data line (310); a first capacitor (350) having a first terminal and a second terminal; A first capacitor (350) having a drain coupled to the first terminal of the first capacitor; and a second transistor (365) having a gate, a source, and a drain, wherein A source is coupled to the V DD line (390) and the gate of the second transistor is connected to the second capacitor of the first capacitor. A second transistor (365) coupled to the first transistor and a second capacitor (355) having a first terminal and a second terminal, wherein the gate of the second transistor is connected to the second capacitor (355). A second capacitor coupled to the first terminal, the source of the second transistor coupled to the second terminal of the second capacitor; and a third capacitor having a gate, a source, and a drain. The transistor (370), wherein the gate of the third transistor is coupled to an auto-zero line (330), the source of the third transistor is coupled to the gate of the second transistor, A third transistor (370) having a drain of the transistor coupled to a drain of the second transistor; A fourth transistor (375) having a source and a drain, the gate of the fourth transistor being coupled to the illumination line (340), and the source of the fourth transistor being coupled to the drain of the third transistor. A lighting member (380) having a fourth transistor (375) and two terminals, wherein the drain of the fourth transistor is coupled to one of the terminals of the lighting member. (380) A display comprising:. 7. A display (520) comprising a plurality of pixels, wherein each pixel (400) is a first transistor (445) having a gate, a source and a drain, said gate being coupled to a select line (420). , A first transistor (445) having a source coupled to a data line (410), and a first capacitor (450) having a first terminal and a second terminal, wherein the first transistor (445) has a first terminal and a second terminal. A first capacitor (450) having a drain coupled to a first terminal of the first capacitor; and a second transistor (460) having a gate, a source, and a drain, the source of the second transistor. Is coupled to the VSWP line (440), and the gate of the second transistor is connected to the second capacitor of the first capacitor. A second transistor (460) coupled to a terminal; and a second capacitor (455) having a first terminal and a second terminal, the gate of the second transistor being connected to the second capacitor (455). A second capacitor coupled to a first terminal, the source of the second transistor coupled to a second terminal of the second capacitor; and a third transistor having a gate, a source, and a drain. (465) wherein the gate of the third transistor is coupled to an auto-zero line (430), the source of the third transistor is coupled to the gate of the second transistor, and the drain of the third transistor Has a third transistor (465) coupled to the drain of the second transistor, and two terminals. An illumination member (470), a display including an, an illumination member (470) coupled to one of the second drain of the transistor of the illumination member terminal. 8. A method for illuminating a display having a plurality of pixels, wherein each pixel includes circuitry for controlling application of energy to a lighting member, said circuitry illuminating the display having a plurality of pixels including a driving transistor. (A) determining an auto-zero voltage for the driving transistor by applying a reference voltage to a data line; and (b) switching the reference voltage to the data voltage of the data line, thereby providing Loading the data; (c) storing the data in a capacitor coupled to a driving transistor; and (d) illuminating the lighting member according to the stored data. 9. A circuit (300) for driving a lighting member having two terminals, a first transistor (360) having a gate, a source and a drain, the gate for connecting a select line (320). Wherein the source is a first transistor (360) for connecting the data line (310), and a first capacitor (350) having a first terminal and a second terminal. A first capacitor (350) having a drain of the first transistor coupled to a first terminal of the first capacitor; and a second transistor (365) having a gate source and a drain. , the source of the transistor of the second is coupled to V DD line (390), the gate of the second transistor is a first con A second transistor (365) coupled to said second terminal of the sensor; and a second capacitor (355) having a first terminal and a second terminal, wherein the gate of said second transistor is A second capacitor coupled to a first terminal of the second capacitor, the source of the second transistor coupled to a second terminal of the second capacitor; a gate, a source, and a drain. A third transistor (370) having the gate of the third transistor coupled to an auto-zero line (330), the source of which is the source of the second transistor. A third transistor coupled to the gate and the drain of the third transistor coupled to the drain of the second transistor; A fourth transistor (375) having a transistor (370), a gate, a source, and a drain, the gate of the fourth transistor being coupled to an illumination line (340); A third transistor coupled to a drain of the third transistor, and a drain of the fourth transistor coupled to a lighting member. . 10. A system (500) comprising: a display controller (510); and a display (520) coupled to the display controller, wherein the display includes a plurality of pixels, the pixels (300) comprising: a gate, a source, and A first transistor (360) having a drain, the gate coupled to the select line (320), and the source coupled to the data line (310); A first capacitor (350) having a terminal and a second terminal, a first capacitor (350) having a drain of the first transistor coupled to a first terminal of the first capacitor; A second transistor (365) having a gate, a source, and a drain, The source of the second transistor is coupled to V DD line (390), a second transistor having a gate of the second transistor is coupled to said second terminal of said first capacitor and (365), the A second capacitor (355) having a first terminal and a second terminal, wherein the gate of the second transistor is coupled to the first terminal of the second capacitor, and the source of the second transistor is Is a second capacitor (355) coupled to a second terminal of the second capacitor; and a third transistor (370) having a gate, a source and a drain, wherein the gate of the third transistor is An auto-zero line (330), the source of the third transistor being coupled to the gate of the second transistor, and the third transistor A third transistor (370) having a drain of the transistor coupled to the drain of the second transistor; and a fourth transistor (375) having a gate, a source, and a drain, the gate of the fourth transistor. Is coupled to an illumination line (340), a source of the fourth transistor is coupled to a drain of the third transistor (375), and an illumination member (380) having two terminals. A lighting member coupled to one of the terminals of the lighting member, wherein the drain of the fourth transistor is coupled to one of the terminals of the lighting member. 11. A display (520) comprising a plurality of pixels, each pixel (700) being a first transistor (710) having a gate, a source and a drain, the gate being coupled to a select line (770). A first transistor (710) having a source coupled to the data line (760); and a second transistor (720) having a gate, a source, and a drain, wherein the drain of the first transistor is the second transistor (720). A second transistor (720) coupled to the gates of two transistors; and a register (750) having two terminals, the source of the second transistor coupled to one of the terminals of the register. And a lighting member (740) having two terminals. A lighting member (740) having a transistor drain coupled to one of the lighting member terminals.
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