JP2001042822A - Active matrix type display device - Google Patents

Active matrix type display device

Info

Publication number
JP2001042822A
JP2001042822A JP11220291A JP22029199A JP2001042822A JP 2001042822 A JP2001042822 A JP 2001042822A JP 11220291 A JP11220291 A JP 11220291A JP 22029199 A JP22029199 A JP 22029199A JP 2001042822 A JP2001042822 A JP 2001042822A
Authority
JP
Japan
Prior art keywords
light
light emitting
display device
light emission
subfield
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11220291A
Other languages
Japanese (ja)
Inventor
Shinichi Ishizuka
真一 石塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Electronic Corp filed Critical Pioneer Electronic Corp
Priority to JP11220291A priority Critical patent/JP2001042822A/en
Publication of JP2001042822A publication Critical patent/JP2001042822A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809Several active elements per pixel in active matrix panels
    • G09G2300/0842Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809Several active elements per pixel in active matrix panels
    • G09G2300/0842Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243Details of the generation of driving signals
    • G09G2310/0251Precharge or discharge of pixel before applying new pixel voltage
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007Display of intermediate tones
    • G09G3/2018Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022Display of intermediate tones by time modulation using two or more time intervals using sub-frames

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain a display device, in which no dispersion of luminance gradation exists over the entire surface of a display panel, by providing a means to stop the light emitting of light-emitting elements after a prescribed light emitting period has elapsed for every subfield. SOLUTION: A controller 26 controls a light-emitting control driver 31 to supply control signals to make a switching circuit conductive and to make organic electroluminescence(EL) elements of the pixels having the data indicating light-emitting emit light. Moreover the controller 26 supplies a signal, which instructs stopping of light-emitting of the organic EL elements of the driver 31 when a beforehand determined light emitting interval time elapses for a first subfield. The driver 31 supplies control signals to stop light-emitting of the organic EL elements to all the switching circuits of a first row and the elements comes to be in non-light emitting state. Then, the controller 26 repeats similar operations for the case of a first subfield, and corresponding light emitting is conducted from the first subfield to the eighth subfield.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はアクティブマトリク
ス型表示装置、特に、有機エレクトロルミネセンス素子
等の発光素子を有するアクティブマトリクス型発光パネ
ルを用いた表示装置に関する。
[0001] 1. Field of the Invention [0002] The present invention relates to an active matrix type display device, and more particularly to a display device using an active matrix type light emitting panel having a light emitting element such as an organic electroluminescence element.

【0002】[0002]

【従来の技術】有機エレクトロルミネセンス素子(以
下、有機EL素子と称する)は発光素子を流れる電流に
よってその発光輝度を制御することができ、このような
発光素子をマトリクス状に配置して構成される発光パネ
ルを用いたマトリクス型ディスプレイの開発が広く進め
られている。かかる有機EL素子を用いた発光パネルと
して、有機EL素子を単にマトリクス状に配置した単純
マトリクス型発光パネルと、マトリクス状に配置した有
機EL素子の各々にトランジスタからなる駆動素子を加
えたアクティブマトリクス型発光パネルがある。アクテ
ィブマトリクス型発光パネルは単純マトリクス型発光パ
ネルに比べて、低消費電力であり、また画素間のクロス
トークが少ないなどの利点を有し、特に大画面ディスプ
レイや高精細度ディスプレイに適している。
2. Description of the Related Art An organic electroluminescent element (hereinafter, referred to as an organic EL element) can control the light emission luminance by a current flowing through a light emitting element, and is constituted by arranging such light emitting elements in a matrix. The development of a matrix type display using a light emitting panel has been widely promoted. As a light emitting panel using such an organic EL element, a simple matrix type light emitting panel in which organic EL elements are simply arranged in a matrix, and an active matrix type in which a driving element including a transistor is added to each of the organic EL elements arranged in a matrix are used. There is a light emitting panel. Active matrix light-emitting panels have advantages such as lower power consumption and less crosstalk between pixels than simple matrix light-emitting panels, and are particularly suitable for large-screen displays and high-definition displays.

【0003】図1は、従来のアクティブマトリクス型発
光パネルの1つの画素10に対応する回路構成の1例を
示している。かかる回路構成は、例えば、特開平8−2
41057号公報に開示されている。図1において、F
ET(Field Effect Transistor)11(アドレス選択用
トランジスタ)のゲートGは、アドレス信号が供給され
るアドレス走査電極線(アドレスライン)に接続され、
FET11のソースSはデータ信号が供給されるデータ
電極線(データライン)に接続されている。FET11
のドレインDはFET12(駆動用トランジスタ)のゲ
ートGに接続され、キャパシタ13を通じて接地されて
いる。FET12のソースSは接地され、ドレインDは
有機EL素子15の陰極に接続され、有機EL素子15
の陽極を通じて電源に接続されている。この回路の発光
制御動作について述べると、先ず、図1においてFET
11のゲートGにオン電圧が供給されると、FET11
はソースSに供給されるデータの電圧に対応した電流を
ソースSからドレインDへ流す。FET11のゲートG
がオフ電圧であるとFET11はいわゆるカットオフと
なり、FET11のドレインDはオープン状態となる。
従って、FET11のゲートGがオン電圧の期間に、ソ
ースSの電圧がキャパシタ13に充電され、その電圧が
FET12のゲートGに供給されて、FET12にはそ
のゲート電圧とソース電圧に基づいた電流が有機EL素
子15を通じてドレインDからソースSへ流れ、有機E
L素子15を発光せしめる。また、FET11のゲート
Gがオフ電圧になると、FET11はオープン状態とな
り、FET12はキャパシタ13に蓄積された電荷によ
りゲートGの電圧が保持され、次の走査まで駆動電流を
維持し、有機EL素子15の発光も維持される。尚、F
ET12のゲートGとソースSの間にはゲート入力容量
が存在するのでキャパシタ13を設けなくとも上記と同
様な動作が可能である。
FIG. 1 shows an example of a circuit configuration corresponding to one pixel 10 of a conventional active matrix light emitting panel. Such a circuit configuration is described in, for example,
It is disclosed in Japanese Patent Publication No. 41057. In FIG. 1, F
The gate G of the ET (Field Effect Transistor) 11 (address selection transistor) is connected to an address scan electrode line (address line) to which an address signal is supplied.
The source S of the FET 11 is connected to a data electrode line (data line) to which a data signal is supplied. FET11
Is connected to the gate G of the FET 12 (driving transistor), and is grounded through the capacitor 13. The source S of the FET 12 is grounded, the drain D is connected to the cathode of the organic EL element 15, and the organic EL element 15
Is connected to a power source through the anode. The light emission control operation of this circuit will be described first.
When the ON voltage is supplied to the gate G of the FET 11, the FET 11
Causes a current corresponding to the voltage of the data supplied to the source S to flow from the source S to the drain D. Gate G of FET11
Is an off voltage, the FET 11 is cut off, and the drain D of the FET 11 is in an open state.
Therefore, while the gate G of the FET 11 is in the ON voltage, the voltage of the source S is charged in the capacitor 13, and the voltage is supplied to the gate G of the FET 12, and the FET 12 receives a current based on the gate voltage and the source voltage. It flows from the drain D to the source S through the organic EL element 15, and the organic E
The L element 15 is caused to emit light. When the gate G of the FET 11 is turned off, the FET 11 is in an open state, and the FET 12 holds the voltage of the gate G by the charge accumulated in the capacitor 13, maintains the drive current until the next scan, and operates the organic EL element 15 Is also maintained. Note that F
Since there is a gate input capacitance between the gate G and the source S of the ET 12, the same operation as described above can be performed without providing the capacitor 13.

【0004】アクティブマトリクス駆動により発光制御
を行う表示パネルの1画素に対応する回路はこのように
構成され、当該画素の有機EL素子15が駆動された場
合に当該画素の発光が維持される。上記したアクティブ
マトリクス型発光パネルの各画素の輝度階調の制御は、
FET12のゲートGにかかる電圧を振幅変調すること
によって行なわれていた。すなわち、FET12のソー
ス−ドレイン電流はゲートGにかかる電圧によって変化
するので、供給される入力映像信号に応じて、ゲートG
に印加する電圧の大きさを調整することにより、有機E
L素子15に流れる駆動電流量を調整することができ
る。従って、有機EL素子15の駆動電流量を調整する
ことによって有機EL素子15の瞬時輝度を調整してい
た。
A circuit corresponding to one pixel of a display panel that performs light emission control by active matrix driving is configured as described above, and when the organic EL element 15 of the pixel is driven, light emission of the pixel is maintained. The control of the brightness gradation of each pixel of the active matrix light emitting panel described above is performed by:
This is performed by amplitude-modulating the voltage applied to the gate G of the FET 12. That is, since the source-drain current of the FET 12 changes according to the voltage applied to the gate G, the gate G depends on the supplied input video signal.
By adjusting the magnitude of the voltage applied to the
The amount of drive current flowing through L element 15 can be adjusted. Therefore, the instantaneous luminance of the organic EL element 15 is adjusted by adjusting the amount of drive current of the organic EL element 15.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上述し
たような振幅変調によって輝度階調表示を行う表示装置
においては、駆動FETのゲートにかかる電圧値とソー
ス−ドレイン間を流れる電流値の関係、すなわち、駆動
FETの電流−電圧特性が非線形であるため、表示パネ
ル面内の駆動FET間の特性ばらつきによって輝度階調
にばらつきが生じ、精度の高い多階調表示が困難である
という問題があった。
However, in a display device which performs luminance gradation display by amplitude modulation as described above, the relationship between the voltage value applied to the gate of the drive FET and the current value flowing between the source and the drain, that is, In addition, since the current-voltage characteristics of the driving FETs are non-linear, the luminance gradation varies due to the characteristic variation between the driving FETs on the display panel surface, and it is difficult to perform high-precision multi-gradation display. .

【0006】本発明はかかる点に鑑みてなされたもので
あり、その目的とするところは、表示パネルの全面に亘
って輝度階調のばらつきのない高精度の多階調表示が可
能なアクティブマトリクス型の表示装置を提供すること
にある。
SUMMARY OF THE INVENTION The present invention has been made in view of the foregoing, and it is an object of the present invention to provide an active matrix capable of performing high-precision multi-gradation display without variation in luminance gradation over the entire surface of a display panel. It is an object of the present invention to provide a display device of the type.

【0007】[0007]

【課題を解決するための手段】本発明による表示装置
は、マトリクス状に配置された発光素子と、データ信号
電流を蓄積して保持する保持回路と、該保持された電圧
に応じて発光素子の各々を駆動する駆動素子と、を含む
アクティブマトリクス型の発光パネルを用いた表示装置
であって、入力映像データの同期タイミングに対応する
単位フレーム期間内に、複数のサブフィールド期間を設
定する設定手段と、上記サブフィールド期間毎に発光パ
ネルの各行を順次走査して、上記複数の入力映像データ
に応じて発光素子を発光せしめる表示制御手段と、サブ
フィールド期間の各々に対し、発光制御手段が発光パネ
ルの全ての行の走査に要する期間であるアドレス期間が
所定発光期間よりも長い場合に、発光素子の各々の発光
期間が所定発光期間に達した時に発光素子の各々の発光
を停止せしめる発光停止手段と、を有することを特徴と
している。
A display device according to the present invention comprises a light emitting element arranged in a matrix, a holding circuit for accumulating and holding a data signal current, and a light emitting element in accordance with the held voltage. A display device using an active matrix light emitting panel including a driving element for driving each of the driving elements, wherein a setting means for setting a plurality of subfield periods within a unit frame period corresponding to a synchronization timing of input video data Display control means for sequentially scanning each row of the light-emitting panel for each of the sub-field periods and causing the light-emitting elements to emit light in accordance with the plurality of input video data, and emission control means for each of the sub-field periods. When the address period, which is the period required for scanning all the rows of the panel, is longer than the predetermined light emitting period, each light emitting period of the light emitting element is changed to the predetermined light emitting period. It is characterized by having a light emission stop means allowed to stop the light emission of each light emitting element when it reaches.

【0008】本発明の他の特徴として、上記発光停止手
段は、発光パネルの各行毎に発光素子の発光を停止せし
める。また、本発明の他の特徴として、上記発光停止手
段は、タイマとタイマの出力に応じて駆動素子の各々の
導通を遮断するスイッチ回路と、を有している。更に、
本発明の他の特徴として、上記スイッチ回路は駆動素子
及び保持回路の間に直列に接続されている。
As another feature of the present invention, the light emission stopping means stops light emission of the light emitting element for each row of the light emitting panel. Further, as another feature of the present invention, the light emission stopping means includes a timer and a switch circuit for cutting off conduction of each of the driving elements according to the output of the timer. Furthermore,
As another feature of the present invention, the switch circuit is connected in series between the driving element and the holding circuit.

【0009】本発明の更なる特徴として、上記スイッチ
回路は保持回路に並列に接続されている。また、本発明
の他の特徴として、上記スイッチ回路は発光素子に直列
に接続されている。
[0009] As a further feature of the present invention, the switch circuit is connected in parallel to the holding circuit. Further, as another feature of the present invention, the switch circuit is connected in series to the light emitting element.

【0010】[0010]

【発明の実施の形態】本発明の実施例を図面を参照しつ
つ詳細に説明する。尚、以下に説明する図において、実
質的に同等な部分には同一の参照符を付している。図2
は、本発明の第1の実施例であるアクティブマトリクス
型発光パネルを用いた有機EL表示装置20の構成を概
略的に示している。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail with reference to the drawings. In the drawings described below, substantially equivalent parts are denoted by the same reference numerals. FIG.
1 schematically shows a configuration of an organic EL display device 20 using an active matrix light emitting panel according to a first embodiment of the present invention.

【0011】図2において、アナログ/デジタル(A/
D)変換器21は、アナログ映像信号入力を受けてデジ
タル映像信号データに変換する。変換により得られたデ
ジタル映像信号はA/D変換器21からフレームメモリ
24へ供給され1フレーム単位のデジタル映像信号デー
タが一旦フレームメモリ24に記憶される。一方、有機
EL表示装置20内の各部の制御をなす表示制御部(以
下、コントローラと称する)26は、相異なる発光時間
をパラメータとする複数のサブフィールド(以下では8
個のサブフィールドの場合を例に説明する)によって、
上記フレームメモリ24に記憶されたデジタル映像信号
データを、列アドレスカウンタ2及び行アドレスカウン
タ23を用いて制御することにより、複数(ここでは8
個)の階調表示データに変換し、それぞれ発光パネル3
0の画素のアドレスに対応する発光・非発光データと共
に順次マルチプレクサ25に供給する。
In FIG. 2, analog / digital (A /
D) The converter 21 receives an analog video signal and converts it into digital video signal data. The digital video signal obtained by the conversion is supplied from the A / D converter 21 to the frame memory 24, and the digital video signal data of one frame unit is temporarily stored in the frame memory 24. On the other hand, a display control unit (hereinafter, referred to as a controller) 26 that controls each unit in the organic EL display device 20 includes a plurality of subfields (hereinafter, referred to as 8) having different emission times as parameters.
Subfields),
By controlling the digital video signal data stored in the frame memory 24 using the column address counter 2 and the row address counter 23, a plurality (here, 8
Of the light-emitting panels 3).
The data is sequentially supplied to the multiplexer 25 together with the emission / non-emission data corresponding to the address of the 0 pixel.

【0012】また、コントローラ26は、マルチプレク
サ25に供給された発光・非発光データの中から各サブ
フィールドに対応する列データを第1行目から順次画素
の配列順に列ドライバ28が有するデータラッチ回路に
保持させるように制御する。コントローラ26は、デー
タラッチ回路によって順次保持された各サブフィールド
毎の列データを、1行単位で発光パネル30に供給する
と共に、行ドライバ27によって対応する行が有する画
素列において同時に発光させる。また、コントローラ2
6は計時装置(タイマ)を内部に有し(図示しない)、
発光制御ドライバ31を制御して、各サブフィールド毎
に各画素の発光期間を制御する。この動作は、1フレー
ムのデータ単位で、第1サブフィールドから第8サブフ
ィールドまでのそれぞれの列データに関して行なわれる
(ここでは8回行なわれる)。発光パネル30の各画素
は、供給される各サブフィールドの各々に対し、後述す
る所定の発光期間だけ発光制御され、1フレーム分の発
光表示を多階調表示によって行うことができる。
Further, the controller 26 includes a data latch circuit having a column driver 28 having column data corresponding to each subfield from the light emitting / non-light emitting data supplied to the multiplexer 25 in order of pixel arrangement in order from the first row. Is controlled to be held. The controller 26 supplies the column data for each subfield sequentially held by the data latch circuit to the light-emitting panel 30 on a row-by-row basis, and causes the row driver 27 to simultaneously emit light in the pixel columns of the corresponding row. Controller 2
6 has a clock device (timer) inside (not shown),
The light emission control driver 31 is controlled to control the light emission period of each pixel for each subfield. This operation is performed for each column data from the first subfield to the eighth subfield in one frame data unit (here, eight times). The light emission of each pixel of the light emitting panel 30 is controlled for each of the supplied subfields for a predetermined light emission period described later, and light emission display for one frame can be performed by multi-tone display.

【0013】なお、図3に示すように、本実施例におい
ては、上記入力映像信号における1フレーム期間を8個
のサブフィールドに分割し、各サブフィールド期間内に
おける輝度の相対比がそれぞれ1/2,1/4,1/
8,1/16,1/32,1/64,1/256(すな
わち、順に第1サブフィールド〜第8サブフィール
ド),となるように設定され、それらのサブフィールド
の選択的組合せにより256通りの輝度階調表示(すな
わち、サブフィールド2n階調法に基づいた方法による
表示)をなすことができる。
As shown in FIG. 3, in this embodiment, one frame period of the input video signal is divided into eight subfields, and the relative ratio of luminance in each subfield period is 1 / 2,1 / 4,1 /
8, 1/16, 1/32, 1/64, 1/256 (that is, from the first subfield to the eighth subfield in order), and 256 patterns are selected by selectively combining these subfields. (That is, display by a method based on the sub-field 2 n gradation method).

【0014】本発明における有機EL表示装置は、この
ように構成され、入力されるアナログ映像信号に対し、
各サブフィールド毎に発光パネルの画面全体のアドレス
走査による発光制御を繰り返すことにより、フレーム単
位の発光表示を多階調表示によって行うことができる。
図4は、本発明の第1の実施例であるアクティブマトリ
クス型発光パネルの1画素に対応する回路構成を示した
ものである。本実施例が図1に示した従来技術の回路構
成と異なるのは、アドレス選択用FET11のソースS
及びキャパシタ13の接続点と駆動用FET12のゲー
トGとの間に、駆動用FET12の導通を制御して有機
EL素子15の発光及び非発光(発光停止)を制御する
スイッチ回路32が設けられている点である。スイッチ
回路32は、後述する発光制御ドライバ31からの発光
制御信号に応じてスイッチングを行う2つのFET3
3、34を有している。スイッチ回路32において、F
ET33はFET11のソースS及びキャパシタ13の
接続点とFET12のゲートGとの間に接続され、FE
T34はFET12のゲートGとグランド(GND)間
に接続されている。従って、FET33が導通し、FE
T34が非導通となったとき、スイッチ回路32は有機
EL素子15を発光せしめる(ON)発光制御を行い、
その逆の場合に有機EL素子15の発光を停止せしめる
(OFF)発光制御を行う。
The organic EL display device according to the present invention is configured as described above,
By repeating light emission control by address scanning of the entire screen of the light emitting panel for each subfield, light emission display in frame units can be performed by multi-tone display.
FIG. 4 shows a circuit configuration corresponding to one pixel of the active matrix light emitting panel according to the first embodiment of the present invention. This embodiment is different from the circuit configuration of the prior art shown in FIG.
A switch circuit 32 is provided between the connection point of the capacitor 13 and the gate G of the driving FET 12 to control conduction of the driving FET 12 to control light emission and non-light emission (light emission stop) of the organic EL element 15. It is a point. The switch circuit 32 includes two FETs 3 that perform switching in accordance with a light emission control signal from a light emission control driver 31 described later.
3 and 34. In the switch circuit 32, F
ET33 is connected between the connection point of the source S of FET11 and the capacitor 13 and the gate G of FET12,
T34 is connected between the gate G of the FET 12 and the ground (GND). Therefore, the FET 33 conducts, and the FE
When T34 becomes non-conductive, the switch circuit 32 performs (ON) light emission control for causing the organic EL element 15 to emit light,
In the opposite case, light emission control for stopping light emission of the organic EL element 15 (OFF) is performed.

【0015】以下に、コントローラ26が、フレームメ
モリ24に記憶されたデジタル映像信号データに基づい
て発光パネル30の発光・非発光を制御して多階調表示
を実現する発光制御動作について、図5及び図6に示す
タイムチャートを参照しつつ詳細に説明する。先ず、コ
ントローラ26は、デジタル映像信号データがフレーム
メモリ24に供給されると、1フレーム分のデジタル映
像信号データをフレームメモリ24に書き込む。次に、
コントローラ26は、マルチプレクサ25に対し第1サ
ブフィールド(SF1)のデータを出力する旨の指令を
出す。次に、コントローラ26は、行アドレスカウンタ
23に対して第1行を指定する旨の指令を出すと共に、
列アドレスカウンタ22に対して第1列を指定する旨の
指令を出す。
The light emission control operation in which the controller 26 controls light emission / non-light emission of the light emitting panel 30 based on the digital video signal data stored in the frame memory 24 to realize multi-tone display will be described with reference to FIG. And a time chart shown in FIG. First, when the digital video signal data is supplied to the frame memory 24, the controller 26 writes the digital video signal data for one frame into the frame memory 24. next,
Controller 26 issues a command to multiplexer 25 to output data of the first subfield (SF1). Next, the controller 26 issues a command to the row address counter 23 to designate the first row,
It issues a command to the column address counter 22 to designate the first column.

【0016】これにより、指定されたアドレス(第1
行、第1列)の1フレーム分のデジタル映像信号データ
が、各サブフィールドに対応する8つの階調表示データ
に変換され、発光パネル30の画素のアドレスに対応す
る発光・非発光データを含んだデータとして順次マルチ
プレクサ25に供給される。コントローラ26は、マル
チプレクサ25に供給された上記指定されたアドレス
(第1行、第1列)のデータの中から第1サブフィール
ドのデータを列ドライバ28に出力する。列ドライバ2
8では、列ドライバ28内に設けられたデータラッチ回
路(図示しない)によってこのデータを保持する。
Thus, the designated address (first address)
The digital video signal data for one frame (row, first column) is converted into eight gradation display data corresponding to each subfield, and includes emission / non-emission data corresponding to the address of the pixel of the light emitting panel 30. The data is sequentially supplied to the multiplexer 25 as data. The controller 26 outputs the data of the first subfield from the data of the specified address (first row, first column) supplied to the multiplexer 25 to the column driver 28. Column driver 2
At 8, the data is held by a data latch circuit (not shown) provided in the column driver 28.

【0017】次に、コントローラ26は、列アドレスカ
ウンタ22に対して列を1つ更新する指令を出す。すな
わち、列アドレスカウンタ22に対して第2列を指定す
る旨の指令を出す。このことにより、アドレス(第1
行、第2列)が指定され、先に述べたアドレス(第1
行、第1列)が指定された場合と同様の動作を繰り返
す。このようにして、コントローラ26は、第1行の各
列に対し順次、上記した動作を繰り返すことにより、第
1行の全ての列のデータを列ドライバ28が有するデー
タラッチ回路に保持させる。
Next, the controller 26 issues a command to the column address counter 22 to update one column. That is, a command to designate the second column is issued to the column address counter 22. This allows the address (first
Row, second column) is specified and the address (first
(Row, first column) is repeated. In this manner, the controller 26 causes the data latch circuit of the column driver 28 to hold the data of all the columns of the first row by repeating the above-described operation sequentially for each column of the first row.

【0018】第1行の全ての列データがラッチされた
後、図5に示すように、コントローラ26は第1行の列
データのそれぞれを、対応する各列の画素に書き込む。
すなわち、各画素に対応するアドレス選択用FET11
を導通せしめる。これと同時に、コントローラ26は発
光制御ドライバ31を制御してスイッチ回路32を導通
(発光制御ON)させる制御信号を供給せしめ、発光を
示すデータを有する画素の有機EL素子を発光せしめ
る。尚、コントローラ26は、更に、第1サブフィール
ドに対し予め決められた所定の発光期間(TL1)が経過
したときに、上記有機EL素子の発光の停止を指示する
信号を発光制御ドライバ31に供給する。発光制御ドラ
イバ31は第1行の全てのスイッチ回路32に有機EL
素子の発光を停止せしめる制御信号(発光制御OFF)
を供給し、有機EL素子は非発光となる。
After all the column data of the first row is latched, the controller 26 writes each of the column data of the first row to the corresponding pixel of each column, as shown in FIG.
That is, the address selection FET 11 corresponding to each pixel
Is made conductive. At the same time, the controller 26 controls the light emission control driver 31 to supply a control signal for turning on the switch circuit 32 (light emission control ON), thereby causing the organic EL element of the pixel having data indicating light emission to emit light. The controller 26 further sends a signal to the light emission control driver 31 to instruct the organic EL element to stop light emission when a predetermined light emission period (T L1 ) elapses for the first subfield. Supply. The light emission control driver 31 applies an organic EL to all the switch circuits 32 in the first row.
Control signal to stop light emission of device (light emission control OFF)
And the organic EL element does not emit light.

【0019】コントローラ26は、第1行の全ての列デ
ータがラッチされた後のステップとして、行アドレスカ
ウンタ23を第2行に指定する旨の指令を出すと共に、
列アドレスカウンタ22を第1列に指定する旨の指令を
出す。上記した第1行の場合の動作と同様にして、第2
行の全ての列データのデータラッチを行うように制御を
実行する。第2行の全ての列データのラッチ後、上記し
た第1行の場合と同様にして第2行の各列の画素の発光
制御動作が実行される。
The controller 26 issues a command to designate the row address counter 23 to the second row as a step after all the column data of the first row is latched.
An instruction to designate the column address counter 22 as the first column is issued. In the same manner as the operation for the first row described above, the second
Control is performed so as to perform data latch of all column data of the row. After latching all the column data of the second row, the light emission control operation of the pixels of each column of the second row is executed in the same manner as in the case of the first row described above.

【0020】コントローラ26は、このような動作を全
ての行(すなわち、第1ライン〜第mライン)に亘って
行うことにより、第1サブフィールドのデータに対応さ
せて発光パネル30の全ての画素の発光制御を行うこと
ができる。次に、コントローラ26は、マルチプレクサ
25に対し第2サブフィールドのデータを出力する旨の
指令を発する。以下、コントローラ26は、先に述べた
第1サブフィールドの場合と同様の動作を繰り返し、第
2サブフィールドのデータに対応した発光がなされる。
The controller 26 performs such an operation over all the rows (that is, the first to m-th lines), so that all the pixels of the light emitting panel 30 correspond to the data of the first subfield. Light emission control can be performed. Next, the controller 26 issues a command to the multiplexer 25 to output data of the second subfield. Thereafter, the controller 26 repeats the same operation as in the case of the first subfield described above, and emits light corresponding to the data of the second subfield.

【0021】このようにして、第1サブフィールドから
第8サブフィールドまでに対応した発光がなされるが、
本発明における特徴として、各サブフィールド毎に所定
の発光期間が経過した後、発光素子の発光を停止せしめ
る手段を有しているので、アドレス期間(TA)よりも
短い任意の発光期間をサブフィールドに対し割り当てる
ことが可能である。すなわち、発光停止手段を有しない
場合にアドレス期間よりも短い発光期間をサブフィール
ドに割り当てることができないのは、次のサブフィール
ドのアドレス期間の開始によって画素の発光(又は非発
光)が更新されるまで、発光していた画素の発光を停止
できず、次のサブフィールドは、全ての行の走査に要す
る期間であるアドレス期間が終了するまで開始できない
からである。
In this manner, light emission corresponding to the first to eighth subfields is performed.
As a feature of the present invention, since a means for stopping light emission of the light emitting element after a predetermined light emission period elapses for each subfield is provided, an arbitrary light emission period shorter than the address period (T A ) can be set as a sub-field. Can be assigned to fields. That is, when the light emission stop means is not provided, the light emission period shorter than the address period cannot be allocated to the subfield because the light emission (or non-light emission) of the pixel is updated at the start of the address period of the next subfield. Until then, the light emission of the pixel that has been emitting light cannot be stopped, and the next subfield cannot be started until the end of the address period, which is the period required for scanning all the rows.

【0022】図5は、第kサブフィールド(1≦k≦
8)に対し、アドレス期間(TA)よりも短い発光期間
で各ラインの発光を制御する場合を示している。コント
ローラ26による前述したのと同様な制御により、各行
はこのサブフィールドに対して設定された所定の発光期
間(TLk)で発光制御される。例えば、1フレームを6
0Hzで表示する場合、1フレームは約16.7ミリ秒
(ms)である。ここで、アドレス期間を0.84ms
(1フレーム期間の40%×1/8)、第1サブフィー
ルド(1/2)における発光期間を1フレーム期間の1
/2以下の値、例えば5msとそれぞれ設定する場合を
例に説明する。このとき、第2サブフィールド以降のサ
ブフィールドにおける発光期間はそれぞれ第1サブフィ
ールドの発光期間の1/21,1/22,1/23,・・
・,1/27である2.5ms,1.25ms,0.6
25ms,・・・,0.039msとなる。従って、こ
の場合、第4サブフィールド以降のサブフィールド(第
4〜第8サブフィールド)における発光期間はアドレス
期間(TA=0.84ms)よりも短いが、各サブフィ
ールドに対し所望の発光期間を有するように制御がなさ
れる。
FIG. 5 shows the k-th subfield (1 ≦ k ≦
8) shows a case in which light emission of each line is controlled in a light emission period shorter than the address period (T A ). Under the same control as described above by the controller 26, each row is controlled to emit light in a predetermined light emission period (T Lk ) set for this subfield. For example, one frame is 6
When displaying at 0 Hz, one frame is about 16.7 milliseconds (ms). Here, the address period is set to 0.84 ms.
(40% × 1/8 of one frame period), the light emission period in the first subfield (1 /) is set to 1
An example will be described in which each value is set to be equal to or less than / 2, for example, 5 ms. At this time, the light emission periods in the subfields after the second subfield are respectively 1/2 1 , 1/2 2 , 1/2 3 ,... Of the light emission period of the first subfield.
.. 2.5ms, 1.25ms, 0.6 which is 1/2 7
25 ms,..., 0.039 ms. Therefore, in this case, the light emission period in the subfields after the fourth subfield (the fourth to eighth subfields) is shorter than the address period (T A = 0.84 ms), but the desired light emission period for each subfield is set. Is controlled to have

【0023】上記したようにして、第1サブフィールド
から第8サブフィールドまでの表示制御が終了した時点
で1フレームの表示が完了する。その後、コントローラ
26は、フレームメモリ24に記憶されるデータを次の
フレームに対応するデータに書き替えて、次のフレーム
の表示制御を行う。従って、本発明によれば、上述した
発光停止制御により、各サブフィールドに対しアドレス
期間よりも短い任意の発光期間で発光を制御できるの
で、広範な階調表示が可能である。
As described above, the display of one frame is completed when the display control from the first subfield to the eighth subfield is completed. Thereafter, the controller 26 rewrites the data stored in the frame memory 24 to data corresponding to the next frame, and controls the display of the next frame. Therefore, according to the present invention, light emission can be controlled in any light emission period shorter than the address period for each subfield by the above-described light emission stop control, so that a wide range of gradation display is possible.

【0024】図7は、本発明の第2の実施例であるアク
ティブマトリクス型発光パネルの1画素に対応する回路
構成を示したものである。本実施例が第1の実施例と異
なるのは、スイッチ回路32がキャパシタ13に並列に
接続されたFET35を有している点である。すなわ
ち、FET35のドレインDはFET11のソースS及
びキャパシタ13の接続点に接続され、ソースSはグラ
ンドに接地されている。従って、ゲートGに供給される
制御信号に応じてFET35が導通したときに有機EL
素子15の発光は停止される。
FIG. 7 shows a circuit configuration corresponding to one pixel of an active matrix type light emitting panel according to a second embodiment of the present invention. This embodiment differs from the first embodiment in that the switch circuit 32 has an FET 35 connected in parallel to the capacitor 13. That is, the drain D of the FET 35 is connected to the connection point between the source S of the FET 11 and the capacitor 13, and the source S is grounded. Therefore, when the FET 35 is turned on in response to the control signal supplied to the gate G, the organic EL
Light emission of the element 15 is stopped.

【0025】図8は、本発明の第3の実施例である発光
パネルの1画素に対応する回路構成を示したものであ
る。本実施例が前述の実施例と異なるのは、スイッチ回
路32がキャパシタ13とFET12のゲートGとの間
に直列に接続されたFET36を有している点である。
すなわち、FET36のドレインDはFET11のソー
スS及びキャパシタ13の接続点に接続され、ソースS
はFET12のゲートGに接続されている。従って、ゲ
ートGに供給される制御信号に応じてFET36が非導
通となったときに有機EL素子15の発光は停止され
る。
FIG. 8 shows a circuit configuration corresponding to one pixel of a light emitting panel according to a third embodiment of the present invention. This embodiment is different from the above-described embodiment in that the switch circuit 32 has an FET 36 connected in series between the capacitor 13 and the gate G of the FET 12.
That is, the drain D of the FET 36 is connected to the connection point between the source S of the FET 11 and the capacitor 13, and the source S
Is connected to the gate G of the FET 12. Therefore, when the FET 36 is turned off in response to the control signal supplied to the gate G, the light emission of the organic EL element 15 is stopped.

【0026】図9ないし11は、本発明の他の実施例で
ある発光パネルの1画素に対応する回路構成をそれぞれ
示したものである。各実施例が前述の実施例と異なるの
は、スイッチ回路32が有機EL素子15と直列に接続
されたFET37を有している点である。すなわち、F
ET37のゲートGに供給される制御信号に応じてFE
T37が非導通となったときに有機EL素子15の発光
は停止される。
FIGS. 9 to 11 show a circuit configuration corresponding to one pixel of a light emitting panel according to another embodiment of the present invention. Each embodiment differs from the above-described embodiments in that the switch circuit 32 includes an FET 37 connected in series with the organic EL element 15. That is, F
FE in response to a control signal supplied to the gate G of the ET 37
When T37 becomes nonconductive, light emission of the organic EL element 15 is stopped.

【0027】上記したように、本発明によれば、上述し
た発光停止制御により、各サブフィールドに対しアドレ
ス期間よりも短い任意の発光期間で発光を制御できるの
で、広範な階調表示が実現できる。尚、上記した実施例
において示した各数値は例であって適宜変更してもよ
い。また、各種のスイッチング回路等は、適宜組み合わ
せて用いることができる。
As described above, according to the present invention, light emission can be controlled in an arbitrary light emission period shorter than the address period for each subfield by the above-described light emission stop control, so that a wide range of gradation display can be realized. . Each numerical value shown in the above-described embodiment is an example, and may be changed as appropriate. Various switching circuits and the like can be used in appropriate combination.

【0028】[0028]

【発明の効果】上記したことから明らかなように、本発
明によれば、各サブフィールドにおける発光期間を任意
に制御できるので、表示パネルの全面に亘って輝度階調
のばらつきのない高精度の多階調表示が可能なアクティ
ブマトリクス型の表示装置を実現できる。
As is apparent from the above description, according to the present invention, the light emission period in each subfield can be arbitrarily controlled, so that a high-precision and uniform luminance gradation can be obtained over the entire display panel. An active matrix display device capable of multi-tone display can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】従来のアクティブマトリクス型発光パネルの1
つの画素に対応する回路構成の1例を概略的に示す図で
ある。
FIG. 1 shows a conventional active matrix light emitting panel 1
FIG. 3 is a diagram schematically illustrating an example of a circuit configuration corresponding to one pixel.

【図2】本発明の実施例であるアクティブマトリクス型
発光パネルを用いた有機EL表示装置の構成を概略的に
示す図である。
FIG. 2 is a diagram schematically showing a configuration of an organic EL display device using an active matrix light emitting panel according to an embodiment of the present invention.

【図3】デジタル映像信号の1フレーム期間、サブフィ
ールド期間、及びアドレス期間を示す図である。
FIG. 3 is a diagram illustrating one frame period, a subfield period, and an address period of a digital video signal.

【図4】本発明の第1の実施例であるアクティブマトリ
クス型発光パネルの1画素に対応する回路構成を示す図
である。
FIG. 4 is a diagram showing a circuit configuration corresponding to one pixel of the active matrix light emitting panel according to the first embodiment of the present invention.

【図5】コントローラがサブフィールド毎に実行する発
光制御のタイミングを示すタイムチャートである。
FIG. 5 is a time chart showing the timing of light emission control executed by the controller for each subfield.

【図6】コントローラが、アドレス期間よりも短い発光
期間で発光を制御する制御タイミングを示すタイムチャ
ートである。
FIG. 6 is a time chart showing a control timing at which a controller controls light emission in a light emission period shorter than an address period.

【図7】本発明の第2の実施例であるアクティブマトリ
クス型発光パネルの1画素に対応する回路構成を示す図
である。
FIG. 7 is a diagram illustrating a circuit configuration corresponding to one pixel of an active matrix light emitting panel according to a second embodiment of the present invention.

【図8】本発明の第3の実施例である発光パネルの1画
素に対応する回路構成を示す図である。
FIG. 8 is a diagram showing a circuit configuration corresponding to one pixel of a light emitting panel according to a third embodiment of the present invention.

【図9】本発明の他の実施例である発光パネルの1画素
に対応する回路構成を示す図である。
FIG. 9 is a diagram showing a circuit configuration corresponding to one pixel of a light emitting panel according to another embodiment of the present invention.

【図10】本発明の他の実施例である発光パネルの1画
素に対応する回路構成を示す図である。
FIG. 10 is a diagram showing a circuit configuration corresponding to one pixel of a light emitting panel according to another embodiment of the present invention.

【図11】本発明の他の実施例である発光パネルの1画
素に対応する回路構成を示す図である。
FIG. 11 is a diagram illustrating a circuit configuration corresponding to one pixel of a light emitting panel according to another embodiment of the present invention.

【主要部分の符号の説明】[Explanation of Signs of Main Parts]

10 画素 11 アドレス選択用FET 12 駆動用FET 13 キャパシタ 15 発光素子 20 表示装置 21 A/D変換器 22 列アドレスカウンタ 23 行アドレスカウンタ 24 フレームメモリ 25 マルチプレクサ 26 コントローラ 27 行ドライバ 28 列ドライバ 30 発光パネル 31 発光制御ドライバ 32 スイッチ回路 33,34,35,36 FET Reference Signs List 10 pixel 11 address selection FET 12 drive FET 13 capacitor 15 light emitting element 20 display device 21 A / D converter 22 column address counter 23 row address counter 24 frame memory 25 multiplexer 26 controller 27 row driver 28 column driver 30 light emitting panel 31 Light emission control driver 32 Switch circuit 33, 34, 35, 36 FET

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 マトリクス状に配置された発光素子と、
データ信号電流を蓄積して保持する保持回路と、該保持
された電圧に応じて前記発光素子の各々を駆動する駆動
素子と、を含むアクティブマトリクス型の発光パネルを
用いた表示装置であって、 入力映像データの同期タイミングに対応する単位フレー
ム期間内に、複数のサブフィールド期間を設定する設定
手段と、 前記サブフィールド期間毎に前記発光パネルの各行を順
次走査して、前記入力映像データに応じて前記発光素子
を発光せしめる表示制御手段と、 前記複数のサブフィールド期間の各々に対し、前記発光
素子の各々の発光期間が所定発光期間に達した時に前記
発光素子の各々の発光を停止せしめる発光停止手段と、
を有することを特徴とする表示装置。
A light-emitting element arranged in a matrix;
A display device using an active-matrix light-emitting panel including a holding circuit that stores and holds a data signal current, and a driving element that drives each of the light-emitting elements according to the held voltage, Setting means for setting a plurality of subfield periods within a unit frame period corresponding to the synchronization timing of the input video data; and sequentially scanning each row of the light emitting panel for each of the subfield periods, according to the input video data. Display control means for causing the light emitting element to emit light, and for each of the plurality of subfield periods, light emission for stopping light emission of each of the light emitting elements when each light emitting period of the light emitting element reaches a predetermined light emitting period. Means for stopping;
A display device comprising:
【請求項2】 前記発光停止手段は、前記発光パネルの
各行毎に前記発光素子の発光を停止せしめることを特徴
とする請求項1に記載の表示装置。
2. The display device according to claim 1, wherein the light emission stopping means stops light emission of the light emitting element for each row of the light emitting panel.
【請求項3】 前記発光停止手段は、タイマと、前記タ
イマの出力に応じて前記駆動素子の各々の導通を遮断す
るスイッチ回路と、を有することを特徴とする請求項1
又は2に記載の表示装置。
3. The light emission stopping means includes a timer, and a switch circuit for interrupting conduction of each of the driving elements in accordance with an output of the timer.
Or the display device according to 2.
【請求項4】 前記スイッチ回路は、前記駆動素子及び
前記保持回路の間に直列に接続されていることを特徴と
する請求項3に記載の表示装置。
4. The display device according to claim 3, wherein the switch circuit is connected in series between the driving element and the holding circuit.
【請求項5】 前記スイッチ回路は、前記保持回路に並
列に接続されていることを特徴とする請求項3に記載の
表示装置。
5. The display device according to claim 3, wherein the switch circuit is connected to the holding circuit in parallel.
【請求項6】 前記スイッチ回路は、前記駆動素子及び
前記保持回路の間に直列に接続された第1のスイッチ素
子及び前記駆動素子に並列に接続された第2のスイッチ
素子を少なくとも有することを特徴とする請求項3に記
載の表示装置。
6. The switch circuit includes at least a first switch element connected in series between the drive element and the holding circuit, and a second switch element connected in parallel to the drive element. The display device according to claim 3, wherein:
【請求項7】 前記スイッチ回路は、前記発光素子に直
列に接続されていることを特徴とする請求項3に記載の
表示装置。
7. The display device according to claim 3, wherein the switch circuit is connected to the light emitting element in series.
【請求項8】 前記所定発光期間は、サブフィールド2
n階調法に基づいて定められることを特徴とする請求項
1ないし7に記載の表示装置。
8. The method according to claim 1, wherein the predetermined light emission period is a subfield 2
The display device according to claim 1, wherein the display device is determined based on an n gradation method.
JP11220291A 1999-08-03 1999-08-03 Active matrix type display device Pending JP2001042822A (en)

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