JPH10312173A - Picture display device - Google Patents
Picture display deviceInfo
- Publication number
- JPH10312173A JPH10312173A JP9136010A JP13601097A JPH10312173A JP H10312173 A JPH10312173 A JP H10312173A JP 9136010 A JP9136010 A JP 9136010A JP 13601097 A JP13601097 A JP 13601097A JP H10312173 A JPH10312173 A JP H10312173A
- Authority
- JP
- Japan
- Prior art keywords
- pixels
- display device
- light emission
- image display
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011159 matrix material Substances 0.000 claims abstract description 19
- 239000003990 capacitor Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 13
- 150000002894 organic compounds Chemical class 0.000 claims description 2
- 235000019557 luminance Nutrition 0.000 abstract 3
- 230000014509 gene expression Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 15
- 238000006243 chemical reaction Methods 0.000 description 5
- 239000010410 layer Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000012044 organic layer Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Electroluminescent Light Sources (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Control Of El Displays (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、有機エレクトロル
ミネッセンス素子（以下、有機ＥＬ素子と称する）等の
エレクトロルミネッセンス素子（ＥＬ素子）を用いた表
示装置に関する。The present invention relates to a display device using an electroluminescent element (EL element) such as an organic electroluminescent element (hereinafter, referred to as an organic EL element).
【０００２】[0002]
【従来の技術】従来、ガラス板、あるいは透明な有機フ
ィルム上に形成した蛍光体に電流を流して発光させる有
機ＥＬ素子が知られている。図５に、かかる有機ＥＬ素
子の概略構成を示す。図５において、ガラス基板３０１
の上面には透明電極３０２が形成されており、この透明
電極３０２の上面には発光層３０３が形成されている。
さらに、かかる発光層３０３の上面には金属電極３０４
が形成されている。2. Description of the Related Art Conventionally, there has been known an organic EL device which emits light by applying a current to a phosphor formed on a glass plate or a transparent organic film. FIG. 5 shows a schematic configuration of such an organic EL element. In FIG. 5, the glass substrate 301
A transparent electrode 302 is formed on the upper surface of the transparent electrode 302, and a light emitting layer 303 is formed on the upper surface of the transparent electrode 302.
Further, a metal electrode 304 is provided on the upper surface of the light emitting layer 303.
Are formed.
【０００３】図６は、有機ＥＬ素子を等価的に表した電
気回路図である。一般に有機ＥＬ素子は図６に示される
が如く、回路抵抗成分Ｒと、容量成分Ｃと、発光成分Ｄ
とにより等価的に表される、容量性の発光素子であると
考えられている。FIG. 6 is an electric circuit diagram equivalently showing an organic EL element. Generally, as shown in FIG. 6, an organic EL element has a circuit resistance component R, a capacitance component C, and a light emission component D.
Is considered to be a capacitive light emitting element equivalently represented by
【０００４】従って、有機ＥＬ素子は、図５に示すスイ
ッチ３０５によって発光駆動電圧３０６が、透明電極３
０２と金属電極３０４間に印加されると、先ず、素子の
電気容量に相当する電荷が電極に変位電流として流れ込
み蓄積される。続いて一定の電圧（障壁電圧）を越える
と、電極から有機層に電流が流れ始め、この電流に比例
して発光が始まる。Accordingly, in the organic EL element, the light emission drive voltage 306 is changed by the switch 305 shown in FIG.
When applied between the electrode 02 and the metal electrode 304, first, a charge corresponding to the capacitance of the element flows into the electrode as a displacement current and is accumulated. Subsequently, when a certain voltage (barrier voltage) is exceeded, a current starts to flow from the electrode to the organic layer, and light emission starts in proportion to the current.
【０００５】さらに、複数の有機ＥＬ素子を用いた表示
装置の例を図７を参照しつつ説明する。このような表示
装置は図７に示すように、陰極線走査回路５１と陽極線
ドライブ回路５２と表示パネル５５とから構成される。
陰極線走査回路５１と表示パネル５５とは接続部を構成
する接続端子ｂ1 〜ｂn を介して接続され、陽極線ドラ
イブ回路５２と表示パネル５５とは同じく接続部を構成
する接続端子ａ1 〜ａm を介して接続されている。Further, an example of a display device using a plurality of organic EL elements will be described with reference to FIG. As shown in FIG. 7, such a display device includes a cathode line scanning circuit 51, an anode line driving circuit 52, and a display panel 55.
The cathode line scanning circuit 51 and the display panel 55 are connected via connection terminals b1 to bn forming a connection portion, and the anode line drive circuit 52 and the display panel 55 are connected via connection terminals a1 to am also forming a connection portion. Connected.
【０００６】図７の駆動方法は、単純マトリクス駆動方
式と呼ばれるもので、陽極線Ａ1 〜Ａm と陰極線Ｂ1 〜
Ｂn をマトリクス（格子）状に配置し、このマトリクス
状に配置した陽極線と陰極線の各交点位置に有機ＥＬ素
子Ｅ1,1 〜Ｅm,n を接続し、この陽極線または陰極線の
いずれか一方を一定の時間間隔で順次選択して走査する
と共に、この走査に同期して他方の線を駆動源たる電流
源５２1 〜５２m でドライブしてやることにより、任意
の交点位置の有機ＥＬ素子を発光させるようにしたもの
である。The driving method shown in FIG. 7 is called a simple matrix driving method, and includes anode lines A1 to Am and cathode lines B1 to B1.
Bn are arranged in a matrix (lattice), and the organic EL elements E1,1 to Em, n are connected to the respective intersections of the anode lines and the cathode lines arranged in the matrix, and one of the anode lines and the cathode lines is connected. Scanning is performed sequentially at fixed time intervals, and the other line is driven by current sources 521 to 52m as driving sources in synchronization with this scanning, so that the organic EL element at an arbitrary intersection point emits light. It was done.
【０００７】有機ＥＬ素子のドライブ法には、陰極線走
査・陽極線ドライブ、陽極線走査・陰極線ドライブの２
つの方法があるが、図７は、陰極線走査・陽極線ドライ
ブの場合を示しており、陰極線Ｂ1 〜Ｂn に陰極線走査
回路５１を接続すると共に、陽極線Ａ1 〜Ａm に電流源
５２1 〜５２m からなる陽極線ドライブ回路５２を接続
したものである。陰極線走査回路５１は、スイッチ５３
1 〜５３n を一定時間間隔で順次アース端子側へ切り換
えながら走査していくことにより、陰極線Ｂ1 〜Ｂn に
対してアース電位（０Ｖ）を順次与えていく。[0007] There are two methods of driving the organic EL element: cathode scan / anode drive, anode scan / cathode drive.
FIG. 7 shows a case of cathode line scanning / anode line driving, in which a cathode line scanning circuit 51 is connected to cathode lines B1 to Bn, and current sources 521 to 52m are connected to anode lines A1 to Am. The anode line drive circuit 52 is connected. The cathode line scanning circuit 51 includes a switch 53
The ground potential (0 V) is sequentially applied to the cathode lines B1 to Bn by sequentially scanning the 1 to 53n while switching to the ground terminal side at regular time intervals.
【０００８】また、陽極線ドライブ回路５２は、前記陰
極線走査回路５１のスイッチ走査に同期してスイッチ５
４1 〜５４m をオン・オフ制御することにより陽極線Ａ
1 〜Ａm に電流源５２1 〜５２m を接続し、所望の交点
位置の有機ＥＬ素子に駆動電流を供給する。The anode line drive circuit 52 switches the switch 5 in synchronization with the switch scan of the cathode line scan circuit 51.
By controlling on / off of 41 to 54 m, the anode wire A
Current sources 521 to 52m are connected to 1 to Am to supply a drive current to the organic EL element at a desired intersection.
【０００９】例えば、有機ＥＬ素子Ｅ2,1 〜Ｅ3,1 を発
光させる場合を例に採ると、図７に示すように、陰極線
走査回路５１のスイッチ５３1 がアース側に切り換えら
れ、第１の陰極線Ｂ1 にアース電位が与えられている時
に、陽極線ドライブ回路５２のスイッチ５４2 と５４3
を電流源側に切り換え、陽極線Ａ2 とＡ3 に電流源５２
2 と５２3 を接続してやれば良い。このような走査とド
ライブを高速で繰り返すことにより、任意の位置の有機
ＥＬ素子を発光させると共に、各有機ＥＬ素子があたか
も同時に発光しているように制御するものである。For example, taking the case where the organic EL elements E2,1 to E3,1 emit light, the switch 531 of the cathode line scanning circuit 51 is switched to the ground side as shown in FIG. When the ground potential is applied to B1, the switches 542 and 543 of the anode line drive circuit 52 are turned on.
Is switched to the current source side, and the current source 52 is connected to the anode lines A2 and A3.
Just connect 2 and 523. By repeating such scanning and driving at a high speed, the organic EL element at an arbitrary position emits light, and control is performed so that each organic EL element emits light simultaneously.
【００１０】走査中の陰極線Ｂ1 以外の他の陰極線Ｂ2
〜Ｂn には電源電圧と同電位の逆バイアス電圧Ｖｃｃを
印加してやることにより、誤発光を防止している。な
お、図７では、駆動源として電流源５２1 〜５２m を用
いたが、電圧源を用いても同様に実現することができ
る。A cathode line B2 other than the scanning cathode line B1
By applying a reverse bias voltage Vcc having the same potential as the power supply voltage to .about.Bn, erroneous light emission is prevented. In FIG. 7, the current sources 521 to 52m are used as the driving sources, but the present invention can be similarly realized by using a voltage source.
【００１１】図８は、上述した構成の有機ＥＬ素子を用
いた有機ＥＬ表示装置の構成を示すブロック図である。
同図において、１０１はＡ／Ｄ変換回路、１０３はフレ
ームメモリ、１０４はコントローラ、１０５は走査回
路、１０６は書き込み回路、１０７は電源回路、１０９
は表示パネルを示す。FIG. 8 is a block diagram showing the structure of an organic EL display device using the organic EL element having the above-described structure.
In the figure, 101 is an A / D conversion circuit, 103 is a frame memory, 104 is a controller, 105 is a scanning circuit, 106 is a writing circuit, 107 is a power circuit, 109
Indicates a display panel.
【００１２】Ａ／Ｄ変換回路１０１は、アナログ映像信
号入力を受けてデジタル映像信号データに変換する。変
換されたデジタル映像信号はＡ／Ｄ変換回路１０１から
フレームメモリ１０３へ供給され、コントローラ１０４
の制御により書き込み蓄積される。コントローラ１０４
は、入力映像信号の水平及び垂直同期信号に同期してフ
レームメモリ１０３他電源回路１０７までの各回路を制
御する。The A / D conversion circuit 101 receives an analog video signal and converts it into digital video signal data. The converted digital video signal is supplied from the A / D conversion circuit 101 to the frame memory 103,
Is written and stored under the control of. Controller 104
Controls each circuit of the frame memory 103 and other power supply circuits 107 in synchronization with the horizontal and vertical synchronization signals of the input video signal.
【００１３】フレームメモリ１０３に蓄積されたデジタ
ル映像信号データは、コントローラ１０４によって読み
出され、書き込み回路１０６に送られる。また、表示パ
ネルの各行及び列に接続された書き込み回路１０６及び
走査回路１０５をコントローラ１０４で順次制御するこ
とにより、フレームメモリに蓄積されていた画像に対応
した表示パネル１０９の有機ＥＬ素子の発光を制御して
所望の画像表示が得られる。電源回路１０７は、表示パ
ネル１０９の全有機ＥＬ素子への電源を供給する。The digital video signal data stored in the frame memory 103 is read by the controller 104 and sent to the write circuit 106. In addition, by sequentially controlling the writing circuit 106 and the scanning circuit 105 connected to each row and column of the display panel by the controller 104, light emission of the organic EL element of the display panel 109 corresponding to the image stored in the frame memory is achieved. By controlling, a desired image display is obtained. The power supply circuit 107 supplies power to all the organic EL elements of the display panel 109.
【００１４】有機ＥＬ表示装置はこのように構成される
が、この有機ＥＬ表示装置を用いて上述したような単純
マトリクス駆動等の線順次駆動を行なうと、配線抵抗の
増加や瞬時輝度の確保のために消費電力が増加するとい
う問題がある。このため、有機ＥＬ表示装置では、各画
素に対応する有機ＥＬ素子をアクティブマトリクス駆動
により発光制御することが望ましい。The organic EL display device is configured as described above. When line sequential driving such as simple matrix driving as described above is performed using the organic EL display device, it is necessary to increase the wiring resistance and to secure the instantaneous luminance. Therefore, there is a problem that power consumption increases. Therefore, in the organic EL display device, it is desirable to control the light emission of the organic EL element corresponding to each pixel by active matrix driving.
【００１５】一方、有機ＥＬ素子は、発光を持続するメ
モリ性を有しないため、有機ＥＬ表示装置では、ＦＥＴ
等のＴＦＴ（薄膜トランジスタ）を用いてメモリ性をも
たせるように回路構成して各画素の駆動時における発光
を維持している。On the other hand, since the organic EL element does not have a memory property for sustaining light emission, an organic EL display device uses a FET.
A circuit is configured to have a memory property by using a TFT (thin film transistor) such as the above, and light emission during driving of each pixel is maintained.
【００１６】図９は、上記アクティブマトリクス駆動に
よる発光制御を行うための表示パネルの単位画素に対応
する回路構成の一例を示した図である。同図において、
ＦＥＴ（Field Effect Transistor）２０１（アドレス
選択用トランジスタ）のゲートＧは、走査回路１０５か
らの行を走査する走査信号が供給されるアドレス走査電
極線を形成し、一方ＦＥＴ２０１のソースＳは、書き込
み回路１０６からのフレームメモリ１０３のデータに対
応した信号が供給されるデータ電極線を形成している。FIG. 9 is a diagram showing an example of a circuit configuration corresponding to a unit pixel of a display panel for performing light emission control by the active matrix drive. In the figure,
The gate G of an FET (Field Effect Transistor) 201 (address selection transistor) forms an address scanning electrode line to which a scanning signal for scanning a row from the scanning circuit 105 is supplied, while the source S of the FET 201 is a writing circuit. A data electrode line to which a signal corresponding to the data of the frame memory 103 from 106 is supplied.
【００１７】ＦＥＴ２０１のドレインＤはＦＥＴ２０２
（ドライブ用トランジスタ）のゲートＧに接続され、キ
ャパシタ（コンデンサ）２０３を通じて接地されてい
る。ＦＥＴ２０２のソースＳは接地され、ドレインＤは
有機ＥＬ素子２０５の陰極に接続され、有機ＥＬ素子２
０５の陽極を通じて電源に接続されている。なお、各画
素の有機ＥＬ素子２０５が有する陽極は共通電極を形成
し、この共通電極が上述した電源に接続されている。The drain D of the FET 201 is
(Drive transistor), and is grounded through a capacitor (capacitor) 203. The source S of the FET 202 is grounded, the drain D is connected to the cathode of the organic EL element 205, and the organic EL element 2
It is connected to a power supply through the anode 05. The anode of the organic EL element 205 of each pixel forms a common electrode, and this common electrode is connected to the above-described power supply.
【００１８】次に、このような回路が行及び列に複数配
列して構成された表示パネルの単位画素の発光制御動作
について述べる。先ず、図９においてＦＥＴ２０１のゲ
ートＧにオン電圧が供給されると、ＦＥＴ２０１はソー
スＳに供給されるデータの電圧に対応した電流をソース
ＳからドレインＤへ流す。Next, a description will be given of the light emission control operation of a unit pixel of a display panel in which a plurality of such circuits are arranged in rows and columns. First, in FIG. 9, when an ON voltage is supplied to the gate G of the FET 201, the FET 201 causes a current corresponding to the voltage of the data supplied to the source S to flow from the source S to the drain D.
【００１９】ＦＥＴ２０１のゲートＧがオフ電圧である
とＦＥＴ２０１はいわゆるカットオフとなり、ＦＥＴ２
０１のドレインＤはオープン状態となる。従って、ＦＥ
Ｔ２０１のゲートＧがオン電圧の期間に、ソースＳの電
圧に基づいた電流でキャパシタ２０３が充電され、その
電圧がＦＥＴ２０２のゲートＧに供給されてＦＥＴ２０
２はそのゲート電圧と電源から有機ＥＬ素子２０５を通
じて供給されるドレインＤにかかる電圧に基づいた電流
が有機ＥＬ素子２０５を通じてドレインＤからソースＳ
へ流れ、有機ＥＬ素子２０５を発光せしめる。When the gate G of the FET 201 is at an off-voltage, the FET 201 is cut off,
01 is in the open state. Therefore, FE
During the period when the gate G of T201 is on voltage, the capacitor 203 is charged with a current based on the voltage of the source S, and the voltage is supplied to the gate G of the FET 202 and
2, a current based on the gate voltage and a voltage applied to the drain D supplied from the power supply through the organic EL element 205 is supplied from the drain D to the source S through the organic EL element 205.
To make the organic EL element 205 emit light.
【００２０】ＦＥＴ２０１のゲートＧがオフ電圧になる
と、ＦＥＴ２０１はオープン状態となり、ＦＥＴ２０２
はキャパシタ２０３に蓄積された電荷によりゲートＧの
電圧が保持され、次の走査まで電流を維持し、有機ＥＬ
素子２０５の発光も維持される。When the gate G of the FET 201 is turned off, the FET 201 is opened and the FET 202
Indicates that the voltage of the gate G is held by the charge accumulated in the capacitor 203, the current is maintained until the next scan,
Light emission of the element 205 is also maintained.
【００２１】なお、ＦＥＴ２０２のゲートＧとソースＳ
間にはゲート入力容量が存在するので、キャパシタ２０
３を省略しても上記と同様の動作が可能である。The gate G and the source S of the FET 202
Since there is a gate input capacitance between them, the capacitor 20
Even if 3 is omitted, the same operation as above can be performed.
【００２２】アクティブマトリクス駆動による発光制御
を行うための表示パネルの単位画素に対応する回路はこ
のように構成され、画素が駆動された場合に当該画素の
発光が維持される。また、各画素の輝度階調は、ゲート
Ｇにかかる電圧の振幅変調によって行われる。即ち、Ｆ
ＥＴ２０２は、ゲートＧにかかる電圧によってソースＳ
・ドレインＤを流れる電流量が変化するため、有機ＥＬ
表示装置の各部が、供給される映像信号に応じて、ゲー
トＧにかかる電圧の大きさを調整することにより、有機
ＥＬ素子２０５に流れる電流量つまり素子の瞬時輝度を
調整することができる。A circuit corresponding to a unit pixel of a display panel for performing light emission control by active matrix driving is configured as described above, and when the pixel is driven, the light emission of the pixel is maintained. The luminance gradation of each pixel is performed by amplitude modulation of a voltage applied to the gate G. That is, F
The ET 202 is connected to the source S by a voltage applied to the gate G.
-Since the amount of current flowing through the drain D changes, the organic EL
Each unit of the display device adjusts the magnitude of the voltage applied to the gate G according to the supplied video signal, so that the amount of current flowing through the organic EL element 205, that is, the instantaneous luminance of the element can be adjusted.
【００２３】[0023]
【発明が解決しようとする課題】ところが、上述したよ
うな振幅変調によって輝度階調を行う表示パネルにおい
ては、ゲートＧにかかる電圧値とソースＳ・ドレインＤ
間を流れる電流値が非線形の関係にあるため、所望の瞬
時輝度を得るための輝度調整が難しいという問題があ
る。However, in a display panel that performs luminance gradation by amplitude modulation as described above, the voltage applied to the gate G and the source S / drain D
There is a problem that it is difficult to adjust the brightness to obtain a desired instantaneous brightness because the current value flowing between them has a non-linear relationship.
【００２４】つまり、ゲートＧにかかる電圧値を２倍に
しても、ソースＳ・ドレインＤ間を流れる電流値は２倍
にはならない（即ち、素子の瞬時輝度は２倍にならな
い）関係にあるため、所望の瞬時輝度を得るためには、
トランジスタの電圧−電流特性を把握した上で、ゲート
Ｇにかかる電圧値を高精度で制御する必要があった。That is, even if the voltage value applied to the gate G is doubled, the current value flowing between the source S and the drain D is not doubled (that is, the instantaneous luminance of the element is not doubled). Therefore, in order to obtain a desired instantaneous luminance,
It is necessary to control the voltage value applied to the gate G with high accuracy after grasping the voltage-current characteristics of the transistor.
【００２５】本発明は上述の問題点に鑑みなされたもの
であり、簡単な構造で容易にしかも映像信号に応じて正
確に輝度階調の表現（表示制御）を行なうことができる
画像表示装置を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and has an image display apparatus capable of easily expressing a luminance gradation (display control) easily and accurately according to a video signal with a simple structure. The purpose is to provide.
【００２６】[0026]
【課題を解決するための手段】請求項１記載の発明は、
複数の画素がマトリクス状に配列されるＥＬ素子を用い
た画像表示装置であって、画素の各々は、駆動電極から
の駆動電流が供給されるＥＬ素子と、ＥＬ素子に直列に
接続され、ゲートに電荷が保持される場合にＥＬ素子を
通電可能とするドライブ用トランジスタと、ＥＬ素子の
発光するか否かを決定すると共に発光する場合はトラン
ジスタのゲートに電荷を供給する発光決定手段とを備え
て構成され、全ての画素の発光又は非発光を決定するア
ドレス期間においては駆動電極からの電流が全ての画素
に供給されないようにすると共に、アドレス期間終了後
には駆動電極からの電流を画素に供給させるようにした
ことを特徴とする。According to the first aspect of the present invention,
An image display device using an EL element in which a plurality of pixels are arranged in a matrix, wherein each of the pixels is connected in series to the EL element to which a driving current is supplied from a driving electrode, and a gate. A drive transistor that enables the EL element to conduct when the electric charge is held therein, and light emission determining means that determines whether the EL element emits light and supplies the charge to the gate of the transistor when the EL element emits light. In the address period for determining light emission or non-light emission of all pixels, current from the drive electrodes is not supplied to all pixels, and after the address period, current from the drive electrodes is supplied to the pixels. It is characterized in that it is made to be.
【００２７】また、請求項２記載の発明は、複数の画素
がマトリクス状に配列されるＥＬ素子を用いた画像表示
装置であって、画素の各々は、駆動電極からの駆動電流
が供給されるＥＬ素子と、ＥＬ素子に直列に接続され、
ゲートに電荷が保持される場合にＥＬ素子を通電可能と
するドライブ用トランジスタと、ＥＬ素子の発光するか
否かを決定すると共に発光する場合はトランジスタのゲ
ートに電荷を供給する発光決定手段と、全ての画素の発
光又は非発光を決定するアドレス期間においては駆動電
極からの電流が全ての画素に供給されないようにすると
共に、アドレス期間終了後には駆動電極からの電流を画
素に供給させるスイッチ手段とから構成されることを特
徴とする。According to a second aspect of the present invention, there is provided an image display device using an EL element in which a plurality of pixels are arranged in a matrix, wherein each of the pixels is supplied with a drive current from a drive electrode. An EL element, connected in series to the EL element,
A drive transistor that enables the EL element to conduct when a charge is held in the gate; and a light emission determination unit that determines whether the EL element emits light and supplies the charge to the gate of the transistor when the EL element emits light. Switch means for preventing current from the drive electrode from being supplied to all pixels during an address period for determining light emission or non-light emission of all pixels, and for supplying current from the drive electrode to pixels after the end of the address period; Characterized by the following.
【００２８】また、請求項３記載の発明は、請求項１又
は２に記載の画像表示装置において、画素の全てにおい
て、発光決定手段がドライブ用のトランジスタのゲート
に供給する電位は同一電位であることを特徴とする。According to a third aspect of the present invention, in the image display device of the first or second aspect, in all of the pixels, the potential supplied to the gate of the driving transistor by the light emission determining means is the same. It is characterized by the following.
【００２９】また、請求項４記載の発明は、請求項１乃
至３に記載の画像表示装置において、発光決定手段は、
アドレス選択用のトランジスタからなるものであり、そ
のソースがデータ電極線に接続され、ゲートがアドレス
データ電極線に接続され、ドレインがドライブ用のトラ
ンジスタに接続されることを特徴とする。According to a fourth aspect of the present invention, in the image display device according to the first to third aspects, the light emission determining means includes:
It comprises a transistor for address selection, characterized in that the source is connected to the data electrode line, the gate is connected to the address data electrode line, and the drain is connected to the drive transistor.
【００３０】また、請求項５記載の発明は、請求項１乃
至４に記載の画像表示装置において、ドライブ用のトラ
ンジスタのゲートには電荷保持用のコンデンサが接続さ
れていることを特徴とする。According to a fifth aspect of the present invention, in the image display device of the first to fourth aspects, a charge holding capacitor is connected to a gate of the driving transistor.
【００３１】また、請求項６記載の発明は、請求項１乃
至５に記載の画像表示装置において、スイッチ手段は、
駆動電極とドライブ用のトランジスタの間に設けられる
ものであることを特徴とする。According to a sixth aspect of the present invention, in the image display device according to the first to fifth aspects, the switch means comprises:
It is provided between a drive electrode and a drive transistor.
【００３２】また、請求項７記載の発明は、請求項１乃
至６に記載の画像表示装置において、画像表示装置は、
サブフィールド２n 階調法による輝度階調を表現するこ
とを特徴とする。According to a seventh aspect of the present invention, in the image display device according to the first to sixth aspects, the image display device comprises:
It is characterized in that a luminance gradation is expressed by a subfield 2 n gradation method.
【００３３】また、請求項８記載の発明は、請求項１乃
至７に記載の画像表示装置において、ＥＬ素子は、有機
化合物からなる発光層を有することを特徴とする。According to an eighth aspect of the present invention, in the image display device according to the first to seventh aspects, the EL element has a light emitting layer made of an organic compound.
【００３４】[0034]
【作用】本発明は以上のように構成したので、発光表示
装置は、複数の画素がマトリクス状に配列される各ＥＬ
素子に直列に接続された各トランジスタのゲートに電荷
が保持される場合に、各ＥＬ素子に電流が流れるように
制御し、ＥＬ素子を発光させる場合は、発光決定手段
が、対応するトランジスタのゲートに電荷を供給し、複
数の画素の全ての発光又は非発光を決定するアドレス期
間においては、駆動電極と複数の画素との全ての接続を
断とすると共に、アドレス期間終了後に駆動電極と複数
の画素とを接続するアクティブマトリクス駆動制御を行
なうようにしたので、各画素においてＥＬ素子の瞬時輝
度をそれぞれ一定にできると共に、２n サブフィールド
法等の発光時間の長さに基づいた輝度調整が可能である
ため、輝度階調の表示を正確に行うことができる。Since the present invention is constructed as described above, the light-emitting display device comprises an EL device in which a plurality of pixels are arranged in a matrix.
When charge is held at the gate of each transistor connected in series with the element, control is performed so that current flows through each EL element, and when the EL element emits light, the light emission determining means determines the gate of the corresponding transistor. During the address period in which all the pixels emit light or no light is emitted, all the connections between the drive electrode and the plurality of pixels are cut off, and after the end of the address period, the drive electrode and the plurality of pixels are turned off. Active matrix drive control for connecting the pixels is performed, so that the instantaneous luminance of the EL element can be kept constant in each pixel, and the luminance can be adjusted based on the length of light emission time, such as the 2 n subfield method. Therefore, it is possible to accurately display the luminance gradation.
【００３５】[0035]
【発明の実施の形態】次に、本発明に好適な実施形態に
ついて図面をもとに説明する。本実施形態における発光
表示装置は、表示パネルの各画素に有機ＥＬ素子を用い
るものとし、各画素は、２n サブフィールド法に基く発
光制御により輝度階調されるものとする。図１は、本発
明における有機ＥＬ表示装置の主要構成を示すブロック
図である。同図において、１はＡ／Ｄ変換器、２は列ア
ドレスカウンタ、３は行アドレスカウンタ、４はフレー
ムメモリ、５はマルチプレクサ、６はコントローラ、７
は行ドライバ、８は列ドライバ、９は表示パネルを示
す。Next, a preferred embodiment of the present invention will be described with reference to the drawings. The light emitting display device according to the present embodiment uses an organic EL element for each pixel of the display panel, and each pixel is subjected to luminance gradation by light emission control based on the 2 n subfield method. FIG. 1 is a block diagram showing a main configuration of an organic EL display device according to the present invention. In the figure, 1 is an A / D converter, 2 is a column address counter, 3 is a row address counter, 4 is a frame memory, 5 is a multiplexer, 6 is a controller, 7
Indicates a row driver, 8 indicates a column driver, and 9 indicates a display panel.
【００３６】Ａ／Ｄ変換回路１は、アナログ映像信号入
力を受けてデジタル映像信号データに変換する。変換さ
れたデジタル映像信号はＡ／Ｄ変換回路１からフレーム
メモリ４へ供給され１フレーム単位のデジタル映像信号
データが一旦フレームメモリ４に記憶される。The A / D conversion circuit 1 receives an analog video signal input and converts it into digital video signal data. The converted digital video signal is supplied from the A / D conversion circuit 1 to the frame memory 4, and the digital video signal data of one frame unit is temporarily stored in the frame memory 4.
【００３７】一方、コントローラ６は、相異なる発光時
間をパラメータとする複数（ここでは８つ）のサブフィ
ールドによって、上記フレームメモリ４に記憶されたデ
ジタル映像信号データを、列アドレスカウンタ２及び行
アドレスカウンタ３を用いて制御することにより、複数
（ここでは８つ）の階調表示データに変換し、それぞれ
表示パネル９の画素のアドレスに対応する発光・非発光
データと共に順次マルチプレクサ５に供給する。On the other hand, the controller 6 converts the digital video signal data stored in the frame memory 4 into the column address counter 2 and the row address by using a plurality (eight in this case) of subfields having different light emission times as parameters. By controlling using the counter 3, the data is converted into a plurality (eight in this case) of gray-scale display data, and the gray-scale display data is sequentially supplied to the multiplexer 5 together with the emission / non-emission data corresponding to the pixel address of the display panel 9.
【００３８】また、コントローラ６は、マルチプレクサ
５に供給された発光・非発光データの中から各サブフィ
ールドに対応する列データを第１行目から順次画素の配
列順にドライバ８が有するデータラッチ回路に保持させ
るように制御する。The controller 6 converts the column data corresponding to each subfield from the light emission / non-light emission data supplied to the multiplexer 5 to the data latch circuit of the driver 8 sequentially from the first row in the pixel arrangement order. Control to keep it.
【００３９】コントローラ６は、データラッチ回路によ
って順次保持された各サブフィールド毎の列データを、
１行単位で表示パネル９に供給すると共に、行ドライバ
７によって対応する行が有する画素列において同時に発
光させる。この動作は、１フレームのデータ単位で、第
１サブフィールドから第８サブフィールドまでのそれぞ
れの列データに関して行われる（ここでは８回行われ
る）ので、表示パネル９の各画素は、供給される各サブ
フィールドに対応する累積発光時間だけ発光し、１フレ
ーム分の発光表示を階調表示によって行うことができ
る。The controller 6 converts the column data for each subfield sequentially held by the data latch circuit into
The light is supplied to the display panel 9 in units of one row, and the row driver 7 simultaneously emits light in the pixel columns of the corresponding row. Since this operation is performed for each column data from the first subfield to the eighth subfield in one frame data unit (here, eight times), each pixel of the display panel 9 is supplied. Light emission is performed for the accumulated light emission time corresponding to each subfield, and light emission display for one frame can be performed by gradation display.
【００４０】なお、本実施形態に用いられる８つのサブ
フィールド（第１サブフィールド〜第８サブフィール
ド）のデータは、所定の高さを有するパルスデータのパ
ルス幅を２n サブフィールド法に基く８種類の幅に設定
している。即ち、第１サブフィールドから第８サブフィ
ールドまでのデータが有するパルス幅の比率を第１サブ
フィールドから順に、それぞれ１／２、１／４、１／
８、１／１６、１／３２、１／６４、１／２５６、と設
定することで、２５６通りの輝度階調表示に対応させて
いる。The data of the eight sub-fields (first sub-field to eighth sub-field) used in the present embodiment is obtained by dividing the pulse width of pulse data having a predetermined height by 8 n based on the 2 n sub-field method. The width is set to the type. That is, the ratio of the pulse width of the data from the first subfield to the eighth subfield is を, ４, and 1/1, respectively, in order from the first subfield.
By setting 8, 1/16, 1/32, 1/64, and 1/256, 256 brightness gradation displays are supported.
【００４１】本発明における有機ＥＬ表示装置は、この
ように構成され、入力されるアナログ映像信号に対し、
各サブフィールド毎に表示パネルの画面全体のアドレス
走査による全面同時発光を繰り返すことにより、フレー
ム単位の発光表示を階調表示によって行う。The organic EL display device according to the present invention is configured as described above, and operates in response to an input analog video signal.
By repeating the simultaneous light emission of the entire surface of the display panel by address scanning for each subfield, light emission display in frame units is performed by gradation display.
【００４２】次に、表示パネル９が有する１画素周辺の
構成について説明する。図２は、図１における表示パネ
ル９の１画素に対応する回路構成の一例を示した図であ
る。また、図２に示す回路構成は、先に述べた図９に示
す各回路構成に加えて切替スイッチ１０を有機ＥＬ素子
２０５の陽極側に設けて、電源Ｖｏｃとアース端子との
切替接続が可能なように構成される。Next, the configuration around one pixel of the display panel 9 will be described. FIG. 2 is a diagram showing an example of a circuit configuration corresponding to one pixel of the display panel 9 in FIG. In addition, the circuit configuration shown in FIG. 2 has a changeover switch 10 provided on the anode side of the organic EL element 205 in addition to the circuit configurations shown in FIG. It is configured as follows.
【００４３】また、有機ＥＬ素子２０５は表示パネル９
の各画素に対応して複数設けられているが、図２に示す
ように、各画素に対応する有機ＥＬ素子２０５の陽極
は、互いに電気的に接続された共通電極を構成してい
る。表示パネル９の１画素に対応する回路は以上のよう
に構成され、このような回路が行及び列に対応して複数
配列して表示パネル９を構成する。The organic EL element 205 is connected to the display panel 9
2, the anodes of the organic EL elements 205 corresponding to the respective pixels constitute a common electrode electrically connected to each other. The circuit corresponding to one pixel of the display panel 9 is configured as described above, and the display panel 9 is configured by arranging a plurality of such circuits corresponding to rows and columns.
【００４４】次に、コントローラ６が、フレームメモリ
４に記憶されたデジタル映像信号データに基づいて表示
パネル９を階調表示による発光制御動作について詳述す
る。先ず、コントローラ６は、デジタル映像信号データ
がフレームメモリ４に供給されると、１フレーム分のデ
ジタル映像信号データをフレームメモリ４に書き込む。Next, an operation of the controller 6 for controlling the light emission of the display panel 9 by gradation display based on the digital video signal data stored in the frame memory 4 will be described in detail. First, when the digital video signal data is supplied to the frame memory 4, the controller 6 writes the digital video signal data for one frame into the frame memory 4.
【００４５】次に、コントローラ６は、マルチプレクサ
５に対し第１サブフィールド（１／２）のデータを出力
する旨の指令を出す。次に、コントローラ６は、行アド
レスカウンタ３に対して第１行を指定する旨の指令を出
すと共に、列アドレスカウンタ２に対して第１列を指定
する旨の指令を出す。Next, the controller 6 issues a command to the multiplexer 5 to output the data of the first subfield (1/2). Next, the controller 6 issues a command to the row address counter 3 to designate the first row, and issues a command to the column address counter 2 to designate the first column.
【００４６】このことにより、指定されたアドレス（第
１行、第１列）の１フレーム分のデジタル映像信号デー
タが８つの階調表示データに変換され、表示パネル９の
画素のアドレスに対応する発光・非発光データを含んだ
データとして順次マルチプレクサ５に供給される。As a result, the digital video signal data for one frame at the designated address (first row, first column) is converted into eight gradation display data, which corresponds to the pixel address of the display panel 9. The data is sequentially supplied to the multiplexer 5 as data including light emission / non-light emission data.
【００４７】次に、コントローラ６は、マルチプレクサ
５に供給された上記指定されたアドレス（第１行、第１
列）のデータの中から第１サブフィールドのデータを列
ドライバ８に出力する。列ドライバ８では、列ドライバ
８が有するデータラッチ回路によってこのデータを保持
する。Next, the controller 6 sends the specified address (first row, first row) supplied to the multiplexer 5.
The data of the first subfield is output to the column driver 8 from the data of the column. In the column driver 8, the data is held by a data latch circuit of the column driver 8.
【００４８】次に、コントローラ６は、列アドレスカウ
ンタ２に対して列を１つ更新する指令を出す。即ち、列
アドレスカウンタ２に対して第２列を指定する旨の指令
を出す。このことにより、アドレス（第１行、第２列）
が指定され、先に述べたアドレス（第１行、第１列）が
指定された場合と同様の動作を繰り返す。Next, the controller 6 issues a command to the column address counter 2 to update one column. That is, a command is issued to the column address counter 2 to designate the second column. This allows the address (first row, second column)
Is specified, and the same operation as when the address (first row, first column) described above is specified is repeated.
【００４９】このようにして、コントローラ６は、第１
行の各列に対し順次同様の動作を繰り返すことにより、
第１行の全ての列のデータを列ドライバ８が有するデー
タラッチ回路の保持させる。In this way, the controller 6
By repeating the same operation sequentially for each column of the row,
Data of all columns in the first row is held in a data latch circuit included in the column driver 8.
【００５０】次に、コントローラ６は、行アドレスカウ
ンタ３を第２行に指定する旨の指令を出すと共に、列ア
ドレスカウンタ２を第１列に指定する旨の指令を出して
先に述べた第１行の場合と同様に第２行のデータラッチ
を行うように制御する。Next, the controller 6 issues a command to designate the row address counter 3 to the second row, and issues a command to designate the column address counter 2 to the first column. Control is performed so that data latching of the second row is performed as in the case of one row.
【００５１】またこの動作と同時に、コントローラ６
は、列ドライバ８及び行ドライバ７を駆動して、各画素
に設けられた回路（図２参照）を後述する手順により動
作させ、既に列ドライバ８のデータラッチ回路に保持さ
れている第１行のデータをそれぞれ対応する各列の画素
に書き込ませる。At the same time as this operation, the controller 6
Drives the column driver 8 and the row driver 7 to operate the circuit (see FIG. 2) provided for each pixel according to a procedure described later, and the first row already held in the data latch circuit of the column driver 8 Is written to the pixels of each corresponding column.
【００５２】次に、コントローラ６は、行アドレスカウ
ンタ３を第３行に指定する旨の指令を出すと共に、列ア
ドレスカウンタ２を第１列に指定する旨の指令を出して
先に述べた第１行及び第２行の場合と同様に第３行のデ
ータラッチを行うように制御する。Next, the controller 6 issues a command to designate the row address counter 3 to the third row, and issues a command to designate the column address counter 2 to the first column. Control is performed so that the data latch of the third row is performed as in the case of the first row and the second row.
【００５３】またこの動作と同時に、コントローラ６
は、列ドライバ８及び行ドライバ７を駆動して、後述す
る手法により、既に列ドライバ８のデータラッチ回路に
保持されている第２行のデータをそれぞれ対応する各列
の画素に書き込ませる。At the same time as this operation, the controller 6
Drives the column driver 8 and the row driver 7 to cause the data of the second row already held in the data latch circuit of the column driver 8 to be written to the corresponding pixel of each column by the method described later.
【００５４】コントローラ６は、このような動作を全て
の行に亘って行うことにより、第１サブフィールドのデ
ータを全ての画素に対応して書き込むことができる。次
に、コントローラ６は、各画素の共通電極である有機Ｅ
Ｌ素子２０５の陽極側に接続される切替スイッチ１０を
電源Ｖｏｃ側に切替えて表示パネル９の全部の画素を一
斉に発光制御する。このことにより、表示パネル９は、
第１サブフィールドのデータに対応した発光がなされ
る。By performing such an operation over all rows, the controller 6 can write the data of the first subfield corresponding to all the pixels. Next, the controller 6 controls the organic E which is a common electrode of each pixel.
By switching the changeover switch 10 connected to the anode side of the L element 205 to the power supply Voc side, all pixels of the display panel 9 are simultaneously controlled to emit light. As a result, the display panel 9
Light emission corresponding to the data of the first subfield is performed.
【００５５】次に、マルチプレクサ５に対し第２サブフ
ィールド（１／４）のデータを出力する旨の指令を出
す。以下、コントローラ６は、先に述べた第１サブフィ
ールドの場合と同様の動作を繰り返し、第２サブフィー
ルドのデータに対応した発光がなされる。Next, the multiplexer 5 is instructed to output the data of the second subfield (1/4). Thereafter, the controller 6 repeats the same operation as in the case of the above-described first subfield, and emits light corresponding to the data of the second subfield.
【００５６】このようにして、第１サブフィールドから
第８サブフィールド（１／２５６）までに対応した発光
がなされ、第８サブフィールドの発光が終了した時点で
１フレームの駆動が完了する。その後、コントローラ６
は、フレームメモリ４に記憶されるデータを次のフレー
ムに対応するデータに書き替えて、次のフレームの発光
制御を行う。In this way, light emission corresponding to the first to eighth subfields (1/256) is performed, and driving of one frame is completed when the light emission of the eighth subfield is completed. After that, the controller 6
Rewrites data stored in the frame memory 4 with data corresponding to the next frame, and performs light emission control of the next frame.
【００５７】次に、コントローラ６が、列ドライバ８及
び行ドライバ７を駆動して、各画素に第１サブフィール
ドから第８サブフィールドまでの各データを順次書き込
んで発光させるために、各画素に設けられた回路（図２
参照）を駆動させる動作手順を説明する。Next, the controller 6 drives the column driver 8 and the row driver 7 to sequentially write each data from the first subfield to the eighth subfield to each pixel to emit light. The provided circuit (Fig. 2
Will be described.
【００５８】図２において、コントローラ６は、切替ス
イッチ１０をアース端子側に切替えて、各画素に対応す
る有機ＥＬ素子２０５の陽極側である共通電極を接地さ
せて、各有機ＥＬ素子２０５が発光しないようにする。In FIG. 2, the controller 6 switches the changeover switch 10 to the ground terminal side, grounds the common electrode on the anode side of the organic EL element 205 corresponding to each pixel, and causes each organic EL element 205 to emit light. Don't do it.
【００５９】次に、コントローラ６は、全ての画素の発
光又は非発光を決定するアドレス期間の第１行に対応す
る所定期間内において、先ず行ドライバ７によって第１
行のアドレス走査電極線を走査し、次に列ドライバ８の
データラッチ回路に保持された第１サブフィールドのデ
ータをデータ電極線を通じて第１行の各列の画素に対応
して入力する。Next, during a predetermined period corresponding to the first row of the address period for determining light emission or non-light emission of all the pixels, the controller 6 first controls the row driver 7 for the first row.
The address scanning electrode lines in the row are scanned, and then the data of the first subfield held in the data latch circuit of the column driver 8 is input through the data electrode lines corresponding to the pixels in each column of the first row.
【００６０】ここで、アドレス走査電極線は走査が行わ
れていない場合には、Ｌの期間となり前回のＯＮ、ＯＦ
Ｆの状態を保持しているが、走査が行われる場合には、
アドレス走査電極線がＨの期間となり、データ電極線に
入力されるデータに応じて電荷がキャパシタ２０３に溜
まり、電圧Ｖが保持される。Here, when scanning is not performed on the address scanning electrode line, the period becomes L and the previous ON, OF
Although the state of F is maintained, when scanning is performed,
The period of the address scanning electrode line becomes H, and charges accumulate in the capacitor 203 according to data input to the data electrode line, and the voltage V is held.
【００６１】従って、第１行のアドレス走査電極線が走
査され、データが入力された場合には、第１行の各列に
対応する各キャパシタ２０３は、入力されるデータの電
位に応じた電荷が溜まることになる。なお、データ電極
線の電位が０Ｖ（接地）の場合には、キャパシタ２０３
には電荷が溜まらず、対応する画素はＯＦＦとなる。Accordingly, when the address scanning electrode lines of the first row are scanned and data is input, each capacitor 203 corresponding to each column of the first row charges the electric charge corresponding to the potential of the input data. Will accumulate. When the potential of the data electrode line is 0 V (ground), the capacitor 203
Does not accumulate charge, and the corresponding pixel is turned off.
【００６２】このことにより、列ドライバ８のデータラ
ッチ回路に保持された第１サブフィールドのデータがデ
ータ電極線を通じて第１行の各列の画素に対応して入力
される。このデータにより、発光させるべき画素に対し
ては対応するＦＥＴ２０１のゲートＧにオン電圧が加わ
り、発光させない画素に対しては対応するＦＥＴ２０１
のゲートＧにオフ電圧が加わる。As a result, the data of the first sub-field held in the data latch circuit of the column driver 8 is inputted to the pixels of each column of the first row through the data electrode lines. With this data, an ON voltage is applied to the gate G of the corresponding FET 201 for a pixel to emit light, and the corresponding FET 201 is applied to a pixel not to emit light.
The off-voltage is applied to the gate G of.
【００６３】次に、コントローラ６は、第２行の走査を
行い、上述した第１行の場合と同様に第２行の各列に対
応する画素に対する第１サブフィールドのデータをデー
タ電極線を通じて入力する。このようにして、コントロ
ーラ６が全行についての走査が終了すると、発光させる
べき画素に対しては、そのＦＥＴ２０２に直列に接続さ
れたキャパシタ２０３に電荷が溜まり、ＦＥＴ２０２の
ゲート電位がＶとなる。また、発光しない画素に対して
は、ＦＥＴ２０２のゲート電位が０となる。Next, the controller 6 scans the second row, and in the same manner as in the case of the first row described above, data of the first subfield for the pixel corresponding to each column of the second row is passed through the data electrode line. input. In this manner, when the controller 6 completes scanning of all rows, charges are accumulated in the capacitor 203 connected in series to the FET 202 for a pixel to emit light, and the gate potential of the FET 202 becomes V. Further, the gate potential of the FET 202 becomes 0 for a pixel that does not emit light.
【００６４】この状態で、コントローラ６は、切替スイ
ッチ１０を電源Ｖｏｃ側に切替えることにより、各画素
の有機ＥＬ素子２０５に共通な陽極である共通電極に、
電圧（Ｖｏｃ）を第１サブフィールドのデータに対応す
る時間だけ印加する。このことにより、各画素の有機Ｅ
Ｌ素子２０５には一斉に電圧（Ｖｏｃ）が加わることと
なるが、この場合に、ＦＥＴ２０２のゲート電位がＶと
なる有機ＥＬ素子には、第１サブフィールドのデータに
対応する時間だけ電流が流れて発光するが、ＦＥＴ２０
２のゲート電位が０となる有機ＥＬ素子には、電流が流
れず、従って発光しない。In this state, the controller 6 switches the changeover switch 10 to the power supply Voc side so that the common electrode, which is the anode common to the organic EL element 205 of each pixel,
The voltage (Voc) is applied for a time corresponding to the data of the first subfield. This allows the organic E of each pixel to be
A voltage (Voc) is applied to the L element 205 all at once. In this case, a current flows through the organic EL element in which the gate potential of the FET 202 becomes V for a time corresponding to the data of the first subfield. Emits light, but FET20
No current flows through the organic EL element in which the gate potential of No. 2 becomes 0, and thus no light is emitted.
【００６５】次に、コントローラ６は、アドレス期間の
第２行に対応する所定期間内において、上述した第１行
に対応する所定期間内における制御動作と同様、各行各
列の画素に対し、第２サブフィールドのデータに対応し
た発光制御を行う。Next, in the predetermined period corresponding to the second row of the address period, the controller 6 controls the pixels in each row and each column in the same manner as the control operation in the predetermined period corresponding to the first row described above. Light emission control corresponding to data of two subfields is performed.
【００６６】図３は、コントローラ６が上記各サブフィ
ールド毎に行う発光制御のタイミングを示す図である。FIG. 3 is a diagram showing the timing of light emission control performed by the controller 6 for each subfield.
【００６７】このようにして、コントローラ６は、各行
各列の画素に対し、１つのアドレス期間終了から次のア
ドレス期間開始までの発光期間において、順次第１サブ
フィールドのデータから第８サブフィールドのデータま
でに対応して発光を繰り返すように制御することによ
り、図４に示すように、デジタル映像信号データの１フ
レーム毎に、各画素を２５６通りの累積発光時間でそれ
ぞれ発光させることができ、表示パネル９を２５６通り
の輝度階調表示によって発光させる。As described above, the controller 6 sequentially changes the data of the first subfield to the data of the eighth subfield during the light emission period from the end of one address period to the start of the next address period for the pixels in each row and each column. By controlling the light emission to be repeated corresponding to the data, as shown in FIG. 4, for each frame of the digital video signal data, each pixel can emit light with 256 kinds of cumulative light emission times, The display panel 9 emits light by 256 kinds of luminance gradation display.
【００６８】なお、本実施形態においては、各画素に対
応するＦＥＴ２０２のゲートに直列に電荷保持用のキャ
パシタ２０３を設けるようにしたが、ＦＥＴ２０２自体
が容量性を有するのでＦＥＴ２０２に電荷を保持させる
ようにしても良い。In this embodiment, the charge holding capacitor 203 is provided in series with the gate of the FET 202 corresponding to each pixel. However, since the FET 202 itself has a capacity, the FET 202 holds the charge. You may do it.
【００６９】また、切替スイッチ１０は、ＦＥＴ２０２
のドレイン側に設けてもよく、この場合、切替スイッチ
１０は、電源Ｖｏｃと同電位の端子もしくはアース端子
のいずれか一方に対し接続可能とされるものである。そ
して、アドレス期間のときは切替スイッチ１０を電源Ｖ
ｏｃと同電位の端子に接続し、発光期間のときは切替ス
イッチ１０をアース端子に接続する。また、ＦＥＴ２０
１、２０２は、一般的な３端子トランジスタであれば利
用可能である。The changeover switch 10 is connected to the FET 202
In this case, the changeover switch 10 can be connected to either the terminal having the same potential as the power supply Voc or the ground terminal. In the address period, the changeover switch 10 is set to the power supply V.
The switch is connected to a terminal having the same potential as oc, and the switch 10 is connected to a ground terminal during the light emission period. In addition, FET20
1 and 202 can be used as long as they are general three-terminal transistors.
【００７０】また、本実施形態においては、表示パネル
の発光素子に有機ＥＬ素子を用いて説明したが、発光素
子はこれに限らず、電流を流すことにより自発光を行う
ＥＬ素子であれば良い。In this embodiment, the organic EL element is used as the light emitting element of the display panel. However, the light emitting element is not limited to this, and may be any EL element that emits light by passing a current. .
【００７１】[0071]
【発明の効果】本発明は以上のように構成したため、発
光表示装置は、複数の画素がマトリクス状に配列される
各ＥＬ素子に直列に接続された各トランジスタのゲート
に電荷が保持される場合に、各ＥＬ素子に電流が流れる
ように制御し、ＥＬ素子を発光させる場合は、発光決定
手段が、対応するトランジスタのゲートに電荷を供給
し、複数の画素の全ての発光又は非発光を決定するアド
レス期間においては、駆動電極と複数の画素との全ての
接続を断とすると共に、アドレス期間終了後に駆動電極
と複数の画素とを接続するアクティブマトリクス駆動制
御を行なうようにしたので、各画素においてＥＬ素子の
瞬時輝度をそれぞれ一定にできると共に、２n サブフィ
ールド法等の発光時間の長さに基づいた輝度調整が可能
であるため、輝度階調の表示を正確に行うことができ
る。Since the present invention is constructed as described above, the light-emitting display device has a structure in which a plurality of pixels are arranged in a matrix. In order to control the current to flow through each EL element and cause the EL element to emit light, the light emission determining means supplies a charge to the gate of the corresponding transistor to determine light emission or non-light emission of all pixels. During the address period, all connections between the drive electrode and the plurality of pixels are disconnected, and active matrix drive control for connecting the drive electrode and the plurality of pixels is performed after the end of the address period. since it is possible a constant instantaneous luminance of the EL element, respectively, it is possible brightness adjustment based on the length of the emission time such as 2 n sub-field method in the luminance floor It is possible to perform the display of exactly.
【図１】本発明における有機ＥＬ表示装置の主要構成を
示すブロック図である。FIG. 1 is a block diagram illustrating a main configuration of an organic EL display device according to the present invention.
【図２】図１における表示パネルの１画素に対応する回
路構成の一例を示した図である。FIG. 2 is a diagram showing an example of a circuit configuration corresponding to one pixel of the display panel in FIG.
【図３】コントローラが上記各サブフィールド毎に行う
発光制御のタイミングを示す図である。FIG. 3 is a diagram showing timing of light emission control performed by a controller for each of the subfields.
【図４】デジタル映像信号データの１フレーム期間にお
ける発光タイミングを示す図である。FIG. 4 is a diagram showing light emission timing in one frame period of digital video signal data.
【図５】有機ＥＬ素子の概略構成を示す図である。FIG. 5 is a diagram showing a schematic configuration of an organic EL element.
【図６】有機ＥＬ素子を等価的に表した電気回路図であ
る。FIG. 6 is an electric circuit diagram equivalently showing an organic EL element.
【図７】有機ＥＬ素子の単純マトリクス駆動方式を示す
図である。FIG. 7 is a diagram showing a simple matrix driving method of an organic EL element.
【図８】単純マトリクス駆動方式を用いた有機ＥＬ表示
装置の構成を示すブロック図である。FIG. 8 is a block diagram illustrating a configuration of an organic EL display device using a simple matrix driving method.
【図９】アクティブマトリクス駆動による発光制御を行
うための表示パネルの単位画素に対応する回路構成の一
例を示した図である。FIG. 9 is a diagram illustrating an example of a circuit configuration corresponding to a unit pixel of a display panel for performing light emission control by active matrix driving.
１・・・・・Ａ／Ｄ変換器 ２・・・・・列アドレスカウンタ ３・・・・・行アドレスカウンタ ４・・・・・フレームメモリ ５・・・・・マルチプレクサ ６・・・・・コントローラ ７・・・・・行ドライバ ８・・・・・列ドライバ ９・・・・・表示パネル １０・・・・切替スイッチ ２０１・・・ＦＥＴ ２０２・・・ＦＥＴ ２０３・・・キャパシタ ２０５・・・有機ＥＬ素子 1 ... A / D converter 2 ... Column address counter 3 ... Row address counter 4 ... Frame memory 5 ... Mux 6 ... Controller 7: Row driver 8: Column driver 9: Display panel 10: Changeover switch 201: FET 202: FET 203: Capacitor 205:・ Organic EL device
Claims (8)
ＥＬ素子を用いた画像表示装置であって、 前記画素の各々は、駆動電極からの駆動電流が供給され
るＥＬ素子と、 前記ＥＬ素子に直列に接続され、ゲートに電荷が保持さ
れる場合に前記ＥＬ素子を通電可能とするドライブ用ト
ランジスタと、 前記ＥＬ素子の発光するか否かを決定すると共に発光す
る場合は前記トランジスタのゲートに電荷を供給する発
光決定手段とを備えて構成され、 全ての前記画素の発光又は非発光を決定するアドレス期
間においては前記駆動電極からの電流が全ての前記画素
に供給されないようにすると共に、前記アドレス期間終
了後には前記駆動電極からの電流を前記画素に供給させ
るようにしたことを特徴とする画像表示装置。1. An image display device using an EL element in which a plurality of pixels are arranged in a matrix, wherein each of the pixels includes an EL element to which a driving current is supplied from a driving electrode; And a drive transistor that enables the EL element to conduct when a charge is held in the gate; and determines whether or not the EL element emits light, and determines whether or not the EL element emits light. Light emission determining means for supplying electric charge, and during an address period for determining light emission or non-light emission of all the pixels, current from the drive electrodes is not supplied to all the pixels, and An image display device, wherein a current from the drive electrode is supplied to the pixel after the end of the address period.
ＥＬ素子を用いた画像表示装置であって、 前記画素の各々は、駆動電極からの駆動電流が供給され
るＥＬ素子と、 前記ＥＬ素子に直列に接続され、ゲートに電荷が保持さ
れる場合に前記ＥＬ素子を通電可能とするドライブ用ト
ランジスタと、 前記ＥＬ素子の発光するか否かを決定すると共に発光す
る場合は前記トランジスタのゲートに電荷を供給する発
光決定手段と、 全ての前記画素の発光又は非発光を決定するアドレス期
間においては前記駆動電極からの電流が全ての前記画素
に供給されないようにすると共に、前記アドレス期間終
了後には前記駆動電極からの電流を前記画素に供給させ
るスイッチ手段とから構成されることを特徴とする画像
表示装置。2. An image display device using an EL element in which a plurality of pixels are arranged in a matrix, wherein each of the pixels includes an EL element to which a driving current is supplied from a driving electrode; And a drive transistor that enables the EL element to conduct when a charge is held in the gate; and determines whether or not the EL element emits light, and determines whether or not the EL element emits light. Light emission determining means for supplying electric charge, and in the address period for determining light emission or non-light emission of all the pixels, current from the drive electrodes is not supplied to all the pixels, and after the end of the address period, An image display device comprising: switch means for supplying a current from the drive electrode to the pixel.
手段が前記ドライブ用のトランジスタのゲートに供給す
る電位は同一電位であることを特徴とする請求項１又は
２に記載の画像表示装置。3. The image display device according to claim 1, wherein the potential supplied to the gate of the driving transistor by the light emission determining unit is the same in all of the pixels.
トランジスタからなるものであり、そのソースがデータ
電極線に接続され、ゲートがアドレスデータ電極線に接
続され、ドレインが前記ドライブ用のトランジスタに接
続されることを特徴とする請求項１乃至３に記載の画像
表示装置。4. The light emission determining means comprises an address selection transistor, the source of which is connected to the data electrode line, the gate of which is connected to the address data electrode line, and the drain of which is connected to the drive transistor. The image display device according to claim 1, wherein the image display device is connected.
には電荷保持用のコンデンサが接続されていることを特
徴とする請求項１乃至４に記載の画像表示装置。5. The image display device according to claim 1, wherein a capacitor for holding a charge is connected to a gate of the driving transistor.
ライブ用のトランジスタの間に設けられるものであるこ
とを特徴とする請求項１乃至５に記載の画像表示装置。6. The image display device according to claim 1, wherein said switch means is provided between a drive electrode and said drive transistor.
n 階調法による輝度階調を表現することを特徴とする請
求項１乃至６に記載の画像表示装置。7. The image display device according to claim 1, wherein:
7. The image display device according to claim 1, wherein a luminance gradation is expressed by an n- gradation method.
光層を有することを特徴とする請求項１乃至７に記載の
画像表示装置。8. The image display device according to claim 1, wherein the EL element has a light emitting layer made of an organic compound.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9136010A JPH10312173A (en) | 1997-05-09 | 1997-05-09 | Picture display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9136010A JPH10312173A (en) | 1997-05-09 | 1997-05-09 | Picture display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10312173A true JPH10312173A (en) | 1998-11-24 |
Family
ID=15165080
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9136010A Pending JPH10312173A (en) | 1997-05-09 | 1997-05-09 | Picture display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10312173A (en) |
Cited By (95)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2001005426A (en) * | 1999-06-23 | 2001-01-12 | Semiconductor Energy Lab Co Ltd | El display device and electronic device |
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