JPH10214060A - Electric field light emission display device and its driving method - Google Patents

Electric field light emission display device and its driving method

Info

Publication number
JPH10214060A
JPH10214060A JP9027323A JP2732397A JPH10214060A JP H10214060 A JPH10214060 A JP H10214060A JP 9027323 A JP9027323 A JP 9027323A JP 2732397 A JP2732397 A JP 2732397A JP H10214060 A JPH10214060 A JP H10214060A
Authority
JP
Japan
Prior art keywords
voltage
electroluminescent
display device
driving
period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
JP9027323A
Other languages
Japanese (ja)
Inventor
Hiroyasu Yamada
裕康 山田
Masaharu Shiotani
雅治 塩谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP9027323A priority Critical patent/JPH10214060A/en
Priority to TW087101059A priority patent/TW441136B/en
Priority to US09/013,708 priority patent/US5990629A/en
Priority to KR1019980707622A priority patent/KR100293329B1/en
Priority to CA002249592A priority patent/CA2249592C/en
Priority to EP98900761A priority patent/EP0906609A1/en
Priority to CNB988000679A priority patent/CN1151483C/en
Priority to PCT/JP1998/000327 priority patent/WO1998033165A1/en
Publication of JPH10214060A publication Critical patent/JPH10214060A/en
Abandoned legal-status Critical Current

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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide the driving method for the electric field light emission display device which can make a gradational display with controllability and be driven with low power consumption. SOLUTION: One frame period of the electric field light emission device which has electric field light emission elements arranged in matrix and selection transistors and driving transistors of the electric field light emission elements connected is divided into eight subframes 1 to 8. Those subframes are so set that they consist of different display discharge times Ton by the respective subframes 1 to 8 and an address period Tadd of the same time among all the subframes 1 to 8. Consequently, total light emission times by pixels can be made different according to whether pixels are selected in the eight subframes 1 to 8, thereby enabling gradational representation.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】この発明は電界発光表示装置
およびその駆動方法に関し、さらに詳しくは、エレクト
ロルミネッセンス発光を行う表示装置の駆動方法に関す
る。[0001] 1. Field of the Invention [0002] The present invention relates to an electroluminescent display device and a method of driving the same, and more particularly, to a method of driving a display device which emits electroluminescence.

【０００２】[0002]

【従来の技術】従来、図１０に示すような、１画素に２
つの薄膜トランジスタ（以下、ＴＦＴという）を備えた
構造の有機ＥＬディスプレイ（電界発光表示装置）があ
る。この有機ＥＬディスプレイにおいては、同図に示す
ように、有機ＥＬ素子１と直列に繋がる駆動ＴＦＴ２の
チャネル抵抗を、そのゲートバイアスを選択ＴＦＴ３が
書き込むことで階調表示させていた。ここで、選択ＴＦ
Ｔ３が走査ラインＸｍで選択されると、書き込む信号が
信号ラインＹｎから供給されるようになっている。図１
１は、このように書き込まれた駆動ＴＦＴ２の、ゲート
電圧（Ｖｇ）とチャネル抵抗との関係、所謂電界効果ト
ランジスタ（ＦＥＴ）の静特性を示すグラフである。図
１２は、１画素における有機ＥＬ素子１と電圧制御手段
Ｖｃと全画素共通ＥＬ電源４との関係を示す等価回路図
である。この電圧制御手段Ｖｃは、選択トランジスタ３
と駆動トランジスタ２とから構成されている。2. Description of the Related Art Conventionally, as shown in FIG.
There is an organic EL display (electroluminescent display) having a structure including two thin film transistors (hereinafter, referred to as TFTs). In this organic EL display, as shown in the figure, the channel resistance of the driving TFT 2 connected in series with the organic EL element 1 is displayed in gradation by writing the gate bias of the driving TFT 2 by the selection TFT 3. Here, select TF
When T3 is selected on the scanning line Xm, a write signal is supplied from the signal line Yn. FIG.
1 is a graph showing the relationship between the gate voltage (Vg) and the channel resistance of the driving TFT 2 written in this way, that is, the static characteristics of a so-called field effect transistor (FET). FIG. 12 is an equivalent circuit diagram showing the relationship among the organic EL element 1, the voltage control means Vc, and the common EL power supply 4 for all pixels in one pixel. The voltage control means Vc is connected to the selection transistor 3
And the driving transistor 2.

【０００３】[0003]

【発明が解決しようとする課題】上記した従来の１画素
２セルＴＦＴ構造の有機ＥＬディスプレイでは、駆動Ｔ
ＦＴ２のゲートバイアスの変化によってチャネルに流れ
る電流を変えることにより、画素ＥＬの発光輝度を変化
させることで階調を表現している。このため、たとえば
２５６階調を実現しようとすると、パネル内の各画素の
駆動ＴＦＴ２の線形領域での特性バラツキが２５６階調
の制御に要求される範囲内になければならず、そのよう
な均一な特性のＴＦＴパネルの製造は実現が困難である
という問題がある。In the above-described conventional organic EL display having a one-pixel two-cell TFT structure, the driving T
By changing the current flowing through the channel by changing the gate bias of the FT2, the gray scale is expressed by changing the light emission luminance of the pixel EL. Therefore, in order to realize, for example, 256 gradations, the characteristic variation in the linear region of the driving TFT 2 of each pixel in the panel must be within the range required for controlling the 256 gradations. There is a problem that it is difficult to manufacture a TFT panel having excellent characteristics.

【０００４】この発明が解決しようとする課題は、制御
性のよい階調表示が行えると共に、低消費電力動作が可
能な電界発光表示装置の駆動方法を得るにはどのような
手段を講じればよいかという点にある。The problem to be solved by the present invention is that what means should be taken to obtain a driving method of an electroluminescent display device which can perform gradation display with good controllability and can operate with low power consumption. It is in the point.

【０００５】[0005]

【課題を解決するための手段】請求項１記載の発明は、
電界発光表示装置であって、それぞれ一対の電極を有
し、電圧の印加に応じて発光する複数の電界発光素子
と、前記各電界発光素子の前記一対の電極の一方のそれ
ぞれに接続され、各アドレス期間に、接地電圧或いは一
定電圧値の駆動電圧のいずれか一方を、前記各アドレス
期間に対応した各発光設定期間に発光すべき電界発光素
子に、出力する複数の第１スイッチング回路と、前記各
電界発光素子の前記一対の電極の他方のそれぞれに接続
され、前記各発光設定期間に、前記接地電圧或いは前記
駆動電圧の他方を、前記全電界発光素子に出力する第２
スイッチング回路と、を具備することを特徴としてい
る。According to the first aspect of the present invention,
An electroluminescent display device, each including a pair of electrodes, a plurality of electroluminescent elements that emit light in response to application of a voltage, and each of the electroluminescent elements is connected to one of the pair of electrodes. A plurality of first switching circuits that output one of a ground voltage and a drive voltage having a constant voltage value to an electroluminescent element to emit light in each light emission setting period corresponding to each address period during the address period; A second electrode that is connected to the other of the pair of electrodes of each of the electroluminescent elements and outputs the other of the ground voltage or the drive voltage to the all electroluminescent elements during each of the emission setting periods.
And a switching circuit.

【０００６】請求項１記載の発明では、各発光設定期間
に発光すべき電界発光素子を予め選択して、対応する各
アドレス期間に接地電圧或いは一定電圧値の駆動電圧の
一方を印加しているので、各発光設定期間に全電界発光
素子の一対の電極の他方に接地電圧或いは駆動電圧の他
方を印加すれば、選択された電界発光素子のみが各発光
設定期間に発光することができる。したがって、複数の
発光設定期間中に選択的に電界発光素子を発光すること
により、言い換えれば、選択された発光設定期間の総時
間に応じて、各電界発光素子の見かけ上の発光輝度を制
御することができる。According to the first aspect of the present invention, an electroluminescent element to emit light in each light emission setting period is selected in advance, and one of a ground voltage and a driving voltage having a constant voltage value is applied to each corresponding address period. Therefore, by applying the other of the ground voltage or the driving voltage to the other of the pair of electrodes of all the electroluminescent elements in each light emission setting period, only the selected electroluminescent element can emit light in each light emission setting period. Therefore, by selectively emitting light from the electroluminescent elements during the plurality of emission setting periods, in other words, controlling the apparent emission luminance of each electroluminescent element according to the total time of the selected emission setting period. be able to.

【０００７】請求項２記載の発明は、前記電界発光素子
はマトリクス状に配列され、１フレーム期間は、前記複
数のアドレス期間と、各アドレス期間にそれぞれ対応し
且つ互いに異なる長さの時間である複数の発光設定期間
と、からなることを特徴としている。請求項２記載の発
明では、各発光設定期間の時間の長さが互いに異なるの
で、階調に応じた発光設定期間を選択すれば一定電圧値
の駆動電圧にもかかわらず、それぞれの画素が１フレー
ム期間に少ない選択数で多くの輝度階調数の発光を実現
することができる。According to a second aspect of the present invention, the electroluminescent elements are arranged in a matrix, and one frame period is a plurality of address periods and time periods respectively corresponding to the address periods and having different lengths. And a plurality of light emission setting periods. According to the second aspect of the present invention, since the time lengths of the light emission setting periods are different from each other, if the light emission setting period according to the gradation is selected, each pixel has one pixel regardless of the driving voltage having a constant voltage value. Light emission of a large number of luminance gradations can be realized with a small number of selections in a frame period.

【０００８】請求項３記載の発明は、前記第１スイッチ
ング回路は、走査電圧が供給される走査ラインにゲート
電極が接続され且つ信号電圧が供給される信号ラインに
ドレイン電極が接続された選択トランジスタと、ゲート
電極が前記選択トランジスタのソース電極に接続され、
且つドレイン電極が前記電界発光素子に接続されると共
に、ソース電極が接地或いは前記駆動電圧のいずれか一
方を出力する駆動電源に接続された駆動トランジスタ
と、を備えることを特徴としている。請求項３記載の発
明では、アドレス期間に選択された電界発光素子に、発
光設定期間中に容易に接地電圧或いは一定電圧値の駆動
電圧の一方を印加できるようチャージできる。According to a third aspect of the present invention, in the first switching circuit, the selection transistor has a gate electrode connected to a scanning line to which a scanning voltage is supplied and a drain electrode connected to a signal line to which a signal voltage is supplied. A gate electrode is connected to a source electrode of the select transistor,
And a drive transistor connected to a drive power supply having a drain electrode connected to the electroluminescent element and a source electrode grounded or outputting one of the drive voltages. According to the third aspect of the present invention, it is possible to charge the electroluminescent element selected during the address period so that one of the ground voltage and the driving voltage having a constant voltage value can be easily applied during the light emission setting period.

【０００９】請求項４記載の発明は、前記走査電圧およ
び前記信号電圧は、それぞれの特性に応じたオン／オフ
の２値信号であることを特徴としている。また、請求項
５記載の発明は、前記第２スイッチング回路には、オン
／オフの２値信号が入力されることを特徴としている。The invention according to claim 4 is characterized in that the scanning voltage and the signal voltage are ON / OFF binary signals corresponding to respective characteristics. The invention according to claim 5 is characterized in that an on / off binary signal is input to the second switching circuit.

【００１０】請求項４および請求項５記載の発明では、
走査電圧、信号電圧および第２スイッチング回路がオン
／オフの２値信号で制御できるので、選択トランジス
タ、駆動トランジスタ、第２スイッチング回路のＶ−Ｉ
特性に多少のばらつきがあっても、飽和電流領域の電圧
を印加すれば、良好に輝度階調を制御することができ
る。[0010] In the invention according to claims 4 and 5,
Since the scanning voltage, the signal voltage, and the second switching circuit can be controlled by a binary signal of ON / OFF, the selection transistor, the driving transistor, and the VI of the second switching circuit can be controlled.
Even if there is some variation in the characteristics, the luminance gradation can be favorably controlled by applying a voltage in the saturation current region.

【００１１】請求項６記載の発明は、前記各発光設定期
間の時間の長さの比率は、それぞれ２のｎ乗（ｎは０以
上の整数）のいずれかであることを特徴としている。The invention according to claim 6 is characterized in that the ratio of the length of each of the light emission setting periods is any of 2 to the power of n (n is an integer of 0 or more).

【００１２】請求項７記載の発明は、電圧の印加に応じ
て発光する複数の電界発光素子を有する電界発光表示装
置の駆動方法において、１フレーム期間が、それぞれ任
意の前記電界発光素子を選択する、複数のアドレス期間
を備え、且つそれぞれの前記アドレス期間の後に、当該
アドレス期間で選択された前記電界発光素子に駆動電圧
を供給する、互いに異なる長さの時間に設定された駆動
電圧供給期間を備えることを特徴としている。According to a seventh aspect of the present invention, in the driving method of the electroluminescent display device having a plurality of electroluminescent elements which emit light in response to the application of a voltage, each of the electroluminescent elements is selected arbitrarily in one frame period. A plurality of address periods, and after each of the address periods, supplying a drive voltage to the electroluminescent element selected in the address period. It is characterized by having.

【００１３】請求項７記載の発明では、各アドレス期間
に、次の駆動電圧供給期間に発光すべき電界発光素子を
予め選択して、駆動電圧供給期間に発光させるが、各駆
動電圧供給期間の時間の長さが互いに異なるので、それ
ぞれの画素が、階調に応じた駆動電圧供給期間を選択す
れば一定電圧値の駆動電圧にもかかわらず、１フレーム
期間に少ない選択で多くの輝度階調数の発光を実現する
ことができる。According to the present invention, in each address period, an electroluminescent element that should emit light in the next drive voltage supply period is selected in advance and emits light in the drive voltage supply period. Since the lengths of time are different from each other, if each pixel selects a drive voltage supply period according to the gray scale, a large number of luminance gray scales can be selected with less selection in one frame period despite the drive voltage having a constant voltage value. A number of emissions can be realized.

【００１４】[0014]

【発明の実施の形態】以下、この発明に係る電界発光表
示装置の駆動方法の詳細を図面に示す実施形態に基づい
て説明する。なお、駆動方法の説明に先駆けて、電界発
光表示装置の構成について説明する。図１は本実施形態
に係る電界発光表示装置の駆動回路図である。同図に示
すように、電界発光素子としての有機ＥＬ素子１０１
が、Ｘ−Ｙマトリクス状に配置されたそれぞれの画素領
域に形成されている。これらの画素領域は、複数の走査
ラインＸと複数の信号ラインＹとがそれぞれ交差する部
分に形成されている。１つの画素領域には、走査ライン
Ｘおよび信号ラインＹに接続された選択トランジスタＱ
1と、この選択トランジスタＱ1にゲートが接続された駆
動トランジスタＱ2とが設けられている。この駆動トラ
ンジスタＱ2は、有機ＥＬ素子１０１の一方の電極に接
続されている。そして、選択トランジスタＱ1が選択さ
れ、且つ信号ラインＹより駆動信号が出力されると駆動
トランジスタＱ2がオン状態になるように設定されてい
る。この駆動信号は、ＯＮ／ＯＦＦの２値信号である。
なお、駆動トランジスタＱ2は、オフ状態では有機ＥＬ
素子１０１に比べて充分高抵抗で、オン状態では有機Ｅ
Ｌ素子１０１に比べて無視できるほど充分低抵抗となる
ようにその特性が設定されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of a method for driving an electroluminescent display device according to the present invention will be described below based on embodiments shown in the drawings. Prior to the description of the driving method, the structure of the electroluminescent display device will be described. FIG. 1 is a drive circuit diagram of the electroluminescent display device according to the present embodiment. As shown in the figure, an organic EL element 101 as an electroluminescent element
Are formed in respective pixel regions arranged in an XY matrix. These pixel regions are formed at portions where a plurality of scanning lines X and a plurality of signal lines Y intersect, respectively. One pixel region includes a selection transistor Q connected to a scanning line X and a signal line Y.
1, a driving transistor Q 2 to which the gate is connected is provided on the select transistor Q 1. This drive transistor Q 2 is connected to one electrode of the organic EL element 101. The selection transistor Q 1 is selected, and the driving transistor Q 2 and the drive signal is outputted from the signal line Y is set to be turned on. This drive signal is a binary signal of ON / OFF.
It should be noted that the drive transistor Q 2 is an organic EL in the off state.
The resistance is sufficiently higher than that of the element 101, and the organic E
The characteristics are set such that the resistance is sufficiently low that it can be ignored as compared with the L element 101.

【００１５】図２は、この電界発光表示装置の１画素部
分の等価回路図である。同図に示すスイッチＳ1は有機
ＥＬ素子１０１の一方の電極に接続されており、このス
イッチＳ1の閉じている状態で、有機ＥＬ素子１０１の
発光が可能となる。また、スイッチＳ2は、有機ＥＬ素
子１０１の他方の電極側に接続されており、全画素に共
通に用いられるとともに、後記するサブフレーム期間内
の発光時間に従って全画素を同時にオン／オフし得るよ
うになっている。なお、図２中Ｐｓは一定電圧に固定さ
れた駆動電源を示している。FIG. 2 is an equivalent circuit diagram of one pixel portion of the electroluminescent display device. Switch S 1 shown in the figure is connected to one electrode of the organic EL element 101, in the closed state of the switch S 1, it is possible to light emission of the organic EL element 101. The switch S 2 is connected to the other electrode side of the organic EL element 101, along with commonly used in all the pixels may be simultaneously turned on / off all the pixels in accordance with light emitting times in the subframe period to be described later It has become. In FIG. 2, Ps indicates a drive power supply fixed to a constant voltage.

【００１６】ここで、本実施形態における電界発光表示
装置の更に具体的な構成を、図３および図４を用いて説
明する。図３は、本実施形態における電界発光表示装置
の１画素部分を示す平面図である。図４は、図３のＡ−
Ａ断面図である。図中１００は電界発光表示装置を示し
ている。Here, a more specific structure of the electroluminescent display device according to the present embodiment will be described with reference to FIGS. FIG. 3 is a plan view illustrating one pixel portion of the electroluminescent display device according to the present embodiment. FIG. 4 is a cross-sectional view of FIG.
It is A sectional drawing. In the figure, reference numeral 100 denotes a light emitting display.

【００１７】本実施形態の電界発光表示装置１００は、
ガラス或いは樹脂フィルムからなる基板１０２の上に例
えばアルミニウム（Ａｌ）でなるゲートメタル膜がパタ
ーニングされてなる、所定方向（Ｘ方向）に沿って平行
かつ等間隔をなす複数の走査ライン１０３と、この走査
ライン１０３に一体的な、選択トランジスタＱ1のゲー
ト電極１０３Ａと、駆動トランジスタＱ2のゲート電極
１０３Ｂと、が形成されている。なお、これらゲート電
極１０３Ａ、１０３Ｂおよび走査ライン１０３の表面に
は、陽極酸化膜１０４が形成されている。また、これら
走査ライン１０３、ゲート電極１０３Ａ、１０３Ｂおよ
び基板１０２の上には、窒化シリコンでなるゲート絶縁
膜１０５が形成されている。さらに、ゲート電極１０３
Ａ、１０３Ｂの上方のゲート絶縁膜１０５Ａ、１０５Ｂ
の上には、アモルファスシリコン（ａ−Ｓｉ）でなる半
導体層１０６Ａ、１０６Ｂがパターン形成されている。
また、それぞれの半導体層１０６Ａ、１０６Ｂの中央に
は、チャネル幅方向に沿って形成されたブロッキング層
１０７Ａ、１０７Ｂが形成されている。そして、半導体
層１０６Ａの上には、ブロッキング層１０７Ａ上でソー
ス側とドレイン側とに分離されたオーミック層１０８
Ａ、１０８Ａが形成されている。さらに、選択トランジ
スタＱ1においては、ドレイン側のオーミック層１０８
Ａに積層されて接続する信号ライン１０９Ａと、ソース
側のオーミック層１０８Ａに積層されて接続するソース
電極１０９Ｂとが形成されている。このソース電極１０
９Ｂは、図３に示すように、駆動トランジスタＱ2のゲ
ート電極１０３Ｂに対して、ゲート絶縁膜１０５に開口
したコンタクトホール１１０を介して接続されている。
駆動トランジスタＱ2においては、ソース側のオーミッ
ク層１０８Ｂに積層されて接続するＧＮＤ線１１１と、
一端がドレイン側のオーミック層１０８Ｂに積層されて
接続し、且つ他端が有機ＥＬ素子１０１の後記するカソ
ード電極１１４に接続するドレイン電極１１２が形成さ
れている。これら選択トランジスタＱ1と駆動トランジ
スタＱ2は、図２に示したスイッチＳ1を構成している。
また、ゲート電極１０３Ｂとゲート絶縁膜１０５とＧＮ
Ｄ線とでキャパシタＣｐ１が構成される。The light emitting display device 100 of the present embodiment is
A plurality of scanning lines 103, which are formed by patterning a gate metal film made of, for example, aluminum (Al) on a substrate 102 made of glass or a resin film, and are parallel and equally spaced along a predetermined direction (X direction). the scan line 103 that integrally includes a gate electrode 103A of the selection transistors Q 1, and the gate electrode 103B of the driving transistor Q 2, is formed. An anodic oxide film 104 is formed on the surfaces of the gate electrodes 103A and 103B and the scanning lines 103. A gate insulating film 105 made of silicon nitride is formed on the scanning lines 103, the gate electrodes 103A and 103B, and the substrate 102. Further, the gate electrode 103
A, Gate insulating films 105A, 105B above 103B
Semiconductor layers 106A and 106B made of amorphous silicon (a-Si) are pattern-formed thereon.
Further, blocking layers 107A and 107B formed along the channel width direction are formed at the centers of the respective semiconductor layers 106A and 106B. Then, on the semiconductor layer 106A, the ohmic layer 108 separated into the source side and the drain side on the blocking layer 107A.
A, 108A are formed. Further, in the select transistor Q 1, the drain side of the ohmic layer 108
A signal line 109A stacked and connected to A and a source electrode 109B stacked and connected to the ohmic layer 108A on the source side are formed. This source electrode 10
9B, as shown in FIG. 3, the gate electrode 103B of the driving transistor Q 2, are connected via a contact hole 110 which is opened in the gate insulating film 105.
In the driving transistor Q 2, the GND line 111 for connecting is laminated on the ohmic layer 108B on the source side,
A drain electrode 112 is formed, one end of which is stacked and connected to the drain-side ohmic layer 108B, and the other end of which is connected to a cathode electrode 114 described later of the organic EL element 101. These select transistors Q 1 and driver transistor Q 2 is, constitutes a switch S 1 shown in FIG.
Further, the gate electrode 103B, the gate insulating film 105, and the GN
The capacitor Cp1 is configured with the D line.

【００１８】次に、有機ＥＬ素子１０１の構成を説明す
る。まず、上記した選択トランジスタＱ1、駆動トラン
ジスタＱ2およびゲート絶縁膜１０５の上に、電界発光
表示装置１００の発光表示領域全域に亙って、層間絶縁
膜１１３が堆積されている。そして、上記した駆動トラ
ンジスタＱ2のドレイン電極１１２の端部上の層間絶縁
膜１１３にコンタクトホール１１３Ａが形成されてい
る。なお、本実施形態では、駆動トランジスタＱ2のド
レイン電極１１２の端部は、１画素領域の略中央に位置
するように設定されている。そして、層間絶縁膜１１３
の上に、例えばＭｇＩｎでなるカソード電極１１４が略
１画素領域全域に亙って矩形状に形成されている。すな
わち、カソード電極１１４は、相隣接する信号ライン１
０９Ａ、１０９Ａと相隣接する走査ライン１０３、１０
３とで囲まれる領域（１画素領域）を略覆うように形成
されている。このため、選択トランジスタＱ1と駆動ト
ランジスタＱ2とは、カソード電極１１４で全面的に覆
われている。Next, the configuration of the organic EL element 101 will be described. First, an interlayer insulating film 113 is deposited over the entire light emitting display region of the electroluminescent display device 100 on the above-described selection transistor Q 1 , driving transistor Q 2 and gate insulating film 105. Then, a contact hole 113A is formed in the interlayer insulating film 113 on the end of the drain electrode 112 of the driving transistor Q 2 to which the above-mentioned. In the present embodiment, the end portion of the drain electrode 112 of the driving transistor Q 2 is set to be positioned at substantially the center of one pixel region. Then, the interlayer insulating film 113
A cathode electrode 114 made of, for example, MgIn is formed in a rectangular shape over substantially the entire pixel region. That is, the cathode electrode 114 is connected to the adjacent signal line 1.
Scanning lines 103 and 10 adjacent to the scanning lines 09A and 109A.
3 is formed so as to substantially cover a region (one pixel region) surrounded by the reference numeral 3. Therefore, the selection transistor Q 1 and the driving transistor Q 2 are entirely covered with the cathode electrode 114.

【００１９】さらに、図４に示すように、各画素毎にパ
ターン形成されたカソード電極１１４、および層間絶縁
膜１１３の上に、有機ＥＬ層１１５が発光表示領域全域
に亙って形成されている。さらに、有機ＥＬ層１１５の
上には、透明なＩＴＯでなるアノード電極１１６が全有
機ＥＬ素子１０１の発光表示領域全域に亙って形成され
ている。また、各有機ＥＬ素子１０１のアノード電極１
１６は、スイッチＳ２を介して駆動電圧Ｖｄｄを供給す
る駆動電源Ｐｓに接続されている。Further, as shown in FIG. 4, an organic EL layer 115 is formed over the entire light emitting display area on the cathode electrode 114 and the interlayer insulating film 113 which are patterned for each pixel. . Further, on the organic EL layer 115, an anode electrode 116 made of transparent ITO is formed over the entire light emitting display region of the entire organic EL element 101. Also, the anode electrode 1 of each organic EL element 101
Reference numeral 16 is connected to a drive power supply Ps for supplying a drive voltage Vdd via a switch S2.

【００２０】ここで、上記した構成の電界発光表示装置
１００の作用について説明する。本実施形態において
は、カソード電極１１４が、相隣接する信号ライン１０
９Ａ、１０９Ａと相隣接する走査ライン１０３、１０３
とで囲まれる領域（１画素領域）を略覆うように形成さ
れているため、有機ＥＬ素子１０１は１画素領域の略全
域に亙って発光を行うことができる。また、カソード電
極１１４が光反射性を有するＭｇＩｎで形成されている
ため、カソード電極１１４とアノード電極１１６との間
に駆動電圧が印加された場合に、有機ＥＬ層１１５で発
生した表示光は、下方（ガラス基板１０２側）に漏れる
ことなくアノード電極１１６側に出射される。このた
め、選択トランジスタＱ1および駆動トランジスタＱ2の
半導体層１０６Ａ、１０６Ｂへ不要に光が入射するのを
防止することができ、各トランジスタの光起電力による
誤動作が生じるのを回避することができる。また、表示
光は、透明なアノード電極１１６側から出射されるた
め、ガラス基板１０２などにより光吸収されることがな
く、輝度の高い状態で出射される。Here, the operation of the electroluminescent display device 100 having the above configuration will be described. In the present embodiment, the cathode electrode 114 is connected to the adjacent signal line 10.
Scan lines 103 and 103 adjacent to 9A and 109A
The organic EL element 101 can emit light over substantially the entire area of one pixel region because the organic EL element 101 is formed so as to substantially cover the region (one pixel region) surrounded by. Further, since the cathode electrode 114 is made of MgIn having light reflectivity, when a driving voltage is applied between the cathode electrode 114 and the anode electrode 116, display light generated in the organic EL layer 115 is: The light is emitted toward the anode electrode 116 without leaking downward (to the glass substrate 102). Therefore, it is possible to avoid the semiconductor layer 106A of the selection transistors Q 1 and driver transistor Q 2, can unnecessarily light to 106B is prevented from entering, from malfunction due to the photovoltaic of each transistor is generated . In addition, since the display light is emitted from the transparent anode electrode 116 side, the display light is emitted with high brightness without being absorbed by the glass substrate 102 or the like.

【００２１】次に、本実施形態の電界発光表示装置１０
０の駆動回路系を説明する。図２の等価回路図が示すよ
うに、有機ＥＬ素子１０１とスイッチＳ1、Ｓ2と駆動電
源Ｐｓとから１画素部分のＥＬ表示回路が構成されてい
る。また、上記したように、スイッチＳ1は、選択トラ
ンジスタＱ1と駆動トランジスタＱ2とから構成され、有
機ＥＬ素子１０１に選択的に接地電位を供給（出力）す
ることができる。有機ＥＬ素子１０１においては、アノ
ード電極側に正極性の一定電圧値の駆動電圧Ｖｄｄを供
給する駆動電源Ｐｓが接続され、そのカソード電極側に
スイッチＳ1が接続され、スイッチＳ1を構成する駆動ト
ランジスタＱ2のソース電極側はＧＮＤ線１１１を介し
て接地されている。Next, the electroluminescent display device 10 of the present embodiment will be described.
A drive circuit system of 0 will be described. As shown in an equivalent circuit diagram of FIG. 2, EL display circuit of a pixel portion of an organic EL element 101 and the switch S 1, S 2 and the drive power Ps is configured. Further, as described above, the switch S 1 includes the selection transistor Q 1 and the driving transistor Q 2, and can selectively supply (output) the ground potential to the organic EL element 101. In the organic EL element 101, the driving power Ps for supplying a driving voltage Vdd constant voltage value of the positive polarity is connected to the anode electrode side, the switch S 1 is connected to the cathode electrode side, constituting the switch S 1 driving the source electrode of the transistor Q 2 is grounded through a GND line 111.

【００２２】以下、本実施形態の電界発光表示装置１０
０の駆動方法について説明する。まず、本実施形態は、
電界発光表示装置１００における走査ライン１０３の本
数を例えば４８０本、信号ライン１０９Ａの本数を例え
ば６４０本に設定する。そして、本実施形態では、図５
に示すような階調表示方式を用いる。同図に示すよう
に、１フレーム期間（１枚の表示を描く期間）が１６.
６ｍｓ固定であるとして、１フレーム期間を８つのサブ
フレーム期間（サブフレーム１〜８）に分割する。各サ
ブフレーム期間は、アドレス書込みを行うためのアドレ
ス期間Ｔａｄｄとアドレス期間に対応した駆動電圧供給
期間Ｔｏｎ１〜８とからなる。この駆動電圧供給期間Ｔ
ｏｎの比率は、Ｔｏｎ１を１（＝２0）とすると、Ｔｏ
ｎ２は２（＝２1）、Ｔｏｎ３は４（＝２2）、Ｔｏｎ４
は８（＝２3）、Ｔｏｎ５は１６（＝２4）、Ｔｏｎ６は
３２（＝２5）、Ｔｏｎ７は６４（＝２6）、Ｔｏｎ８は
１２８（＝２7）となる。このような駆動電圧供給期間
において、１の駆動電圧供給期間で１という輝度を表示
するとすると、サブフレーム１のみを点灯することで１
の輝度が得られる。輝度２のときはサブフレーム２のみ
を、輝度３のときはサブフレーム１とサブフレーム２
を、４のときはサブフレーム３のみを点灯するというよ
うに、以下同様にして組み合わせにより合計２５６（＝
２8）の階調を表示することが可能となる。Hereinafter, the electroluminescent display device 10 of the present embodiment will be described.
The method of driving 0 will be described. First, in the present embodiment,
In the electroluminescent display device 100, the number of the scanning lines 103 is set to, for example, 480, and the number of the signal lines 109A is set to, for example, 640. In the present embodiment, FIG.
The gradation display method shown in FIG. As shown in the figure, one frame period (a period for drawing one display) is 16.
One frame period is divided into eight subframe periods (subframes 1 to 8), assuming that the period is fixed to 6 ms. Each sub-frame period includes an address period Tadd for performing address writing and drive voltage supply periods Ton1 to Ton8 corresponding to the address period. This drive voltage supply period T
Assuming that Ton1 is 1 (= 2 0 ), the ratio of on is To
n2 is 2 (= 2 1 ), Ton3 is 4 (= 2 2 ), Ton4
Is 8 (= 2 3 ), Ton 5 is 16 (= 2 4 ), Ton 6 is 32 (= 2 5 ), Ton 7 is 64 (= 2 6 ), and Ton 8 is 128 (= 2 7 ). If a luminance of 1 is displayed in one drive voltage supply period in such a drive voltage supply period, only one sub-frame 1 is turned on to display 1 luminance.
Is obtained. When the brightness is 2, only the subframe 2 is used. When the brightness is 3, the subframe 1 and the subframe 2 are used.
, When the number is 4, only the sub-frame 3 is lit, and so on in the same manner as described above, for a total of 256 (=
It is possible to display the gray scale of 2 8).

【００２３】各サブフレームにおいては、アドレス期間
Ｔａｄｄにアドレス書込みが終了した後に駆動電圧供給
期間Ｔｏｎの間アドレス選択された画素を同時に点灯さ
せる。その次のサブフレームではアドレス期間Ｔａｄｄ
中にアドレス書き換えを行って駆動電圧供給期間Ｔｏｎ
にアドレス選択された画素を同時に点灯させる。このよ
うにサブフレーム１からサブフレーム８まで１フレーム
期間内に行う。アドレス選択のタイミングは、図２に示
したスイッチＳ1で制御し、駆動電圧供給時間はスイッ
チＳ2のオン時間で制御することができる。すなわち、
１つのサブフレーム期間内において、走査ラインと信号
ラインとの線順次走査により、このサブフレーム特有の
表示放電期間に点灯すべき画素の選択トランジスタＱ1
がオン状態となる。そして、選択トランジスタＱ1がオ
ンになると信号ラインから選択トランジスタＱ1を介し
て駆動トランジスタＱ２のゲート電極への書込みが行わ
れ、アドレス期間Ｔａｄｄ内においては駆動トランジス
タＱ2にチャネルが形成された状態が保持される。この
アドレス期間で点灯すべき画素がすべて選択された後、
すなわちアドレス期間Ｔａｄｄ終了後の駆動電圧供給期
間Ｔｏｎまで選択状態が保持される。駆動電圧供給期間
Ｔｏｎ中には、アノード電極１１６に接続された駆動電
源ＰｓがスイッチＳ2でオンされる。この駆動電圧供給
期間は、上記したようにそれぞれのサブフレームでその
長さが設定されている。ここで、１フレーム期間中の全
アドレス期間Ｔａｄｄの時間の長さと駆動電圧供給期間
Ｔｏｎ１〜Ｔｏｎ８の時間の長さを等しくすると、各ア
ドレス期間Ｔａｄｄは、１.０４ｍｓ程度となり、各走
査ラインＸ1〜Ｘ480の１駆動電圧供給期間で選択される
時間は、２.２μｓ程度となる。In each sub-frame, after the address writing is completed in the address period Tadd, the pixels whose addresses are selected during the drive voltage supply period Ton are simultaneously turned on. In the next subframe, the address period Tadd
During address rewriting, the drive voltage supply period Ton
At the same time, the pixels whose addresses have been selected are turned on. As described above, the processing from subframe 1 to subframe 8 is performed within one frame period. Timing of address selection, controlled by switch S 1 shown in FIG. 2, the drive voltage supply time can be controlled by the on-time of the switch S 2. That is,
Within one sub-frame period, the selection transistor Q 1 of a pixel to be turned on during a display discharge period unique to this sub-frame by line-sequential scanning of the scanning line and the signal line.
Is turned on. The state selection transistor Q 1 is from the consisting the signal lines on via the selection transistor Q 1 is performed writing to the gate electrode of the driving transistor Q2, the channel drive transistor Q 2 is in the address period Tadd is formed Is held. After all the pixels to be lit during this address period are selected,
That is, the selected state is maintained until the drive voltage supply period Ton after the end of the address period Tadd. During the drive voltage supply period Ton, connected driving power Ps is turned on by the switch S 2 to the anode electrode 116. The length of the drive voltage supply period is set in each subframe as described above. Here, when the time length of the entire address period Tadd in one frame period is equal to the time length of the drive voltage supply periods Ton1 to Ton8, each address period Tadd becomes about 1.04 ms, and each scan line X 1 time selected by the first driving voltage supply period to X 480 becomes about 2.2 microseconds.

【００２４】次に、本実施形態の駆動方法で階調表示が
行える原理を図６を用いて説明する。この図は、簡略化
するために、１フレーム期間を３つのサブフレームに分
割した例であり、サブフレーム１の駆動電圧供給期間
（発光時間）は１（＝２0）、サブフレーム２の駆動電
圧供給期間は２（＝２1）、サブフレーム３の駆動電圧
供給期間は４（＝２2）とした。図６は、網状の斜線を
付した部分の画素１３、２２、２４、３１、３５、４
２、４４、５３の輝度が高くなるように表示された例を
示している。具体的には、サブフレーム１で全画素が選
択されて輝度１の発光を行ったとすると、サブフレーム
２、３では線順次走査により画素１３、２２、２４、３
１、３５、４２、４４、５３のみが選択され、輝度２と
輝度４が加算されたと設定する。このため、３つのサブ
フレームが終了した（１フレーム期間が終了した）状態
では、画素１３、２２、２４、３１、３５、４２、４
４、５３が輝度７となり、他の画素が輝度１であるのと
比較して高輝度となる。このように、１フレーム期間を
複数のサブフレームに分割することにより、アドレス期
間合計と駆動電圧供給期間合計との比を変えることがで
きるため、電界発光表示装置１００の階調表示が可能と
なる。また、図７に示す有機ＥＬ素子の電圧−輝度−効
率特性で最も効率の良い電圧値を発光駆動に用いるよう
に設定すれば、低消費電力で発光駆動させることができ
る。このような原理は、１フレーム期間を８つのサブフ
レームに分割した場合での同様に適用できるものであ
り、２５６階調の表現も可能となる。Next, the principle of performing gray scale display by the driving method of this embodiment will be described with reference to FIG. This diagram shows an example in which one frame period is divided into three subframes for simplification. The driving voltage supply period (light emission time) of subframe 1 is 1 (= 2 0 ), and the driving of subframe 2 is performed. The voltage supply period was 2 (= 2 1 ), and the drive voltage supply period of subframe 3 was 4 (= 2 2 ). FIG. 6 shows the pixels 13, 22, 24, 31, 35, and 4 in the hatched portions of the mesh.
An example is shown in which the luminances of 2, 44, and 53 are displayed so as to increase. Specifically, assuming that all the pixels are selected in subframe 1 and light emission of luminance 1 is performed, in subframes 2 and 3, pixels 13, 22, 24, 3
Only 1, 35, 42, 44, and 53 are selected, and it is set that luminance 2 and luminance 4 have been added. Therefore, in a state where three sub-frames have been completed (one frame period has been completed), the pixels 13, 22, 24, 31, 35, 42, 4
4 and 53 have a luminance of 7 and are higher in luminance than other pixels having a luminance of 1. As described above, by dividing one frame period into a plurality of subframes, the ratio between the total address period and the total drive voltage supply period can be changed, so that the gray scale display of the electroluminescent display device 100 becomes possible. . In addition, if the most efficient voltage value in the voltage-luminance-efficiency characteristics of the organic EL element shown in FIG. 7 is set for light emission driving, light emission driving can be performed with low power consumption. Such a principle can be similarly applied to a case where one frame period is divided into eight sub-frames, and 256 gradations can be expressed.

【００２５】上記したように、本実施形態によれば、一
定の駆動電圧Ｖｄｄのスイッチングをオン／オフの２値
信号で制御するスイッチＳ2を用い、且つ選択トランジ
スタＱ1と駆動トランジスタＱ2にもオン／オフの２値信
号をいずれかを選択的に出力するため、図１０のソース
・ドレイン間電圧ＶSDをソース・ドレイン間電流が飽和
電流になる範囲に設定するので、各トランジスタの電圧
ＶSDの１Ｖ〜５Ｖ間でのＶ−Ｉ特性に多少のばらつきが
あっても、良好に輝度階調を制御することができ、安定
した階調制御を行うことが可能となる。特に、１つの有
機ＥＬ素子に対し選択トランジスタＱ1、駆動トランジ
スタＱ2、スイッチＳ2の３つのスイッチング素子が構成
している場合、それぞれのわずかな電気的特性のずれが
相乗され、１つの画素として大きく輝度階調がずれてし
ます恐れがあるが、選択トランジスタＱ1や駆動トラン
ジスタＱ2およびスイッチＳ2は、飽和電流領域での電圧
値を用いオン／オフ制御を行うだけであるため、特性に
多少のバラツキがあった場合でもその影響を受けにくい
という利点がある。また、有機ＥＬ素子１０１にとって
発光効率のよい電圧値を駆動電圧として設定できるた
め、低消費電力化を達成することができる。[0025] As described above, according to this embodiment, using a switch S 2 to control a binary signal on / off switching of the constant drive voltage Vdd, and a selection transistor Q 1 to the driving transistor Q 2 Also, since either one of the binary signals of ON / OFF is selectively output, the source-drain voltage VSD in FIG. 10 is set to a range where the source-drain current becomes a saturation current. Even if the VI characteristics vary slightly between 1 V and 5 V, it is possible to control the luminance gradation satisfactorily and perform stable gradation control. In particular, when three switching elements, ie, the selection transistor Q 1 , the driving transistor Q 2 , and the switch S 2 , are configured for one organic EL element, slight differences in their electrical characteristics are synergistic, and one pixel is formed. for larger there is a risk that will offset the luminance gradation as, select transistors Q 1 and driver transistor Q 2 and the switch S 2 is that only performs on / off control using a voltage value in the saturation current region, There is an advantage that even if there is some variation in characteristics, it is hardly affected by the variation. In addition, a voltage value with high luminous efficiency for the organic EL element 101 can be set as a driving voltage, so that low power consumption can be achieved.

【００２６】以上、本実施形態について説明したが、本
発明はこれに限定されるものではなく、構成の要旨に付
随する各種の設計変更が可能である。例えば、上記した
実施形態においては、サブフレーム期間におけるアドレ
ス期間内でアドレス選択状態を保持するために、選択ト
ランジスタＱ1と駆動トランジスタＱ2とを備えた構成と
したが、図８の１画素等価回路で示すような構成として
もアドレス選択状態を保持することができる。同図にお
いてＱ3は選択トランジスタ、Ｑ4は駆動トランジスタ、
Ｃｐ２は容量を示している。なお、この駆動トランジス
タＱ4は別途容量Ｃｐ２が接続されているため、ＥＥＰ
ＲＯＭ機能を有しないＴＦＴを用いることができる。駆
動トランジスタＱ4のソース・ドレインの一方が各有機
ＥＬ素子１０１の各カソード電極に接続され、他方がス
イッチＳ2を介して負電位Ｖｄｄ′を供給する直流電源
Ｐｓ′に接続されている。有機ＥＬ素子１０１は、発光
表示領域全域に亙って形成されたアノード電極が接地さ
れ構造であり、駆動トランジスタＱ4が選択され、スイ
ッチＳ2がオンすると発光する。また、上記した実施形
態においては、電界発光素子として直流電界で発光でき
る有機ＥＬ素子１０１に特に有効であるが、無機ＥＬ素
子やその他の電界発光素子を適用することも勿論可能で
ある。本実施形態では、有機ＥＬ素子の発光層は電荷輸
送性の異なる２層以上の有機層から構成されてもよく、
アノード電極１１６上に酸素および水の侵入を防止する
封止層を設けてもよい。また、基板１０２側からアノー
ド電極１１６、有機ＥＬ層１１５、カソード電極１１４
の順に積層した構造としてもよい。Although the present embodiment has been described above, the present invention is not limited to this, and various design changes accompanying the gist of the configuration are possible. For example, in the above embodiment, in order to hold the address selected in the address period in the sub-frame period, a configuration having a selection transistor Q 1, the driving transistor Q 2, 1 pixel equivalent of FIG. 8 The address selection state can be held even with a configuration shown by a circuit. In the figure, Q 3 is a selection transistor, Q 4 is a driving transistor,
Cp2 indicates the capacity. Since the driving transistor Q 4 is separately connected to the capacitor Cp 2, the EEP
A TFT having no ROM function can be used. One of the source and drain of the driving transistor Q 4 is connected to the cathode electrodes of the organic EL element 101, the other is connected to the 'DC power supply Ps supplies' negative potential Vdd via a switch S 2. The organic EL element 101 is an anode electrode formed over the light emitting entire display area is grounded structure, the driving transistor Q 4 is selected to emit light when the switch S 2 is turned on. In the above-described embodiment, the electroluminescent device is particularly effective for the organic EL device 101 that can emit light in a DC electric field. However, an inorganic EL device or another electroluminescent device can of course be applied. In this embodiment, the light emitting layer of the organic EL element may be composed of two or more organic layers having different charge transporting properties,
A sealing layer for preventing entry of oxygen and water may be provided over the anode electrode 116. Further, from the substrate 102 side, the anode electrode 116, the organic EL layer 115, the cathode electrode 114
In this order.

【００２７】なお、本実施形態では、１フレーム期間中
の全アドレス期間Ｔａｄｄの時間の長さと駆動電圧供給
期間Ｔｏｎ１〜Ｔｏｎ８の時間の長さを等しくしたが、
選択トランジスタＱ1、Ｑ3、駆動トランジスタＱ2、Ｑ4
の特性に応じて、アドレス期間Ｔａｄｄ、駆動電圧供給
期間Ｔｏｎの一方を長くしたり、他方を短くしたりして
もよい。また、各駆動電圧供給期間Ｔｏｎは短い順（Ｔ
ｏｎ１、Ｔｏｎ２、…、Ｔｏｎ８）に印加されるがこれ
に限らず、長い順（Ｔｏｎ８、Ｔｏｎ７、…、Ｔｏｎ
１）でのよく、或いはＴｏｎ８、Ｔｏｎ１、Ｔｏｎ５、
Ｔｏｎ４、Ｔｏｎ７、Ｔｏｎ２、Ｔｏｎ６、Ｔｏｎ３の
順のように時間の長さの順番通りでなくてもよい。ま
た、駆動電源Ｐｓが供給する駆動電圧Ｖｄｄは、直流電
圧での交流でのでもよい。さらに、階調数は２５６階調
に限らず、複数の階調であれば２５６階調より多くても
少なくてもよい。In this embodiment, the length of the entire address period Tadd in one frame period is equal to the length of the drive voltage supply periods Ton1 to Ton8.
Select transistors Q 1 , Q 3 , drive transistors Q 2 , Q 4
According to the above characteristics, one of the address period Tadd and the drive voltage supply period Ton may be lengthened, and the other may be shortened. In addition, the driving voltage supply periods Ton are in the order of shortest (T
on1, Ton2,..., Ton8), but is not limited to this, and is applied in the long order (Ton8, Ton7,.
1) good, or Ton8, Ton1, Ton5,
The order of the time lengths, such as the order of Ton4, Ton7, Ton2, Ton6, and Ton3, does not have to be the same. The drive voltage Vdd supplied by the drive power supply Ps may be an alternating current of a DC voltage. Further, the number of gradations is not limited to 256 gradations, and may be more or less than 256 gradations as long as there are a plurality of gradations.

【００２８】本実施形態では、選択トランジスタＱ1と
駆動トランジスタＱ2とからなるスイッチＳ1がＧＮＤ線
１１１に接続され、駆動電圧供給期間Ｔにオンするスイ
ッチＳ2が駆動電源Ｐｓに接続されているが、図９に示
すように、有機ＥＬ素子１０１のアノード電極側のスイ
ッチＳ２を駆動電源Ｐｓを介さずに直接接地させ、有機
ＥＬ素子１０１のカソード電極側のスイッチＳ1の駆動
トランジスタＱ2をＧＮＤ線１１１の代わりに負極性の
一定値の駆動電圧Ｖｄｄ′を供給する駆動電源Ｐｓ′に
接続させてもよい。この場合であっても、走査ライン
Ｘ、信号ラインＹに、それぞれ２値信号のいずれかを出
力し、有機ＥＬ素子１０１のアノード電極に接続された
スイッチＳ2を２値信号でオン、オフ制御することがで
きる。すなわち、アドレス期間Ｔａｄｄには、選択され
た有機ＥＬ素子１０１のカソード電極側に駆動電圧Ｖｄ
ｄ′が供給され、駆動電圧供給期間Ｔｏｎに全スイッチ
Ｓ2がオンされ、有機ＥＬ素子１０１のアノード電極が
接地され発光する。In the present embodiment, the switch S 1 composed of the selection transistor Q 1 and the drive transistor Q 2 is connected to the GND line 111, and the switch S 2 that turns on during the drive voltage supply period T is connected to the drive power supply Ps. It is, but as shown in FIG. 9, the organic EL anode electrode side of the switch S2 of the element 101 is grounded directly without passing through the driving power Ps, the driving transistor Q 2 switches S 1 of the cathode side of the organic EL element 101 May be connected to a driving power supply Ps ′ that supplies a driving voltage Vdd ′ having a constant value of negative polarity instead of the GND line 111. Even in this case, scan lines X, the signal line Y, and outputs one of the respective binary signal, turning on the switch S 2 which is connected to the anode electrode of the organic EL element 101 in a binary signal, OFF control can do. That is, during the address period Tadd, the drive voltage Vd is applied to the cathode electrode side of the selected organic EL element 101.
d 'is supplied to the drive voltage supply period Ton entire switch S 2 is turned on, the anode electrode of the organic EL element 101 is grounded to emit light.

【００２９】さらに、本実施形態では、有機ＥＬ素子１
０１をスイッチＳ1の上方に形成したが、スイッチＳ1と
同一平面上に形成してもよい。なお、この場合は、基板
１０２側からアノード電極１１６、有機ＥＬ層１１５、
カソード電極１１４の順に積層して形成すれば、仕事関
数の低く酸化されやすい材料からなるカソード電極１１
４をアノード電極１１６、有機ＥＬ層１１５の形成工程
により劣化させることがない。Further, in this embodiment, the organic EL element 1
01 has been formed over the switch S 1, may be formed on the switch S 1 and the same plane. Note that, in this case, the anode electrode 116, the organic EL layer 115,
If the cathode electrode 114 is formed by laminating in order, the cathode electrode 11 made of a material having a low work function and easily oxidized.
4 is not deteriorated by the process of forming the anode electrode 116 and the organic EL layer 115.

【００３０】[0030]

【発明の効果】以上の説明から明らかなように、この発
明によれば、電界発光表示装置を制御性よく階調表示で
きる共に、低消費電力動作を可能にするという効果を奏
する。As is apparent from the above description, according to the present invention, it is possible to perform gradation display of the electroluminescent display device with good controllability, and to operate at low power consumption.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施形態に係る電界発光表示装置の駆
動回路図。FIG. 1 is a drive circuit diagram of an electroluminescent display device according to an embodiment of the present invention.

【図２】本実施形態における電界発光表示装置の１画素
部分の等価回路図。FIG. 2 is an equivalent circuit diagram of one pixel portion of the electroluminescent display device according to the embodiment.

【図３】本実施形態における電界発光表示装置の平面
図。FIG. 3 is a plan view of the electroluminescent display device according to the embodiment.

【図４】図３のＡ−Ａ断面図。FIG. 4 is a sectional view taken along line AA of FIG. 3;

【図５】本実施形態の駆動方法示す説明図。FIG. 5 is an explanatory diagram illustrating a driving method according to the embodiment.

【図６】１フレーム期間を３サブフレームに分割した場
合の階調表示原理を説明する説明図。FIG. 6 is an explanatory diagram illustrating the principle of gray scale display when one frame period is divided into three sub-frames.

【図７】本実施形態における有機ＥＬ素子の電圧−輝度
−効率特性を示すグラフ。FIG. 7 is a graph showing voltage-luminance-efficiency characteristics of the organic EL element according to the embodiment.

【図８】本発明を適用し得る電界発光表示装置の１画素
部分を示す等価回路図。FIG. 8 is an equivalent circuit diagram showing one pixel portion of a light emitting display device to which the present invention can be applied.

【図９】本発明の他の実施形態に電界発光表示装置の駆
動回路図。FIG. 9 is a driving circuit diagram of an electroluminescent display device according to another embodiment of the present invention.

【図１０】従来の電界発光表示装置の１画素部分を示す
等価回路図。FIG. 10 is an equivalent circuit diagram showing one pixel portion of a conventional electroluminescent display device.

【図１１】従来の電界発光表示装置における駆動ＴＦＴ
２の、ゲート電圧（Ｖｇ）とチャネル抵抗との関係を示
すグラフ。FIG. 11 shows a driving TFT in a conventional electroluminescent display device.
2 is a graph showing the relationship between the gate voltage (Vg) and the channel resistance of FIG.

【図１２】従来の電界発光表示装置の１画素における有
機ＥＬ素子１と電圧制御手段Ｖｃと全画素共通ＥＬ電源
４との関係を示す等価回路図。FIG. 12 is an equivalent circuit diagram showing a relationship among an organic EL element 1, a voltage control means Vc, and an all-pixel common EL power supply 4 in one pixel of a conventional electroluminescent display device.

【符号の説明】[Explanation of symbols]

１００ 電界発光表示装置 １０１ 有機ＥＬ素子 １０３ 走査ライン １０９Ａ 信号ライン Ｑ1 選択トランジスタ Ｑ2 駆動トランジスタ Ｓ2 スイッチ100 light emitting display device 101 organic EL device 103 scanning lines 109A signal lines Q 1 selected transistor Q 2 driving transistor S 2 switch

Claims (12)

【特許請求の範囲】[Claims] 【請求項１】 それぞれ一対の電極を有し、電圧の印加
に応じて発光する複数の電界発光素子と、 前記各電界発光素子の前記一対の電極の一方のそれぞれ
に接続され、各アドレス期間に、接地電圧或いは一定電
圧値の駆動電圧のいずれか一方を、前記各アドレス期間
に対応した各発光設定期間に発光すべき電界発光素子
に、出力する複数の第１スイッチング回路と、 前記各電界発光素子の前記一対の電極の他方のそれぞれ
に接続され、前記各発光設定期間に、前記接地電圧或い
は前記駆動電圧の他方を、前記全電界発光素子に出力す
る第２スイッチング回路と、 を具備することを特徴とする電界発光表示装置。1. A plurality of electroluminescent elements each having a pair of electrodes and emitting light in response to application of a voltage, connected to one of the pair of electrodes of each of the electroluminescent elements, and connected to each of the address periods. A plurality of first switching circuits that output one of a ground voltage and a driving voltage having a constant voltage value to an electroluminescent element to emit light in each light emission setting period corresponding to each address period; A second switching circuit that is connected to each of the other of the pair of electrodes of the element and outputs the other of the ground voltage or the drive voltage to the entire electroluminescent element during each of the light emission setting periods. An electroluminescent display device characterized by the above-mentioned. 【請求項２】 前記電界発光素子はマトリクス状に配列
され、１フレーム期間は、前記複数のアドレス期間と、
各アドレス期間にそれぞれ対応し且つ互いに異なる長さ
の時間である複数の発光設定期間と、からなることを特
徴とする請求項１記載の電界発光表示装置。2. The method according to claim 1, wherein the electroluminescent elements are arranged in a matrix, and one frame period includes the plurality of address periods.
2. The electroluminescent display device according to claim 1, comprising a plurality of light emission setting periods respectively corresponding to each address period and having different lengths. 【請求項３】 前記第１スイッチング回路は、走査電圧
が供給される走査ラインにゲート電極が接続され且つ信
号電圧が供給される信号ラインにドレイン電極が接続さ
れた選択トランジスタと、ゲート電極が前記選択トラン
ジスタのソース電極に接続され、且つドレイン電極が前
記電界発光素子に接続されると共に、ソース電極が接地
或いは前記駆動電圧のいずれか一方を出力する駆動電源
に接続された駆動トランジスタと、を備えることを特徴
とする請求項１または請求項２に記載の電界発光表示装
置。3. The first switching circuit according to claim 1, wherein the first switching circuit includes a selection transistor having a gate electrode connected to a scan line to which a scan voltage is supplied, and a drain electrode connected to a signal line to which a signal voltage is supplied. A drive transistor connected to a source electrode of the select transistor, a drain electrode connected to the electroluminescent element, and a source electrode connected to a drive power supply that outputs one of the ground and the drive voltage. The electroluminescent display device according to claim 1 or 2, wherein: 【請求項４】 前記走査電圧および前記信号電圧は、そ
れぞれの特性に応じたオン／オフの２値信号であること
を特徴とする請求項３記載の電界発光表示装置。4. The electroluminescent display device according to claim 3, wherein the scanning voltage and the signal voltage are ON / OFF binary signals corresponding to respective characteristics. 【請求項５】 前記第２スイッチング回路には、オン／
オフの２値信号が入力されることを特徴とする請求項１
〜請求項４のいずれかに記載の電界発光表示装置。5. The method according to claim 1, wherein the second switching circuit includes an on / off switch.
2. An off-state binary signal is input.
The electroluminescent display device according to claim 4. 【請求項６】 前記各発光設定期間の時間の長さの比率
は、それぞれ２のｎ乗（ｎは０以上の整数）のいずれか
であることを特徴とする請求項１〜請求項５のいずれか
に記載の電界発光表示装置。6. The method according to claim 1, wherein a ratio of a length of time of each of the light emission setting periods is any one of 2 n (n is an integer of 0 or more). The electroluminescent display device according to any one of the above. 【請求項７】 電圧の印加に応じて発光する複数の電界
発光素子を有する電界発光表示装置の駆動方法におい
て、 １フレーム期間が、それぞれ任意の前記電界発光素子を
選択する、複数のアドレス期間を備え、且つそれぞれの
前記アドレス期間の後に、当該アドレス期間で選択され
た前記電界発光素子に駆動電圧を供給する、互いに異な
る長さの時間に設定された駆動電圧供給期間を備えるこ
とを特徴とする電界発光表示装置の駆動方法。7. A method for driving an electroluminescent display device having a plurality of electroluminescent elements which emit light in response to application of a voltage, wherein one frame period includes a plurality of address periods for selecting any of the electroluminescent elements. And a driving voltage supply period that is set to a different length of time for supplying a driving voltage to the electroluminescent element selected in the address period after each of the address periods. A method for driving an electroluminescent display device. 【請求項８】 前記複数の電界発光素子は、それぞれ一
対の電極を有し、前記複数の電界発光素子の前記一対の
電極の一方はそれぞれに対応した複数の第１スイッチン
グ回路に接続され、前記複数の電界発光素子の前記一対
の電極の他方はそれぞれ第２スイッチング回路に接続さ
れ、前記第１スイッチング回路は、前記各アドレス期間
毎に前記電界発光素子を選択して接地電圧或いは一定電
圧値の駆動電圧のいずれか一方を出力し、前記第２スイ
ッチング回路は、前記各アドレス期間に応じて選択され
た電界発光素子を前記各アドレス期間に対応する前記駆
動電圧供給期間に前記接地電圧或いは前記駆動電圧のい
ずれか他方を出力することを特徴とする請求項７に記載
の電界発光表示装置の駆動方法。8. The plurality of electroluminescent devices each have a pair of electrodes, and one of the pair of electrodes of the plurality of electroluminescent devices is connected to a plurality of first switching circuits respectively corresponding to the plurality of electroluminescent devices, The other of the pair of electrodes of the plurality of electroluminescent elements is respectively connected to a second switching circuit, and the first switching circuit selects the electroluminescent element for each of the address periods and selects a ground voltage or a fixed voltage value. The second switching circuit outputs the ground voltage or the drive voltage to the electroluminescent element selected according to each of the address periods during the drive voltage supply period corresponding to each of the address periods. 8. The method according to claim 7, wherein the other of the voltages is output. 【請求項９】 前記第１スイッチング回路は、走査電圧
が供給される走査ラインにゲート電極が接続され、信号
電圧が供給される信号ラインにドレイン電極が接続され
た選択トランジスタと、ゲート電極が前記選択トランジ
スタのソース電極に接続され、ドレイン電極が前記電界
発光素子に接続され、ソース電極が前記接地電圧或いは
前記駆動電圧の一方を入力する駆動トランジスタと、を
備えることを特徴とする請求項８記載の電界発光表示装
置の駆動方法。9. The selection transistor, wherein the first switching circuit has a gate electrode connected to a scan line to which a scan voltage is supplied, and a drain electrode connected to a signal line to which a signal voltage is supplied, and a gate electrode, 9. The driving transistor connected to a source electrode of the selection transistor, a drain electrode connected to the electroluminescent element, and a source electrode including a driving transistor for inputting one of the ground voltage or the driving voltage. Driving method of the electroluminescent display device. 【請求項１０】 前記走査電圧、前記信号電圧および前
記第２スイッチング回路は、それぞれの特性に応じたオ
ン／オフの２値信号が入力されることを特徴とする請求
項９記載の電界発光表示装置の駆動方法。10. The electroluminescent display according to claim 9, wherein the scanning voltage, the signal voltage, and the second switching circuit are supplied with on / off binary signals corresponding to respective characteristics. How to drive the device. 【請求項１１】 前記電界発光素子はマトリクス状に配
列され、前記１フレーム期間は、前記アドレス期間と駆
動電圧供給期間とが交互に設定されることを特徴とする
請求項７〜請求項１０のいずれかに記載の電界発光表示
装置の駆動方法。11. The device according to claim 7, wherein the electroluminescent elements are arranged in a matrix, and in the one frame period, the address period and the drive voltage supply period are set alternately. A driving method of the electroluminescent display device according to any one of the above. 【請求項１２】 前記各駆動電圧供給期間の時間の長さ
の比率は、それぞれ２のｎ乗（ｎは０以上の整数）のい
ずれかであることを特徴とする請求項７〜請求項１１の
いずれかに記載の電界発光表示装置の駆動方法。12. The method according to claim 7, wherein a ratio of a time length of each of the drive voltage supply periods is any of 2 to the n-th power (n is an integer of 0 or more). The driving method of the electroluminescent display device according to any one of the above.
JP9027323A 1997-01-28 1997-01-28 Electric field light emission display device and its driving method Abandoned JPH10214060A (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
JP9027323A JPH10214060A (en) 1997-01-28 1997-01-28 Electric field light emission display device and its driving method
TW087101059A TW441136B (en) 1997-01-28 1998-01-26 An electroluminescent display device and a driving method thereof
US09/013,708 US5990629A (en) 1997-01-28 1998-01-26 Electroluminescent display device and a driving method thereof
KR1019980707622A KR100293329B1 (en) 1997-01-28 1998-01-27 Active Matrix Electroluminescent Display and Driving Method
CA002249592A CA2249592C (en) 1997-01-28 1998-01-27 Active matrix electroluminescent display device and a driving method thereof
EP98900761A EP0906609A1 (en) 1997-01-28 1998-01-27 Active matrix electroluminescent display device and a driving method thereof
CNB988000679A CN1151483C (en) 1997-01-28 1998-01-27 Electroluminescent display device and driving method thereof
PCT/JP1998/000327 WO1998033165A1 (en) 1997-01-28 1998-01-27 Active matrix electroluminescent display device and a driving method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9027323A JPH10214060A (en) 1997-01-28 1997-01-28 Electric field light emission display device and its driving method

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