CN111508899A - Preparation method of semiconductor package - Google Patents
Preparation method of semiconductor package Download PDFInfo
- Publication number
- CN111508899A CN111508899A CN202010371287.4A CN202010371287A CN111508899A CN 111508899 A CN111508899 A CN 111508899A CN 202010371287 A CN202010371287 A CN 202010371287A CN 111508899 A CN111508899 A CN 111508899A
- Authority
- CN
- China
- Prior art keywords
- semiconductor chip
- grooves
- conductive structure
- forming
- pits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
- H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
Abstract
The invention provides a preparation method of a semiconductor package, which comprises the following steps: the method comprises the steps of arranging a first semiconductor chip on a first carrier plate, forming a plurality of first grooves on the peripheral side face of the first semiconductor chip, forming a first conductive structure in the first grooves, forming a first wiring layer on the second surface of the first semiconductor chip, arranging a second semiconductor chip on the first semiconductor chip, forming a plurality of second grooves on the peripheral side face of the second semiconductor chip, forming a second conductive structure in the second grooves, forming a second wiring layer on the upper surface of the second semiconductor chip, arranging a third semiconductor chip on the second semiconductor chip, forming a packaging adhesive layer to cover the first, second and third semiconductor chips, and mounting the first semiconductor chip on a circuit substrate.
Description
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a preparation method of a semiconductor package.
Background
Semiconductor package is meant to pass the testWaferAnd processing to obtain the independent chip according to the product model and the functional requirements. The packaging process comprises the following steps: the wafer from the previous wafer process is diced into small chips (Die) through a dicing process, and the diced chips are attached to corresponding substrates with glue (c)Lead wireFrame structure) The method comprises the steps of connecting a bonding Pad (Bond Pad) of a wafer to a corresponding pin (L ead) of a substrate on a small island of a rack by using an ultrafine metal (gold tin copper aluminum) wire or conductive resin to form a required circuit, packaging and protecting an independent wafer by using a plastic shell, carrying out a series of operations after plastic packaging, carrying out finished product testing after packaging, generally carrying out procedures of Incoming inspection, testing, packaging and the like, and finally warehousing and shipping.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned deficiencies of the prior art and providing a method for manufacturing a semiconductor package.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor package, comprising the steps of:
(1) providing a first carrier board, arranging a first semiconductor chip on the first carrier board, wherein the first semiconductor chip comprises a first surface and a second surface, arranging a source region and a conductive pad on the first surface of the first semiconductor chip, and fixing the first surface of the first semiconductor chip on the first carrier board through a temporary adhesive film.
(2) Forming a plurality of first grooves on the peripheral side surface of the first semiconductor chip, wherein the first grooves penetrate through the first semiconductor chip, then forming a plurality of first pits on the bottom and the side wall of the first grooves through a laser ablation process, and then forming a first insulating medium layer on the peripheral side surface of the first semiconductor chip and the second surface through a thermal oxidation process, so that the first insulating medium layer is formed on the bottom of the first grooves, the side wall of the first grooves and the first pits.
(3) A first conductive structure is then formed in the first trench such that portions of the first conductive structure are embedded in the first pits, thereby forming a plurality of second pits in a surface of the first conductive structure.
(4) A first wiring layer is then formed on the second surface of the first semiconductor chip, the first wiring layer being electrically connected to the first conductive structure.
(5) And arranging a second semiconductor chip on the first semiconductor chip, wherein a source region and a conductive bonding pad are arranged on the lower surface of the second semiconductor chip, and the conductive bonding pad of the second semiconductor chip is electrically connected with the first wiring layer.
(6) Forming a plurality of second grooves on the peripheral side face of the second semiconductor chip, wherein the second grooves penetrate through the second semiconductor chip, then forming a plurality of third pits on the bottom and the side wall of the second grooves through a laser ablation process, and then forming second insulating medium layers on the peripheral side face and the upper surface of the second semiconductor chip through a thermal oxidation process, so that the second insulating medium layers are formed on the bottom of the second grooves, the side wall of the second grooves and the third pits.
(7) And then forming a second conductive structure in the second groove, so that part of the second conductive structure is embedded into the third pits, so that the second conductive structure is electrically connected with the first wiring layer, and further forming a plurality of fourth pits on the surface of the second conductive structure.
(8) A second wiring layer is then formed on the upper surface of the second semiconductor chip, the second wiring layer being electrically connected to the second conductive structure.
(9) And arranging a third semiconductor chip on the second semiconductor chip, wherein a source region and a conductive bonding pad are arranged on the lower surface of the third semiconductor chip, and the conductive bonding pad of the third semiconductor chip is electrically connected with the second wiring layer.
(10) And then forming an encapsulation adhesive layer to cover the first, second and third semiconductor chips, embedding part of the encapsulation adhesive layer into the second concave pit and the fourth concave pit, and then removing the first carrier plate.
(11) Providing a circuit substrate, and mounting the first semiconductor chip on the circuit substrate, so that the conductive pad of the first semiconductor chip is electrically connected with the circuit substrate, and the first conductive structure is electrically connected with the circuit substrate.
Preferably, the material of the first carrier plate is one of a plastic plate, a silicon substrate, a glass plate, a ceramic plate, a germanium substrate, and a sapphire substrate.
Preferably, in the step (2), the first trench is formed by wet etching or dry etching, the plurality of first trenches are arranged at intervals, the depth of the first trench is 10-100 micrometers, the width of the first trench is 100-300 micrometers, the plurality of first pits are arranged randomly, and the depth of the first pit is 500-2000 nanometers.
Preferably, in the steps (3) and (7), the material of the first conductive structure and the second conductive structure includes one or more of gold, titanium, chromium, copper, aluminum, silver, palladium, nickel, tungsten, ITO, AZO, and FTO, and the first conductive structure and the second conductive structure are formed by one of magnetron sputtering, thermal evaporation, electron beam evaporation, electroplating, electroless plating, and physical vapor deposition.
Preferably, in the steps (4) and (8), the first wiring layer and the second wiring layer include a dielectric layer and a patterned metal layer.
Preferably, in the step (6), the second grooves are formed by wet etching or dry etching, the plurality of second grooves are arranged at intervals, the depth of the second grooves is 6-50 micrometers, the width of the second grooves is 50-100 micrometers, the plurality of third pits are arranged randomly, and the depth of the third pits is 400 nanometers-1500 nanometers.
Preferably, in the step (10), the encapsulation adhesive layer is one of silicon gel, epoxy resin and silicon gel.
Compared with the prior art, the invention has the following advantages:
in the preparation process of the semiconductor package, a plurality of first grooves are formed on the peripheral side face of a first semiconductor chip, a plurality of first pits are formed on the bottom and the side wall of each first groove through a laser ablation process, a conductive structure is embedded into each first groove, a plurality of second pits are formed on the surface of each first conductive structure, a first wiring layer is formed on the second surface of the first semiconductor chip, the first wiring layer is electrically connected with the first conductive structure, a second semiconductor chip is arranged on the first semiconductor chip, a similar structure is formed on the second semiconductor chip, and a third semiconductor chip is mounted. The arrangement of the structure avoids the use of a circuit board, and effectively utilizes the edge area of the semiconductor chip to form a conductive path, thereby being convenient for forming a miniaturized, low-cost and high-integration semiconductor package. In the preparation process of the semiconductor package, the first conductive structure and the second conductive structure are embedded into the corresponding first pit and the third pit, the second pit and the fourth pit are formed on the first conductive structure and the second conductive structure, the package adhesive layer is formed to cover the first semiconductor chip, the second semiconductor chip and the third semiconductor chip, and part of the package adhesive layer is embedded into the second pit and the fourth pit.
Drawings
Fig. 1-4 are schematic structural views illustrating a manufacturing process of a semiconductor package according to an embodiment of the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
The invention provides a preparation method of a semiconductor package, which comprises the following steps:
(1) providing a first carrier board, arranging a first semiconductor chip on the first carrier board, wherein the first semiconductor chip comprises a first surface and a second surface, arranging a source region and a conductive pad on the first surface of the first semiconductor chip, and fixing the first surface of the first semiconductor chip on the first carrier board through a temporary adhesive film.
(2) Forming a plurality of first grooves on the peripheral side surface of the first semiconductor chip, wherein the first grooves penetrate through the first semiconductor chip, then forming a plurality of first pits on the bottom and the side wall of the first grooves through a laser ablation process, and then forming a first insulating medium layer on the peripheral side surface of the first semiconductor chip and the second surface through a thermal oxidation process, so that the first insulating medium layer is formed on the bottom of the first grooves, the side wall of the first grooves and the first pits.
(3) A first conductive structure is then formed in the first trench such that portions of the first conductive structure are embedded in the first pits, thereby forming a plurality of second pits in a surface of the first conductive structure.
(4) A first wiring layer is then formed on the second surface of the first semiconductor chip, the first wiring layer being electrically connected to the first conductive structure.
(5) And arranging a second semiconductor chip on the first semiconductor chip, wherein a source region and a conductive bonding pad are arranged on the lower surface of the second semiconductor chip, and the conductive bonding pad of the second semiconductor chip is electrically connected with the first wiring layer.
(6) Forming a plurality of second grooves on the peripheral side face of the second semiconductor chip, wherein the second grooves penetrate through the second semiconductor chip, then forming a plurality of third pits on the bottom and the side wall of the second grooves through a laser ablation process, and then forming second insulating medium layers on the peripheral side face and the upper surface of the second semiconductor chip through a thermal oxidation process, so that the second insulating medium layers are formed on the bottom of the second grooves, the side wall of the second grooves and the third pits.
(7) And then forming a second conductive structure in the second groove, so that part of the second conductive structure is embedded into the third pits, so that the second conductive structure is electrically connected with the first wiring layer, and further forming a plurality of fourth pits on the surface of the second conductive structure.
(8) A second wiring layer is then formed on the upper surface of the second semiconductor chip, the second wiring layer being electrically connected to the second conductive structure.
(9) And arranging a third semiconductor chip on the second semiconductor chip, wherein a source region and a conductive bonding pad are arranged on the lower surface of the third semiconductor chip, and the conductive bonding pad of the third semiconductor chip is electrically connected with the second wiring layer.
(10) And then forming an encapsulation adhesive layer to cover the first, second and third semiconductor chips, embedding part of the encapsulation adhesive layer into the second concave pit and the fourth concave pit, and then removing the first carrier plate.
(11) Providing a circuit substrate, and mounting the first semiconductor chip on the circuit substrate, so that the conductive pad of the first semiconductor chip is electrically connected with the circuit substrate, and the first conductive structure is electrically connected with the circuit substrate.
Further, the material of the first carrier plate is one of a plastic plate, a silicon substrate, a glass plate, a ceramic plate, a germanium substrate and a sapphire substrate.
Further, in the step (2), the first trenches are formed by wet etching or dry etching, the plurality of first trenches are arranged at intervals, the depth of the first trenches is 10-100 micrometers, the width of the first trenches is 100-300 micrometers, the plurality of first pits are arranged randomly, and the depth of the first pits is 500-2000 nanometers.
Further, in the steps (3) and (7), the material of the first conductive structure and the second conductive structure includes one or more of gold, titanium, chromium, copper, aluminum, silver, palladium, nickel, tungsten, ITO, AZO, and FTO, and the first conductive structure and the second conductive structure are formed by one of magnetron sputtering, thermal evaporation, electron beam evaporation, electroplating, electroless plating, and physical vapor deposition.
Further, in the steps (4) and (8), the first wiring layer and the second wiring layer include a dielectric layer and a patterned metal layer.
Further, in the step (6), the second grooves are formed by wet etching or dry etching, the plurality of second grooves are arranged at intervals, the depth of the second grooves is 6-50 micrometers, the width of the second grooves is 50-100 micrometers, the plurality of third pits are arranged randomly, and the depth of the third pits is 400 nanometers-1500 nanometers.
Further, in the step (10), the encapsulation adhesive layer is one of silicon gel, epoxy resin and silicon gel.
Please refer to fig. 1 to 4. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1 to 4, the present embodiment provides a method for manufacturing a semiconductor package, the method including the steps of:
as shown in fig. 1, which is a top view, first, step (1) is performed, a first carrier board 1 is provided, a first semiconductor chip 2 is disposed on the first carrier board 1, the first semiconductor chip 2 includes a first surface and a second surface, a source region and a conductive pad are disposed on the first surface of the first semiconductor chip 2, and the first surface of the first semiconductor chip 2 is fixed on the first carrier board 1 through a temporary adhesive film. The material of the first carrier plate 1 is one of a plastic plate, a silicon substrate, a glass plate, a ceramic plate, a germanium substrate and a sapphire substrate, and the temporary adhesive film may lose its adhesiveness in a light or heat state to facilitate the dissociation of the first semiconductor chip 2.
Then, step (2) is performed, a plurality of first trenches 21 are formed on the peripheral side surface of the first semiconductor chip 2, the first trenches 21 penetrate through the first semiconductor chip 2, a plurality of first pits are formed on the bottom and the side wall of the first trenches 21 through a laser ablation process, a first insulating medium layer is formed on the peripheral side surface and the second surface of the first semiconductor chip 2 through a thermal oxidation process, and the first insulating medium layer is formed on the bottom of the first trenches 21, the side wall of the first trenches 21, and the first pits.
In a specific embodiment, the first trench 21 is formed by wet etching or dry etching, the plurality of first trenches 21 are arranged at intervals, the depth of the first trench 21 is 10-100 micrometers, the width of the first trench 21 is 100-300 micrometers, the plurality of first pits are arranged randomly, the depth of the first pit is 500 nanometers-2000 nanometers, preferably, the depth of the first trench 21 is 30-80 micrometers, the width of the first trench 21 is 150-250 micrometers, the depth of the first pit is 800 nanometers-1500 nanometers, further, the depth of the first trench 21 is 50-60 micrometers, the width of the first trench 21 is 180-220 micrometers, the depth of the first pit is 1000 nanometers-1200 nanometers, and by optimizing the size of the first trench and the size of the first pit, the thickness of the first insulating dielectric layer is 50-200 nm, and specifically, the thickness of the first insulating dielectric layer is 100-150 nm.
Then, step (3) is performed, and then a first conductive structure 3 is formed in the first trench 21, so that a portion of the first conductive structure 3 is embedded into the first pit, and then a plurality of second pits are formed on the surface of the first conductive structure 3, and further the depth of each second pit is 200 nm to 1500 nm, further the depth of each second pit is 500 nm to 1200 nm, and further the depth of each second pit is 800 nm to 1000 nm.
Wherein the first conductive structure 3 comprises one or more of gold, titanium, chromium, copper, aluminum, silver, palladium, nickel, tungsten, ITO, AZO, and FTO, the first conductive structure 3 is formed by one of magnetron sputtering, thermal evaporation, electron beam evaporation, electroplating, chemical plating, and physical vapor deposition, and in a specific embodiment, the first conductive structure 3 is copper and is formed by thermal evaporation.
As shown in fig. 2, which is a cross-sectional view, step (4) is then performed to form a first wiring layer 4 on the second surface of the first semiconductor chip 2, the first wiring layer 4 is electrically connected to the first conductive structure 3, and the first wiring layer 4 includes a dielectric layer and a patterned metal layer. In a specific embodiment, the dielectric layer is formed by deposition through a chemical vapor deposition process, an atomic layer deposition process or a physical vapor deposition process, the material of the dielectric layer may be one or more of silicon oxide, silicon nitride, silicon oxynitride and aluminum oxide, the patterned metal layer may be formed through evaporation, magnetron sputtering, electroplating or chemical plating, and the material of the patterned metal layer is one or a combination of two or more of titanium, palladium, silver, copper, aluminum and nickel.
Next, step (5) is performed, in which a second semiconductor chip 5 is provided on the first semiconductor chip 2, a source region and a conductive pad are provided on a lower surface of the second semiconductor chip 5, and the conductive pad of the second semiconductor chip 5 is electrically connected to the first wiring layer 4.
As shown in fig. 3, which is a top view, a step (6) is performed to form a plurality of second trenches 51 on the peripheral side surfaces of the second semiconductor chip 5, where the second trenches 51 penetrate through the second semiconductor chip 5, then form a plurality of third pits on the bottom and the side walls of the second trenches 51 through a laser ablation process, then form a second insulating medium layer on the peripheral side surfaces and the upper surface of the second semiconductor chip 5 through a thermal oxidation process, and further form the second insulating medium layer on the bottom of the second trenches 51, the side walls of the second trenches 51, and the third pits.
In a specific embodiment, the second trench 51 is formed by wet etching or dry etching, the second trenches 51 are arranged at intervals, the depth of the second trenches is 6 to 50 micrometers, the width of the second trenches is 50 to 100 micrometers, the third pits are arranged randomly, the depth of each third pit is 400 nanometers to 1500 nanometers, preferably, the depth of each second trench is 10 to 40 micrometers, the width of each second trench is 60 to 90 micrometers, the depth of each third pit is 600 nanometers to 1200 nanometers, further, the depth of each second trench is 20 to 30 micrometers, the width of each second trench is 70 to 80 micrometers, and the depth of each third pit is 800 nanometers to 1000 nanometers, so as to facilitate stability of a subsequently formed conductive structure by optimizing the size of each second trench and the size of each third pit, the thickness of the second insulating medium layer is 50-180 nm, and specifically, the thickness of the first insulating medium layer is 90-120 nm.
And (7) forming a second conductive structure 6 in the second groove 51, so that a part of the second conductive structure 6 is embedded into the third recess, so that the second conductive structure 6 is electrically connected with the first wiring layer 4, thereby forming a plurality of fourth recesses on the surface of the second conductive structure 6, thereby making the depth of the fourth recesses 300 nm to 1200 nm, further making the depth of the fourth recesses 400 nm to 1000 nm, and further making the depth of the fourth recesses 600 nm to 800 nm.
Wherein the second conductive structure 6 comprises one or more of gold, titanium, chromium, copper, aluminum, silver, palladium, nickel, tungsten, ITO, AZO, and FTO, the second conductive structure 6 is formed by one of magnetron sputtering, thermal evaporation, electron beam evaporation, electroplating, chemical plating, and physical vapor deposition, and in a specific embodiment, the second conductive structure 6 is copper and is formed by thermal evaporation.
As shown in fig. 4, which is a cross-sectional view, next, step (8) is performed to form a second wiring layer 7 on the upper surface of the second semiconductor chip 5, where the second wiring layer 7 is electrically connected to the second conductive structure 6, and the second wiring layer 7 includes a dielectric layer and a patterned metal layer. In a specific embodiment, the dielectric layer is formed by deposition through a chemical vapor deposition process, an atomic layer deposition process or a physical vapor deposition process, the material of the dielectric layer may be one or more of silicon oxide, silicon nitride, silicon oxynitride and aluminum oxide, the patterned metal layer may be formed through evaporation, magnetron sputtering, electroplating or chemical plating, and the material of the patterned metal layer is one or a combination of two or more of titanium, palladium, silver, copper, aluminum and nickel.
And (9) arranging a third semiconductor chip 8 on the second semiconductor chip 5, wherein a source region and a conductive pad are arranged on the lower surface of the third semiconductor chip 8, and the conductive pad of the third semiconductor chip 8 is electrically connected with the second wiring layer 7.
Then, step (10) is performed to form an encapsulation adhesive layer 9 to cover the first, second, and third semiconductor chips 2,5,8, and a portion of the encapsulation adhesive layer 9 is embedded into the second recess and the fourth recess, where the encapsulation adhesive 9 is one of epoxy resin and silicone, and specifically, the encapsulation adhesive layer 9 may be formed by using a mold, and then the first carrier is removed.
Next, step (11) is performed, a circuit board 10 is provided, and the first semiconductor chip 2 is mounted on the circuit board 10, so that the conductive pad of the first semiconductor chip 2 is electrically connected to the circuit board 10, and the first conductive structure 3 is electrically connected to the circuit board.
In the preparation process of the semiconductor package, a plurality of first grooves are formed on the peripheral side face of a first semiconductor chip, a plurality of first pits are formed on the bottom and the side wall of each first groove through a laser ablation process, a conductive structure is embedded into each first groove, a plurality of second pits are formed on the surface of each first conductive structure, a first wiring layer is formed on the second surface of the first semiconductor chip, the first wiring layer is electrically connected with the first conductive structure, a second semiconductor chip is arranged on the first semiconductor chip, a similar structure is formed on the second semiconductor chip, and a third semiconductor chip is mounted. The arrangement of the structure avoids the use of a circuit board, and effectively utilizes the edge area of the semiconductor chip to form a conductive path, thereby being convenient for forming a miniaturized, low-cost and high-integration semiconductor package. In the preparation process of the semiconductor package, the first conductive structure and the second conductive structure are embedded into the corresponding first pit and the third pit, the second pit and the fourth pit are formed on the first conductive structure and the second conductive structure, the package adhesive layer is formed to cover the first semiconductor chip, the second semiconductor chip and the third semiconductor chip, and part of the package adhesive layer is embedded into the second pit and the fourth pit.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (7)
1. A method for manufacturing a semiconductor package, comprising: the method comprises the following steps:
(1) providing a first carrier board, arranging a first semiconductor chip on the first carrier board, wherein the first semiconductor chip comprises a first surface and a second surface, an active area and a conductive pad are arranged on the first surface of the first semiconductor chip, and the first surface of the first semiconductor chip is fixed on the first carrier board through a temporary adhesive film;
(2) forming a plurality of first grooves on the peripheral side surface of the first semiconductor chip, wherein the first grooves penetrate through the first semiconductor chip, then forming a plurality of first pits on the bottom and the side wall of the first grooves through a laser ablation process, and then forming a first insulating medium layer on the peripheral side surface of the first semiconductor chip and the second surface through a thermal oxidation process, so that the first insulating medium layer is formed on the bottom of the first grooves, the side wall of the first grooves and the first pits;
(3) then forming a first conductive structure in the first groove, so that part of the first conductive structure is embedded into the first pits, and further forming a plurality of second pits on the surface of the first conductive structure;
(4) then forming a first wiring layer on the second surface of the first semiconductor chip, the first wiring layer being electrically connected to the first conductive structure;
(5) arranging a second semiconductor chip on the first semiconductor chip, wherein a source region and a conductive bonding pad are arranged on the lower surface of the second semiconductor chip, and the conductive bonding pad of the second semiconductor chip is electrically connected with the first wiring layer;
(6) forming a plurality of second grooves on the peripheral side face of the second semiconductor chip, wherein the second grooves penetrate through the second semiconductor chip, then forming a plurality of third pits on the bottom and the side wall of the second grooves through a laser ablation process, and then forming a second insulating medium layer on the peripheral side face and the upper surface of the second semiconductor chip through a thermal oxidation process, so that the second insulating medium layer is formed on the bottom of the second grooves, the side wall of the second grooves and the third pits;
(7) then forming a second conductive structure in the second groove, so that part of the second conductive structure is embedded into the third pits, so that the second conductive structure is electrically connected with the first wiring layer, and further forming a plurality of fourth pits on the surface of the second conductive structure;
(8) then forming a second wiring layer on the upper surface of the second semiconductor chip, wherein the second wiring layer is electrically connected with the second conductive structure;
(9) arranging a third semiconductor chip on the second semiconductor chip, wherein a source region and a conductive bonding pad are arranged on the lower surface of the third semiconductor chip, and the conductive bonding pad of the third semiconductor chip is electrically connected with the second wiring layer;
(10) forming a packaging adhesive layer to cover the first, second and third semiconductor chips, embedding part of the packaging adhesive layer into the second concave pit and the fourth concave pit, and removing the first carrier plate;
(11) providing a circuit substrate, and mounting the first semiconductor chip on the circuit substrate, so that the conductive pad of the first semiconductor chip is electrically connected with the circuit substrate, and the first conductive structure is electrically connected with the circuit substrate.
2. The method for manufacturing a semiconductor package according to claim 1, wherein: the material of the first carrier plate is one of a plastic plate, a silicon substrate, a glass plate, a ceramic plate, a germanium substrate and a sapphire substrate.
3. The method for manufacturing a semiconductor package according to claim 1, wherein: in the step (2), the first grooves are formed by wet etching or dry etching, the first grooves are arranged at intervals, the depth of the first grooves is 10-100 micrometers, the width of the first grooves is 100-300 micrometers, the first pits are randomly arranged, and the depth of the first pits is 500-2000 nanometers.
4. The method for manufacturing a semiconductor package according to claim 1, wherein: in the steps (3) and (7), the material of the first conductive structure and the second conductive structure includes one or more of gold, titanium, chromium, copper, aluminum, silver, palladium, nickel, tungsten, ITO, AZO, and FTO, and the first conductive structure and the second conductive structure are formed by one of magnetron sputtering, thermal evaporation, electron beam evaporation, electroplating, electroless plating, and physical vapor deposition.
5. The method for manufacturing a semiconductor package according to claim 1, wherein: in the steps (4) and (8), the first wiring layer and the second wiring layer include a dielectric layer and a patterned metal layer.
6. The method for manufacturing a semiconductor package according to claim 1, wherein: in the step (6), the second grooves are formed by wet etching or dry etching, the plurality of second grooves are arranged at intervals, the depth of the second grooves is 6-50 micrometers, the width of the second grooves is 50-100 micrometers, the plurality of third pits are arranged randomly, and the depth of the third pits is 400 nanometers-1500 nanometers.
7. The method for manufacturing a semiconductor package according to claim 1, wherein: in the step (10), the encapsulation adhesive layer is one of silicon gel, epoxy resin and silicon gel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010371287.4A CN111508899B (en) | 2020-05-06 | 2020-05-06 | Preparation method of semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010371287.4A CN111508899B (en) | 2020-05-06 | 2020-05-06 | Preparation method of semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111508899A true CN111508899A (en) | 2020-08-07 |
| CN111508899B CN111508899B (en) | 2022-02-11 |
Family
ID=71864412
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010371287.4A Active CN111508899B (en) | 2020-05-06 | 2020-05-06 | Preparation method of semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111508899B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112053962A (en) * | 2020-09-14 | 2020-12-08 | 山东傲天环保科技有限公司 | System-level stack package and preparation method thereof |
| CN112382575A (en) * | 2020-11-11 | 2021-02-19 | 济南南知信息科技有限公司 | Semiconductor storage package for 5G equipment and preparation method thereof |
| CN114161591A (en) * | 2021-12-03 | 2022-03-11 | 江西省纳米技术研究院 | Nondestructive cleavage method for semiconductor chip |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010129172A2 (en) * | 2009-04-28 | 2010-11-11 | Wafer-Level Packaging Portfolio Llc | Dual interconnection in stacked memory and controller module |
| US20120115278A1 (en) * | 2007-10-16 | 2012-05-10 | Hynix Semiconductor Inc. | Stacked semiconductor package without reduction in data storage capacity and method for manufacturing the same |
| EP2455968A1 (en) * | 2010-11-23 | 2012-05-23 | Honeywell International, Inc. | Batch fabricated 3d interconnect |
| CN108630625A (en) * | 2017-03-15 | 2018-10-09 | 南茂科技股份有限公司 | Semiconductor packaging structure, semiconductor wafer and semiconductor chip |
| CN110943041A (en) * | 2019-12-16 | 2020-03-31 | 山东砚鼎电子科技有限公司 | Semiconductor structure with side surface led out, manufacturing method thereof and stacking structure |
-
2020
- 2020-05-06 CN CN202010371287.4A patent/CN111508899B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120115278A1 (en) * | 2007-10-16 | 2012-05-10 | Hynix Semiconductor Inc. | Stacked semiconductor package without reduction in data storage capacity and method for manufacturing the same |
| WO2010129172A2 (en) * | 2009-04-28 | 2010-11-11 | Wafer-Level Packaging Portfolio Llc | Dual interconnection in stacked memory and controller module |
| EP2455968A1 (en) * | 2010-11-23 | 2012-05-23 | Honeywell International, Inc. | Batch fabricated 3d interconnect |
| CN108630625A (en) * | 2017-03-15 | 2018-10-09 | 南茂科技股份有限公司 | Semiconductor packaging structure, semiconductor wafer and semiconductor chip |
| CN110943041A (en) * | 2019-12-16 | 2020-03-31 | 山东砚鼎电子科技有限公司 | Semiconductor structure with side surface led out, manufacturing method thereof and stacking structure |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112053962A (en) * | 2020-09-14 | 2020-12-08 | 山东傲天环保科技有限公司 | System-level stack package and preparation method thereof |
| CN112053962B (en) * | 2020-09-14 | 2022-09-27 | 苏州钜升精密模具有限公司 | System-level stack package and preparation method thereof |
| CN112382575A (en) * | 2020-11-11 | 2021-02-19 | 济南南知信息科技有限公司 | Semiconductor storage package for 5G equipment and preparation method thereof |
| CN112382575B (en) * | 2020-11-11 | 2022-09-30 | 苏州明彰半导体技术有限公司 | Semiconductor storage package for 5G equipment and preparation method thereof |
| CN114161591A (en) * | 2021-12-03 | 2022-03-11 | 江西省纳米技术研究院 | Nondestructive cleavage method for semiconductor chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111508899B (en) | 2022-02-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN210006732U (en) | Chip packaging structure | |
| TWI619218B (en) | Chip package and method for forming the same | |
| US8110900B2 (en) | Manufacturing process of semiconductor device and semiconductor device | |
| CN101800207B (en) | Packaging structure of semiconductor element and manufacture method thereof | |
| CN111508899B (en) | Preparation method of semiconductor package | |
| TWM591703U (en) | Chip structure | |
| TWI517322B (en) | Semiconductor device and method of manufacturing the same | |
| US20110057321A1 (en) | 3-d multi-wafer stacked semiconductor structure and method for manufacturing the same | |
| TW201742223A (en) | Semiconductor package | |
| JP5942823B2 (en) | Electronic component device manufacturing method, electronic component device, and electronic device | |
| US11233028B2 (en) | Chip packaging method and chip structure | |
| WO2011120389A1 (en) | Semiconductor package and method of manufacturing the same | |
| TWI233188B (en) | Quad flat no-lead package structure and manufacturing method thereof | |
| TWI567894B (en) | Chip package | |
| CN101807560A (en) | Packaging structure of semiconductor device and manufacture method thereof | |
| KR20110107989A (en) | Method for forming stacked semiconductor package | |
| CN112420641A (en) | Power element packaging structure and preparation method thereof | |
| US20170278810A1 (en) | Embedded die in panel method and structure | |
| KR102619532B1 (en) | Semiconductor Package | |
| CN109037082B (en) | Package structure and method for forming the same | |
| JP2004342862A (en) | Semiconductor device and its manufacturing method, false wafer and its manufacturing method, and multi-chip module | |
| CN108962772B (en) | Package structure and method for forming the same | |
| CN108962868B (en) | Package structure and method for fabricating the same | |
| TW202008520A (en) | Packaged semiconductor device and method for preparing the same | |
| US9125320B2 (en) | Method of manufacturing passive component module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20220119 Address after: 518000 35 / F, Shenzhen Bay venture capital building, 25 Haitian 2nd Road, Binhai community, Yuehai street, Nanshan District, Shenzhen City, Guangdong Province Applicant after: Shenzhen Xinwen Technology Co.,Ltd. Address before: Room 707, block a, Rongsheng Times International Plaza, 9 Beiyuan street, Licheng District, Jinan City, Shandong Province Applicant before: Ji Nannan knows Information technology Co.,Ltd. |
|
| TA01 | Transfer of patent application right | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |