CN112382575B - Semiconductor storage package for 5G equipment and preparation method thereof - Google Patents

Semiconductor storage package for 5G equipment and preparation method thereof Download PDF

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Publication number
CN112382575B
CN112382575B CN202011252941.6A CN202011252941A CN112382575B CN 112382575 B CN112382575 B CN 112382575B CN 202011252941 A CN202011252941 A CN 202011252941A CN 112382575 B CN112382575 B CN 112382575B
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semiconductor memory
molding layer
organic molding
metal wiring
layer
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CN112382575A (en
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侯新飞
崔文杰
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Suzhou Mingzhang Semiconductor Technology Co ltd
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Suzhou Mingzhang Semiconductor Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view

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Abstract

The invention relates to a semiconductor storage package for 5G equipment and a preparation method thereof, wherein a plurality of first bulges are arranged on one side of an organic molding layer, a first groove is arranged at the edge of the side of the organic molding layer, so that one part of a first metal wiring layer is positioned on the surfaces of the first bulges, and the other part of the first metal wiring layer is embedded into the first groove. In the subsequent preparation process, the concave cavity is arranged in the circuit substrate, the semiconductor control chip is arranged in the concave cavity, and then the plurality of first semiconductor storage modules can be respectively arranged on the upper surface and the lower surface of the circuit substrate, so that the number of the storage modules can be effectively increased, and the integration level of semiconductor storage packaging can be improved.

Description

Semiconductor storage package for 5G equipment and preparation method thereof
Technical Field
The invention relates to the field of semiconductor storage element packaging, in particular to a preparation method of a semiconductor storage package for 5G equipment.
Background
The fifth generation mobile communication technology (5G or 5G technology for short) is the latest generationCellular mobile communicationTechnique, also relays4G、3GAnd2Gextension behind the system. The performance goals of 5G are high data rates, reduced latency, energy savings, reduced cost, increased system capacity, and large-scale device connectivity. In recent years, the 5G technology has become a hot spot in the communication industry and academia. Due to the explosive increase of the demand of mobile data, the existing mobile communication system is difficult to meet the future demand, and the development of a new generation 5G system is urgently needed. With the rapid development of the 5G technology, the packaging technology of semiconductor devices such as cpu chips and memory chips is also developed to "low power, high operation speed, high reliability and high density". To forIn a semiconductor memory device package, a conventional semiconductor memory device package is usually electrically connected by using metal leads, and the use of the metal leads is liable to cause unstable electrical connection, thereby causing functional failure of the semiconductor memory device package.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned disadvantages of the prior art and providing a method for manufacturing a semiconductor memory package for 5G devices.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor memory package for a 5G device, comprising the steps of:
(1) providing a first temporary carrier plate, arranging a first organic molding layer on the first temporary carrier plate, arranging a plurality of first bulges on one side of the first organic molding layer, then arranging a first groove at the edge of the side of the first organic molding layer, then forming a first metal wiring layer on the first organic molding layer, wherein one part of the first metal wiring layer is positioned on the surface of the first bulges, and the other part of the first metal wiring layer is embedded into the first groove, and then arranging a first semiconductor memory chip on the first organic molding layer, so that the first semiconductor memory chip is directly and electrically connected to the first metal wiring layer.
(2) Then, a second organic molding layer is arranged on the first organic molding layer, then, the surface of the second organic molding layer is subjected to thinning treatment, so that the thinned second organic molding layer exposes the back surface of the first semiconductor memory chip, then, a plurality of second bulges are arranged on one side of the second organic molding layer, then, a second groove is arranged at the edge of the side of the second organic molding layer, then, a second metal wiring layer is formed on the second organic molding layer, one part of the second metal wiring layer is arranged on the surface of the second bulges, the other part of the second metal wiring layer is embedded into the second groove, then, a second semiconductor memory chip is arranged on the second organic molding layer, so that the second semiconductor memory chip is directly and electrically connected to the second metal wiring layer, the second semiconductor memory chip partially overlaps the first semiconductor memory chip.
(3) Then, a third organic molding layer is arranged on the second organic molding layer, then, the surface of the third organic molding layer is subjected to thinning treatment, so that the thinned third organic molding layer exposes the back surface of the second semiconductor memory chip, then, a plurality of third bulges are arranged on one side of the third organic molding layer, then, a third groove is arranged at the edge of the side of the third organic molding layer, then, a third metal wiring layer is formed on the third organic molding layer, one part of the third metal wiring layer is positioned on the surface of the third bulges, the other part of the third metal wiring layer is embedded into the third groove, then, a third semiconductor memory chip is arranged on the third organic molding layer, so that the third semiconductor memory chip is directly and electrically connected to the third metal wiring layer, the third semiconductor memory chip partially overlaps the second semiconductor memory chip.
(4) Then, a fourth organic molding layer is arranged on the third organic molding layer, then, the surface of the fourth organic molding layer is thinned, so that the thinned fourth organic molding layer exposes the back surface of the third semiconductor memory chip, then, a plurality of fourth protrusions are arranged on one side of the fourth organic molding layer, then, a fourth groove is arranged at the edge of the side of the fourth organic molding layer, then, a fourth metal wiring layer is formed on the fourth organic molding layer, one part of the fourth metal wiring layer is arranged on the surface of the fourth protrusions, the other part of the fourth metal wiring layer is embedded into the fourth groove, then, a fourth semiconductor memory chip is arranged on the fourth organic molding layer, so that the fourth semiconductor memory chip is directly and electrically connected to the fourth metal wiring layer, the fourth semiconductor memory chip is partially overlapped with the third semiconductor memory chip, then a fifth organic molding layer is arranged on the fourth organic molding layer, and then the first temporary carrier plate is removed to form a first semiconductor memory module.
(5) Providing a circuit substrate, arranging a cavity in the circuit substrate, arranging a semiconductor control chip in the cavity, arranging a plurality of first semiconductor memory modules on the upper surface and the lower surface of the circuit substrate respectively, forming a sixth organic molding layer to protect the circuit substrate and the plurality of first semiconductor memory modules, forming a plurality of conductive through holes in the sixth organic molding layer, and forming conductive balls on the conductive through holes to form a semiconductor memory package.
Preferably, the first, second, third and fourth protrusions are strip-shaped protrusions arranged in parallel or column-shaped protrusions arranged in a matrix, and side surfaces of the first, second, third and fourth protrusions are inclined side surfaces.
Preferably, the material of the first, second, third and fourth bumps is one of resin, oxide and nitride.
Preferably, the height of the first protrusion is greater than the height of the second protrusion, the height of the second protrusion is equal to the height of the third protrusion, and the height of the third protrusion is less than the height of the fourth protrusion.
Preferably, a ratio of a depth of the first groove to a thickness of the first organic molding layer is 0.2 to 0.3, a ratio of a depth of the second groove to a thickness of the second organic molding layer is 0.4 to 0.5, a ratio of a depth of the third groove to a thickness of the third organic molding layer is 0.4 to 0.5, and a ratio of a depth of the fourth groove to a thickness of the fourth organic molding layer is 0.2 to 0.3.
Preferably, the material of the first, second, third and fourth metal wiring layers includes one or a combination of two or more of copper, aluminum, silver, titanium, nickel, palladium, chromium and gold, and the first, second, third and fourth metal wiring layers are formed by deposition through one or more of an electroplating process, an electroless plating process, a chemical vapor deposition process and a physical vapor deposition process.
Preferably, before the first semiconductor memory module is disposed on the circuit substrate, the first metal wiring layer in the first groove, the second metal wiring layer in the second groove, the third metal wiring layer in the third groove, and the fourth metal wiring layer in the fourth groove are etched to form a pit, respectively.
Preferably, in the step of subsequently disposing the first semiconductor memory module on the circuit board, solder is disposed in the recess, and the first semiconductor memory module and the circuit board are electrically connected by the solder.
The invention also provides a semiconductor storage package for 5G equipment, which is prepared by adopting the method.
Compared with the prior art, the invention has the following advantages:
in the preparation process of the semiconductor memory package for the 5G device, the plurality of first bulges are arranged on one side of the organic molding layer, the first groove is arranged at the edge of the side of the organic molding layer, so that one part of the first metal wiring layer is positioned on the surfaces of the first bulges, and the other part of the first metal wiring layer is embedded into the first groove. Furthermore, the height of the first bulge is larger than that of the second bulge, the height of the second bulge is equal to that of the third bulge, and the height of the third bulge is smaller than that of the fourth bulge. In the subsequent preparation process, the concave cavity is arranged in the circuit substrate, the semiconductor control chip is arranged in the concave cavity, and then the first semiconductor storage modules can be respectively arranged on the upper surface and the lower surface of the circuit substrate, so that the number of the storage modules can be effectively increased, and the integration level of the semiconductor storage package can be improved.
Drawings
Fig. 1-5 are schematic structural diagrams of respective processes for manufacturing a semiconductor memory package for a 5G device according to an embodiment of the present invention.
Detailed Description
It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements thereof are described below to simplify the description of the disclosure. These are, of course, merely examples and are not intended to limit the disclosure. For example, the following disclosure describes forming a first feature over or on a second feature, including embodiments in which the first feature and the second feature are formed in direct contact, and also including embodiments in which additional features may be formed between the first feature and the second feature, such that the first feature and the second feature may not be in direct contact. In addition, various examples of the disclosure may use repeated reference characters and/or wording. The repeated symbols or words are for the purpose of simplicity and clarity, and
and are not intended to limit the relationship between the various embodiments and/or the appearance structures.
Furthermore, spatially relative terms, such as "under", "below", "lower", "over", "upper" and the like, may be used herein for convenience in describing the relationship of one element or component to another element(s) or component(s) in the figures. Spatially relative terms may also encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as exemplary only and not as limiting. Thus, other examples of the exemplary embodiments may have different values.
Please refer to fig. 1 to 5. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1 to 5, the present embodiment provides a semiconductor memory package for a 5G device and a method of fabricating the same.
In a specific embodiment, a method for manufacturing a semiconductor memory package for a 5G device includes the steps of: as shown in fig. 1, step (1) is performed first, a first temporary carrier 11 is provided, a first organic molding layer 12 is disposed on the first temporary carrier 11, a plurality of first protrusions 13 are disposed on one side of the first organic molding layer 12, a first groove 121 is disposed at an edge of the one side of the first organic molding layer 12, a first metal wiring layer 14 is formed on the first organic molding layer 12, a portion of the first metal wiring layer 14 is disposed on a surface of the first protrusions 13, another portion of the first metal wiring layer 14 is embedded in the first groove 121, and a first semiconductor memory chip 15 is disposed on the first organic molding layer such that the first semiconductor memory chip 15 is directly electrically connected to the first metal wiring layer 14.
In a specific embodiment, the first protrusions 13 are bar-shaped protrusions arranged in parallel or column-shaped protrusions arranged in a matrix, and the side surfaces of the first protrusions 13 are inclined side surfaces. The material of the first protrusions 13 is one of resin, oxide and nitride, the ratio of the depth of the first grooves 121 to the thickness of the first organic molding layer 12 is 0.2-0.3, the material of the first metal wiring layer 14 includes one or a combination of two or more of copper, aluminum, silver, titanium, nickel, palladium, chromium and gold, and the first metal wiring layer 14 is formed by deposition through one or two or more of electroplating, electroless plating, chemical vapor deposition or physical vapor deposition.
In a specific embodiment, a peelable layer is directly provided on the first temporary carrier 11 and the first organic molding layer 12.
In a specific embodiment, in the process of forming the first organic molding layer 12, by providing a plurality of cavities in an injection mold, the first protrusion 13 and the first organic molding layer 12 are integrally formed, and the first organic molding layer 12 includes an epoxy resin, in other embodiments, the material of the first protrusion 13 may be silicon oxide or silicon nitride, in a specific manufacturing process, after the first organic molding layer 12 is formed by an injection molding process, a silicon oxide layer or a silicon nitride layer is deposited by using a PECVD process, and then the silicon oxide layer or the silicon nitride layer is etched by using a photoresist mask to form the first protrusion, in a preferred embodiment, when the side surface of the first protrusion 13 is an inclined side surface, an included angle between the inclined side surface and the bottom surface of the first protrusion 13 is 25-60 degrees, and an included angle between the inclined side surface and the bottom surface is greater than 60 degrees, it is not favorable to attach the first metal wiring layer 14 to the inclined side surface, and therefore the first metal wiring layer 14 on the side surface of the first bump 13 is easy to fall off, so that the included angle between the inclined side surface and the bottom surface is set to be not more than 60 degrees, so as to enhance the stability of the first metal wiring layer 14 on the side surface of the first bump 13, and when the included angle between the inclined side surface and the bottom surface is less than 25 degrees, it is not favorable to ensure the bending resistance of the first metal wiring layer 14, and the size of the first bump 13 is easy to be too large.
In a specific embodiment, the first groove 121 is formed by a wet etching process, a dry etching process or a mechanical cutting process, a ratio of a depth of the first groove 121 to a thickness of the first organic molding layer 12 is 0.2 to 0.3, more preferably, a ratio of a depth of the first groove 121 to a thickness of the first organic molding layer 12 is 0.25, the material of the first metal wiring layer 14 includes copper, and is formed by a plating process.
In a specific embodiment, a through hole is formed by performing a laser hole opening process on the first metal wiring layer 14, and then a conductive solder is disposed in the through hole, so that in the process of electrically connecting the first semiconductor memory chip 15 and the first metal wiring layer 14, the conductive pad of the first semiconductor memory chip 15 is embedded in the through hole, thereby improving the stability of the electrical connection between the first semiconductor memory chip 15 and the first metal wiring layer 14, and eliminating a gap between the first semiconductor memory chip 15 and the first metal wiring layer 14.
As shown in fig. 2, step (2) is performed, a second organic molding layer 16 is disposed on the first organic molding layer 12, the surface of the second organic molding layer 16 is thinned, so that the thinned second organic molding layer 16 exposes the back surface of the first semiconductor memory chip 15, a plurality of second bumps 17 are disposed on one side of the second organic molding layer 16, a second groove 161 is disposed at the edge of the side of the second organic molding layer 16, a second metal wiring layer 18 is formed on the second organic molding layer 16, a portion of the second metal wiring layer 18 is disposed on the surface of the second bumps 17, another portion of the second metal wiring layer 18 is embedded in the second groove 161, a second semiconductor memory chip 19 is disposed on the second organic molding layer 16, so that the second semiconductor memory chip 19 is directly electrically connected to the second metal wiring layer 18, the second semiconductor memory chip 19 partially overlapping with the first semiconductor memory chip 15.
In a specific embodiment, the second protrusions 17 are bar-shaped protrusions arranged in parallel or column-shaped protrusions arranged in a matrix, and the side surfaces of the second protrusions 17 are inclined side surfaces. The material of the second protrusions 17 is one of resin, oxide and nitride. The height of the first protrusion 13 is greater than the height of the second protrusion 17, the ratio of the depth of the second groove 161 to the thickness of the second organic molding layer 16 is 0.4-0.5, the material of the second metal wiring layer 18 includes one or a combination of two or more of copper, aluminum, silver, titanium, nickel, palladium, chromium, and gold, and the second metal wiring layer 18 is deposited by one or more of an electroplating process, an electroless plating process, a chemical vapor deposition process, or a physical vapor deposition process.
In a specific embodiment, in the process of forming the second organic molding layer 16, by providing a plurality of cavities in an injection mold, the second protrusion 17 and the second organic molding layer 16 are integrally formed, and the second organic molding layer 16 includes an epoxy resin, in other embodiments, the second protrusion 17 may be made of silicon oxide or silicon nitride, in a specific manufacturing process, after the second organic molding layer 16 is formed by an injection molding process, a silicon oxide layer or a silicon nitride layer is deposited by a PECVD process, and then the silicon oxide layer or the silicon nitride layer is etched by using a photoresist mask to form the second protrusion 17, in a preferred embodiment, when the side surface of the second protrusion 17 is an inclined side surface, an included angle between the inclined side surface and the bottom surface of the second protrusion 17 is 25-60 degrees, and an included angle between the inclined side surface and the bottom surface is greater than 60 degrees, it is not favorable to attach the second metal wiring layer 18 to the inclined side surface, and therefore the second metal wiring layer 18 on the side surface of the second bump 17 is easy to fall off, so that the included angle between the inclined side surface and the bottom surface is set to be not more than 60 degrees, so as to enhance the stability of the second metal wiring layer 18 on the side surface of the second bump 17, and when the included angle between the inclined side surface and the bottom surface is less than 25 degrees, it is not favorable to ensure the bending resistance of the second metal wiring layer 18, and the size of the second bump 17 is easy to be too large.
In a specific embodiment, the ratio of the height of the second protrusion 17 to the height of the first protrusion 13 is 0.7-0.9, and more preferably, the ratio of the height of the second protrusion 17 to the height of the first protrusion 13 is 0.8. By optimizing the height of the second bump 17, the thickness of the entire semiconductor memory package and the bending resistance of the second metal wiring layer 18 are balanced.
In a specific embodiment, the second groove 161 is formed by a wet etching process, a dry etching process or a mechanical cutting process, a ratio of a depth of the second groove 161 to a thickness of the second organic molding layer 16 is 0.4 to 0.5, more preferably, a ratio of a depth of the second groove 161 to a thickness of the second organic molding layer 16 is 0.45, the material of the second metal wiring layer 18 includes copper, and the second metal wiring layer is formed by a plating process.
In a specific embodiment, a through hole is formed by performing a laser drilling process on the second metal wiring layer 18, and then a conductive solder is disposed in the through hole, so that in the process of electrically connecting the second semiconductor memory chip 19 and the second metal wiring layer 18, the conductive pad of the second semiconductor memory chip 19 is embedded in the through hole, thereby improving the stability of the electrical connection between the second semiconductor memory chip 19 and the second metal wiring layer 18, and eliminating a gap between the second semiconductor memory chip 19 and the second metal wiring layer 18.
As shown in fig. 3, step (3) is performed, a third organic molding layer 20 is disposed on the second organic molding layer 16, a surface of the third organic molding layer 20 is thinned, so that the thinned third organic molding layer 20 exposes a back surface of the second semiconductor memory chip 19, a plurality of third bumps 21 are disposed on one side of the third organic molding layer 20, a third groove 201 is disposed at an edge of the side of the third organic molding layer 20, a third metal wiring layer 22 is formed on the third organic molding layer 20, a portion of the third metal wiring layer 22 is disposed on a surface of the third bump 21, another portion of the third metal wiring layer 22 is embedded in the third groove 201, a third semiconductor memory chip 23 is disposed on the third organic molding layer 22, so that the third semiconductor memory chip 23 is directly electrically connected to the third metal wiring layer 22, the third semiconductor memory chip 23 partially overlaps with the second semiconductor memory chip 19.
The third protrusions 21 are bar-shaped protrusions arranged in parallel or column-shaped protrusions arranged in a matrix, and the side surfaces of the third protrusions 21 are inclined side surfaces. The material of the third protrusions 21 is one of resin, oxide, and nitride. The height of the second protrusion 17 is equal to the height of the third protrusion 21, the ratio of the depth of the third groove 201 to the thickness of the third organic molding layer 20 is 0.4-0.5, the material of the third metal wiring layer 22 includes one or a combination of two or more of copper, aluminum, silver, titanium, nickel, palladium, chromium, and gold, and the third metal wiring layer 22 is deposited by one or more of an electroplating process, an electroless plating process, a chemical vapor deposition process, or a physical vapor deposition process.
In a particular embodiment, the third organic molding layer 20 includes an epoxy resin.
In a specific embodiment, the process, material and structure of the third bump 21 are the same as those of the second bump 17.
In a specific embodiment, the third groove 201 is formed by a wet etching process, a dry etching process or a mechanical cutting process, a ratio of a depth of the third groove 201 to a thickness of the third organic molding layer 20 is 0.4 to 0.5, more preferably, a ratio of a depth of the third groove 201 to a thickness of the third organic molding layer 20 is 0.45, and the third metal wiring layer 22 includes copper and is formed by a plating process.
In a specific embodiment, a through hole is formed by performing a laser hole opening process on the third metal wiring layer 22, and then a conductive solder is disposed in the through hole, so that in the process of electrically connecting the third semiconductor memory chip 23 and the third metal wiring layer 22, the conductive pad of the third semiconductor memory chip 23 is embedded in the through hole, thereby improving the stability of the electrical connection between the third semiconductor memory chip 23 and the third metal wiring layer 22, and eliminating a gap between the third semiconductor memory chip 23 and the third metal wiring layer 22.
As shown in fig. 4, step (4) is performed, a fourth organic molding layer 24 is disposed on the third organic molding layer 20, a surface of the fourth organic molding layer 24 is thinned, so that the thinned fourth organic molding layer 24 exposes a back surface of the third semiconductor memory chip 23, a plurality of fourth bumps 25 are disposed on one side of the fourth organic molding layer 24, a fourth groove 241 is disposed at an edge of the side of the fourth organic molding layer 24, a fourth metal wiring layer 26 is formed on the fourth organic molding layer 24, a portion of the fourth metal wiring layer 26 is disposed on a surface of the fourth bump 25, another portion of the fourth metal wiring layer 26 is embedded in the fourth groove 241, a fourth semiconductor memory chip 27 is disposed on the fourth organic molding layer 24, so that the fourth semiconductor memory chip 27 is directly electrically connected to the fourth metal wiring layer 26, the fourth semiconductor memory chip 27 partially overlaps the third semiconductor memory chip 23, then a fifth organic molding layer 28 is disposed on the fourth organic molding layer 24, and then the first temporary carrier is removed to form a first semiconductor memory module 29.
The fourth protrusions 25 are strip-shaped protrusions arranged in parallel or column-shaped protrusions arranged in a matrix, and the side surfaces of the fourth protrusions 25 are inclined side surfaces. The material of the fourth protrusions 25 is one of resin, oxide, and nitride. The height of the third protrusions 21 is smaller than the height of the fourth protrusions 25. The ratio of the depth of the fourth groove 241 to the thickness of the fourth organic molding layer 24 is 0.2 to 0.3. The material of the fourth metal wiring layer 26 includes one or a combination of two or more of copper, aluminum, silver, titanium, nickel, palladium, chromium, and gold, and the fourth metal wiring layer 26 is deposited by one or more of an electroplating process, an electroless plating process, a chemical vapor deposition process, or a physical vapor deposition process.
In a particular embodiment, the fourth and fifth organic molding layers 24, 28 comprise epoxy.
In a specific embodiment, the manufacturing process, material and structure of the fourth bump 25 are the same as those of the first bump 13.
In a specific embodiment, the third groove 241 is formed by wet etching, dry etching or mechanical cutting, a ratio of a depth of the fourth groove 241 to a thickness of the fourth organic molding layer 24 is 0.4 to 0.5, more preferably, a ratio of a depth of the fourth groove 241 to a thickness of the fourth organic molding layer 24 is 0.45, and the fourth metal wiring layer 26 is made of copper and formed by electroplating.
In a specific embodiment, a through hole is formed by performing a laser drilling process on the fourth metal wiring layer 26, and then a conductive solder is disposed in the through hole, so that in the process of electrically connecting the fourth semiconductor memory chip 27 and the fourth metal wiring layer 26, a conductive pad of the fourth semiconductor memory chip 27 is embedded in the through hole, thereby improving the stability of the electrical connection between the fourth semiconductor memory chip 27 and the fourth metal wiring layer 26, and eliminating a gap between the fourth semiconductor memory chip 27 and the fourth metal wiring layer 26.
As shown in fig. 5, step (5) is performed to provide a circuit substrate 30, a cavity is formed in the circuit substrate 30, a semiconductor control chip 31 is formed in the cavity, a plurality of first semiconductor memory modules 29 are respectively formed on the upper surface and the lower surface of the circuit substrate 30, a sixth organic molding layer 32 is formed to protect the circuit substrate and the plurality of first semiconductor memory modules 29, a plurality of conductive vias 33 are formed in the sixth organic molding layer 32, and conductive balls 34 are formed on the conductive vias 33 to form a semiconductor memory package.
Before the first semiconductor memory module 29 is disposed on the circuit substrate 30, the first metal wiring layer 14 in the first groove, the second metal wiring layer 18 in the second groove, the third metal wiring layer 22 in the third groove, and the fourth metal wiring layer 26 in the fourth groove are etched to form a pit respectively. Subsequently, in the process of mounting the first semiconductor memory module 29 on the circuit board 30, solder is provided in the recess, and the first semiconductor memory module 29 and the circuit board 30 are electrically connected by the solder.
In a specific embodiment, the semiconductor control chip 31 is electrically connected to the circuit board 30, specifically, the semiconductor control chip 31 is flip-chip mounted in the cavity of the circuit board 30, and a protective adhesive is filled in the back surface of the semiconductor control chip 31 and a gap between the semiconductor control chip 31 and the cavity, so as to facilitate the mounting of the plurality of first semiconductor memory modules 29.
In a particular embodiment, the sixth organic molding layer 32 includes an epoxy resin.
In a specific embodiment, the conductive vias 33 are formed by electroplating copper, and the conductive balls 34 may be solder balls.
As shown in fig. 5, the present invention also provides a semiconductor memory package for a 5G device, which is prepared by the above method.
Compared with the prior art, the invention has the following advantages: in the preparation process of the semiconductor memory package for the 5G device, the plurality of first bulges are arranged on one side of the organic molding layer, the first groove is arranged at the edge of the side of the organic molding layer, so that one part of the first metal wiring layer is positioned on the surfaces of the first bulges, and the other part of the first metal wiring layer is embedded into the first groove. Furthermore, the height of the first bulge is larger than that of the second bulge, the height of the second bulge is equal to that of the third bulge, and the height of the third bulge is smaller than that of the fourth bulge. In the subsequent preparation process, the concave cavity is arranged in the circuit substrate, the semiconductor control chip is arranged in the concave cavity, and then the first semiconductor storage modules can be respectively arranged on the upper surface and the lower surface of the circuit substrate, so that the number of the storage modules can be effectively increased, and the integration level of the semiconductor storage package can be improved.
In other embodiments, the present invention provides a method for manufacturing a semiconductor memory package for a 5G device, including the steps of:
(1) providing a first temporary carrier plate, arranging a first organic molding layer on the first temporary carrier plate, arranging a plurality of first bulges on one side of the first organic molding layer, then arranging a first groove at the edge of the side of the first organic molding layer, then forming a first metal wiring layer on the first organic molding layer, wherein one part of the first metal wiring layer is positioned on the surface of the first bulges, and the other part of the first metal wiring layer is embedded into the first groove, and then arranging a first semiconductor memory chip on the first organic molding layer, so that the first semiconductor memory chip is directly and electrically connected to the first metal wiring layer.
(2) Then, a second organic molding layer is arranged on the first organic molding layer, then, the surface of the second organic molding layer is subjected to thinning treatment, so that the thinned second organic molding layer exposes the back surface of the first semiconductor memory chip, then, a plurality of second bulges are arranged on one side of the second organic molding layer, then, a second groove is arranged at the edge of the side of the second organic molding layer, then, a second metal wiring layer is formed on the second organic molding layer, one part of the second metal wiring layer is arranged on the surface of the second bulges, the other part of the second metal wiring layer is embedded into the second groove, then, a second semiconductor memory chip is arranged on the second organic molding layer, so that the second semiconductor memory chip is directly and electrically connected to the second metal wiring layer, the second semiconductor memory chip partially overlaps with the first semiconductor memory chip.
(3) Then, a third organic molding layer is arranged on the second organic molding layer, then, the surface of the third organic molding layer is subjected to thinning treatment, so that the thinned third organic molding layer exposes the back surface of the second semiconductor memory chip, then, a plurality of third bulges are arranged on one side of the third organic molding layer, then, a third groove is arranged at the edge of the side of the third organic molding layer, then, a third metal wiring layer is formed on the third organic molding layer, one part of the third metal wiring layer is arranged on the surface of the third bulges, the other part of the third metal wiring layer is embedded into the third groove, then, a third semiconductor memory chip is arranged on the third organic molding layer, so that the third semiconductor memory chip is directly and electrically connected to the third metal wiring layer, the third semiconductor memory chip partially overlaps the second semiconductor memory chip.
(4) Then, a fourth organic molding layer is arranged on the third organic molding layer, then, the surface of the fourth organic molding layer is thinned, so that the thinned fourth organic molding layer exposes the back surface of the third semiconductor memory chip, then, a plurality of fourth protrusions are arranged on one side of the fourth organic molding layer, then, a fourth groove is arranged at the edge of the side of the fourth organic molding layer, then, a fourth metal wiring layer is formed on the fourth organic molding layer, one part of the fourth metal wiring layer is arranged on the surface of the fourth protrusions, the other part of the fourth metal wiring layer is embedded into the fourth groove, then, a fourth semiconductor memory chip is arranged on the fourth organic molding layer, so that the fourth semiconductor memory chip is directly and electrically connected to the fourth metal wiring layer, the fourth semiconductor memory chip is partially overlapped with the third semiconductor memory chip, then a fifth organic molding layer is arranged on the fourth organic molding layer, and then the first temporary carrier plate is removed to form a first semiconductor memory module.
(5) Providing a circuit substrate, arranging a cavity in the circuit substrate, arranging a semiconductor control chip in the cavity, arranging a plurality of first semiconductor memory modules on the upper surface and the lower surface of the circuit substrate respectively, forming a sixth organic molding layer to protect the circuit substrate and the plurality of first semiconductor memory modules, forming a plurality of conductive through holes in the sixth organic molding layer, and forming conductive balls on the conductive through holes to form a semiconductor memory package.
In some other embodiments, the first, second, third and fourth protrusions are strip-shaped protrusions arranged in parallel or column-shaped protrusions arranged in matrix, and the side surfaces of the first, second, third and fourth protrusions are inclined side surfaces.
In some other embodiments, the material of the first, second, third and fourth bumps is one of resin, oxide and nitride.
In some other embodiments, the height of the first bump is greater than the height of the second bump, the height of the second bump is equal to the height of the third bump, and the height of the third bump is less than the height of the fourth bump.
In some other embodiments, a ratio of a depth of the first groove to a thickness of the first organic molding layer is 0.2 to 0.3, a ratio of a depth of the second groove to a thickness of the second organic molding layer is 0.4 to 0.5, a ratio of a depth of the third groove to a thickness of the third organic molding layer is 0.4 to 0.5, and a ratio of a depth of the fourth groove to a thickness of the fourth organic molding layer is 0.2 to 0.3.
In some other embodiments, the material of the first, second, third and fourth metal wiring layers includes one or a combination of two or more of copper, aluminum, silver, titanium, nickel, palladium, chromium and gold, and the first, second, third and fourth metal wiring layers are formed by deposition through one or more of an electroplating process, an electroless plating process, a chemical vapor deposition process or a physical vapor deposition process.
In some other embodiments, before the first semiconductor memory module is disposed on the circuit substrate, the first metal wiring layer in the first groove, the second metal wiring layer in the second groove, the third metal wiring layer in the third groove, and the fourth metal wiring layer in the fourth groove are etched to form a recess, respectively.
In some other embodiments, the first semiconductor memory module is electrically connected to the circuit substrate by solder provided in the recess in the course of being subsequently provided to the circuit substrate.
In some other embodiments, the invention also provides a semiconductor storage package for 5G equipment, which is prepared by adopting the method.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims (9)

1. A preparation method of a semiconductor storage package for a 5G device is characterized by comprising the following steps: the method comprises the following steps:
(1) providing a first temporary carrier plate, arranging a first organic molding layer on the first temporary carrier plate, arranging a plurality of first bulges on one side of the first organic molding layer, then arranging a first groove on the edge of the side of the first organic molding layer, then forming a first metal wiring layer on the first organic molding layer, wherein one part of the first metal wiring layer is positioned on the surface of the first bulges, and the other part of the first metal wiring layer is embedded into the first groove, and then arranging a first semiconductor memory chip on the first organic molding layer, so that the first semiconductor memory chip is directly electrically connected to the first metal wiring layer;
(2) then, a second organic molding layer is arranged on the first organic molding layer, then, the surface of the second organic molding layer is subjected to thinning treatment, so that the thinned second organic molding layer exposes the back surface of the first semiconductor memory chip, then, a plurality of second bulges are arranged on one side of the second organic molding layer, then, a second groove is arranged at the edge of the side of the second organic molding layer, then, a second metal wiring layer is formed on the second organic molding layer, one part of the second metal wiring layer is arranged on the surface of the second bulges, the other part of the second metal wiring layer is embedded into the second groove, then, a second semiconductor memory chip is arranged on the second organic molding layer, so that the second semiconductor memory chip is directly and electrically connected to the second metal wiring layer, the second semiconductor memory chip partially overlaps with the first semiconductor memory chip;
(3) then, a third organic molding layer is arranged on the second organic molding layer, then, the surface of the third organic molding layer is subjected to thinning treatment, so that the thinned third organic molding layer exposes the back surface of the second semiconductor memory chip, then, a plurality of third bulges are arranged on one side of the third organic molding layer, then, a third groove is arranged at the edge of the side of the third organic molding layer, then, a third metal wiring layer is formed on the third organic molding layer, one part of the third metal wiring layer is positioned on the surface of the third bulges, the other part of the third metal wiring layer is embedded into the third groove, then, a third semiconductor memory chip is arranged on the third organic molding layer, so that the third semiconductor memory chip is directly and electrically connected to the third metal wiring layer, the third semiconductor memory chip partially overlaps with the second semiconductor memory chip;
(4) then, a fourth organic molding layer is arranged on the third organic molding layer, then, the surface of the fourth organic molding layer is thinned, so that the thinned fourth organic molding layer exposes the back surface of the third semiconductor memory chip, then, a plurality of fourth protrusions are arranged on one side of the fourth organic molding layer, then, a fourth groove is arranged at the edge of the side of the fourth organic molding layer, then, a fourth metal wiring layer is formed on the fourth organic molding layer, one part of the fourth metal wiring layer is arranged on the surface of the fourth protrusions, the other part of the fourth metal wiring layer is embedded into the fourth groove, then, a fourth semiconductor memory chip is arranged on the fourth organic molding layer, so that the fourth semiconductor memory chip is directly and electrically connected to the fourth metal wiring layer, the fourth semiconductor memory chip is partially overlapped with the third semiconductor memory chip, then a fifth organic molding layer is arranged on the fourth organic molding layer, and then the first temporary carrier plate is removed to form a first semiconductor memory module;
(5) providing a circuit substrate, arranging a cavity in the circuit substrate, arranging a semiconductor control chip in the cavity, arranging a plurality of first semiconductor memory modules on the upper surface and the lower surface of the circuit substrate respectively, forming a sixth organic molding layer to protect the circuit substrate and the plurality of first semiconductor memory modules, forming a plurality of conductive through holes in the sixth organic molding layer, and forming conductive balls on the conductive through holes to form a semiconductor memory package.
2. The method of manufacturing a semiconductor memory package for a 5G device according to claim 1, wherein: the first, second, third and fourth protrusions are strip-shaped protrusions arranged in parallel or column-shaped protrusions arranged in a matrix, and the side surfaces of the first, second, third and fourth protrusions are inclined side surfaces.
3. The method of manufacturing a semiconductor memory package for a 5G device according to claim 2, wherein: the material of the first, second, third and fourth bulges is one of resin, oxide and nitride.
4. The method of manufacturing a semiconductor memory package for a 5G device according to claim 3, wherein: the height of the first protrusion is greater than that of the second protrusion, the height of the second protrusion is equal to that of the third protrusion, and the height of the third protrusion is less than that of the fourth protrusion.
5. The method of manufacturing a semiconductor memory package for a 5G device according to claim 1, wherein: the ratio of the depth of the first groove to the thickness of the first organic molding layer is 0.2-0.3, the ratio of the depth of the second groove to the thickness of the second organic molding layer is 0.4-0.5, the ratio of the depth of the third groove to the thickness of the third organic molding layer is 0.4-0.5, and the ratio of the depth of the fourth groove to the thickness of the fourth organic molding layer is 0.2-0.3.
6. The method of manufacturing a semiconductor memory package for a 5G device according to claim 1, wherein: the first, second, third and fourth metal wiring layers are made of one or a combination of more than two of copper, aluminum, silver, titanium, nickel, palladium, chromium and gold, and are formed by deposition through one or more than two of electroplating process, chemical plating process, chemical vapor deposition process or physical vapor deposition process.
7. The method of manufacturing a semiconductor memory package for a 5G device according to claim 1, wherein: and before the first semiconductor memory module is arranged on the circuit substrate, etching the first metal wiring layer in the first groove, the second metal wiring layer in the second groove, the third metal wiring layer in the third groove and the fourth metal wiring layer in the fourth groove to respectively form a pit.
8. The method of manufacturing a semiconductor memory package for a 5G device according to claim 7, wherein: and then, in the process of arranging the first semiconductor memory module on the circuit substrate, arranging solder in the concave pit, and electrically connecting the first semiconductor memory module with the circuit substrate through the solder.
9. A semiconductor memory package for a 5G device, prepared by the method of any one of claims 1-8.
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