CN112420641A - Power element packaging structure and preparation method thereof - Google Patents
Power element packaging structure and preparation method thereof Download PDFInfo
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- CN112420641A CN112420641A CN202011348505.9A CN202011348505A CN112420641A CN 112420641 A CN112420641 A CN 112420641A CN 202011348505 A CN202011348505 A CN 202011348505A CN 112420641 A CN112420641 A CN 112420641A
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
- H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
- H01L23/4012—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws for stacked arrangements of a plurality of semiconductor devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
- H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
- H01L2023/4037—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws characterised by thermal path or place of attachment of heatsink
- H01L2023/405—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws characterised by thermal path or place of attachment of heatsink heatsink to package
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
- H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
- H01L2023/4037—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws characterised by thermal path or place of attachment of heatsink
- H01L2023/4068—Heatconductors between device and heatsink, e.g. compliant heat-spreaders, heat-conducting bands
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention relates to a power element packaging structure and a preparation method thereof, wherein the method comprises the following steps: mounting the power element on a first carrier plate, forming a plurality of first grooves arranged at intervals on the power element, forming a plurality of first heat-conducting columns in the first grooves respectively, then arranging a first packaging layer, arranging a circuit board on the power element, forming a plurality of second grooves arranged at intervals on the circuit board, and forming a plurality of second heat-conducting pillars in the plurality of second grooves, respectively, to form a first package assembly, arranging a plurality of accommodating cavities arranged in parallel on the upper surface of the radiator, arranging a first packaging assembly in each accommodating cavity to form a first power stack, and arranging the first power stack on the upper surface and the lower surface of the conductive substrate, and then forming a second packaging layer which wraps the conductive substrate and the two first power stacks.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a power element packaging structure and a preparation method thereof.
Background
In the existing stack package structure, most of the chips in the component are stacked by gold wire bonding, and the number of stacked layers can be from 2 to 8. The stack package structure comprises a PIP package structure and a POP stack structure, wherein in the PIP package structure, the chips in the package are stacked on the substrate by gold wire bonding, the same stack bonds the substrate between the two stacks by gold wire, and then the whole package is a component, namely the PIP package structure. The appearance height of the PiP packaging structure is low, a standard SMT circuit board assembly process can be adopted, and the assembly cost of a single device is low. But since individual chips cannot be tested individually before packaging, the overall cost can be high; in the POP stacking structure, the packaging structure is placed on the packaging structure at the bottom, the appearance height is slightly higher, but each packaging structure can be tested independently before assembly, higher yield is guaranteed, and the total stacking assembly cost can be reduced to the lowest. How to improve the existing stack package structure to improve the comprehensive performance of the stack package structure.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned deficiencies in the prior art, and to provide a power device package structure and a method for manufacturing the same.
In order to achieve the purpose, the invention adopts the technical scheme that:
a preparation method of a power element packaging structure comprises the following steps:
(1) providing a first carrier plate and a power element, wherein the power element is provided with an active surface and a non-active surface, the active surface of the power element is provided with a conductive bonding pad, and then the power element is mounted on the first carrier plate in a manner that the active surface of the power element faces the first carrier plate;
(2) then, a mask layer is arranged on the first carrier plate, the mask layer is provided with a plurality of openings which are arranged at intervals, the openings expose the non-active surface of the power element, the power element is etched by using the mask layer to form a plurality of first grooves which are arranged at intervals, wherein the first grooves are arranged in a row, the depth of the first grooves in the middle of the row is the largest, the depth of the first grooves in the two end parts of the row is the smallest, and the depth of the first grooves from the middle to each end part is gradually reduced;
(3) then, a plurality of first heat-conducting columns are respectively formed in the first grooves, and the top surfaces of the first heat-conducting columns are positioned on the same horizontal plane;
(4) then, arranging a first packaging layer on the first carrier plate, wherein the first heat conduction columns protrude out of the upper surface of the first packaging layer;
(5) providing a second carrier plate, bonding the second carrier plate to the upper surface of the first packaging layer, removing the first carrier plate, arranging a circuit board on the power element, electrically connecting the circuit board to the power element, forming a plurality of second grooves arranged at intervals on the circuit board, respectively forming a plurality of second heat-conducting columns in the second grooves, wherein the top surfaces of the second heat-conducting columns are positioned on the same horizontal plane, and removing the second carrier plate to form a first packaging assembly;
(6) providing a heat radiator, wherein a plurality of accommodating cavities which are arranged in parallel are arranged on the upper surface of the heat radiator, a strip-shaped groove is arranged on two opposite side surfaces of each accommodating cavity, then a first packaging assembly is arranged in each accommodating cavity, and the first heat-conducting columns and the second heat-conducting columns are respectively embedded into the corresponding strip-shaped grooves to form a first power stack;
(7) providing a conductive substrate, arranging the first power stacks on the upper surface and the lower surface of the conductive substrate, so that the two first power stacks are electrically connected with the conductive substrate, and then forming a second packaging layer, wherein the second packaging layer wraps the conductive substrate and the two first power stacks.
Preferably, in the step 1), an organic functional layer is first formed in a central region of the first carrier, then an adhesive layer is formed on the surfaces of the first carrier and the organic functional layer, an adhesive force between the adhesive layer and the organic functional layer is smaller than an adhesive force between the adhesive layer and the first carrier, and then the power element is adhesively disposed on the adhesive layer.
Preferably, in the step 2), the mask layer is a photoresist mask layer, the first grooves are formed by wet etching or dry etching, the depth of the first groove located in the middle of the row is 40 to 60 micrometers, and the depth of the first groove located at both end portions of the row is 10 to 30 micrometers.
Preferably, in the step 3), the material of the first heat-conducting pillar is one or more of silver, copper, aluminum, iron, tin and lead, and the first heat-conducting pillar is formed by one or more of chemical vapor deposition, physical vapor deposition, electroplating and electroless plating.
Preferably, in the step 4), the material of the first encapsulation layer is epoxy resin, and a ratio of a height of the protruding portion of the first thermal conductive pillar to a height of the first thermal conductive pillar is 0.2 to 0.4.
Preferably, in the step 5), the power element and the circuit board are electrically connected through a conductive bump, the depth of the second groove is 50-80 μm, the second heat-conducting pillar protrudes out of the surface of the circuit board, and the ratio of the height of the protruding portion of the second heat-conducting pillar to the height of the second heat-conducting pillar is 0.15-0.3.
Preferably, in the step 6), after the first package assembly is placed in the accommodating cavity, a heat conducting insulating material is injected into the accommodating cavity, so that the heat conducting insulating material fills a gap between the accommodating cavity and the first package assembly.
Preferably, in the step 7), the second encapsulating layer is thinned so that a bottom surface of the heat spreader is exposed.
The invention also provides a power element packaging structure which is prepared and formed by adopting the method.
Compared with the prior art, the invention has the following advantages:
in the preparation process of the power element packaging structure, a plurality of first grooves arranged at intervals are formed on the non-active surface of the power element, the first grooves are arranged in a row, the depth of the first groove at the middle position of the row is the largest, the depth of the first groove at the two end parts of the row is the smallest, and the depths of the first grooves from the middle position to each end part are gradually reduced; then, a plurality of first heat-conducting columns are respectively formed in the first grooves, and the top surfaces of the first heat-conducting columns are positioned on the same horizontal plane; then forming a plurality of second grooves arranged at intervals on the circuit board, then respectively forming a plurality of second heat-conducting pillars in the plurality of second grooves, the top surfaces of the plurality of second heat-conducting pillars being located at the same horizontal plane, the above structure being arranged to facilitate heat dissipation of the power element, and the upper surface of the heat sink being provided with a plurality of receiving cavities arranged in parallel, each of the receiving cavities having a strip-shaped groove on both opposite sides, and then each of the receiving cavities being provided with one of the first heat-conducting pillars, and the plurality of first heat-conducting pillars and the plurality of second heat-conducting pillars being respectively embedded in the corresponding strip-shaped grooves to form a first power stack having excellent heat dissipation performance, and the upper surface of the heat sink being provided with a plurality of receiving cavities arranged in parallel, each of the first heat-conducting pillars being longitudinally embedded in the receiving cavity, the integration level of the power element packaging structure is improved.
Drawings
Fig. 1-7 are schematic structural diagrams of the power device package structure of the present invention during the manufacturing process.
Detailed Description
In order to better understand the technical scheme of the invention, the following detailed description of the embodiments of the invention is provided with the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be understood that although the terms first, second, etc. may be used to describe semiconductor chips in embodiments of the present invention, these semiconductor chips should not be limited to these terms. These terms are only used to distinguish the semiconductor chips from one another. For example, the first semiconductor chip may also be referred to as a second semiconductor chip, and similarly, the second semiconductor chip may also be referred to as a first semiconductor chip, without departing from the scope of embodiments of the present invention.
Please refer to fig. 1 to 7. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1 to 7, the present embodiment provides a method for manufacturing a power device package structure, including the following steps:
first, as shown in fig. 1, in step (1), a first carrier board 1 and a power device 2 are provided, the power device 1 has an active surface and a non-active surface, the active surface of the power device 2 has a conductive pad, and then the power device 2 is mounted on the first carrier board with the active surface of the power device 2 facing the first carrier board 1.
In the step 1), an organic functional layer 11 is firstly formed in the central area of the first carrier 1, then an adhesive layer 12 is formed on the surfaces of the first carrier 1 and the organic functional layer 11, the adhesion between the adhesive layer 12 and the organic functional layer 11 is smaller than the adhesion between the adhesive layer 12 and the first carrier 1, and then the power element 2 is adhesively arranged on the adhesive layer 12.
In this embodiment, the first carrier 1 may be one of a semiconductor substrate, a metal substrate, a ceramic substrate, a glass substrate, or a plastic substrate. The organic functional layer 11 may be perfluorododecyl trichlorosilane, perfluorooctyl trichlorosilane, tetrahydrooctyl triethoxysilane, or tetrahydrooctyl methyl dichlorosilane, and the thickness of the organic functional layer 11 is preferably 10 to 20 nm. The organic functional layer 11 is arranged to facilitate the subsequent stripping process.
Next, as shown in fig. 2, in step (2), a mask layer 3 is disposed on the first carrier 1, the mask layer 3 has a plurality of openings spaced apart from each other, the openings expose the non-active surface of the power elements 2, and the power elements 2 are etched by using the mask layer 3 to form a plurality of first recesses 21 spaced apart from each other, wherein the plurality of first recesses 21 are arranged in a row, the depth of the first recess 21 located at the middle of the row is the largest, the depth of the first recess 21 located at the two end portions of the row is the smallest, and the depths of the plurality of first recesses from the middle to each end portion gradually decrease.
In the step 2), the mask layer 3 is a photoresist mask layer, the first grooves 21 are formed by wet etching or dry etching, the depth of the first grooves 21 located in the middle of the row is 40 to 60 micrometers, and the depth of the first grooves 21 located at the two end portions of the row is 10 to 30 micrometers. More preferably, the depth of the first groove 21 located at the middle of the row is 40 micrometers, 45 micrometers, 50 micrometers, 55 micrometers, 60 micrometers, and the depth of the first groove 21 located at the both ends of the row is 10 micrometers, 15 micrometers, 20 micrometers, 25 micrometers, 30 micrometers.
In a specific embodiment, a photoresist solution is coated on the first carrier 1, an exposure and development process is performed to form the photoresist mask layer 3, and then the photoresist mask layer 3 is used to perform a wet etching process on the power element 2, so as to form a plurality of first grooves 21 respectively.
Next, as shown in fig. 3, in step (3), a plurality of first heat-conducting pillars 4 are formed in the plurality of first grooves 21, respectively, and top surfaces of the plurality of first heat-conducting pillars 4 are located at the same horizontal plane. In the step 3), the material of the first heat-conducting column 4 is one or more of silver, copper, aluminum, iron, tin and lead, and the first heat-conducting column 4 is formed by one or more of chemical vapor deposition, physical vapor deposition, electroplating and electroless plating. In a specific embodiment, the material of the first heat-conducting pillar 4 is copper or aluminum, and is formed by an evaporation process.
As shown in fig. 4, in step (4), a first package layer 5 is disposed on the first carrier 1, and the first thermal pillars 4 protrude from the upper surface of the first package layer 1.
In the step 4), the material of the first encapsulation layer 5 is epoxy resin, and a ratio of a height of the protruding portion of the first thermal conductive pillar 4 to a height of the first thermal conductive pillar 4 is 0.2-0.4.
In a preferred embodiment, the ratio of the height of the protruding portion of the first heat conduction column 4 to the height of the first heat conduction column 4 is 0.2, 0.25, 0.3, 0.35 or 0.4, and by optimizing the ratio of the height of the protruding portion of the first heat conduction column 4 to the height of the first heat conduction column 4, the stability and the heat conduction performance of the first heat conduction column 4 are effectively ensured.
In other embodiments, a first package layer may be formed on the first carrier, a photoresist mask layer may be formed on the first package layer, the photoresist mask layer may have a plurality of openings spaced apart from each other, the openings expose the first package layer, the first package layer and the power device may be etched using the photoresist mask layer to form a plurality of grooves spaced apart from each other in the power device, wherein the plurality of grooves are arranged in a row, a depth of the groove located at a middle position of the row is the largest, a depth of the groove located at both end portions of the row is the smallest, and depths of the grooves from the middle position to each of the end portions are gradually reduced, and then a thermal conductive material may be deposited in the grooves to form a first thermal conductive pillar protruding from the first package layer, and further removing the photoresist mask layer to obtain a structure similar to the step 4.
Next, as shown in fig. 5, in step (5), a second carrier 6 is provided, the second carrier 6 is bonded to the upper surface of the first package layer 5, the first carrier 1 is removed, a circuit board 7 is disposed on the power device 2, the circuit board 7 is electrically connected to the power device 2, a plurality of second grooves 71 are formed on the circuit board 7 at intervals, a plurality of second heat-conducting pillars 8 are formed in the plurality of second grooves 71, top surfaces of the plurality of second heat-conducting pillars 8 are located at the same horizontal plane, and the second carrier 6 is removed to form a first package assembly.
In the step 5), the power element 2 and the circuit board 7 are electrically connected through a conductive bump, the depth of the second groove 71 is 50-80 μm, the second heat-conducting pillar 8 protrudes from the surface of the circuit board 7, and the ratio of the height of the protruding portion of the second heat-conducting pillar 8 to the height of the second heat-conducting pillar 8 is 0.15-0.3. In a preferred embodiment, the conductive bump may be a solder ball, and the depth of the second groove 71 is preferably 50 microns, 55 microns, 60 microns, 65 microns, 70 microns, 75 microns, 80 microns. The ratio of the height of the protruding portion of the second heat conduction column 8 to the height of the second heat conduction column 8 is preferably 0.15, 0.2, 0.25, 0.3, and by optimizing the ratio of the height of the protruding portion of the second heat conduction column 8 to the height of the second heat conduction column 8, the stability and the heat conduction performance of the second heat conduction column 8 are effectively ensured.
In the step 5), the middle area of the second carrier plate 6 has an opening penetrating through the second carrier plate 6 so that the plurality of first heat conduction pillars 4 penetrate through the second carrier plate 6, and a resin protection layer capable of protecting the conductive bumps may be further provided between the power element 2 and the circuit board 7.
In a specific embodiment, an organic functional layer (not shown) is formed in a central region of the second carrier 6, an adhesive layer (not shown) is formed on the surfaces of the second carrier 6 and the organic functional layer, an adhesion force between the adhesive layer and the organic functional layer is smaller than an adhesion force between the adhesive layer and the second carrier substrate, and the adhesive layer is bonded to the upper surface of the first encapsulation layer.
In this embodiment, the second carrier 6 may be one of a semiconductor substrate, a metal substrate, a ceramic substrate, a glass substrate, or a plastic substrate. The organic functional layer can be perfluorododecyl trichlorosilane, perfluorooctyl trichlorosilane, tetrahydrooctyl triethoxysilane or tetrahydrooctyl methyl dichlorosilane, and the thickness of the organic functional layer is preferably 10-20 nanometers. The organic functional layer is convenient for the subsequent stripping process.
In a specific embodiment, the specific steps of peeling off the first carrier 1 are as follows: cutting part of the first packaging layer 5 and part of the first carrier plate 1 to completely remove the bonding area between the first carrier plate 1 and the bonding adhesive layer 12, and because the adhesive force between the bonding adhesive layer 12 and the organic functional layer 11 is small, the first carrier substrate 1 can be peeled off under the action of small external force, so that the first carrier substrate 1 can be peeled off without using a CMP (chemical mechanical polishing) process, and the cost of the peeling process is effectively reduced.
In this embodiment, the material of the second heat-conducting pillar 8 is one or more of silver, copper, aluminum, iron, tin, and lead, and the second heat-conducting pillar 8 is formed by one or more of chemical vapor deposition, physical vapor deposition, electroplating, and electroless plating. In a specific embodiment, the material of the second heat-conducting pillar 8 is copper or aluminum, and is formed by an evaporation process.
Next, as shown in fig. 6, in step (6), a heat sink 9 is provided, a plurality of receiving cavities 91 are arranged in parallel on the upper surface of the heat sink 9, a strip-shaped groove is arranged on two opposite side surfaces of each receiving cavity 91, then a first packaging component is arranged in each receiving cavity 91, and the plurality of first heat-conducting pillars 4 and the plurality of second heat-conducting pillars 8 are respectively embedded into the corresponding strip-shaped grooves to form a first power stack.
In the step 6), after the first package assembly is placed in the accommodating cavity 91, a heat conducting and insulating material is injected into the accommodating cavity 91, so that the heat conducting and insulating material fills a gap between the accommodating cavity 91 and the first package assembly to seal the first package assembly, thereby effectively eliminating a gap between the first package assembly and the accommodating cavity 91 and effectively improving heat dissipation performance.
In a specific embodiment, heat dissipation channels are disposed between adjacent receiving cavities 91 in the heat sink 9 and on one side of the heat sink, so that heat dissipation fluid can flow through the heat dissipation channels, and an inlet and an outlet of the heat dissipation fluid are disposed on two sides of the heat sink 9.
Next, as shown in fig. 7, in step (7), a conductive substrate 10 is provided, and the first power stacks are disposed on both the upper surface and the lower surface of the conductive substrate 10, so that both the first power stacks are electrically connected to the conductive substrate 10, and then a second packaging layer 50 is formed, where the second packaging layer 50 wraps the conductive substrate 10 and both the first power stacks.
In the step 7), the second encapsulating layer 50 is thinned so that the bottom surface of the heat sink 9 is exposed, and the second encapsulating layer 50 may be epoxy resin.
As shown in fig. 7, the invention further provides a power device package structure, which is formed by the above method.
In the preparation process of the power element packaging structure, a plurality of first grooves arranged at intervals are formed on the non-active surface of the power element, the first grooves are arranged in a row, the depth of the first groove at the middle position of the row is the largest, the depth of the first groove at the two end parts of the row is the smallest, and the depths of the first grooves from the middle position to each end part are gradually reduced; then, a plurality of first heat-conducting columns are respectively formed in the first grooves, and the top surfaces of the first heat-conducting columns are positioned on the same horizontal plane; then forming a plurality of second grooves arranged at intervals on the circuit board, then respectively forming a plurality of second heat-conducting pillars in the plurality of second grooves, the top surfaces of the plurality of second heat-conducting pillars being located at the same horizontal plane, the above structure being arranged to facilitate heat dissipation of the power element, and the upper surface of the heat sink being provided with a plurality of receiving cavities arranged in parallel, each of the receiving cavities having a strip-shaped groove on both opposite sides, and then each of the receiving cavities being provided with one of the first heat-conducting pillars, and the plurality of first heat-conducting pillars and the plurality of second heat-conducting pillars being respectively embedded in the corresponding strip-shaped grooves to form a first power stack having excellent heat dissipation performance, and the upper surface of the heat sink being provided with a plurality of receiving cavities arranged in parallel, each of the first heat-conducting pillars being longitudinally embedded in the receiving cavity, the integration level of the power element packaging structure is improved.
The invention provides a power element packaging structure and a preparation method thereof.
Example 1: a preparation method of a power element packaging structure comprises the following steps:
(1) providing a first carrier plate and a power element, wherein the power element is provided with an active surface and a non-active surface, the active surface of the power element is provided with a conductive bonding pad, and then the power element is mounted on the first carrier plate in a manner that the active surface of the power element faces the first carrier plate;
(2) then, a mask layer is arranged on the first carrier plate, the mask layer is provided with a plurality of openings which are arranged at intervals, the openings expose the non-active surface of the power element, the power element is etched by using the mask layer to form a plurality of first grooves which are arranged at intervals, wherein the first grooves are arranged in a row, the depth of the first grooves in the middle of the row is the largest, the depth of the first grooves in the two end parts of the row is the smallest, and the depth of the first grooves from the middle to each end part is gradually reduced;
(3) then, a plurality of first heat-conducting columns are respectively formed in the first grooves, and the top surfaces of the first heat-conducting columns are positioned on the same horizontal plane;
(4) then, arranging a first packaging layer on the first carrier plate, wherein the first heat conduction columns protrude out of the upper surface of the first packaging layer;
(5) providing a second carrier plate, bonding the second carrier plate to the upper surface of the first packaging layer, removing the first carrier plate, arranging a circuit board on the power element, electrically connecting the circuit board to the power element, forming a plurality of second grooves arranged at intervals on the circuit board, respectively forming a plurality of second heat-conducting columns in the second grooves, wherein the top surfaces of the second heat-conducting columns are positioned on the same horizontal plane, and removing the second carrier plate to form a first packaging assembly;
(6) providing a heat radiator, wherein a plurality of accommodating cavities which are arranged in parallel are arranged on the upper surface of the heat radiator, a strip-shaped groove is arranged on two opposite side surfaces of each accommodating cavity, then a first packaging assembly is arranged in each accommodating cavity, and the first heat-conducting columns and the second heat-conducting columns are respectively embedded into the corresponding strip-shaped grooves to form a first power stack;
(7) providing a conductive substrate, arranging the first power stacks on the upper surface and the lower surface of the conductive substrate, so that the two first power stacks are electrically connected with the conductive substrate, and then forming a second packaging layer, wherein the second packaging layer wraps the conductive substrate and the two first power stacks.
Example 2: in the step 1), an organic functional layer is firstly formed in a central area of the first carrier, then an adhesive layer is formed on the surfaces of the first carrier and the organic functional layer, the adhesive force between the adhesive layer and the organic functional layer is smaller than that between the adhesive layer and the first carrier, and then the power element is arranged on the adhesive layer in a bonding mode.
Example 3: in the step 2), the mask layer is a photoresist mask layer, the first grooves are formed by wet etching or dry etching, the depth of the first grooves in the middle of the row is 40-60 micrometers, and the depth of the first grooves in the two end portions of the row is 10-30 micrometers.
Example 4: in the step 3), the material of the first heat-conducting pillar is one or more of silver, copper, aluminum, iron, tin and lead, and the first heat-conducting pillar is formed by one or more of chemical vapor deposition, physical vapor deposition, electroplating and electroless plating.
Example 5: in the step 4), the material of the first encapsulation layer is epoxy resin, and the ratio of the height of the protruding portion of the first heat conduction pillar to the height of the first heat conduction pillar is 0.2-0.4.
Example 6: in the step 5), the power element and the circuit board are electrically connected through a conductive bump, the depth of the second groove is 50-80 micrometers, the second heat-conducting pillar protrudes out of the surface of the circuit board, and the ratio of the height of the protruding portion of the second heat-conducting pillar to the height of the second heat-conducting pillar is 0.15-0.3.
Example 7: in the step 6), after the first package component is placed in the accommodating cavity, a heat conducting insulating material is injected into the accommodating cavity, so that the heat conducting insulating material fills a gap between the accommodating cavity and the first package component.
Example 8: in the step 7), thinning processing is performed on the second packaging layer, so that the bottom surface of the heat sink is exposed.
Example 9: the invention also provides a power element packaging structure which is prepared and formed by adopting the method.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (9)
1. A preparation method of a power element packaging structure is characterized by comprising the following steps: the method comprises the following steps:
(1) providing a first carrier plate and a power element, wherein the power element is provided with an active surface and a non-active surface, the active surface of the power element is provided with a conductive bonding pad, and then the power element is mounted on the first carrier plate in a manner that the active surface of the power element faces the first carrier plate;
(2) then, a mask layer is arranged on the first carrier plate, the mask layer is provided with a plurality of openings which are arranged at intervals, the openings expose the non-active surface of the power element, the power element is etched by using the mask layer to form a plurality of first grooves which are arranged at intervals, wherein the first grooves are arranged in a row, the depth of the first grooves in the middle of the row is the largest, the depth of the first grooves in the two end parts of the row is the smallest, and the depth of the first grooves from the middle to each end part is gradually reduced;
(3) then, a plurality of first heat-conducting columns are respectively formed in the first grooves, and the top surfaces of the first heat-conducting columns are positioned on the same horizontal plane;
(4) then, arranging a first packaging layer on the first carrier plate, wherein the first heat conduction columns protrude out of the upper surface of the first packaging layer;
(5) providing a second carrier plate, bonding the second carrier plate to the upper surface of the first packaging layer, removing the first carrier plate, arranging a circuit board on the power element, electrically connecting the circuit board to the power element, forming a plurality of second grooves arranged at intervals on the circuit board, respectively forming a plurality of second heat-conducting columns in the second grooves, wherein the top surfaces of the second heat-conducting columns are positioned on the same horizontal plane, and removing the second carrier plate to form a first packaging assembly;
(6) providing a heat radiator, wherein a plurality of accommodating cavities which are arranged in parallel are arranged on the upper surface of the heat radiator, a strip-shaped groove is arranged on two opposite side surfaces of each accommodating cavity, then a first packaging assembly is arranged in each accommodating cavity, and the first heat-conducting columns and the second heat-conducting columns are respectively embedded into the corresponding strip-shaped grooves to form a first power stack;
(7) providing a conductive substrate, arranging the first power stacks on the upper surface and the lower surface of the conductive substrate, so that the two first power stacks are electrically connected with the conductive substrate, and then forming a second packaging layer, wherein the second packaging layer wraps the conductive substrate and the two first power stacks.
2. The method for manufacturing the power device package structure according to claim 1, wherein: in the step 1), an organic functional layer is firstly formed in a central area of the first carrier, then an adhesive layer is formed on the surfaces of the first carrier and the organic functional layer, the adhesive force between the adhesive layer and the organic functional layer is smaller than that between the adhesive layer and the first carrier, and then the power element is arranged on the adhesive layer in a bonding mode.
3. The method for manufacturing the power device package structure according to claim 1, wherein: in the step 2), the mask layer is a photoresist mask layer, the first grooves are formed by wet etching or dry etching, the depth of the first grooves in the middle of the row is 40-60 micrometers, and the depth of the first grooves in the two end portions of the row is 10-30 micrometers.
4. The method for manufacturing the power device package structure according to claim 1, wherein: in the step 3), the material of the first heat-conducting pillar is one or more of silver, copper, aluminum, iron, tin and lead, and the first heat-conducting pillar is formed by one or more of chemical vapor deposition, physical vapor deposition, electroplating and electroless plating.
5. The method for manufacturing the power device package structure according to claim 1, wherein: in the step 4), the material of the first encapsulation layer is epoxy resin, and the ratio of the height of the protruding portion of the first heat conduction pillar to the height of the first heat conduction pillar is 0.2-0.4.
6. The method for manufacturing the power device package structure according to claim 1, wherein: in the step 5), the power element and the circuit board are electrically connected through a conductive bump, the depth of the second groove is 50-80 micrometers, the second heat-conducting pillar protrudes out of the surface of the circuit board, and the ratio of the height of the protruding portion of the second heat-conducting pillar to the height of the second heat-conducting pillar is 0.15-0.3.
7. The method for manufacturing the power device package structure according to claim 1, wherein: in the step 6), after the first package component is placed in the accommodating cavity, a heat conducting insulating material is injected into the accommodating cavity, so that the heat conducting insulating material fills a gap between the accommodating cavity and the first package component.
8. The method for manufacturing the power device package structure according to claim 1, wherein: in the step 7), thinning processing is performed on the second packaging layer, so that the bottom surface of the heat sink is exposed.
9. A power device package structure prepared by the method of any one of claims 1-8.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011348505.9A CN112420641A (en) | 2020-11-26 | 2020-11-26 | Power element packaging structure and preparation method thereof |
| PCT/CN2021/114631 WO2022110936A1 (en) | 2020-11-26 | 2021-08-26 | Power element packaging structure and manufacturing method therefor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011348505.9A CN112420641A (en) | 2020-11-26 | 2020-11-26 | Power element packaging structure and preparation method thereof |
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| CN112420641A true CN112420641A (en) | 2021-02-26 |
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| CN202011348505.9A Withdrawn CN112420641A (en) | 2020-11-26 | 2020-11-26 | Power element packaging structure and preparation method thereof |
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| CN (1) | CN112420641A (en) |
| WO (1) | WO2022110936A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113675099A (en) * | 2021-10-25 | 2021-11-19 | 南通市铭腾精密电子有限公司 | Heat dissipation type stacked package body and manufacturing method thereof |
| WO2022110936A1 (en) * | 2020-11-26 | 2022-06-02 | 苏州矽锡谷半导体科技有限公司 | Power element packaging structure and manufacturing method therefor |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4012496B2 (en) * | 2003-09-19 | 2007-11-21 | カシオ計算機株式会社 | Semiconductor device |
| WO2010132724A1 (en) * | 2009-05-14 | 2010-11-18 | Megica Corporation | System-in packages |
| US8933551B2 (en) * | 2013-03-08 | 2015-01-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D-packages and methods for forming the same |
| CN111564411B (en) * | 2020-06-08 | 2022-12-23 | 深圳铨力半导体有限公司 | Semiconductor device and forming method thereof |
| CN112420641A (en) * | 2020-11-26 | 2021-02-26 | 苏州矽锡谷半导体科技有限公司 | Power element packaging structure and preparation method thereof |
-
2020
- 2020-11-26 CN CN202011348505.9A patent/CN112420641A/en not_active Withdrawn
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2021
- 2021-08-26 WO PCT/CN2021/114631 patent/WO2022110936A1/en active Application Filing
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022110936A1 (en) * | 2020-11-26 | 2022-06-02 | 苏州矽锡谷半导体科技有限公司 | Power element packaging structure and manufacturing method therefor |
| CN113675099A (en) * | 2021-10-25 | 2021-11-19 | 南通市铭腾精密电子有限公司 | Heat dissipation type stacked package body and manufacturing method thereof |
| CN113675099B (en) * | 2021-10-25 | 2021-12-17 | 南通市铭腾精密电子有限公司 | Heat dissipation type stacked package body and manufacturing method thereof |
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| WO2022110936A1 (en) | 2022-06-02 |
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Application publication date: 20210226 |