KR20110107989A - Method for forming stacked semiconductor package - Google Patents

Method for forming stacked semiconductor package Download PDF

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Publication number
KR20110107989A
KR20110107989A KR1020100027223A KR20100027223A KR20110107989A KR 20110107989 A KR20110107989 A KR 20110107989A KR 1020100027223 A KR1020100027223 A KR 1020100027223A KR 20100027223 A KR20100027223 A KR 20100027223A KR 20110107989 A KR20110107989 A KR 20110107989A
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South Korea
Prior art keywords
semiconductor chip
reshaped
wafer
forming
electrode
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KR1020100027223A
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Korean (ko)
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김성철
정관호
손호영
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주식회사 하이닉스반도체
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Priority to KR1020100027223A priority Critical patent/KR20110107989A/en
Publication of KR20110107989A publication Critical patent/KR20110107989A/en

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Abstract

적층 반도체 패키지 형성방법이 개시되어 있다. 개시된 적층 반도체 패키지 형성방법은, 웨이퍼에 형성된 본딩 패드를 갖는 복수개의 반도체 칩들을 관통하는 관통 전극을 형성하는 단계와, 상기 관통 전극이 형성된 반도체 칩들을 칩 레벨로 개별화하는 단계와, 상기 반도체 칩들 중 불량 반도체 칩을 제거하고 상기 불량 반도체 칩이 제거된 부분에 관통 전극이 형성된 양품 반도체 칩을 부착하여 재형상 웨이퍼를 형성하는 단계와, 상기 관통 전극이 상호 연결되도록 상기 재형상 웨이퍼들을 적층하는 단계와, 상기 적층된 재형상 웨이퍼들을 칩 레벨로 절단하여 적층 반도체 칩 모듈들을 형성하는 단계를 포함하는 것을 특징으로 한다. A method of forming a laminated semiconductor package is disclosed. The disclosed method of forming a stacked semiconductor package includes forming a through electrode penetrating a plurality of semiconductor chips having a bonding pad formed on a wafer, individualizing the semiconductor chips on which the through electrode is formed at a chip level, and among the semiconductor chips. Removing a defective semiconductor chip and attaching a good semiconductor chip having a through electrode formed to a portion where the defective semiconductor chip has been removed to form a reshaped wafer, and stacking the reshaped wafers so that the through electrodes are interconnected; And cutting the stacked reshaped wafers to a chip level to form stacked semiconductor chip modules.

Description

적층 반도체 패키지 형성방법{METHOD FOR FORMING STACKED SEMICONDUCTOR PACKAGE}METHOD FOR FORMING STACKED SEMICONDUCTOR PACKAGE}

본 발명은 관통 전극을 이용한 적층 반도체 패키지 형성방법에 관한 것이다.The present invention relates to a method for forming a laminated semiconductor package using a through electrode.

관통 전극을 이용한 적층 반도체 패키지 형성방법으로는 칩 대 칩 본딩(chip to chip bonding), 웨이퍼 대 웨이퍼 본딩(wafer to wafer bonding) 방법이 있다.As a method of forming a stacked semiconductor package using a through electrode, there are a chip to chip bonding and a wafer to wafer bonding method.

칩 대 칩 본딩 방법은 스크라이브 레인(scribe lane)을 따라서 웨이퍼를 절단하여 웨이퍼 내의 반도체 칩들을 개별화시킨 다음, 개별화된 반도체 칩들 중 양품 반도체 칩(good chip)들만을 적층하여 적층 반도체 패키지를 형성하는 방법으로, 기술적 난이도가 낮아 용이하게 적용할 수 있는 반면에 반도체 칩들을 개별적으로 일일이 적층해야 하므로 시간 및 노력이 많이 소요되어 생산성이 떨어지는 문제가 있다.The chip-to-chip bonding method is a method of cutting a wafer along a scribe lane to individualize semiconductor chips in the wafer, and then stacking only good semiconductor chips among the individualized semiconductor chips to form a stacked semiconductor package. On the other hand, the technical difficulty can be easily applied, while the semiconductor chips need to be stacked individually, thereby requiring a lot of time and effort, thereby reducing productivity.

웨이퍼 대 웨이퍼 본딩 방법은 웨이퍼들을 적층한 다음 적층된 웨이퍼들을 스크라이브 레인을 따라 한꺼번에 절단하여 다수의 적층 반도체 패키지를 형성하는 방법으로, 다수의 적층 반도체 패키지를 한꺼번에 제작할 수 있어 생산성 측면에서 매우 유리하다. 그러나, 각 웨이퍼 별로 불량 반도체 칩의 위치가 다르고, 적층 반도체 패키지 내에 하나의 불량 반도체 칩이 존재하는 경우에도 해당 적층 반도체 패키지 전체가 불량으로 처리되어 사용할 수 없게 되기 때문에, 적층되는 웨이퍼의 개수가 증가할수록 수율이 급격히 떨어지는 단점이 있다. 예컨데, 수율이 80%인 웨이퍼를 4장 적층하였을 경우, 수율은 46%에 불과하다.The wafer-to-wafer bonding method is a method of stacking wafers and then cutting the stacked wafers together along a scribe lane to form a plurality of stacked semiconductor packages, which is very advantageous in terms of productivity because a plurality of stacked semiconductor packages can be manufactured at once. However, since the position of the defective semiconductor chip is different for each wafer, and even if one defective semiconductor chip exists in the stacked semiconductor package, the entire stacked semiconductor package is treated as defective and cannot be used, so the number of stacked wafers increases. There is a drawback that the more rapidly the yield falls. For example, when four wafers with 80% yield are stacked, the yield is only 46%.

본 발명은, 생산성 및 수율을 향상시키기 위한 적층 반도체 패키지 형성방법을 제공하는데, 그 목적이 있다. SUMMARY OF THE INVENTION The present invention provides a method of forming a laminated semiconductor package for improving productivity and yield.

본 발명의 일 견지에 따른 적층 반도체 패키지 형성방법은, 웨이퍼에 형성된 본딩 패드를 갖는 복수개의 반도체 칩들을 관통하는 관통 전극을 형성하는 단계와, 상기 관통 전극이 형성된 반도체 칩들을 칩 레벨로 개별화하는 단계와, 상기 반도체 칩들 중 불량 반도체 칩을 제거하고 상기 불량 반도체 칩이 제거된 부분에 관통 전극이 형성된 양품 반도체 칩을 부착하여 재형상 웨이퍼를 형성하는 단계와, 상기 관통 전극이 상호 연결되도록 상기 재형상 웨이퍼들을 적층하는 단계와, 상기 적층된 재형상 웨이퍼들을 칩 레벨로 절단하여 적층 반도체 칩 모듈들을 형성하는 단계를 포함하는 것을 특징으로 한다. In accordance with an aspect of the present invention, a method of forming a stacked semiconductor package includes forming a through electrode penetrating a plurality of semiconductor chips having a bonding pad formed on a wafer, and individualizing the semiconductor chips having the through electrode formed at a chip level. And removing a defective semiconductor chip among the semiconductor chips and attaching a good semiconductor chip having a through electrode to a portion from which the defective semiconductor chip is removed to form a reshaped wafer, and wherein the reshaped electrode is connected to each other. Stacking the wafers, and cutting the stacked reshaped wafers at a chip level to form stacked semiconductor chip modules.

상기 관통 전극을 형성하는 단계는, 상기 본딩 패드가 위치하는 상기 웨이퍼의 전면으로부터 상기 반도체 칩을 식각하여 블라인드 비아홀을 형성하는 단계와, 상기 블라인드 비아홀에 금속 물질을 충진하여 상기 관통 전극을 형성하는 단계와, 상기 전면과 대향하는 후면으로 상기 관통 전극이 노출되도록 상기 후면을 연마하는 단계를 포함하는 것을 특징으로 한다.The forming of the through electrode may include forming a blind via hole by etching the semiconductor chip from a front surface of the wafer where the bonding pad is located, and filling the blind via hole with a metal material to form the through electrode. And polishing the rear surface such that the through electrode is exposed to the rear surface opposite to the front surface.

상기 후면을 연마하는 단계 전에, 상기 전면에 휨 방지 기판을 부착하는 단계를 더 포함하는 것을 특징으로 한다.The method may further include attaching a warpage prevention substrate to the front surface before the polishing of the back surface.

상기 휨 방지 기판은 상기 반도체 칩들을 칩 레벨로 개별화하기 전에 제거하는 것을 특징으로 한다. The anti-warp substrate may be removed before individualizing the semiconductor chips to the chip level.

상기 반도체 칩들을 칩 레벨로 개별화하는 단계 전에, 상기 본딩 패드가 위치하는 상기 웨이퍼의 전면과 대향하는 후면에 마운팅 테이프를 부착하는 단계를 더 포함하는 것을 특징으로 한다.Prior to the step of individualizing the semiconductor chip to the chip level, further comprising the step of attaching a mounting tape on the back surface opposite the front surface of the wafer where the bonding pad is located.

상기 재형상 웨이퍼를 적층하는 단계 전에, 상기 반도체 칩들을 개별화하는 단계로 인해 벌어진 상기 반도체 칩들간 간격을 좁히는 단계를 더 포함하는 것을 특징으로 한다.Before the stacking the reshaped wafer, characterized in that it further comprises the step of narrowing the gap between the semiconductor chips caused by the step of individualizing the semiconductor chips.

상기 재형상 웨이퍼를 형성하는 단계 후, 상기 재형상 웨이퍼들을 적층하는 단계 전에, 상기 재형상 웨이퍼에 캐리어 기판을 부착하는 단계를 더 포함하는 것을 특징으로 한다.And attaching a carrier substrate to the reshaped wafer after forming the reshaped wafer and before stacking the reshaped wafers.

상기 적층 반도체 칩 모듈들을 형성하는 단계 후에, 상기 적층 반도체 칩 모듈을 기판에 실장하는 단계를 더 포함하는 것을 특징으로 한다.After the forming of the stacked semiconductor chip modules, the method may further include mounting the stacked semiconductor chip module on a substrate.

본 발명의 다른 견지에 따른 적층 반도체 패키지 형성방법은, 웨이퍼에 형성된 본딩 패드를 갖는 복수개의 반도체 칩들을 상기 본딩 패드가 위치하는 전면으로부터 식각하여 제 1 블라인드 비아홀을 형성하고 상기 제 1 블라인드 비아홀에 관통 전극을 형성하는 단계와, 상기 반도체 칩들 중 불량 반도체 칩 주변의 스크라이브 레인을 상기 전면으로부터 식각하여 제 2 블라인드 비아홀을 형성하는 단계와, 상기 관통 전극 및 상기 제 2 블라인드 비아홀이 노출되도록 상기 후면을 연마하여 상기 불량 반도체 칩을 상기 웨이퍼로부터 제거하는 단계와, 상기 불량 반도체 칩이 제거된 부분에 관통 전극이 형성된 양품 반도체 칩을 부착하여 재형상 웨이퍼를 형성하는 단계와, 상기 관통 전극이 상호 연결되도록 상기 재형상 웨이퍼들을 적층하는 단계와, 상기 적층된 재형상 웨이퍼들을 칩 레벨로 절단하여 적층 반도체 칩 모듈을 형성하는 단계를 포함하는 것을 특징으로 한다.According to another aspect of the present invention, a method of forming a stacked semiconductor package includes etching a plurality of semiconductor chips having bonding pads formed on a wafer from a front surface where the bonding pads are located to form a first blind via hole and penetrate the first blind via hole. Forming an electrode, etching a scribe lane around the defective semiconductor chip from the front surface to form a second blind via hole, and polishing the back surface to expose the through electrode and the second blind via hole Removing the defective semiconductor chip from the wafer, attaching a good semiconductor chip having a through electrode to a portion from which the defective semiconductor chip has been removed, and forming a reshaped wafer; Stacking the reshaped wafers; And cutting the stacked reshaped wafers at the chip level to form a stacked semiconductor chip module.

상기 제 2 블라인드 비아홀은 상기 관통 전극보다 깊은 깊이로 형성하는 것을 특징으로 한다.The second blind via hole may be formed deeper than the through electrode.

상기 제 2 블라인드 비아홀을 형성하는 단계는 레이저 드릴링 공정, 드릴링 공정 및 사진 식각 공정 중 적어도 어느 하나를 사용하여 수행되는 것을 특징으로 한다.The forming of the second blind via hole may be performed using at least one of a laser drilling process, a drilling process, and a photolithography process.

상기 재형상 웨이퍼를 적층하는 단계 전에, 상기 재형상 웨이퍼에 캐리어 기판을 부착하는 단계를 더 포함하는 것을 특징으로 한다.The method may further include attaching a carrier substrate to the reshaped wafer prior to stacking the reshaped wafer.

상기 적층 반도체 칩 모듈들을 형성하는 단계 후, 상기 적층 반도체 칩 모듈을 기판에 실장하는 단계를 더 포함하는 것을 특징으로 한다.After the forming of the stacked semiconductor chip modules, the method further comprises mounting the stacked semiconductor chip module on a substrate.

본 발명은, 적층 반도체 패키지 제작에 소요되는 시간 및 노력을 줄일 수 있고, 수율을 향상시킬 수 있는 효과가 있다.The present invention can reduce the time and effort required to manufacture a laminated semiconductor package, and can improve the yield.

도 1 내지 도 13은 본 발명의 제 1 실시예에 의한 적층 반도체 패키지 형성 과정을 공정 수순에 따라 도시한 단면도들이다.
도 14 내지 25는 본 발명의 제 2 실시예에 의한 적층 반도체 패키지 형성 과정을 공정 수순에 따라 도시한 단면도들이다.
도 26 내지 도 28은 도 16에 도시된 제 2 블라인드 비아홀 형성 과정을 도시한 단면도들이다.1 to 13 are cross-sectional views illustrating a process of forming a multilayer semiconductor package according to a first embodiment of the present invention according to a process procedure.
14 to 25 are cross-sectional views illustrating a process of forming a multilayer semiconductor package according to a second embodiment of the present invention according to a process procedure.
26 to 28 are cross-sectional views illustrating a process of forming the second blind via hole illustrated in FIG. 16.

이하, 첨부된 도면들을 참조하여 본 발명의 바람직한 실시예들을 상세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

-제 1 실시예-- First Embodiment -

도 1 내지 도 13은 본 발명의 제 1 실시예에 의한 적층 반도체 패키지 형성 과정을 공정 수순에 따라 도시한 단면도들이다.1 to 13 are cross-sectional views illustrating a process of forming a multilayer semiconductor package according to a first embodiment of the present invention according to a process procedure.

도 1을 참조하면, 본딩패드(미도시)를 갖는 복수개의 반도체 칩(D)들이 형 성된 웨이퍼(W)가 제공된다.Referring to FIG. 1, a wafer W in which a plurality of semiconductor chips D having a bonding pad (not shown) is formed is provided.

웨이퍼(W)는 전면(前面, 110) 및 전면(110)과 대향하는 후면(後面, 120)을 갖는다. 반도체 칩(D)의 본딩 패드는 웨이퍼(W)에 전면(110)에 위치된다. 반도체 칩(D)은 데이터를 저장 및 처리하기 위한 회로부(미도시)를 포함하며, 본딩 패드는 와부와의 연결을 위한 회로부의 전기적 접점에 해당한다.The wafer W has a front surface 110 and a back surface 120 facing the front surface 110. The bonding pads of the semiconductor chip D are positioned on the front surface 110 of the wafer W. The semiconductor chip D includes a circuit unit (not shown) for storing and processing data, and the bonding pad corresponds to an electrical contact of the circuit unit for connection with the vortex.

이어, EDS(Electric Die Sorting) 테스트와 같은 불량 검사를 실시하여 불량 여부에 따라서 반도체 칩(D)들을 불량 반도체 칩과 양품 반도체 칩로 구분한다. 도면에서, 도트(dot) 표시된 반도체 칩은 불량 반도체 칩을, 도트 표시되지 않은 반도체 칩은 양품 반도체 칩을 나타낸다. 그리고, 미설명한 도면부호 S는 반도체 칩(D)들 사이에 위치하는 스크라이브 레인(scribe lane)을 나타낸다. Subsequently, a defect inspection such as an electric die sorting (EDS) test is performed to classify the semiconductor chips D into a defective semiconductor chip and a good semiconductor chip according to a defect. In the figure, a semiconductor chip with dots is represented by a defective semiconductor chip, and a semiconductor chip without dots is represented by a good semiconductor chip. In addition, reference numeral S denotes a scribe lane located between the semiconductor chips D. FIG.

도 2 내지 도 4를 참조하면, 반도체 칩(D)을 관통하는 관통 전극(10)을 형성한다.2 to 4, a through electrode 10 penetrating the semiconductor chip D is formed.

구체적으로, 도 2를 참조하면, 사진 식각 공정으로 전면(110)으로부터 반도체 칩(D)을 식각하여 블라인드 비아홀(blind via hole, 11)들을 형성하고, 블라인드 비아홀(11) 내부에 금속 물질, 예컨데 구리를 충진하여 반도체 칩(D)의 본딩 패드와 전기적으로 연결되는 관통 전극(10)을 형성한다. Specifically, referring to FIG. 2, a blind via hole 11 is formed by etching the semiconductor chip D from the front surface 110 by a photolithography process, and a metal material, for example, inside the blind via hole 11. Copper is filled to form the through electrode 10 electrically connected to the bonding pad of the semiconductor chip D.

블라인드 비아홀(11)은 본딩 패드를 관통하는 위치에 형성될 수 있다. 블라인드 비아홀(11)은 드릴링 공정, 레이저 드릴링 공정 및 사진 식각 공정 중 어느 하나에 의해 형성될 수 있다. 관통 전극(10)은 무전해 도금 공정 또는 씨드 금속층을 이용한 전해 도금 공정에 의해 형성될 수 있다.The blind via hole 11 may be formed at a position passing through the bonding pad. The blind via hole 11 may be formed by any one of a drilling process, a laser drilling process, and a photolithography process. The through electrode 10 may be formed by an electroless plating process or an electrolytic plating process using a seed metal layer.

도 3을 참조하면, 웨이퍼(W)의 전면(110)에 휨 방지 기판(200)이 부착한다. Referring to FIG. 3, the warpage prevention substrate 200 is attached to the front surface 110 of the wafer (W).

휨 방지 기판(200)은 유리 기판(glass substrate) 또는 베어 실리콘 기판(bare silicon substrate)일 수 있다. 휨 방지 기판(200)을 웨이퍼(W)의 전면(110)에 부착함으로써, 이후 진행되는 후면 연마 공정 중에 웨이퍼(W) 또는 웨이퍼(W)에 형성된 반도체 칩(D)의 휨 및/또는 형상 변형을 방지할 수 있다. The anti-warp substrate 200 may be a glass substrate or a bare silicon substrate. By attaching the warpage prevention substrate 200 to the front surface 110 of the wafer W, the warpage and / or deformation of the semiconductor chip D formed on the wafer W or the wafer W during the subsequent backside polishing process. Can be prevented.

도 4를 참조하면, 웨이퍼(W)의 후면(120)을 연마하여 관통 전극(10)을 후면(120)으로 노출시킨다.Referring to FIG. 4, the back surface 120 of the wafer W is polished to expose the through electrode 10 to the back surface 120.

도 5를 참조하면, 웨이퍼(W)의 후면(120)에 마운팅 테이프(mounting tape, 300)를 부착하고 스크라이브 레인(S)을 따라서 웨이퍼(W)를 절단하여 반도체 칩(D)들을 개별화한다.Referring to FIG. 5, the mounting tape 300 is attached to the rear surface 120 of the wafer W, and the semiconductor chips D are separated by cutting the wafer W along the scribe lane S. Referring to FIG.

이때, 웨이퍼(W)가 마운팅 테이프(300)에 부착된 상태에서 절단되기 때문에 반도체 칩(D)들이 개별화되더라도 반도체 칩(D)들은 마운팅 테이프(300)에 부착된 상태로 흩어지지 않는다.At this time, since the wafer W is cut in the state in which it is attached to the mounting tape 300, even if the semiconductor chips D are individualized, the semiconductor chips D are not scattered in the state where they are attached to the mounting tape 300.

도 6을 참조하면, 불량 반도체 칩을 제거한다. Referring to FIG. 6, the defective semiconductor chip is removed.

불량 반도체 칩을 제거하는 방법으로는 불량 반도체 칩 아래쪽에서 위쪽으로 힘을 가하여 불량 반도체 칩 하부의 마운팅 테이프(300)를 신장(伸長)시켜 마운팅 테이프(300)와 불량 반도체 칩간 접착력을 약화시킨 상태에서 다이 픽업 장치로 불량 반도체 칩을 흡착시키어 마운팅 테이프(300)로부터 불량 반도체 칩을 떼어내는 방법을 사용할 수 있다.In order to remove the defective semiconductor chip, a force is applied from the bottom of the defective semiconductor chip upward to extend the mounting tape 300 under the defective semiconductor chip to weaken the adhesive force between the mounting tape 300 and the defective semiconductor chip. The method of adsorb | sucking a bad semiconductor chip with a die pick-up apparatus, and removing a bad semiconductor chip from the mounting tape 300 can be used.

도 7을 참조하면, 불량 반도체 칩이 제거된 부위에 양품 반도체 칩을 부착하여 양품 반도체 칩들로 이루어진 재형상 웨이퍼(RW)를 형성한다. 상기 부착되는 반도체 칩은 웨이퍼(W)에 제조된 반도체 칩(D)과 실질적으로 동일한 형태를 갖는다. Referring to FIG. 7, a good semiconductor chip is attached to a portion where a bad semiconductor chip is removed to form a reshaped wafer RW formed of good semiconductor chips. The attached semiconductor chip has substantially the same shape as the semiconductor chip D manufactured on the wafer W. FIG.

도 8을 참조하면, 반도체 칩(D)들을 개별화하는 과정에서 벌어진 반도체 칩(D)들간 간격을 좁힌다. 이 단계는 경우에 따라서 생략 가능하다.Referring to FIG. 8, the gap between the semiconductor chips D formed in the process of individualizing the semiconductor chips D is narrowed. This step may be omitted in some cases.

도 9를 참조하면, 마운팅 테이프(300)를 매개로 재형상 웨이퍼(RW)에 캐리어 기판(400)을 부착한다.9, the carrier substrate 400 is attached to the reshaped wafer RW through the mounting tape 300.

캐리어 기판(400)은 유리 기판 또는 베어 실리콘 기판일 수 있다. 캐리어 기판(400)을 부착함으로써, 이후 진행되는 재형상 웨이퍼(RW)를 적층하는 공정 중에 재형상 웨이퍼(RW) 또는 재형상 웨이퍼(RW)에 존재하는 반도체 칩(D)의 휨 및/또는 형상 변형을 방지할 수 있다. The carrier substrate 400 may be a glass substrate or a bare silicon substrate. By attaching the carrier substrate 400, the bending and / or shape of the semiconductor chip D present in the reshaped wafer RW or the reshaped wafer RW during the subsequent process of stacking the reshaped wafer RW. The deformation can be prevented.

이러한 방법으로, 후면(120)에 마운팅 테이프(300) 및 캐리어 기판(400)이 부착된 재형상 웨이퍼(RW)를 복수개 형성한다.In this way, a plurality of reshaped wafers RW having the mounting tape 300 and the carrier substrate 400 attached thereto are formed on the rear surface 120.

도 10을 참조하면, 관통 전극(10)들이 상호 연결되도록 재형상 웨이퍼(RW)들을 적층한다. Referring to FIG. 10, reshaped wafers RW are stacked such that the through electrodes 10 are interconnected.

도 11을 참조하면, 상부에 적층된 재형상 웨이퍼(RW)에 부착된 마운팅 테이프(300) 및 캐리어 기판(400)을 제거한다.Referring to FIG. 11, the mounting tape 300 and the carrier substrate 400 attached to the reshaped wafer RW stacked thereon are removed.

도 12를 참조하면, 관통 전극(10)이 상호 연결되도록 재형상 웨이퍼(RW)를 적층하고 상부에 적층된 재형상 웨이퍼(RW)에 부착된 마운팅 테이프(300) 및 캐리어 기판(400)을 제거하는 과정을 반복하여, 원하는 수만큼 재형상 웨이퍼(RW)들을 적층한다.Referring to FIG. 12, the reshaped wafer RW is stacked so that the through electrodes 10 are interconnected, and the mounting tape 300 and the carrier substrate 400 attached to the reshaped wafer RW stacked thereon are removed. The process is repeated to stack the reshaped wafers RW as many times as desired.

도 13을 참조하면, 적층된 재형상 웨이퍼(RW)들 하부에 부착된 마운팅 테이프(300) 및 캐리어 기판(400)을 제거하고, 적층된 재형상 웨이퍼(RW)들을 칩 레벨로 절단하여 적층 반도체 칩 모듈(500)을 형성한다.Referring to FIG. 13, the mounting tape 300 and the carrier substrate 400 attached to the stacked reshaped wafers RW are removed, and the stacked reshaped wafers RW are cut at a chip level to stack semiconductors. The chip module 500 is formed.

이어, 적층 반도체 칩 모듈(500)을 상면(610)에 접속 패드(630)가 형성된 기판(600) 상에 관통 전극(10)이 접속 패드(630)와 연결되도록 실장하고, 적층 반도체 칩 모듈(500)을 포함한 기판(600) 상부를 몰딩하는 몰드부(700)를 형성한다. 그리고, 기판(600) 하면(620)에 형성된 볼랜드(640)에 솔더볼과 같은 외부접속단자(800)를 장착하여 최종적으로 적층 반도체 패키지를 완성한다.
Subsequently, the stacked semiconductor chip module 500 is mounted on the substrate 600 on which the connection pads 630 are formed on the upper surface 610 such that the through electrode 10 is connected to the connection pads 630. A mold part 700 that forms an upper portion of the substrate 600 including the 500 is formed. Then, the external connection terminal 800 such as solder balls is mounted on the ball land 640 formed on the lower surface 620 of the substrate 600 to finally complete the laminated semiconductor package.

-제 2 실시예-- Second Embodiment -

도 14 내지 25는 본 발명의 제 2 실시예에 의한 적층 반도체 패키지 형성 과정을 공정 수순에 따라 도시한 단면도들이다.14 to 25 are cross-sectional views illustrating a process of forming a multilayer semiconductor package according to a second embodiment of the present invention according to a process procedure.

도 14를 참조하면, 본딩패드(미도시)를 갖는 복수개의 반도체 칩(D)들이 형 성된 웨이퍼(W)가 제공된다.Referring to FIG. 14, a wafer W in which a plurality of semiconductor chips D having a bonding pad (not shown) is formed is provided.

웨이퍼(W)는 전면(110) 및 전면(110)과 대향하는 후면(120)을 갖는다. 반도체 칩(D)의 본딩 패드는 웨이퍼(W)에 전면(110)에 위치된다. 반도체 칩(D)은 데이터를 저장 및 처리하기 위한 회로부(미도시)를 포함하며, 본딩 패드는 와부와의 연결을 위한 회로부의 전기적 접점에 해당한다.The wafer W has a front surface 110 and a back surface 120 opposite the front surface 110. The bonding pads of the semiconductor chip D are positioned on the front surface 110 of the wafer W. The semiconductor chip D includes a circuit unit (not shown) for storing and processing data, and the bonding pad corresponds to an electrical contact of the circuit unit for connection with the vortex.

이어, EDS 테스트와 같은 불량 검사를 실시하여 불량 여부에 따라서 반도체 칩(D)들을 불량 반도체 칩과 양품 반도체 칩로 구분한다. 도면에서, 도트 표시된 반도체 칩은 불량 반도체 칩을, 도트 표시되지 않은 반도체 칩은 양품 반도체 칩을 나타낸다. 그리고, 미설명한 도면부호 S는 반도체 칩(D)들 사이에 위치하는 스크라이브 레인을 나타낸다. Subsequently, a defect inspection such as an EDS test is performed to classify the semiconductor chips D into a defective semiconductor chip and a good semiconductor chip according to a defect. In the figure, a dot-coded semiconductor chip represents a defective semiconductor chip, and a dot-free semiconductor chip represents a good semiconductor chip. In addition, reference numeral S denotes a scribe lane located between the semiconductor chips D. FIG.

도 15를 참조하면, 사진 식각 공정으로 전면(110)으로부터 반도체 칩(D)들을 식각하여 제 1 블라인드 비아홀(11)을 형성하고, 제 1 블라인드 비아홀(11) 내부에 금속 물질, 예컨데 구리를 충진하여 각 반도체 칩(D)들의 본딩패드와 전기적으로 연결되는 관통 전극(10)을 형성한다. Referring to FIG. 15, the semiconductor chips D are etched from the front surface 110 by a photolithography process to form a first blind via hole 11, and a metal material, for example, copper, is filled in the first blind via hole 11. As a result, the through electrode 10 electrically connected to the bonding pads of the semiconductor chips D is formed.

제 1 블라인드 비아홀(11)은 본딩패드를 관통하는 위치에 형성될 수 있다. 제 1 블라인드 비아홀(11)은 드릴링 공정, 레이저 드릴링 공정 및 사진 식각 공정 중 어느 하나에 의해 형성될 수 있다. 관통 전극(10)은 무전해 도금 공정 또는 씨드 금속층을 이용한 전해 도금 공정에 의해 형성될 수 있다.The first blind via hole 11 may be formed at a position passing through the bonding pad. The first blind via hole 11 may be formed by any one of a drilling process, a laser drilling process, and a photolithography process. The through electrode 10 may be formed by an electroless plating process or an electrolytic plating process using a seed metal layer.

도 16을 참조하면, 불량 반도체 칩 주위의 스크라이브 레인(S)을 전면(110)으로부터 식각하여 제 2 블라인드 비아홀(12)을 형성한다. Referring to FIG. 16, the scribe lane S around the bad semiconductor chip is etched from the front surface 110 to form the second blind via hole 12.

본 실시예에서, 제 2 블라인드 비아홀(12)은 관통 전극(10)보다 깊은 깊이로 형성한다. 제 2 블라인드 비아홀(12) 형성방법으로는 레이저 드릴링 공정, 드릴링 공정 및 사진 식각 공정 중 적어도 어느 하나를 사용할 수 있다.In the present embodiment, the second blind via hole 12 is formed deeper than the through electrode 10. As the method of forming the second blind via hole 12, at least one of a laser drilling process, a drilling process, and a photolithography process may be used.

제 2 블라인드 비아홀(12)을 형성하는 방법의 일예를, 도 26 내지 도 28을 참조하여 구체적으로 살펴보면 다음과 같다.An example of a method of forming the second blind via hole 12 will now be described in detail with reference to FIGS. 26 to 28.

도 26을 참조하면, 웨이퍼(W)의 전면(110)에는 실리콘층 상에 반도체 제조 공정을 통해 금속, 절연층, 실리콘 등으로 이루어진 복잡하고 다양한 패턴층이 형성되어 있다.Referring to FIG. 26, a complicated and various pattern layer made of metal, an insulating layer, silicon, and the like is formed on a front surface 110 of a wafer W through a semiconductor manufacturing process on a silicon layer.

도 27을 참조하면, 먼저 패턴층을 절단하기 위하여 레이저 드릴링 공정으로 불량 반도체 칩 주위의 스크라이브 레인(S)을 전면(110)으로부터 일정 깊이, 예컨데, 5 내지 10㎛의 깊이로 절단한다.Referring to FIG. 27, first, the scribe lane S around the bad semiconductor chip is cut from the front surface 110 to a predetermined depth, for example, 5 to 10 μm, by a laser drilling process to cut the pattern layer.

도 28을 참조하면, 전면(110)에 불량 반도체 칩 주위의 스크라이브 레인(S)을 오픈하는 포토레지스트 패턴(PR)을 형성하고, 포토레지스트 패턴(PR)을 마스크로 스크라이브 레인(S)을 관통 전극(10)보다 깊게 식각하여 제 2 블라인드 비아홀(12)을 형성한다. Referring to FIG. 28, a photoresist pattern PR is formed on the front surface 110 to open the scribe lane S around the defective semiconductor chip, and penetrates the scribe lane S using the photoresist pattern PR as a mask. The second blind via hole 12 is formed by etching deeper than the electrode 10.

이후, 포토레지스트 패턴(PR)을 제거한다. Thereafter, the photoresist pattern PR is removed.

이처럼, 패턴층이 형성된 부위를 레이저 드릴링 공정을 이용해 절단한 다음에 식각 공정으로 적용하면 작은 피치의 스크라이브 레인(S)에 효과적으로 제 2 블라인드 비아홀(12)을 형성할 수 있다.As such, when the portion where the pattern layer is formed is cut by using a laser drilling process and then applied by an etching process, the second blind via hole 12 may be effectively formed in the scribe lane S having a small pitch.

도 17을 참조하면, 제 2 블라인드 비아홀(12) 및 관통 전극(10)이 노출되도록 웨이퍼(W)의 후면(120)을 연마한다.Referring to FIG. 17, the rear surface 120 of the wafer W is polished to expose the second blind via hole 12 and the through electrode 10.

상기 연마 공정에 의하여 제 2 블라인드 비아홀(12)의 바닥이 뚫림에 따라 불량 반도체 칩은 웨이퍼(W)로부터 분리된다.As the bottom of the second blind via hole 12 is drilled by the polishing process, the defective semiconductor chip is separated from the wafer W.

도 18을 참조하면, 분리된 불량 반도체 칩을 제거한다.Referring to FIG. 18, the separated bad semiconductor chip is removed.

도 19를 참조하면, 웨이퍼(W)의 후면(120)에 마운팅 테이프(300)를 부착하고, 마운팅 테이프(300)를 매개로 캐리어 기판(400)을 부착한다.Referring to FIG. 19, the mounting tape 300 is attached to the rear surface 120 of the wafer W, and the carrier substrate 400 is attached to the mounting tape 300 via the mounting tape 300.

도 20을 참조하면, 불량 반도체 칩이 제거된 부분에 양품 반도체 칩을 부착하여, 양품 반도체 칩들로만 이루어진 재형상 웨이퍼(RW)를 형성한다. 상기 부착되는 반도체 칩은 웨이퍼(W) 상에 형성된 반도체 칩(D)과 실질적으로 동일한 형태를 갖는다. Referring to FIG. 20, a good semiconductor chip is attached to a portion from which a bad semiconductor chip is removed to form a reshaped wafer RW consisting of only good semiconductor chips. The attached semiconductor chip has substantially the same shape as the semiconductor chip D formed on the wafer W. FIG.

이러한 방식으로 마운팅 테이프(300) 및 캐리어 기판(400)이 부착된 재형상 웨이퍼(RW)를 복수개 형성한다.In this manner, a plurality of reshaped wafers RW to which the mounting tape 300 and the carrier substrate 400 are attached are formed.

도 21을 참조하면, 관통 전극(10)이 상호 연결되도록 재형상 웨이퍼(RW)들을 적층한다.Referring to FIG. 21, reshaped wafers RW are stacked such that the through electrodes 10 are interconnected.

도 22를 참조하면, 상부에 적층된 재형상 웨이퍼(RW)에 부착된 마운팅 테이프(300) 및 캐리어 기판(400)을 제거한다.Referring to FIG. 22, the mounting tape 300 and the carrier substrate 400 attached to the reshaped wafer RW stacked thereon are removed.

도 23을 참조하면, 관통 전극(10)이 상호 연결되도록 재형상 웨이퍼(RW)를 적층하고 상부에 적층된 재형상 웨이퍼(RW)에 부착된 마운팅 테이프(300) 및 캐리어 기판(400)을 제거하는 과정을 반복하여, 원하는 수만큼 재형상 웨이퍼(RW)들을 적층한다.Referring to FIG. 23, a reshaped wafer RW is stacked so that the through electrodes 10 are interconnected, and the mounting tape 300 and the carrier substrate 400 attached to the reshaped wafer RW stacked thereon are removed. The process is repeated to stack the reshaped wafers RW as many times as desired.

도 24를 참조하면, 적층된 재형상 웨이퍼(RW)들 하부에 부착된 마운팅 테이프(300) 및 캐리어 기판(400)을 제거한다.Referring to FIG. 24, the mounting tape 300 and the carrier substrate 400 attached to the stacked reshaped wafers RW are removed.

도 25를 참조하면, 적층된 재형상 웨이퍼(RW)들을 칩 레벨로 절단하여 적층 반도체 칩 모듈(500)을 형성한다.Referring to FIG. 25, the stacked reshaped wafers RW are cut at a chip level to form a stacked semiconductor chip module 500.

이어, 적층 반도체 칩 모듈(500)을 상면(610)에 접속 패드(630)가 형성된 기판(600) 상에 관통 전극(10)이 접속 패드(630)와 연결되도록 실장하고, 적층 반도체 칩 모듈(500)을 포함한 기판(600) 상부를 몰딩하는 몰드부(700)를 형성한다. 그리고, 기판(600) 하면(620)에 형성된 볼랜드(640)에 솔더볼과 같은 외부접속단자(800)를 장착하여 최종적으로 적층 반도체 패키지를 완성한다.Subsequently, the through-electrode 10 is mounted on the substrate 600 on which the connection pad 630 is formed on the top surface 610 so as to be connected to the connection pad 630. A mold part 700 that forms an upper portion of the substrate 600 including the 500 is formed. Then, the external connection terminal 800 such as solder balls is mounted on the ball land 640 formed on the lower surface 620 of the substrate 600 to finally complete the laminated semiconductor package.

이상에서 상세하게 설명한 바에 의하면, 적층 반도체 패키지 제작에 소요되는 시간 및 노력을 줄일 수 있고, 수율을 향상시킬 수 있는 효과가 있다.As described in detail above, the time and effort required for manufacturing the laminated semiconductor package can be reduced, and the yield can be improved.

앞서 설명한 본 발명의 상세한 설명에서는 본 발명의 실시예들을 참조하여 설명하였지만, 해당 기술분야의 숙련된 당업자 또는 해당 기술분야에 통상의 지식을 갖는 자라면 후술 될 특허청구범위에 기재된 본 발명의 사상 및 기술 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.In the detailed description of the present invention described above with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the present invention described in the claims and It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.

RW : 재형상 웨이퍼
300 : 마운팅 테이프
400 : 캐리어 기판
500 : 적층 반도체 칩 모듈RW: Reshaped wafer
300: mounting tape
400: carrier substrate
500: laminated semiconductor chip module

Claims (13)

웨이퍼에 형성된 본딩 패드를 갖는 복수개의 반도체 칩들을 관통하는 관통 전극을 형성하는 단계;
상기 관통 전극이 형성된 반도체 칩들을 칩 레벨로 개별화하는 단계;
상기 반도체 칩들 중 불량 반도체 칩을 제거하고 상기 불량 반도체 칩이 제거된 부분에 관통 전극이 형성된 양품 반도체 칩을 부착하여 재형상 웨이퍼를 형성하는 단계;
상기 관통 전극이 상호 연결되도록 상기 재형상 웨이퍼들을 적층하는 단계;및
상기 적층된 재형상 웨이퍼들을 칩 레벨로 절단하여 적층 반도체 칩 모듈들을 형성하는 단계;
를 포함하는 것을 특징으로 하는 적층 반도체 패키지 형성방법.Forming a through electrode penetrating the plurality of semiconductor chips having a bonding pad formed on the wafer;
Individualizing the semiconductor chips having the through electrodes formed at a chip level;
Removing a defective semiconductor chip among the semiconductor chips and attaching a good semiconductor chip having a through electrode formed to a portion where the defective semiconductor chip is removed to form a reshaped wafer;
Stacking the reshaped wafers such that the through electrodes are interconnected; and
Cutting the stacked reshaped wafers to a chip level to form stacked semiconductor chip modules;
Laminated semiconductor package forming method comprising a. 제 1항에 있어서,
상기 관통 전극을 형성하는 단계는,
상기 본딩 패드가 위치하는 상기 웨이퍼의 전면으로부터 상기 반도체 칩을 식각하여 블라인드 비아홀을 형성하는 단계;
상기 블라인드 비아홀에 금속 물질을 충진하여 상기 관통 전극을 형성하는 단계;및
상기 전면과 대향하는 후면으로 상기 관통 전극이 노출되도록 상기 후면을 연마하는 단계;
를 포함하는 것을 특징으로 하는 적층 반도체 패키지 형성방법.The method of claim 1,
Forming the through electrode,
Etching the semiconductor chip from a front surface of the wafer where the bonding pad is located to form a blind via hole;
Filling the blind via hole with a metal material to form the through electrode; and
Polishing the rear surface such that the through electrode is exposed to the rear surface opposite to the front surface;
Laminated semiconductor package forming method comprising a. 제 2항에 있어서,
상기 후면을 연마하는 단계 전에, 상기 전면에 휨 방지 기판을 부착하는 단계를 더 포함하는 것을 특징으로 하는 적층 반도체 패키지 형성방법.The method of claim 2,
And attaching a warpage preventing substrate to the front surface before the polishing of the back surface. 제 3항에 있어서,
상기 휨 방지 기판은 상기 반도체 칩들을 칩 레벨로 개별화하기 전에 제거하는 것을 특징으로 하는 적층 반도체 패키지 형성방법.The method of claim 3, wherein
And wherein the warpage preventing substrate is removed prior to individualizing the semiconductor chips to a chip level. 제 1항에 있어서,
상기 반도체 칩들을 칩 레벨로 개별화하는 단계 전에, 상기 본딩 패드가 위치하는 상기 웨이퍼의 전면과 대향하는 후면에 마운팅 테이프를 부착하는 단계를 더 포함하는 것을 특징으로 하는 적층 반도체 패키지 형성방법.The method of claim 1,
And attaching a mounting tape to a rear surface opposite to the front surface of the wafer on which the bonding pad is located, before the individualizing the semiconductor chips at the chip level. 제 1항에 있어서,
상기 재형상 웨이퍼를 적층하는 단계 전에, 상기 반도체 칩들을 개별화하는 단계로 인해 벌어진 상기 반도체 칩들간 간격을 좁히는 단계를 더 포함하는 것을 특징으로 하는 적층 반도체 패키지 형성방법.The method of claim 1,
Before the stacking of the reshaped wafers, further comprising narrowing the gaps between the semiconductor chips caused by individualizing the semiconductor chips. 제 1항에 있어서,
상기 재형상 웨이퍼를 형성하는 단계 후, 상기 재형상 웨이퍼들을 적층하는 단계 전에, 상기 재형상 웨이퍼에 캐리어 기판을 부착하는 단계를 더 포함하는 것을 특징으로 하는 적층 반도체 패키지 형성방법.The method of claim 1,
And attaching a carrier substrate to the reshaped wafer after forming the reshaped wafer and before laminating the reshaped wafers. 제 1항에 있어서,
상기 적층 반도체 칩 모듈들을 형성하는 단계 후에, 상기 적층 반도체 칩 모듈을 기판에 실장하는 단계를 더 포함하는 것을 특징으로 하는 적층 반도체 패키지 형성방법.The method of claim 1,
And after the forming of the laminated semiconductor chip modules, mounting the laminated semiconductor chip module on a substrate. 웨이퍼에 형성된 본딩 패드를 갖는 복수개의 반도체 칩들을 상기 본딩 패드가 위치하는 전면으로부터 식각하여 제 1 블라인드 비아홀을 형성하고 상기 제 1 블라인드 비아홀에 관통 전극을 형성하는 단계;
상기 반도체 칩들 중 불량 반도체 칩 주변의 스크라이브 레인을 상기 전면으로부터 식각하여 제 2 블라인드 비아홀을 형성하는 단계;
상기 관통 전극 및 상기 제 2 블라인드 비아홀이 노출되도록 상기 후면을 연마하여 상기 불량 반도체 칩을 상기 웨이퍼로부터 제거하는 단계;
상기 불량 반도체 칩이 제거된 부분에 관통 전극이 형성된 양품 반도체 칩을 부착하여 재형상 웨이퍼를 형성하는 단계;
상기 관통 전극이 상호 연결되도록 상기 재형상 웨이퍼들을 적층하는 단계;및
상기 적층된 재형상 웨이퍼들을 칩 레벨로 절단하여 적층 반도체 칩 모듈을 형성하는 단계;
를 포함하는 것을 특징으로 하는 적층 반도체 패키지 형성방법.Etching a plurality of semiconductor chips having bonding pads formed on a wafer from a front surface of the bonding pads to form first blind via holes and forming through electrodes in the first blind via holes;
Etching a scribe lane around the defective semiconductor chip among the semiconductor chips from the front surface to form a second blind via hole;
Grinding the back surface to expose the through electrode and the second blind via hole to remove the defective semiconductor chip from the wafer;
Forming a reshaped wafer by attaching a good semiconductor chip having a through electrode formed on a portion where the defective semiconductor chip is removed;
Stacking the reshaped wafers such that the through electrodes are interconnected; and
Cutting the stacked reshaped wafers at a chip level to form a stacked semiconductor chip module;
Laminated semiconductor package forming method comprising a. 제 9항에 있어서,
상기 제 2 블라인드 비아홀은 상기 관통 전극보다 깊은 깊이로 형성하는 것을 특징으로 하는 적층 반도체 패키지 형성방법.The method of claim 9,
And forming the second blind via hole deeper than the through electrode. 제 9항에 있어서,
상기 제 2 블라인드 비아홀을 형성하는 단계는 레이저 드릴링 공정, 드릴링 공정 및 사진 식각 공정 중 적어도 어느 하나를 사용하여 수행되는 것을 특징으로 하는 적층 반도체 패키지 형성방법.The method of claim 9,
The forming of the second blind via hole may be performed using at least one of a laser drilling process, a drilling process, and a photolithography process. 제 9항에 있어서,
상기 재형상 웨이퍼를 적층하는 단계 전에, 상기 재형상 웨이퍼에 캐리어 기판을 부착하는 단계를 더 포함하는 것을 특징으로 하는 적층 반도체 패키지 형성방법.The method of claim 9,
And attaching a carrier substrate to the reshaped wafer prior to stacking the reshaped wafers. 제 9항에 있어서,
상기 적층 반도체 칩 모듈들을 형성하는 단계 후, 상기 적층 반도체 칩 모듈을 기판에 실장하는 단계를 더 포함하는 것을 특징으로 하는 적층 반도체 패키지 형성방법.The method of claim 9,
And after the forming of the stacked semiconductor chip modules, mounting the stacked semiconductor chip module on a substrate.
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US9165897B2 (en) 2012-11-05 2015-10-20 Samsung Electronics Co., Ltd. Semiconductor package having unified semiconductor chips
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US9159659B2 (en) 2012-05-11 2015-10-13 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the semiconductor package
US9165897B2 (en) 2012-11-05 2015-10-20 Samsung Electronics Co., Ltd. Semiconductor package having unified semiconductor chips
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