CN110476153A - The method and electronic equipment of access instruction SRAM - Google Patents

The method and electronic equipment of access instruction SRAM Download PDF

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Publication number
CN110476153A
CN110476153A CN201880000220.0A CN201880000220A CN110476153A CN 110476153 A CN110476153 A CN 110476153A CN 201880000220 A CN201880000220 A CN 201880000220A CN 110476153 A CN110476153 A CN 110476153A
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China
Prior art keywords
address
instruction
controller
sram
electronic device
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CN201880000220.0A
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Chinese (zh)
Inventor
吴双
刘丹
刘育峰
靳文鹤
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Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/72—Masking faults in memories by using spares or by reconfiguring with optimized replacement algorithms
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0638—Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/251—Local memory within processor subsystem

Abstract

The embodiment of the present application provides the method and electronic equipment of a kind of access instruction SRAM, and after exception occurs in the content of some addresses in instruction SRAM, the operation irregularity that ICE prevention instruction SRAM occurs improves the reliability of system.This method is applied to electronic equipment, which includes the first controller, instruction SRAM and ICE；This method comprises: the ICE receives the first address that first controller accesses instruction SRAM；If first address is identical as the second address, which sends the first instruction to first controller, which is address corresponding to address location abnormal in instruction SRAM, which is the right instructions of the address location of the exception；If first address is different from second address, the ICE obtained from instruction SRAM first address it is corresponding second instruction, and to first controller send this second instruction.

Description

Method and electronic equipment for accessing instruction SRAM Technical Field
The present application relates to the field of storage, and more particularly, to a method and electronic device for accessing an instruction SRAM.
Background
A Code Static Random Access Memory (SRAM) in a chip may cause some address contents to be abnormal due to process variations and other reasons, for example, some bits may jump between 0 and 1, and some bits are fixed to 0 or 1, and further, an instruction executed by a micro programmed Control Unit (MCU) may be wrong, which may cause a fatal problem. At the present stage, for a chip with an early-death condition, a common coping method is to recall the early-death chip, but the workload is large, the period is long, and negative effects are brought to a chip design and manufacturing enterprise. Therefore, how to avoid the fatal problem caused by the instruction error executed by the MCU after the contents of some addresses in the instruction SRAM are abnormal is a problem to be solved urgently.
Disclosure of Invention
The application provides a method and electronic equipment for accessing an instruction SRAM (static random access memory), wherein after the contents of some addresses in the instruction SRAM are abnormal, a circuit simulator prevents the instruction SRAM from working abnormally, and the reliability of a system is improved.
In a first aspect, a method for accessing a command SRAM is provided, which is applied to an electronic device, where the electronic device includes a first controller, a command SRAM, and an In Circuit Emulator (ICE);
the method comprises the following steps:
the circuit simulator receives a first address of the first controller for accessing the instruction SRAM;
if the first address is the same as the second address, the circuit simulator sends a first instruction to the first controller, the second address is an address corresponding to an abnormal address unit in the instruction SRAM, and the first instruction is a correct instruction of the abnormal address unit; or
If the first address is different from the second address, the circuit simulator acquires a second instruction corresponding to the first address from the instruction SRAM and sends the second instruction to the first controller.
In the embodiment of the application, the circuit simulator can replace the instruction of the abnormal address unit in the instruction SRAM with the correct instruction of the address unit after the abnormal address unit occurs in the instruction SRAM, so that the electronic equipment can still normally work after the abnormal address unit occurs in the instruction SRAM in the electronic equipment, the reliability of a system is improved, and the loss caused by the recovery of the electronic equipment is avoided.
In some possible implementations, the circuit emulator includes an address comparison module,
after the circuit emulator receives the first address of the instruction SRAM accessed by the first controller, the method further includes:
the address comparison module compares the first address to the second address.
In some possible implementations, the method further includes:
the first controller executes instructions retrieved from the circuit simulator.
In some possible implementations, the first controller is an MCU.
In some possible implementations, the electronic device further includes a second controller,
before the circuit emulator receives the first address of the instruction SRAM to which the first controller accesses, the method further includes:
the second controller checks all address units in the instruction SRAM;
when the address unit exists in the instruction SRAM, the second controller records the second address corresponding to the address unit;
the second controller determines the first instruction according to the second address;
the second controller sends the second address and the first instruction to the circuit emulator.
In some possible implementations, the instruction SRAM includes a memory built-in self-test module,
the second controller checks all address locations in the instruction SRAM, including:
the second controller controls to start the memory built-in self-test module;
the memory built-in self-test module checks all address cells in the instruction SRAM.
In some possible implementations, the determining, by the second controller, the first instruction according to the second address includes:
and the second controller inquires the first instruction in standard firmware according to the second address, wherein correct instructions of all address units in the instruction SRAM are stored in the standard firmware.
In some possible implementations, the circuit emulator includes an address register and an instruction register,
the second controller sending the second address and the first instruction to the circuit emulator, including:
the second controller sending the second address to the address register;
the second controller sends the first instruction to the instruction register.
In some possible implementations, the first controller is an MCU, and the second controller is a Central Processing Unit (CPU).
In a second aspect, an electronic device is provided, the electronic device comprising a first controller, an instruction SRAM, and a circuit emulator;
the circuit emulator is used for receiving a first address of the first controller for accessing the instruction SRAM;
if the first address is the same as the second address, the circuit simulator is further configured to send the first instruction to the first controller, where the second address is an address corresponding to an abnormal address unit in the instruction SRAM, and the first instruction is a correct instruction of the abnormal address unit; or
If the first address is different from the second address, the circuit simulator is further configured to obtain a second instruction corresponding to the first address from the instruction SRAM, and send the second instruction to the first controller.
In the embodiment of the application, the circuit simulator can replace the instruction of the abnormal address unit in the instruction SRAM with the correct instruction of the address unit after the abnormal address unit occurs in the instruction SRAM, so that the electronic equipment can still normally work after the abnormal address unit occurs in the instruction SRAM in the electronic equipment, the reliability of a system is improved, and the loss caused by the recovery of the electronic equipment is avoided.
In some possible implementations, the circuit emulator includes an address register and an instruction register,
the address register is used for storing the second address sent by the second controller;
the instruction register is used for storing the first instruction sent by the second controller.
In some possible implementations, the circuit emulator includes an address comparison module and a multiplexer,
after the circuit emulator receives the first address of the instruction SRAM accessed by the first controller, the address comparison module is configured to compare the first address with the second address;
if the first address is the same as the second address, the address comparison module is further configured to control the multiplexer to send the first instruction to the first controller; or
And if the first address is different from the second address, the address comparison module is further configured to control the multiplexer to send the second instruction to the first controller.
In some possible implementations, the first controller is to execute instructions retrieved from the circuit simulator.
In some possible implementations, the first controller is an MCU.
In some possible implementations, the electronic device further includes a second controller,
before the circuit emulator receives the first address of the instruction SRAM accessed by the first controller,
the second controller is used for checking all address units in the instruction SRAM;
when the address unit exists in the instruction SRAM, the second controller is further used for recording the second address corresponding to the address unit;
the second controller is further configured to determine the first instruction from the second address;
the second controller is further configured to send the second address and the first instruction to the circuit emulator.
In some possible implementations, the instruction SRAM includes a memory built-in self-test module,
the second controller is also used for controlling and starting the built-in self-test module of the memory;
the memory built-in self-test module is used for checking all address units in the instruction SRAM.
In some possible implementations, the second controller is specifically configured to:
and querying the first instruction in standard firmware according to the second address, wherein correct instructions of all address units in the instruction SRAM are stored in the standard firmware.
In some possible implementation manners, the first controller is an MCU, and the second controller is a CPU.
In a third aspect, a computer storage medium is provided, in which a program code is stored, and the program code can be used to instruct the execution of the method in the first aspect or any possible implementation manner thereof.
In a fourth aspect, there is provided a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method of the first aspect described above or any possible implementation thereof.
Drawings
FIG. 1 is a schematic flow chart diagram of a method for accessing an instruction SRAM according to one embodiment of the present application.
Fig. 2 is a flow of accessing an instruction SRAM according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application.
It is understood that the SRAM may be classified into a Data (Data) SRAM and a Code (Code) SRAM. The embodiment of the application is mainly applied to the instruction SRAM.
It should be understood that, in the normal use process, if the contents of some addresses of the SRAM are abnormal due to process variations, the SRAM is integrated inside the chip, which may cause the chip to fail early.
It should also be appreciated that ICE, as an important debugging tool for embedded system development, can perform breakpoint debugging. The breakpoint debugging can calculate the instruction address of the breakpoint after setting the program breakpoint, and by comparing the address in the Program Counter (PC) and the address of the breakpoint during the program execution process, when the program is executed to the address of the breakpoint, the CPU can be stopped, and the developer can analyze the state of the system at this time.
In the embodiment of the application, while the address comparison module in the ICE is used for realizing the address comparison, an instruction replacement module (for example, a multiplexer) is added in the ICE for replacing the instruction of the abnormal address unit in the instruction SRAM with the correct instruction of the address unit, so that the electronic equipment can still normally work after the abnormal address unit appears in the instruction SRAM in the electronic equipment, the reliability of the system is improved, and the loss caused by the recall of the electronic equipment is avoided.
Hereinafter, a method for accessing the command SRAM according to an embodiment of the present application will be described in detail with reference to fig. 1 and fig. 2.
FIG. 1 is a schematic flow chart diagram of a method for accessing an instruction SRAM according to one embodiment of the present application. It should be understood that fig. 1 shows steps or operations of the method, but these steps or operations are only examples, and the embodiments of the present application may also perform other operations or variations of the respective operations in fig. 1. The method 100 may be applied to an electronic device comprising a first controller, an instruction SRAM and an ICE.
S110, the ICE receives a first address of the instruction SRAM accessed by the first controller.
The first controller may be an MCU.
The instruction SRAM may be configured to store instructions, and the first controller may read and execute the instructions in the instruction SRAM through the ICE.
It should be understood that the first address may be an address corresponding to any address location in the instruction SRAM.
S120, judging whether a first address and a second address are the same, if the first address and the second address are the same, the ICE sends a first instruction to the first controller, the second address is an address corresponding to an abnormal address unit in the instruction SRAM, and the first instruction is a correct instruction of the abnormal address unit; or
If the first address is different from the second address, the ICE obtains a second instruction corresponding to the first address from the instruction SRAM and sends the second instruction to the first controller.
For example, in an abnormal address unit, some bits will jump between 0 and 1, and some bits are fixed to 0 or 1, so that the read/write modification cannot be performed in a normal manner.
The second address may be stored in the ICE, and upon receiving the first address, the second address is called directly for comparison with the first address.
For example, the second address may be pre-stored in an address register in the ICE.
The first instruction may be stored in the ICE, directly invoked when the first address is the same as the second address, and sent to the first controller.
For example, the first instruction may be pre-stored in an instruction register in the ICE.
For example, there are three abnormal address units a, B and C in the instruction SRAM, where address unit a corresponds to address a, address unit B corresponds to address B, and address unit C corresponds to address C, instruction X is a correct instruction of address unit a, instruction Y is a correct instruction of address unit B, and instruction Z is a correct instruction of address unit C, address a is stored in address register 11, address B is stored in address register 12, address C is stored in address register 13, instruction X is stored in instruction register 21, instruction Y is stored in instruction register 22, and instruction Z is stored in instruction register 23.
Alternatively, the ICE may obtain the second address from the CPU and store it in the address register in advance, and obtain the first instruction from the CPU and store it in the instruction register in advance, and when the MCU reads and executes the instruction in the instruction SRAM through the ICE, the ICE may call the second address directly from the address register and call the first instruction from the instruction register.
Optionally, an address comparison module and a multiplexer are included in the ICE.
The address comparison module is connected with the address register, the first controller and the multiplexer, and the multiplexer is connected with the instruction register, the instruction SRAM and the first controller.
Specifically, the address comparison module is used for comparing the first address with the second address, an
When the first address is the same as the second address, sending first control information to the multiplexer, wherein the first control information is used for controlling the multiplexer to send the first instruction to the first controller; or
And when the first address is different from the second address, sending second control information to the multiplexer, wherein the second control information is used for controlling the multiplexer to acquire a second instruction corresponding to the first address from the instruction SRAM and sending the second instruction to the first controller.
Specifically, the multiplexer sends the first instruction to the first controller after receiving the first control information; or
After receiving the second control information, the multiplexer acquires a second instruction corresponding to the first address from the instruction SRAM and sends the second instruction to the first controller.
Optionally, the first controller executes instructions retrieved from the ICE.
Optionally, as an embodiment, the electronic device may be a chip such as a touch chip, a fingerprint identification chip, a display chip, and the like. For example, the electronic device is a fingerprint identification chip, the fingerprint identification chip includes an MCU, an instruction SRAM, and an ICE, and the MCU reads and executes the instruction in the instruction SRAM through the ICE, so that the electronic device can still operate normally after the instruction SRAM in the electronic device has an abnormal address unit, thereby improving the reliability of the system and avoiding the loss caused by the recall of the electronic device.
Optionally, as an embodiment, the electronic device may also be a device having an MCU, an instruction SRAM, an ICE, and a CPU, for example, a mobile phone or a tablet computer, where the MCU, the instruction SRAM, and the ICE may be integrated in chips such as a touch chip, a fingerprint identification chip, and a display chip in the electronic device, and the MCU reads and executes the instruction in the instruction SRAM through the ICE, so that, after an abnormal address location occurs in the instruction SRAM in the electronic device, the touch chip may still work normally, and reliability of a system of the electronic device is improved.
Specifically, the electronic device further includes a second controller, for example, the second controller is a CPU.
Optionally, before the ICE receives the first address of the instruction SRAM for the first controller to access (S110), the method 100 further includes:
the second controller checks all address units in the command SRAM;
when an abnormal address unit exists in the instruction SRAM, the second controller records the second address corresponding to the abnormal address unit;
the second controller determines a first instruction storing the address unit with the exception according to the second address;
the second controller sends the second address and the first instruction to the ICE.
That is, the second controller determines the second address and the first instruction in advance, and feeds back the second address and the first instruction to the ICE, so that the ICE can directly call the second address and the first instruction when the MCU reads and executes the instructions in the instruction SRAM through the ICE.
Optionally, the second address is stored in an address register in the ICE, and the first instruction is stored in an instruction register in the ICE.
Optionally, the instruction SRAM includes a Memory built-in self-test module (Memory Bist),
the second controller may check all address cells in the command SRAM through the memory built-in self-test module.
Specifically, the second controller controls to start the memory built-in self-test module, and the memory built-in self-test module checks all address units in the command SRAM.
Alternatively, the second controller may determine the first instruction by querying standard firmware.
Specifically, after determining the second address, the second controller may query the standard firmware for the first instruction according to the second address, where the standard firmware stores correct instructions for all address units in the instruction SRAM. Thus, the second controller may feed back the second address, and the first instruction, to the ICE in time, so that when the MCU reads and executes the instructions in the instruction SRAM through the ICE, the ICE may call the second address directly from the address register, and the first instruction directly from the instruction register.
The standard firmware may be firmware stored in a flash memory (flash) of the second controller for updating a touch, fingerprint, etc. chip.
Optionally, the second controller passes through I2The C bus sends the second address and the first instruction to the ICE.
Hereinafter, the flow of the access command SRAM according to the embodiment of the present application will be described in detail with reference to fig. 2.
It should be understood that the example shown in fig. 2 is for the purpose of helping those skilled in the art better understand the embodiments of the present application, and is not intended to limit the scope of the embodiments of the present application. It will be apparent to those skilled in the art from this disclosure that various equivalent modifications or changes may be made in view of fig. 2 given that such modifications or changes also fall within the scope of the embodiments of the present application.
Fig. 2 is a flow of accessing an instruction SRAM according to an embodiment of the present application.
S201, stopping the MCU.
Specifically, the CPU controls to stop the MCU.
S202, starting the built-in self-test module of the memory.
And the CPU controls and starts the built-in self-test module of the memory.
S203, detecting whether the result is abnormal.
When the detection result of the built-in self-test module of the memory is normal, step S209 is executed.
When the detection result of the built-in self-test module of the memory is abnormal, step S204 is executed.
S204, testing the address unit in the abnormal area.
For example, write 0x55/0xAA into the exception region and read back the check.
It should be appreciated that 0x55/0xAA is two hexadecimal numbers commonly used in memory testing to quickly test out abnormal address locations in memory.
The memory built-in self test module writes 0x55/0xAA into the exception region and reads back the check.
S205, whether an abnormal address unit exists or not.
For example, when 0x55/0xAA is written and the address location where no exception exists is read back checked, step S209 is performed.
For another example, when 0x55/0xAA is written and the address location where the abnormality is checked is read back, step S206 is executed.
S206, recording a second address, wherein the second address is an address corresponding to the abnormal address unit.
The CPU records the second address.
S207, a first instruction is inquired in the standard firmware, and the first instruction is a correct instruction of the abnormal address unit.
And the CPU inquires the first instruction in standard firmware according to the second address, and the standard firmware stores correct instructions of all address units in the instruction SRAM.
S208, passing the second address and the first instruction through I2C is sent to the ICE.
The CPU makes the second address and the first instruction pass through I2The C bus is sent to the ICE.
Optionally, the second address is stored in an address register and the first instruction is stored in an instruction register.
S209, starting the MCU.
The MCU accesses the first address of the instruction SRAM through the ICE.
If the first address is the same as the second address, the ICE sends the first instruction to the MCU; or
If the first address is different from the second address, the ICE obtains a second instruction corresponding to the first address from the instruction SRAM and sends the second instruction to the first controller.
The MCU executes the instructions retrieved from the ICE.
In the embodiment of the application, the ICE can replace the instruction of the abnormal address unit in the instruction SRAM with the correct instruction of the address unit after the abnormal address unit occurs in the instruction SRAM, so that the electronic device can still work normally after the abnormal address unit occurs in the instruction SRAM in the electronic device, the reliability of the system is improved, and the loss caused by the recovery of the electronic device is avoided.
Fig. 3 is a schematic block diagram of an electronic device 300 according to an embodiment of the present application. Optionally, as an embodiment, the electronic device 300 may be a chip such as a touch chip, a fingerprint identification chip, a display chip, and the like, and as shown in fig. 3, the electronic device 300 includes: MCU 310, command SRAM 320 and ICE 330, the electronic device 300 being controlled by CPU 340. Optionally, as an embodiment, the electronic device 300 may also be a device having an MCU, an instruction SRAM, an ICE, and a CPU, as shown in fig. 3, where the electronic device 300 includes: MCU 310, instruction SRAM 320, ICE 330, and CPU 340.
Specifically, ICE 330 includes an address comparison module 331, a multiplexer 332, an address register 333, and an instruction register 334;
the address register 333 stores a second address, which is an address corresponding to an abnormal address unit in the instruction SRAM 320;
the instruction register 334 stores the first instruction, which is the correct instruction of the exception address unit.
Specifically, the address comparison module 331 receives a first address of the MCU 310 access instruction SRAM 320;
the address comparison module 331 compares the first address with the second address;
if the first address is the same as the second address, the address comparison module 331 sends control information 1 to the multiplexer 332, so that the multiplexer 332 sends the first instruction to the MCU 310; or
If the first address is different from the second address, the address comparison module 331 sends control information 0 to the multiplexer 332, so that the multiplexer 332 obtains the second instruction corresponding to the first address from the instruction SRAM 320 and sends the second instruction to the MCU 310.
Optionally, the MCU 310 executes instructions retrieved from the ICE 330.
Optionally, before the address comparison module 331 receives the first address instructing the SRAM 320 to be accessed by the MCU 310,
CPU340 examines all address locations in the instruction SRAM 320;
when an abnormal address unit exists in the instruction SRAM 320, the CPU340 records the second address corresponding to the abnormal address unit;
the CPU340 determines the first instruction from the second address;
CPU340 sends the second address and the first instruction to the ICE 330.
Optionally, the second address is stored in an address register 333 and the first instruction is stored in an instruction register 334.
Specifically, the instruction SRAM 320 includes a memory built-in self-test module 321,
the CPU340 controls to start the memory built-in self-test module 321;
the memory built-in self test module 321 examines all address cells in the command SRAM 320.
Specifically, the CPU340 queries the first instruction in standard firmware according to the second address, where the standard firmware stores correct instructions for all address units in the instruction SRAM.
The standard firmware is firmware stored in a flash memory (flash) of the CPU340 for updating a chip such as a touch, a fingerprint, etc.
It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the unit is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (18)

  1. The method for accessing the instruction SRAM is applied to an electronic device, and the electronic device comprises a first controller, the SRAM and a circuit simulator;
    the method comprises the following steps:
    receiving, by the circuit emulator, a first address of the first controller for accessing the instruction SRAM;
    if the first address is the same as the second address, the circuit simulator sends a first instruction to the first controller, the second address is an address corresponding to an abnormal address unit in the instruction SRAM, and the first instruction is a correct instruction of the abnormal address unit; or
    And if the first address is different from the second address, the circuit simulator acquires a second instruction corresponding to the first address from the instruction SRAM and sends the second instruction to the first controller.
  2. The method of claim 1, wherein the circuit emulator includes an address comparison module,
    after the circuit emulator receives the first address of the instruction SRAM accessed by the first controller, the method further includes:
    the address comparison module compares the first address to the second address.
  3. The method according to claim 1 or 2, characterized in that the method further comprises:
    the first controller executes instructions retrieved from the circuit simulator.
  4. The method according to any one of claims 1 to 3, wherein the first controller is a micro-programmed controller (MCU).
  5. The method of any of claims 1-4, wherein the electronic device further comprises a second controller,
    before the circuit emulator receives the first address of the instruction SRAM to which the first controller accesses, the method further includes:
    the second controller checks all address units in the instruction SRAM;
    when the address unit exists in the instruction SRAM, the second controller records the second address corresponding to the address unit;
    the second controller determines the first instruction according to the second address;
    the second controller sends the second address and the first instruction to the circuit emulator.
  6. The method of claim 5, wherein the instruction SRAM comprises a memory built-in self-test module,
    the second controller checks all address locations in the instruction SRAM, including:
    the second controller controls to start the memory built-in self-test module;
    the memory built-in self-test module checks all address cells in the instruction SRAM.
  7. The method of claim 5 or 6, wherein the second controller determines the first instruction from the second address, comprising:
    and the second controller inquires the first instruction in standard firmware according to the second address, wherein correct instructions of all address units in the instruction SRAM are stored in the standard firmware.
  8. The method of any of claims 5 to 7, wherein the circuit emulator comprises an address register and an instruction register,
    the second controller sending the second address and the first instruction to the circuit emulator, including:
    the second controller sending the second address to the address register;
    the second controller sends the first instruction to the instruction register.
  9. The method according to any one of claims 5 to 8, wherein the first controller is an MCU and the second controller is a CPU.
  10. An electronic device, comprising a first controller, an instruction SRAM, and a circuit emulator;
    the circuit emulator is used for receiving a first address of the first controller for accessing the instruction SRAM;
    if the first address is the same as the second address, the circuit simulator is further configured to send the first instruction to the first controller, where the second address is an address corresponding to an abnormal address unit in the instruction SRAM, and the first instruction is a correct instruction of the abnormal address unit; or
    If the first address is different from the second address, the circuit simulator is further configured to obtain a second instruction corresponding to the first address from the instruction SRAM, and send the second instruction to the first controller.
  11. The electronic device of claim 10, wherein the circuit emulator includes an address comparison module and a multiplexer,
    after the circuit emulator receives the first address of the instruction SRAM accessed by the first controller, the address comparison module is configured to compare the first address with the second address;
    if the first address is the same as the second address, the address comparison module is further configured to control the multiplexer to send the first instruction to the first controller; or
    And if the first address is different from the second address, the address comparison module is further configured to control the multiplexer to send the second instruction to the first controller.
  12. The electronic device of claim 10 or 11, wherein the first controller is configured to execute instructions obtained from the circuit simulator.
  13. The electronic device of any of claims 10-12, wherein the first controller is an MCU.
  14. The electronic device of any of claims 10-13, further comprising a second controller,
    before the circuit emulator receives the first address of the instruction SRAM accessed by the first controller,
    the second controller is used for checking all address units in the instruction SRAM;
    when the address unit exists in the instruction SRAM, the second controller is further used for recording the second address corresponding to the address unit;
    the second controller is further configured to determine the first instruction from the second address;
    the second controller is further configured to send the second address and the first instruction to the circuit emulator.
  15. The electronic device of claim 14, wherein the instruction SRAM comprises a memory built-in self-test module,
    the second controller is also used for controlling and starting the built-in self-test module of the memory;
    the memory built-in self-test module is used for checking all address units in the instruction SRAM.
  16. The electronic device according to claim 14 or 15, wherein the second controller is specifically configured to:
    and querying the first instruction in standard firmware according to the second address, wherein correct instructions of all address units in the instruction SRAM are stored in the standard firmware.
  17. The electronic device of any of claims 14-16, wherein the circuit emulator comprises an address register and an instruction register,
    the address register is used for storing the second address sent by the second controller;
    the instruction register is used for storing the first instruction sent by the second controller.
  18. The electronic device of any of claims 14-17, wherein the first controller is an MCU and the second controller is a CPU.
CN201880000220.0A 2018-03-09 2018-03-09 The method and electronic equipment of access instruction SRAM Pending CN110476153A (en)

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EP3557422A1 (en) 2019-10-23

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