CN111221701A - Chip and circuit logic reconfiguration system thereof - Google Patents
Chip and circuit logic reconfiguration system thereof Download PDFInfo
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- CN111221701A CN111221701A CN201911122480.8A CN201911122480A CN111221701A CN 111221701 A CN111221701 A CN 111221701A CN 201911122480 A CN201911122480 A CN 201911122480A CN 111221701 A CN111221701 A CN 111221701A
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- 230000002159 abnormal effect Effects 0.000 claims abstract description 46
- 230000008439 repair process Effects 0.000 claims abstract description 18
- 238000012545 processing Methods 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 9
- 238000012544 monitoring process Methods 0.000 claims description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0793—Remedial or corrective actions
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3065—Monitoring arrangements determined by the means or processing involved in reporting the monitored data
- G06F11/3072—Monitoring arrangements determined by the means or processing involved in reporting the monitored data where the reporting involves data filtering, e.g. pattern matching, time or event triggered, adaptive or policy-based reporting
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Abstract
The invention discloses a circuit logic reconfiguration system, wherein a processor can continuously monitor the abnormal state of a circuit and controls a core control module of a chip to execute corresponding circuit repair logic by rewriting the numerical value of a read-write register when the abnormal state is monitored, so that the speed of finding and solving problems is improved, the abnormal state which appears instantly can not be omitted, a worker does not need to operate through a debugging terminal, and the labor cost is saved. The invention also discloses a chip which has the same beneficial effects as the circuit logic reconfiguration system.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a circuit logic reconfiguration system and a chip.
Background
With the development of electronic technology, various chips are also developed, the chips include a plurality of circuits, a read-only register, a read-write register, a core processing module and a bus interface, the read-only register can acquire and store the circuit state of each circuit in the chip, and the core processing module can change the circuit logic to be executed by the core processing module according to the value in the read-write register so as to realize different functions; the worker can connect the debugging terminal to the bus interface and write the preset register value into the read-write register through the bus interface, so that the core processing module can change the circuit logic executed by the core processing module according to the preset register value, for example, when the worker finds that the circuit state in the read-only register is abnormal, the preset register value can be written into the read-write register through the debugging interface, so that the core processing module can execute the circuit logic for repairing the circuit abnormal state, and the like.
However, the numerical value in the read-only register is read through the debugging terminal, and circuit abnormity judgment cannot be carried out all the time, so that the efficiency is low, a worker is likely to find the abnormal state of the circuit for a long time through the debugging terminal, or cannot find the abnormal state of the circuit in the chip for timely repairing because only the register value used for representing the circuit abnormity exists in the read-only register for a short time through the debugging terminal, the chip is likely to be damaged, and the labor cost is high.
Therefore, how to provide a solution to the above technical problem is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a circuit logic reconfiguration system, which improves the speed of finding and solving problems, does not omit instant abnormal states, does not need workers to operate through a debugging terminal, and saves labor cost; another object of the present invention is to provide a chip including the above circuit logic reconfiguration system, which improves the speed of problem discovery and problem solution, does not omit the abnormal state occurring instantaneously, and does not require a worker to perform an operation through a debugging terminal, thereby saving labor cost.
To solve the above technical problem, the present invention provides a circuit logic reconfiguration system, including:
reading and writing a register;
the read-only register is used for acquiring and storing the circuit state of the circuit in the chip;
the processor is used for monitoring and judging that the circuit state is an abnormal state and writing a preset register value into the read-write register;
and the core processing module is used for executing the circuit repair logic corresponding to the preset register value in the chip according to the corresponding relation between the preset register value and the circuit logic.
Preferably, the read-only registers are multiple;
the step of writing the preset register value into the read-write register when the circuit state is judged to be the abnormal state specifically comprises the following steps:
and writing a preset register value corresponding to the preset abnormal logic into a read-write register when the combination of the storage numerical values in the read-only registers is judged to accord with the preset abnormal logic.
Preferably, the number of the read-write registers is multiple;
when the combination of the stored values in the read-only registers is judged to accord with the preset abnormal logic, the step of writing the preset register value corresponding to the preset abnormal logic into the read-write register specifically comprises the following steps:
when the combination of the storage numerical values in the read-only registers is judged to accord with preset abnormal logic, a preset register value rewriting scheme corresponding to the preset abnormal logic is determined;
rewriting the stored numerical values in the plurality of read-write registers according to the preset register value rewriting scheme;
the core processing module is specifically configured to:
and when the stored numerical values of the plurality of read-write registers are judged to present the combination of the preset register values in the preset register value rewriting scheme, executing circuit repair logic corresponding to the combination of the preset register values in the chip.
Preferably, the preset exception logic includes:
and the size relation stored by the two specified read-only registers does not accord with the preset normal size relation.
Preferably, the circuit repair logic comprises:
a fault repair procedure for a specified circuit within the chip.
Preferably, the read-only register and/or the read-write register are/is an original part of the chip.
Preferably, the processor is a single chip microcomputer.
Preferably, the circuit logic reconfiguration system further comprises:
and the data interface is connected with the processor and is used for adding or modifying the corresponding relation between the preset exception logic and the preset register value.
In order to solve the above technical problem, the present invention further provides a chip including the circuit logic reconfiguration system as described in any one of the above.
The invention provides a circuit logic reconfiguration system, in the application, a processor can continuously monitor the abnormal state of a circuit and controls a core control module of a chip to execute corresponding circuit repair logic by rewriting the numerical value of a read-write register when the abnormal state is monitored, so that the speed of finding and solving problems is improved, the abnormal state which appears instantly can not be omitted, a worker does not need to operate through a debugging terminal, and the labor cost is saved.
The invention also provides a chip which has the same beneficial effects as the circuit logic reconfiguration system.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a circuit logic reconfiguration system according to the present invention;
fig. 2 is a schematic structural diagram of another circuit logic reconfiguration system provided by the present invention.
Detailed Description
The core of the invention is to provide a circuit logic reconfiguration system, which improves the speed of finding and solving problems, does not omit instant abnormal states, does not need workers to operate through a debugging terminal, and saves labor cost; the other core of the invention is to provide a chip comprising the circuit logic reconfiguration system, which improves the speed of finding and solving problems, does not omit abnormal states occurring instantaneously, does not need workers to operate through a debugging terminal, and saves labor cost.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a circuit logic reconfiguration system provided in the present invention, including:
reading and writing the register 1;
the read-only register 2 is used for acquiring and storing the circuit state of a circuit in the chip;
the processor 3 is used for monitoring and judging that the circuit state is an abnormal state and writing a preset register value into the read-write register 1;
and the core processing module 4 is used for executing the circuit repair logic corresponding to the preset register value in the chip according to the corresponding relation between the preset register value and the circuit logic.
Specifically, the Chip may be of various types, for example, an SOC (System-on-a-Chip) Chip, and the embodiment of the present invention is not limited herein.
Specifically, the circuit read by the read-only register 2 may be a circuit partially specified in the chip, or may be all circuits in the chip, which needs to be determined according to specific characteristics and requirements of the chip, and the embodiment of the present invention is not limited herein.
The read-write register 1 can be used for a user to write various register values into the read-write register 1 through the read-write register 1, and can be used for the core processing module 4 of the chip to read the register values in the read-write register 1 and execute corresponding circuit logic.
The preset corresponding relationship between the register value and the circuit logic may be set autonomously, and may be of various types, which is not limited herein in the embodiments of the present invention.
It should be noted that although a technician in the prior art can read the value in the read-only register 2 and rewrite the value in the read-write register 1 through the bus interface of the chip, it is obviously impossible to observe the value in the read-only register 2 and rewrite the value in the read-write register 1 adaptively, and therefore, it is likely to miss or delay the processing of some abnormal circuit states.
The core processing module 4 may be a core processing module 4 of a chip.
The invention provides a circuit logic reconfiguration system, in the application, a microprocessor can continuously monitor the abnormal state of a circuit and controls a core control module of a chip to execute corresponding circuit repair logic by rewriting the numerical value of a read-write register when the abnormal state is monitored, so that the speed of finding and solving problems is improved, the abnormal state which appears instantly can not be omitted, and a worker does not need to operate through a debugging terminal, so that the labor cost is saved.
For better explaining the embodiment of the present invention, please refer to fig. 2, fig. 2 is a schematic structural diagram of another circuit logic reconfiguration system provided by the present invention, and on the basis of the above embodiment:
as a preferred embodiment, the read-only register 2 is plural;
when the circuit state is judged to be an abnormal state, the step of writing the preset register value into the read-write register 1 specifically comprises the following steps:
when the combination of the storage numerical values in the read-only registers 2 is judged to accord with the preset abnormal logic, the preset register value corresponding to the preset abnormal logic is written into the read-write register 1.
Specifically, the number of the read only registers 2 in the chip may be multiple, so as to store the state of a large number of circuits in the chip, and the number of the circuits corresponding to the circuit state stored in each read only register 2 may be set independently.
In some cases, a fault existing in the chip cannot be determined only by the circuit state of a single circuit stored in a single register, so that it is necessary to perform comprehensive judgment on a plurality of circuit states, perform fault diagnosis by judging the relationship between the plurality of circuit states, and write a preset register value corresponding to a preset abnormal logic into the read-write register 1 after the fault is diagnosed.
The stored value corresponds to a circuit state, and the preset exception logic may be set autonomously, which is not limited in the embodiments of the present invention.
Specifically, the number of the read-only registers 2 may be a plurality of specific values, and the embodiment of the present invention is not limited herein.
As a preferred embodiment, the read-write register 1 is plural;
when the combination of the stored values in the read-only registers 2 is judged to conform to the preset abnormal logic, the writing of the preset register value corresponding to the preset abnormal logic into the read-write register 1 specifically includes:
when the combination of the storage numerical values in the read-only registers 2 is judged to accord with the preset abnormal logic, a preset register value rewriting scheme corresponding to the preset abnormal logic is determined;
rewriting the stored numerical values in the plurality of read-write registers 1 according to a preset register value rewriting scheme;
the core processing module 4 is specifically configured to:
and when the stored values of the plurality of read-write registers 1 are judged to present the combination of the preset register values in the preset register value rewriting scheme, executing circuit repair logic corresponding to the combination of the preset register values in the chip.
Specifically, considering that when the core processing module 4 determines the circuit logic corresponding to the stored value in the read/write register 1, in some cases, it needs to determine through the combination of register values presented by the stored values in the multiple read/write registers 1, in the embodiment of the present invention, a corresponding preset register value rewriting scheme is generated when the combination of the stored values in the read-only register 2 meets the preset abnormal logic, so that the register values in the multiple read/write registers 1 can be rewritten according to the preset register value rewriting scheme to present the preset register value combination, and when the core processing module 4 reads the preset register combination, the core processing module 4 can execute the circuit repair logic corresponding to the preset register combination.
The specific number of the read/write registers 1 may be set autonomously, which is not limited herein in the embodiments of the present invention.
Specifically, the preset register value combinations may be set autonomously, and each preset register value combination corresponds to a different circuit repair logic, which is not limited herein.
As a preferred embodiment, the preset exception logic includes:
the size relationship stored by the specified two read-only registers 2 does not conform to the preset normal size relationship.
Specifically, the size relationship stored by the two specified read-only registers 2 does not meet the preset normal size relationship, and specifically, the value of the read-only register a 2 is greater than the value of the read-only register B2, and the like.
The preset exception logic provided in the embodiment of the present invention is relatively simple, and certainly, the preset exception logic may also be of other various types, which is not limited herein.
As a preferred embodiment, the circuit repair logic comprises:
a fail-over procedure for a specified circuit within the chip.
Specifically, besides the circuit repair logic that is split in the embodiment of the present invention, the circuit repair logic may also be of other types, and the embodiment of the present invention is not limited herein.
As a preferred embodiment the read only register 2 and/or the read write register 1 are part of the chip itself.
Specifically, the cost can be saved by adopting the original read-only register 2 and/or the read-write register 1 in the chip, and the structure of the chip is not required to be greatly modified.
Of course, in addition to using the original read-only register 2 and/or the read-write register 1 in the chip, the read-only register 2 and/or the read-write register 1 may also be additionally added on the basis of the chip, and the embodiment of the present invention is not limited herein.
As a preferred embodiment, the processor 3 is a single chip.
Specifically, the single chip microcomputer has the advantages of small size, low cost, long service life and the like.
The processor 3 can support a plurality of basic instructions, including arithmetic logic operation, bit operation, jump, data movement, and the like.
Of course, the processor 3 may be of other various types, and the embodiment of the present invention is not limited herein.
As a preferred embodiment, the circuit logic reconfiguration system further includes:
and the data interface 5 is connected with the processor 3 and is used for adding or modifying the corresponding relation between the preset exception logic and the register value.
Specifically, considering that the corresponding relationship between the preset abnormal logic and the register value in the processor 3 may need to be increased or modified along with the change of time or the upgrade of the chip, in the embodiment of the present invention, a worker may add or modify the corresponding relationship between the preset abnormal logic and the register value in the processor 3 through the data interface 5, which is relatively convenient and fast to operate, and improves the working efficiency.
The data interface 5 may be of various types, for example, may be of various types of bus interfaces, and the like, and the embodiment of the present invention is not limited herein.
The invention also provides a chip comprising the circuit logic reconfiguration system in the embodiment.
For the introduction of the chip provided by the embodiment of the present invention, reference is made to the foregoing embodiment of the circuit logic reconfiguration system, and the embodiment of the present invention is not described herein again.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. It should also be noted that, in the present specification, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. A circuit logic reconfiguration system, comprising:
reading and writing a register;
the read-only register is used for acquiring and storing the circuit state of the circuit in the chip;
the processor is used for monitoring and judging that the circuit state is an abnormal state and writing a preset register value into the read-write register;
and the core processing module is used for executing the circuit repair logic corresponding to the preset register value in the chip according to the corresponding relation between the preset register value and the circuit logic.
2. The circuit logic reconfiguration system according to claim 1, wherein said read-only registers are plural;
the step of writing the preset register value into the read-write register when the circuit state is judged to be the abnormal state specifically comprises the following steps:
and writing a preset register value corresponding to the preset abnormal logic into a read-write register when the combination of the storage numerical values in the read-only registers is judged to accord with the preset abnormal logic.
3. The circuit logic reconfiguration system according to claim 2, wherein said read-write register is plural;
when the combination of the stored values in the read-only registers is judged to accord with the preset abnormal logic, the step of writing the preset register value corresponding to the preset abnormal logic into the read-write register specifically comprises the following steps:
when the combination of the storage numerical values in the read-only registers is judged to accord with preset abnormal logic, a preset register value rewriting scheme corresponding to the preset abnormal logic is determined;
rewriting the stored numerical values in the plurality of read-write registers according to the preset register value rewriting scheme;
the core processing module is specifically configured to:
and when the stored numerical values of the plurality of read-write registers are judged to present the combination of the preset register values in the preset register value rewriting scheme, executing circuit repair logic corresponding to the combination of the preset register values in the chip.
4. The circuit logic reconfiguration system according to claim 3, wherein said preset exception logic comprises:
and the size relation stored by the two specified read-only registers does not accord with the preset normal size relation.
5. The circuit logic reconfiguration system according to claim 3, wherein said circuit repair logic comprises:
a fault repair procedure for a specified circuit within the chip.
6. The circuit logic reconfiguration system according to claim 1, wherein said read-only registers and/or said read-write registers are originally part of said chip.
7. The circuit logic reconfiguration system according to claim 1, wherein said processor is a single-chip microcomputer.
8. The circuit logic reconfiguration system according to any one of claims 2 to 5, further comprising:
and the data interface is connected with the processor and is used for adding or modifying the corresponding relation between the preset exception logic and the preset register value.
9. A chip comprising a circuit logic reconfiguration system according to any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911122480.8A CN111221701A (en) | 2019-11-15 | 2019-11-15 | Chip and circuit logic reconfiguration system thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911122480.8A CN111221701A (en) | 2019-11-15 | 2019-11-15 | Chip and circuit logic reconfiguration system thereof |
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| Publication Number | Publication Date |
|---|---|
| CN111221701A true CN111221701A (en) | 2020-06-02 |
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| CN201911122480.8A Withdrawn CN111221701A (en) | 2019-11-15 | 2019-11-15 | Chip and circuit logic reconfiguration system thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117453495A (en) * | 2023-12-26 | 2024-01-26 | 睿思芯科(成都)科技有限公司 | Chip supporting online error correction and debugging, design method and related equipment |
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2019
- 2019-11-15 CN CN201911122480.8A patent/CN111221701A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117453495A (en) * | 2023-12-26 | 2024-01-26 | 睿思芯科(成都)科技有限公司 | Chip supporting online error correction and debugging, design method and related equipment |
| CN117453495B (en) * | 2023-12-26 | 2024-03-26 | 睿思芯科(成都)科技有限公司 | Chip supporting online error correction and debugging, design method and related equipment |
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Application publication date: 20200602 |