CN114121138B - Memory voltage testing method, device, computing equipment and system - Google Patents
Memory voltage testing method, device, computing equipment and system Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application relates to the field of computer equipment, in particular to a memory voltage testing method, a device, a computing device and a system, which are applied to BMC (baseboard management controller), wherein the BMC is connected with the memory device, and the method comprises the following steps: acquiring a voltage adjustment instruction, wherein the voltage adjustment instruction is used for indicating to adjust the output voltage in the memory device; acquiring a current state corresponding to the memory device; and adjusting the output voltage of the memory device according to the current state so as to test the memory device. According to the memory voltage testing method, the BMC acquires the voltage adjusting instruction and adjusts the output voltage of the memory device, so that the operation of adjusting the output voltage of the memory device is reduced, no additional tools are needed, and the efficiency of the memory voltage testing is improved. In addition, the output voltage of the memory device in various states can be adjusted, and the test accuracy of the memory device is improved.
Description
Technical Field
The present application relates to the field of computer devices, and in particular, to a method, an apparatus, a computing device, and a system for testing a memory voltage.
Background
Along with the rapid development of cloud computing and big data technology, the informatization and intellectualization trend of the current society is increasingly accelerated, and the server is used as core equipment of an informatization system, so that the requirements on performance and reliability are higher and higher. In the development process of the server, the server should be tested sufficiently and strictly to ensure the product quality, and the memory is one of important components, which is a part needing important attention in the test process.
The four-corner test of the memory is an important one in the related test of the memory, and comprises four conditions of high temperature and low pressure, high temperature and high pressure, low temperature and low pressure and low temperature and high pressure. After the server is placed in the high-low temperature box, the power supply voltage of the memory needs to be adjusted according to the temperature set value. Taking the currently mainstream DDR4 memory as an example, there are three kinds of supply voltage output buffer supply voltage (Supply Voltage for Output, abbreviated as VDDQ), memory chip activation supply voltage (Supply Voltage for DRAM Activating, abbreviated as VPP), and input/output signal termination supply voltage (Supply Voltage for I/O termination, abbreviated as VTT), where the input/output signal termination supply voltage is 1/2 of the output buffer supply voltage, and no separate adjustment is required.
The voltage adjustment methods available for the current test are: the debugging tool of VR manufacturer is used to connect the debugging interface and PC reserved on the server motherboard, after the debugging software is installed on the PC, the voltage values of the output buffer power supply voltage and the storage chip activation power supply voltage can be modified, and the internal wiring of the chassis is used to adjust the voltage of the memory.
The voltage adjustment method is complex in operation process and requires additional debugging tools and software, so that the voltage adjustment efficiency is low.
Disclosure of Invention
In view of the above, the embodiments of the present application provide a method, an apparatus, a computing device, and a system method for testing a memory voltage, which aim to solve the problems that the operation process of testing the memory voltage is complicated and requires additional debugging tools and software, so that the voltage adjustment efficiency is low.
According to a first aspect, an embodiment of the present application provides a memory voltage testing method, applied to a BMC, where the BMC is connected to a memory device, the method including:
acquiring a voltage adjustment instruction, wherein the voltage adjustment instruction is used for indicating to adjust the output voltage in the memory device;
acquiring a current state corresponding to the memory device;
and adjusting the output voltage of the memory device according to the current state so as to test the memory device.
According to the memory voltage testing method provided by the embodiment of the application, the voltage adjustment instruction is obtained, and the current state corresponding to the memory device is obtained. Therefore, the output voltage of the memory device can be adjusted according to the current state, and the memory device can be tested under various output voltages by adjusting the output voltage of the memory device. According to the memory voltage testing method, a debugging interface reserved on a server mainboard and a PC (personal computer) are not required to be connected by using a debugging tool of a VR manufacturer, debugging software is installed on the PC, and then the voltage value of the output voltage of the memory device is modified. The BMC acquires the voltage adjustment instruction and adjusts the output voltage of the memory device, so that the operation of adjusting the output voltage of the memory device is reduced, no additional tool is needed, and the efficiency of the memory voltage test is improved. In addition, the method can adjust the output voltage of the memory device according to the current state corresponding to the memory device, so that the output voltage of the memory device is matched with the current state corresponding to the memory device, the output voltage of the memory device in various states can be adjusted, and the test accuracy of the memory device is improved.
With reference to the first aspect, in a first implementation manner of the first aspect, according to a current state, adjusting an output voltage of the memory device to test the memory device includes:
switching the control mode of the memory device into a target control mode according to the voltage adjustment instruction;
the output voltage of the memory device is adjusted based on the target control mode.
According to the memory voltage testing method provided by the embodiment of the application, the control mode of the memory device is switched to the target control mode according to the voltage adjustment instruction, and the output voltage of the memory device is adjusted based on the target control mode. Therefore, the accuracy of the output voltage adjustment of the memory device can be improved, and the error of the output voltage adjustment of the memory device caused by the mismatching of the control modes of the memory device is avoided.
With reference to the first aspect, in a second implementation manner of the first aspect, obtaining a current state corresponding to the memory device includes:
acquiring power state information sent by target equipment;
and determining the current state corresponding to the memory device according to the power state information.
According to the memory voltage testing method provided by the embodiment of the application, the current state corresponding to the memory device is determined by acquiring the power state information sent by the target device and according to the power state information. Therefore, the accuracy of the current state corresponding to the acquired memory device can be ensured.
With reference to the second implementation manner of the first aspect, in a third implementation manner of the first aspect, determining, according to the power state information, a current state corresponding to the memory device includes:
if the power supply state information is high-level information, determining that the current state is a normal working state;
if the power state information is low level information, the current state is determined to be the power-on and power-off state.
According to the memory voltage testing method provided by the embodiment of the application, whether the current state is the normal working state or the power-on and power-off state is determined according to the high-level information and the low-level information of the power state information, so that the accuracy of the acquired current state corresponding to the memory device is further ensured.
With reference to the first aspect, in a fourth implementation manner of the first aspect, according to the current state, adjusting an output voltage of the memory device includes:
if the current state is a normal working state, a first control instruction is sent to the memory device; the first control instruction is used for instructing the memory device to adjust the voltage output register; the voltage output register is used for adjusting the active power supply voltage and the output buffer power supply voltage of the memory chip of the memory device under the normal working state.
According to the memory voltage testing method provided by the embodiment of the application, under the condition that the current state corresponding to the memory device is the normal working state, the first control instruction is sent to the memory device, so that the memory device can adjust the voltage output register, and the activation power supply voltage and the output buffer power supply voltage of the memory chip of the memory device are adjusted. The method and the device realize the adjustment of the activation power supply voltage and the output buffer power supply voltage of the memory chip of the memory device in a normal working state, and have complete coverage of voltage adjustment.
With reference to the first aspect, in a fifth implementation manner of the first aspect, adjusting an output voltage of the memory device according to the current state includes:
if the current state is the power-on and power-off state, a second control instruction is sent to the memory device; the second control instruction is used for instructing the memory device to adjust the starting voltage register; the starting voltage register is used for adjusting the activation power supply voltage and the output buffer power supply voltage of the memory chip of the memory device in the power-on and power-off state.
According to the memory voltage testing method provided by the embodiment of the application, under the condition that the current state corresponding to the memory device is the power-on and power-off state, the second control instruction is sent to the memory device, so that the memory device can adjust the starting voltage register, and the activation power supply voltage and the output buffer power supply voltage of the memory chip of the memory device are adjusted. The method and the device realize adjustment of the activation power supply voltage and the output buffer power supply voltage of the memory chip of the memory device in the power-on and power-off state, and have complete coverage of voltage adjustment.
With reference to the first implementation manner of the first aspect, in a sixth implementation manner of the first aspect, after adjusting an output voltage of the memory device according to the current state, the method further includes:
and switching the control mode of the memory device from the target control mode to the normal control mode.
According to the memory voltage testing method provided by the embodiment of the application, after the output voltage of the memory device is regulated according to the current state, the control mode of the memory device is switched from the target control mode to the normal control mode, so that the normal operation of the memory device is not influenced after the voltage regulation of the memory device is finished.
According to a second aspect, an embodiment of the present application further provides a memory voltage testing apparatus, which is applied to a BMC, where the BMC is connected to a memory device to be adjusted, and the apparatus includes:
the first acquisition module is used for acquiring a voltage adjustment instruction, wherein the voltage adjustment instruction is used for indicating to adjust the output voltage in the memory device;
the second acquisition module is used for acquiring the current state corresponding to the memory device;
and the adjusting module is used for adjusting the output voltage of the memory device according to the current state so as to test the memory device.
The memory voltage testing device provided by the embodiment of the application obtains the voltage adjustment instruction and obtains the current state corresponding to the memory device. Therefore, the output voltage of the memory device can be adjusted according to the current state, and the memory device can be tested under various output voltages by adjusting the output voltage of the memory device. According to the memory voltage testing method, a debugging interface reserved on a server mainboard and a PC (personal computer) are not required to be connected by using a debugging tool of a VR manufacturer, debugging software is installed on the PC, and then the voltage value of the output voltage of the memory device is modified. The BMC acquires the voltage adjustment instruction and adjusts the output voltage of the memory device, so that the operation of adjusting the output voltage of the memory device is reduced, no additional tool is needed, and the efficiency of the memory voltage test is improved. In addition, the method can adjust the output voltage of the memory device according to the current state corresponding to the memory device, so that the output voltage of the memory device is matched with the current state corresponding to the memory device, the output voltage of the memory device in various states can be adjusted, and the test accuracy of the memory device is improved.
According to a third aspect, an embodiment of the present application further provides a computing device, which is characterized by including a memory and a processor, where the memory stores computer instructions, and the processor executes the computer instructions, thereby executing the memory voltage testing method in any implementation manner of the first aspect and the first aspect.
According to a fourth aspect, the embodiment of the present application further provides a memory voltage testing system, which includes a BMC and a memory device, the BMC being connected to the memory device,
the BMC acquires a voltage adjustment instruction, wherein the voltage adjustment instruction is used for indicating to adjust the output voltage in the memory device;
the BMC acquires the current state corresponding to the memory device;
and the BMC adjusts the output voltage of the memory device according to the current state so as to test the memory device.
The memory voltage testing system provided by the embodiment of the application obtains the voltage adjustment instruction and obtains the current state corresponding to the memory device. Therefore, the output voltage of the memory device can be adjusted according to the current state, and the memory device can be tested under various output voltages by adjusting the output voltage of the memory device. According to the memory voltage testing method, a debugging interface reserved on a server mainboard and a PC (personal computer) are not required to be connected by using a debugging tool of a VR manufacturer, debugging software is installed on the PC, and then the voltage value of the output voltage of the memory device is modified. The BMC acquires the voltage adjustment instruction and adjusts the output voltage of the memory device, so that the operation of adjusting the output voltage of the memory device is reduced, no additional tool is needed, and the efficiency of the memory voltage test is improved. In addition, the method can adjust the output voltage of the memory device according to the current state corresponding to the memory device, so that the output voltage of the memory device is matched with the current state corresponding to the memory device, the output voltage of the memory device in various states can be adjusted, and the test accuracy of the memory device is improved.
According to a fifth aspect, an embodiment of the present application provides a computer-readable storage medium storing computer instructions for causing a computer to perform the first aspect or any one of the implementation manners of the first aspect of the present application.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a memory voltage testing method according to an embodiment of the present application;
FIG. 2 is a flowchart of a memory voltage testing method according to another embodiment of the present application;
FIG. 3 is a flowchart of a memory voltage testing method according to another embodiment of the present application;
FIG. 4 is a flowchart of a memory voltage testing method according to another embodiment of the present application;
FIG. 5 is a functional block diagram of a memory voltage testing apparatus according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a hardware architecture of a computing device to which embodiments of the present application are applied;
fig. 7 is a schematic structural diagram of a memory voltage testing system according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be noted that, the execution body of the method for testing the memory voltage provided in the embodiment of the present application may be a device for testing the memory voltage, where the device for testing the memory voltage may be implemented as part or all of a computer device in a manner of software, hardware or a combination of software and hardware, where the computer device may be a server or a terminal, where the server in the embodiment of the present application may be a server or a server cluster formed by multiple servers, and the terminal in the embodiment of the present application may be other intelligent hardware devices such as a smart phone, a personal computer, a tablet computer, a wearable device, and an intelligent robot. In the following method embodiments, the execution subject is a computing device as an example.
In one embodiment of the present application, as shown in fig. 1, a memory voltage testing method is provided, and the method is applied to a BMC for illustration, where the BMC is connected to a memory device, and the method includes the following steps:
s11, acquiring a voltage adjustment instruction.
The voltage adjustment instruction is used for indicating to adjust the output voltage in the memory device.
In an alternative embodiment, the BMC may receive a voltage adjustment command input by the user based on the BMC display interface, and may also receive a voltage adjustment command sent by another device.
In another alternative embodiment, the BMC may also obtain the voltage adjustment command based on the detection of the memory device.
S12, obtaining the current state corresponding to the memory device.
Specifically, the BMC may transmit detection information to the other device, the detection information being used to detect whether the other device is operating normally. If the BMC receives response information sent by other equipment based on the detection information, the BMC determines that the current state corresponding to the memory equipment is a normal working state; if the BMC does not receive the response information sent by the other equipment based on the detection information, the BMC determines that the current state corresponding to the memory equipment is the power-on and power-off state. The other devices may be a CPU, or may be devices such as an integrated south bridge or north bridge.
S13, adjusting the output voltage of the memory device according to the current state so as to test the memory device.
In an alternative embodiment, the BMC may determine an adjustment policy corresponding to the current state of the memory device according to the current state of the memory device, and then adjust an output voltage corresponding to the memory device according to the adjustment policy, so as to test the memory device. The adjustment policy may be to directly adjust the value of the output voltage of the memory device, for example, adjust the active power supply voltage of the memory chip to 5V, adjust the output buffer power supply voltage to 6V,
according to the memory voltage testing method provided by the embodiment of the application, the voltage adjustment instruction is obtained, and the current state corresponding to the memory device is obtained. Therefore, the output voltage of the memory device can be adjusted according to the current state, and the memory device can be tested under various output voltages by adjusting the output voltage of the memory device. According to the memory voltage testing method, a debugging interface reserved on a server mainboard and a PC (personal computer) are not required to be connected by using a debugging tool of a VR manufacturer, debugging software is installed on the PC, and then the voltage value of the output voltage of the memory device is modified. The BMC acquires the voltage adjustment instruction and adjusts the output voltage of the memory device, so that the operation of adjusting the output voltage of the memory device is reduced, no additional tool is needed, and the efficiency of the memory voltage test is improved. In addition, the method can adjust the output voltage of the memory device according to the current state corresponding to the memory device, so that the output voltage of the memory device is matched with the current state corresponding to the memory device, the output voltage of the memory device in various states can be adjusted, and the test accuracy of the memory device is improved.
In an alternative embodiment of the present application, as shown in fig. 2, after the step S11 of "obtaining the voltage adjustment command", the method may further include the steps of:
s21, switching the control mode of the memory device into a target control mode according to the voltage adjustment instruction.
Specifically, in general, the output voltage of the memory device supports multiple control manners, and exemplary multiple control manners may include a SVID bus, a PMBus, an I2C bus, and other control manners.
After the BMC acquires the voltage adjustment instruction, a target control mode corresponding to the memory device can be determined according to the voltage adjustment instruction, and then the control mode of the memory device is switched to the target control mode.
For example, assuming that the control mode corresponding to the current output voltage of the memory device is a PMBus control mode, after the BMC obtains the voltage adjustment instruction, it determines that the target control mode corresponding to the memory device is I2C bus control, so the BMC switches the control mode of the memory device from the PMBus control to the I2C bus control.
S22, adjusting the output voltage of the memory device based on the target control mode.
Specifically, after the control mode of the memory device is switched to the target control mode, the BMC may adjust the output voltage of the memory device based on the switched target control mode.
According to the memory voltage testing method provided by the embodiment of the application, the control mode of the memory device is switched to the target control mode according to the voltage adjustment instruction, and the output voltage of the memory device is adjusted based on the target control mode. Therefore, the accuracy of the output voltage adjustment of the memory device can be improved, and the error of the output voltage adjustment of the memory device caused by the mismatching of the control modes of the memory device is avoided.
In an alternative embodiment of the present application, as shown in fig. 3, the memory voltage testing method provided in the embodiment of the present application may include the following steps:
s31, acquiring a voltage adjustment instruction.
The voltage adjustment instruction is used for indicating to adjust the output voltage in the memory device.
Referring to fig. 1, the above description of S11 is detailed.
S32, obtaining the current state corresponding to the memory device.
The step S32 may include the following steps:
s321, acquiring power state information sent by the target equipment.
Specifically, the BMC may receive power state information sent by the target device based on communication with the target device, where the target device may be a CPU, or may be a device such as an integrated south bridge or north bridge. The power state information may characterize the current operating state of the target device.
S322, determining the current state corresponding to the memory device according to the power state information.
In an alternative embodiment, if the power state information is high level information, the current state is determined to be a normal operation state.
In another alternative embodiment, if the power state information is low level information, then the current state is determined to be the power on/off state.
Specifically, after receiving the power state information sent by the target device, the BMC may identify and study the power state information, and if the power state information is high level information, it indicates that there is a power passing in the target device, and the target device is in normal operation, and the BMC determines that the current state is a normal operation state. If the power state information is low level information, the target device is indicated that the power passes through, but the target device does not work normally, and the BMC determines that the current state is the power-on and power-off state.
According to the memory voltage testing method provided by the embodiment of the application, whether the current state is the normal working state or the power-on and power-off state is determined according to the high-level information and the low-level information of the power state information, so that the accuracy of the acquired current state corresponding to the memory device is further ensured.
S33, adjusting the output voltage of the memory device according to the current state so as to test the memory device.
The above S33 may include the following cases:
in one case, if the current state is a normal working state, a first control instruction is sent to the memory device; the first control instruction is used for instructing the memory device to adjust the voltage output register; the voltage output register is used for adjusting the active power supply voltage and the output buffer power supply voltage of the memory chip of the memory device under the normal working state.
In another case, if the current state is the power-on and power-off state, a second control instruction is sent to the memory device; the second control instruction is used for instructing the memory device to adjust the starting voltage register; the starting voltage register is used for adjusting the activation power supply voltage and the output buffer power supply voltage of the memory chip of the memory device in the power-on and power-off state.
Specifically, after determining the current state corresponding to the memory device, the BMC may determine a control instruction to be sent to the memory device according to the current state of the memory device.
In one case, if the current state is a normal working state, the BMC sends a first control instruction to the memory device. After the memory device receives a first control instruction sent by the BMC, the voltage output register is adjusted according to the first control instruction, so that the activation supply voltage and the output buffer supply voltage of a storage chip of the memory device are adjusted.
In another case, if the current state is the power-on/off state, the BMC sends a second control instruction to the memory device. After the memory device receives a second control instruction sent by the BMC, the starting voltage register is adjusted according to the second control instruction, so that the activation supply voltage and the output buffer supply voltage of the memory chip of the memory device are adjusted.
According to the memory voltage testing method provided by the embodiment of the application, under the condition that the current state corresponding to the memory device is the normal working state, the first control instruction is sent to the memory device, so that the memory device can adjust the voltage output register, and the activation supply voltage and the output buffer supply voltage of the memory device storage chip are adjusted. The method and the device realize the adjustment of the activation power supply voltage and the output buffer power supply voltage of the memory chip of the memory device in the normal working state. And under the condition that the current state corresponding to the memory device is the power-on and power-off state, sending a second control instruction to the memory device, so that the memory device can adjust the starting voltage register, and further adjust the activation supply voltage and the output buffer supply voltage of the memory device storage chip. The method and the device realize adjustment of the activation power supply voltage and the output buffer power supply voltage of the memory chip of the memory device in the power-on and power-off state, and have complete coverage of voltage adjustment.
In an alternative embodiment of the present application, as shown in fig. 4, the memory voltage testing method provided in the embodiment of the present application may include the following steps:
s41, acquiring a voltage adjustment instruction.
Please refer to fig. 3, for a detailed description of S31.
S42, switching the control mode of the memory device to a target control mode according to the voltage adjustment instruction.
Referring to fig. 2, the above description of S21 is detailed.
S43, obtaining the current state corresponding to the memory device.
Referring to fig. 3, the above description of S32 is detailed.
S44, adjusting the output voltage of the memory device based on the target control mode according to the current state so as to test the memory device.
Please refer to fig. 3, for a detailed description of S33.
S45, switching the control mode of the memory device from the target control mode to the normal control mode.
Specifically, after the output voltage adjustment of the memory device is completed, the BMC switches the control mode of the memory device from the target control mode to the normal control mode.
According to the memory voltage testing method provided by the embodiment of the application, after the output voltage of the memory device is regulated according to the current state, the control mode of the memory device is switched from the target control mode to the normal control mode, so that the normal operation of the memory device is not influenced after the voltage regulation of the memory device is finished.
As shown in fig. 5, the present embodiment provides a memory voltage testing apparatus applied to a BMC, where the BMC is connected to a memory device to be adjusted, the apparatus includes:
a first obtaining module 51, configured to obtain a voltage adjustment instruction, where the voltage adjustment instruction is used to instruct to adjust an output voltage in the memory device;
a second obtaining module 52, configured to obtain a current state corresponding to the memory device;
the adjusting module 53 is configured to adjust an output voltage of the memory device according to the current state, so as to test the memory device.
In one embodiment of the present application, the adjustment module 53 is specifically configured to switch the control mode of the memory device to the target control mode according to the voltage adjustment instruction; the output voltage of the memory device is adjusted based on the target control mode.
In one embodiment of the present application, the second obtaining module 52 is specifically configured to obtain power status information sent by the target device; and determining the current state corresponding to the memory device according to the power state information.
In one embodiment of the present application, the second obtaining module 52 is specifically configured to determine that the current state is a normal working state if the power status information is high level information; if the power state information is low level information, the current state is determined to be the power-on and power-off state.
In one embodiment of the present application, the adjusting module 53 is specifically configured to send a first control instruction to the memory device if the current state is a normal working state; the first control instruction is used for instructing the memory device to adjust the voltage output register; the voltage output register is used for adjusting the active power supply voltage and the output buffer power supply voltage of the memory chip of the memory device under the normal working state.
In one embodiment of the present application, the adjusting module 53 is specifically configured to send a second control instruction to the memory device if the current state is an power-on/power-off state; the second control instruction is used for instructing the memory device to adjust the starting voltage register; the starting voltage register is used for adjusting the activation power supply voltage and the output buffer power supply voltage of the memory chip of the memory device in the power-on and power-off state.
In an embodiment of the present application, the adjustment module 53 is further configured to switch the control mode of the memory device from the target control mode to the normal control mode.
For specific limitations of the memory voltage testing apparatus, reference may be made to the above limitations of the memory voltage testing method, and detailed descriptions thereof are omitted herein. The modules in the memory voltage testing apparatus may be implemented in whole or in part by software, hardware, or a combination thereof. The above modules may be embedded in hardware or independent of a processor in the electronic device, or may be stored in software in a memory in the electronic device, so that the processor may call and execute operations corresponding to the above modules.
The embodiment of the application also provides a computing device which is provided with the memory voltage testing device shown in the figure 5.
FIG. 6 is a schematic diagram of a computing device according to an alternative embodiment of the present application, as shown in FIG. 6, where the computing device may include: at least one processor 61, such as a CPU (Central Processing Unit ), at least one communication interface 63, a memory 64, at least one communication bus 62. Wherein the communication bus 62 is used to enable connected communication between these components. The communication interface 63 may include a Display screen (Display) and a Keyboard (Keyboard), and the optional communication interface 63 may further include a standard wired interface and a wireless interface. The memory 64 may be a high-speed RAM memory (Random Access Memory, volatile random access memory) or a non-volatile memory (non-volatile memory), such as at least one disk memory. The memory 64 may also optionally be at least one storage device located remotely from the aforementioned processor 61. Where the processor 61 may be an apparatus as described in connection with fig. 6 or fig. 6, the memory 64 stores an application program, and the processor 61 invokes the program code stored in the memory 64 for performing any of the method steps described above.
The communication bus 62 may be a peripheral component interconnect standard (peripheral component interconnect, PCI) bus or an extended industry standard architecture (extended industry standard architecture, EISA) bus, among others. The communication bus 62 may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one thick line is shown in fig. 6, but not only one bus or one type of bus.
Wherein the memory 64 may include volatile memory (English) such as random-access memory (RAM); the memory may also include a nonvolatile memory (english: non-volatile memory), such as a flash memory (english: flash memory), a hard disk (english: hard disk drive, abbreviated as HDD) or a solid state disk (english: solid-state drive, abbreviated as SSD); memory 64 may also include a combination of the types of memory described above.
The processor 61 may be a central processor (English: central processing unit, abbreviated: CPU), a network processor (English: network processor, abbreviated: NP) or a combination of CPU and NP.
The processor 61 may further include a hardware chip, among others. The hardware chip may be an application-specific integrated circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof (English: programmable logic device). The PLD may be a complex programmable logic device (English: complex programmable logic device, abbreviated: CPLD), a field programmable gate array (English: field-programmable gate array, abbreviated: FPGA), a general-purpose array logic (English: generic array logic, abbreviated: GAL), or any combination thereof.
Optionally, the memory 64 is also used to store program instructions. Processor 61 may invoke program instructions to implement the memory voltage testing method as shown in the embodiments of fig. 1-3 of the present application.
Fig. 7 is a schematic diagram of a memory voltage testing system according to an alternative embodiment of the application. As shown in fig. 7, in the motherboard, the BMC and the memory device are connected based on an I2C bus. A debug interface for connecting a debug tool is reserved in the main board, and the debug interface is connected with the memory device based on the I2C bus. Further, the CPU is connected to the memory device based on the SVID bus. The memory device includes two voltage modes, i.e., a LOOPA and a LOOPB, in which the LOOPA outputs a VDDQ voltage and the LOOPB outputs a VPP voltage, and the output voltage of each power supply is controlled by two registers, i.e., a start voltage register and an output voltage register, and the VPP voltage is also controlled by two registers, i.e., a start voltage register and an output voltage register.
The embodiment of the application also provides a non-transitory computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions can execute the memory voltage testing method in any of the method embodiments. The storage medium may be a magnetic Disk, an optical Disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a Flash Memory (Flash Memory), a Hard Disk (HDD), or a Solid State Drive (SSD); the storage medium may also comprise a combination of memories of the kind described above.
Although embodiments of the present application have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the application, and such modifications and variations fall within the scope of the application as defined by the appended claims.
Claims (8)
1. A memory voltage testing method, which is applied to a BMC, wherein the BMC is connected to a memory device, the method comprising:
acquiring a voltage adjustment instruction, wherein the voltage adjustment instruction is used for indicating to adjust the output voltage in the memory device;
acquiring a current state corresponding to the memory device;
according to the current state, adjusting the output voltage of the memory device to test the memory device;
the adjusting the output voltage of the memory device according to the current state includes:
if the current state is a normal working state, a first control instruction is sent to the memory device; the first control instruction is used for indicating the memory device to adjust a voltage output register; the voltage output register is used for adjusting the activation power supply voltage and the output buffer power supply voltage of the memory chip of the memory device in a normal working state;
the adjusting the output voltage of the memory device according to the current state includes:
if the current state is the power-on and power-off state, a second control instruction is sent to the memory device; the second control instruction is used for indicating the memory device to adjust a starting voltage register; the starting voltage register is used for adjusting the activation power supply voltage and the output buffer power supply voltage of the memory chip of the memory device in the power-on and power-off state.
2. The method of claim 1, wherein adjusting the output voltage of the memory device to test the memory device based on the current state comprises:
switching the control mode of the memory device to a target control mode according to the voltage adjustment instruction;
and acquiring a current state corresponding to the memory device, and adjusting the output voltage of the memory device based on the target control mode according to the current state so as to test the memory device.
3. The method of claim 1, wherein the obtaining the current state corresponding to the memory device comprises:
acquiring power state information sent by target equipment;
and determining the current state corresponding to the memory device according to the power state information.
4. The method of claim 3, wherein determining the current state of the memory device according to the power state information comprises:
if the power state information is high-level information, determining that the current state is a normal working state;
and if the power supply state information is low-level information, determining that the current state is an electrifying and shutdown state.
5. The method of claim 2, wherein after adjusting the output voltage of the memory device according to the current state, the method further comprises:
and switching the control mode of the memory device from the target control mode to a normal control mode.
6. A memory voltage testing apparatus, applied to a BMC, the BMC being connected to a memory device to be adjusted, the apparatus comprising:
the first acquisition module is used for acquiring a voltage adjustment instruction, wherein the voltage adjustment instruction is used for indicating to adjust the output voltage in the memory device;
the second acquisition module is used for acquiring the current state corresponding to the memory device;
the adjusting module is used for adjusting the output voltage of the memory device according to the current state so as to test the memory device;
the adjusting module is specifically configured to send a first control instruction to the memory device if the current state is a normal working state; the first control instruction is used for instructing the memory device to adjust the voltage output register; the voltage output register is used for adjusting the activation power supply voltage and the output buffer power supply voltage of the memory chip of the memory device in a normal working state;
the adjusting module is specifically configured to send a second control instruction to the memory device if the current state is an on-off state; the second control instruction is used for instructing the memory device to adjust the starting voltage register; the starting voltage register is used for adjusting the activation power supply voltage and the output buffer power supply voltage of the memory chip of the memory device in the power-on and power-off state.
7. A computing device comprising a memory having stored therein computer instructions and a processor that, upon execution of the computer instructions, performs the memory voltage testing method of any of claims 1-5.
8. A memory voltage test system is characterized in that the system comprises a BMC and a memory device, wherein the BMC is connected with the memory device,
the BMC acquires a voltage adjustment instruction, wherein the voltage adjustment instruction is used for indicating to adjust the output voltage in the memory device;
the BMC acquires the current state corresponding to the memory device;
the BMC adjusts the output voltage of the memory device according to the current state so as to test the memory device;
the BMC adjusts the output voltage of the memory device according to the current state, and the BMC comprises:
if the current state is a normal working state, a first control instruction is sent to the memory device; the first control instruction is used for indicating the memory device to adjust a voltage output register; the voltage output register is used for adjusting the activation power supply voltage and the output buffer power supply voltage of the memory chip of the memory device in a normal working state;
the BMC adjusts the output voltage of the memory device according to the current state, and the BMC comprises:
if the current state is the power-on and power-off state, a second control instruction is sent to the memory device; the second control instruction is used for indicating the memory device to adjust a starting voltage register; the starting voltage register is used for adjusting the activation power supply voltage and the output buffer power supply voltage of the memory chip of the memory device in the power-on and power-off state.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109683696A (en) * | 2018-12-25 | 2019-04-26 | 浪潮电子信息产业股份有限公司 | Fault of server power supply detection system, method, apparatus, equipment and medium |
| CN112732498A (en) * | 2020-12-29 | 2021-04-30 | 北京浪潮数据技术有限公司 | Test method, device, equipment and storage medium for simulating single-point power-on and power-off of equipment |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109683696A (en) * | 2018-12-25 | 2019-04-26 | 浪潮电子信息产业股份有限公司 | Fault of server power supply detection system, method, apparatus, equipment and medium |
| CN112732498A (en) * | 2020-12-29 | 2021-04-30 | 北京浪潮数据技术有限公司 | Test method, device, equipment and storage medium for simulating single-point power-on and power-off of equipment |
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