CN110476153A - 访问指令sram的方法和电子设备 - Google Patents

访问指令sram的方法和电子设备 Download PDF

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Publication number
CN110476153A
CN110476153A CN201880000220.0A CN201880000220A CN110476153A CN 110476153 A CN110476153 A CN 110476153A CN 201880000220 A CN201880000220 A CN 201880000220A CN 110476153 A CN110476153 A CN 110476153A
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China
Prior art keywords
address
instruction
controller
sram
electronic device
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Pending
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CN201880000220.0A
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English (en)
Inventor
吴双
刘丹
刘育峰
靳文鹤
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Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
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Publication of CN110476153A publication Critical patent/CN110476153A/zh
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/72—Masking faults in memories by using spares or by reconfiguring with optimized replacement algorithms
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0638—Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/251—Local memory within processor subsystem

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Quality & Reliability (AREA)
  • Debugging And Monitoring (AREA)

Abstract

本申请实施例提供了一种访问指令SRAM的方法和电子设备，在指令SRAM中的一些地址的内容出现异常之后，ICE预防指令SRAM出现的工作异常，提高系统的可靠性。该方法应用于电子设备，该电子设备包括第一控制器、指令SRAM和ICE；该方法包括：该ICE接收该第一控制器访问该指令SRAM的第一地址；若该第一地址与第二地址相同，该ICE向该第一控制器发送第一指令，该第二地址为该指令SRAM中异常的地址单元所对应的地址，该第一指令为该异常的地址单元的正确指令；或者若该第一地址与该第二地址不同，该ICE从该指令SRAM中获取该第一地址对应的第二指令，以及向该第一控制器发送该第二指令。

Description

PCT国内申请，说明书已公开。

Claims (18)

  1. PCT国内申请，权利要求书已公开。
CN201880000220.0A 2018-03-09 2018-03-09 访问指令sram的方法和电子设备 Pending CN110476153A (zh)

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PCT/CN2018/078499 WO2019169615A1 (zh) 2018-03-09 2018-03-09 访问指令sram的方法和电子设备

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CN110476153A true CN110476153A (zh) 2019-11-19

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US (1) US10922023B2 (zh)
EP (1) EP3557422A4 (zh)
CN (1) CN110476153A (zh)
WO (1) WO2019169615A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115686353A (zh) * 2021-07-27 2023-02-03 北京特纳飞电子技术有限公司 用于异常情况同步处理的固件控制且基于表的条件作用

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CN1540518A (zh) * 1994-12-28 2004-10-27 ��ʽ���綫֥ 微处理器
US20120246544A1 (en) * 2003-05-20 2012-09-27 Cray Inc. Method and apparatus for memory read-refresh, scrubbing and variable-rate refresh
CN101196847A (zh) * 2006-12-08 2008-06-11 深圳艾科创新微电子有限公司 Cpu程序存储器自动维护的方法及硬件单元结构
US20090248955A1 (en) * 2008-03-31 2009-10-01 Satoru Tamada Redundancy for code in rom
CN102270162A (zh) * 2011-07-29 2011-12-07 中国航天科技集团公司第五研究院第五一三研究所 一种应用于sparcv8结构计算机的容错引导方法
CN103412829A (zh) * 2013-08-16 2013-11-27 深圳市汇顶科技股份有限公司 扩大mcu程序地址空间的方法及装置
US20160080002A1 (en) * 2014-09-12 2016-03-17 Freescale Semiconductor, Inc. ADAPTIVE ERROR CORRECTION CODES (ECCs) FOR ELECTRONIC MEMORIES
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CN107544923A (zh) * 2016-06-28 2018-01-05 Arm 有限公司 用于控制对存储器设备的访问的装置以及相关方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115686353A (zh) * 2021-07-27 2023-02-03 北京特纳飞电子技术有限公司 用于异常情况同步处理的固件控制且基于表的条件作用

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EP3557422A4 (en) 2020-01-08
US20190310800A1 (en) 2019-10-10
WO2019169615A1 (zh) 2019-09-12
EP3557422A1 (en) 2019-10-23

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