JP2016122338A - Error correction apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an error correction apparatus configured to improve error correction capability without increasing circuit scale.SOLUTION: When a determination is made that read data DT2 is in an abnormal state of 25 bits or more, on the basis of error bit information EB2 obtained from a correction circuit 14A, a controller control section 12A enters two-stage correction processing. In steps ST25-ST27, first-stage correction processing is executed to restore the read data DT2 to read data DT1 of 24 bit or less with a bit error, including bit error correction processing using a correction circuit 14A with a second syndrome S2 stored in an SRAM 13 in a warning state. In steps ST28 and ST29, second-stage correction processing is executed to restore the read data DT1 to read data DT0 without bit error, including bit error correction processing using the correction circuit 14A with an initial syndrome S1.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an error correction apparatus that performs error correction at the time of reading from a semiconductor memory composed of cells in which a bit error occurs due to deterioration of a NAND cell or the like.

  In a memory system composed of a memory controller and a NAND memory (nonvolatile memory having NAND cells) as a semiconductor memory, a bit error due to read disturb occurs due to the characteristics of the NAND memory. .

  In addition, the use of NAND memory continuously accumulates damage to memory cells, and the memory cells that have been damaged deteriorate the retention characteristics, and generate more bit errors than normal memory cells. Or

  Normally, a certain amount of bit errors can be corrected by the error correction function, but if a bit error exceeding the error correction capability occurs, normal data reading becomes impossible.

  The following countermeasures are generally taken against bit errors that increase in the NAND memory.

  (1) A plurality of (error) correction circuits having different error correction capabilities are mounted, and error correction is performed by selecting one of the plurality of correction circuits according to the bit error occurrence state.

  (2) The retained data is returned to the normal state by refresh (rewriting normal data).

  As an example of the above (1), for example, in Patent Document 1, a plurality of correction circuits having different error correction capabilities are mounted, and among the plurality of correction circuits, the correction circuit to be used is operated according to the occurrence state of a bit error. A technique is disclosed in which a bit error exceeding the error correction capability is prevented from occurring by changing the error.

  In addition, the error correction capability of a single correction circuit is not achieved by combining multiple correction circuits with different error correction capabilities or code lengths (units of data to be corrected), instead of dynamically changing the correction circuit selection. For example, Patent Document 2 discloses a technique that can correct each other in a complementary manner even if a bit error exceeding 1 is generated.

JP2013-152604A JP 2011-507066 A

  However, in order to improve the error correction capability, the techniques disclosed in Patent Document 1 and Patent Document 2 have a problem that the circuit scale increases because a plurality of correction circuits are required.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain an error correction apparatus having improved error correction capability without increasing the circuit scale.

  An error correction apparatus according to claim 1 of the present invention is an error correction apparatus that performs error correction at the time of reading from a semiconductor memory in which user data and initial syndrome are stored in address units, and the correction is performed using the correction syndrome. And a correction circuit for executing a bit error correction process for correcting the bit error in the correction target data including the syndrome and obtaining the corrected data, and the correction circuit has a bit error number of the correction target data within the correctable number of bits. A temporary storage unit that stores the second syndrome in association with an address, the read data including the user data and the initial syndrome obtained from the semiconductor memory in units of addresses, Data correction reading including the bit error correction processing by the correction circuit And a control unit that obtains corrected read data by performing execution control of the read processing, and the data correction read processing is (a) in a normal state, the read data is the correction target data, and the initial syndrome is the As a correction syndrome, the step of causing the correction circuit to execute the bit error correction process and making the data included in the corrected data the corrected read data; and (b) the number of bit errors in the read data The read data is used as a syndrome generation target data in a warning state where the number of correctable bits or less reaches a preset warning reference bit number or more, and the second data for the syndrome generation target data is generated by the correction circuit. A syndrome is generated, and the second syndrome is changed during reading of the read data. (C) determining whether there is an abnormal state of the read data; (d) determining whether the read data is abnormal in step (c); The step (d) includes: (d-1) converting the read data and the second syndrome stored in the temporary storage unit to the correction target data. The second syndrome is used as the correction syndrome, the correction circuit is caused to execute the bit error correction processing, the user data portion in the corrected data is used as corrected user data, and the initial syndrome portion is used as a corrected initial syndrome. (D-2) the corrected user data and the corrected initial syndrome as the correction target data, and the corrected initial syndrome Using the correction circuit as the syndrome for correction, causing the correction circuit to execute the bit error correction processing, and using the data included in the corrected data as the corrected read data.

  When the error correction apparatus of the present invention according to claim 1 of the present invention determines the abnormal state of the read data in step (c), the error correction apparatus in two steps according to steps (d-1) and (d-2) of step (d) Correction processing is being executed.

  For this reason, the error correction apparatus according to the first aspect of the present invention provides a bit as corrected read data even when read data having a large number of bit errors exceeding the correctable number of bits of the correction circuit is stored in the semiconductor memory. Normal read data with error correction can be obtained.

  As a result, the present invention according to claim 1 can obtain an error correction device having a bit error correction capability exceeding the error correction capability of the built-in correction circuit with a relatively simple configuration including a single correction circuit. it can.

1 is a block diagram showing a configuration of a memory system according to Embodiment 1 of the present invention. FIG. 6 is an explanatory diagram illustrating a flow of data correction read processing of the error correction device according to the first embodiment. FIG. 6 is an explanatory diagram illustrating contents of read data and corrected data at the time of execution of data correction read processing according to the first embodiment. FIG. 6 is an explanatory diagram showing the contents of correction target data and correction syndrome in the first embodiment. It is a block diagram which shows the structure of the memory system which is Embodiment 2 of this invention. FIG. 10 is an explanatory diagram illustrating a flow of data correction read processing of the error correction device according to the second embodiment. FIG. 10 is an explanatory diagram illustrating the contents of read data and corrected data when executing a data correction read process according to the second embodiment. FIG. 10 is an explanatory diagram showing the contents of correction target data and correction syndrome in the second embodiment. It is a block diagram which shows the structure of the memory system which is Embodiment 3 of this invention. FIG. 10 is an explanatory diagram illustrating a flow of data correction read processing of the error correction device according to the third embodiment. FIG. 10 is an explanatory diagram showing the contents of read data and corrected data when executing a data correction read process according to the third embodiment. FIG. 10 is an explanatory diagram showing the contents of correction target data and correction syndrome in the third embodiment. 4 is a graph (No. 1) showing the number of bit errors associated with the number of reads in a NAND memory. It is a graph (the 2) which shows the number of bit errors accompanying the frequency | count of reading in NAND memory. 7 is a graph (No. 3) showing the number of bit errors associated with the number of reads in a NAND memory.

<Embodiment 1>
(overall structure)
FIG. 1 is a block diagram showing a configuration of a memory system 51 according to the first embodiment of the present invention. As shown in the figure, the memory system 51 according to the first embodiment includes a host 6, a memory controller 1, and a NAND memory 7.

  The host 6 writes data to or reads data from the NAND memory 7, which is a nonvolatile memory to be controlled, via the memory controller 1.

  The NAND memory 7 is a semiconductor memory composed of memory cells having a NAND cell structure in which data retention characteristics deteriorate due to deterioration due to continuous use.

  The NAND memory 7 stores correction management data D51, which will be described later, in the management area 71, and stores a combination of user data D1 and initial syndrome S1 in address units in the user data area 72. The initial syndrome S1 is an error correction code that is set when the user data D1 is written to the NAND memory 7.

  The memory controller 1 has a built-in error correction device 41, and performs an erase operation, a write operation, and a read operation on the NAND memory 7 in response to requests from the host 6 such as writing and reading.

  The memory controller 1 includes a host I / F 11, a NAND control unit 15, and an error correction device 41. The error correction device 41 includes a controller control unit 12A, SRAM 13, and (error) correction circuit 14A inside, and performs error correction when accessing the NAND memory 7.

  The host I / F 11 is an interface between the host 6 and the memory controller 1. The NAND control unit 15 controls data exchange between the memory controller 1 and the NAND memory 7, and the memory controller 1 and the NAND memory 7. Interface function.

  The SRAM 13 stores a second syndrome, which will be described later, in association with an address and stores it as correction management data D51, and functions as a temporary storage unit in the error correction device 41.

  The correction circuit 14A uses the correction syndrome CS to execute a bit error correction process for correcting the bit error in the correction target data CT including the correction syndrome CS itself to obtain the corrected data CD.

  The correction circuit 14A has a bit error correction capability that can be corrected when the number of bit errors generated in the correction target data CT is within 24 bits that can be corrected, and an error that indicates an error bit number of 28 bits or less. It has a bit error detection capability for outputting bit information EB. Thus, the correction circuit 14A has a bit error detection capability (28 bits) that exceeds the bit error correction capability (24 bits).

  The controller control unit 12A (control unit) has an erase function, a write function, and a read function for controlling an erase operation, a write operation, and a read operation with respect to the NAND memory 7. Then, the controller control unit 12A uses the SRAM 13 and the correction circuit 14A described above to execute and control data correction read processing capable of bit error correction exceeding the bit error correction capability (24 bits) of the correction circuit 14A. doing.

(Operation)
FIG. 2 is an explanatory diagram showing a flow of data correction read processing of the error correction apparatus 41 according to the first embodiment. FIG. 3 is an explanatory diagram showing the contents of read data and post-correction data when the error correction device 41 executes data correction read processing. FIG. 4 is an explanatory diagram showing the contents of correction target data and correction syndrome. Hereinafter, the contents of the data correction read processing by the error correction apparatus 41 according to the first embodiment will be described with reference to FIGS.

  For convenience of explanation, the read data DT, user data D1, correction target data CT, corrected data CD, and error bit information EB may be identified and marked as follows.

  In the read data DT (DT0 to DT2), data having no bit error is “read data DT0”, and data having a bit error of 24 bits or less that is the number of bits that can be corrected by the correction circuit 14A is “read data DT1”, 25 bits. Data having such a large amount of bit errors is denoted as “read data DT2”. The read data DT includes at least user data D1 and initial syndrome S1.

  Further, in the correction target data CT (CT1, CT2) output from the controller control unit 12A to the correction circuit 14A, the data when the initial syndrome S1 is the correction syndrome CS is “correction target data CT1”, and the second syndrome S2 is Data in the case of the correction syndrome CS is denoted as “correction target data CT2”.

  Further, in the corrected data CD (CD1, CD2) obtained by the bit error correction processing of the correction circuit 14A, the data obtained using the initial syndrome S1 is represented by “corrected data CD1” and the second syndrome S2. The obtained data is denoted as “corrected data CD2”.

  Also, in the error bit information EB (EB0 to EB2), the information indicating the bit error “0” is “error bit information EB0”, and the information indicating the number of correctable bit errors of 24 bits or less is “error”. Bit information EB1 ”and information indicating a large bit error of 25 bits or more are denoted as“ error bit information EB2 ”.

(1. When there is no bit error in the read data (normal state))
First, the case where the read data DT including the user data D1 and the initial syndrome S1 is read data DT0 having no bit error will be described. The read section PD0 in FIG. 2 shows the data correction read processing for the read data DT0.

  First, in step ST1, the controller control unit 12A reads the read data DT from the user data area 72 of the NAND memory 7 via the NAND control unit 15. As shown in FIG. 3A, since the read data DT is the read data DT0, there is a bit error in both the user data D1 included in the read data DT0 and the initial syndrome S1 corresponding to the user data D1. Absent.

  Next, in step ST2, the controller control unit 12A outputs the combination of the read data DT0 and the dummy data MD as the correction target data CT1, and outputs the initial syndrome S1 as the correction syndrome CS to the correction circuit 14A. As a result, as shown in FIG. 4A, the user data D1, the dummy data MD, and the initial syndrome S1 are stored as the correction target data CT1 in the setting state before the execution of the bit error correction processing of the correction circuit 14A. At this time, the initial syndrome S1 is set as the correcting syndrome CS. The dummy data MD has the same number of bits as the initial syndrome S1, and all are set to “0”. Further, part of the process of step ST2 can be executed in parallel with the process of step ST1. That is, the controller control unit 12A may immediately execute the process of step ST2 without waiting for the completion of reception as soon as the controller control unit 12A receives the data of the read data DT0 in step ST1.

  Thereafter, in step ST3, the correction circuit 14A outputs the corrected data CD1 obtained by executing the bit error correction process using the initial syndrome S1 to the controller control unit 12A. Since no bit error originally exists in the read data DT0, the corrected data CD1 includes the read data DT0 and error bit information EB0 indicating “0”. Although corrected dummy data MD also exists in the corrected data CD1, illustration thereof is omitted.

(2. When a bit error occurs in the read data and the number of bits is less than the correctable bit (24 bits) (normal state))
(2-1. When the number of bit errors is less than the warning reference bit number (16 bits))
Next, a case where a bit error occurs in the read data DT and the number of bits is the read data DT1 having 24 bits or less will be described. The read section PD1 in FIG. 2 shows the data correction read process for the read data DT1.

  First, in step ST11, the controller control unit 12A reads the read data DT from the NAND memory 7. Since the read data DT is read data DT1 in which a bit error exists, a bit error exists in at least one of the user data D1 and the initial syndrome S1 included in the read data DT1.

  Next, in step ST12, the controller control unit 12A outputs the combination of the read data DT1 and the dummy data MD as the correction target data CT1, and outputs the initial syndrome S1 as the correction syndrome CS to the correction circuit 14A. Further, part of the process of step ST12 can be executed in parallel with the process of step ST11.

  In step ST13, the correction circuit 14A outputs the corrected data CD1 obtained by performing the bit error correction process using the initial syndrome S1 to the controller control unit 12A. Since there is a bit error in the read data DT1, there is no bit error in the corrected data CD1, and error bit information indicating the number of bit errors in the corrected read data DT0 and the read data DT1 before correction EB1 is included.

  When the error bit information EB1 obtained in step ST13 indicates 15 or less below “16” which is the number of warning reference bits, the process ends in step ST13 described above. On the other hand, when the error bit information EB1 indicates 16 or more (24 or less), a warning is required, and steps ST14 to ST16 described in the next item (2-2.) Are continued. The number of warning reference bits is a value set in advance satisfying the condition of the number of correctable bits or less.

  Note that the processing of the items (1.) and (2-1.) Described above is executed as processing in the normal state because it does not become an abnormal state described later.

(2-2. When the number of bit errors is in a cautionary state where the number of warning bits is 16 or more)
In step ST14, the controller control unit 12A outputs the read data DT1 (user data D1 + initial syndrome S1) as syndrome generation target data CTS to the correction circuit 14A as shown in FIG.

  In step ST15, the correction circuit 14A generates a second syndrome S2 corresponding to the syndrome generation target data CTS, and outputs the second syndrome S2 to the controller control unit 12A.

  In step ST16, the controller control unit 12A manages the correction management data D51 in the SRAM 13 in the SRAM 13 by combining the second syndrome S2 and the address information AD indicating the address at the time of reading the read data DT1. Store in area R13. That is, as shown on the right side of FIG. 3, the SRAM management area R13 stores correction management data D51 including a combination of the second syndrome S2, address information AD, and flag information FG described later. Note that the initial value of the flag information FG is “0”.

(3. When a bit error occurs in the read data and the number of bits exceeds the correctable number of bits (24 bits))
(3-1. Determination of presence or absence of abnormal state)
Next, a case where a bit error occurs in the read data DT and the read data DT2 has a large number of bit errors exceeding 24 bits will be described. The read section PD2 in FIG. 2 shows the data correction read processing for the read data DT2.

  First, in step ST21, the controller control unit 12A reads the read data DT from the NAND memory 7. As shown in FIG. 3C, the read data DT is read data DT2 in which a large number of bit errors exist, so that the total number of bit errors existing in the user data D1 and the initial syndrome S1 included in the read data DT2 is 25. There are more than a bit.

  Next, in step ST22, the controller control unit 12A outputs the combination of the read data DT2 and the dummy data MD as the correction target data CT1, and outputs the initial syndrome S1 as the correction syndrome CS to the correction circuit 14A. Part of the process in step ST22 can be executed in parallel with the process in step ST21.

  In step ST23, the correction circuit 14A outputs the corrected data CD1 obtained by executing the bit error correction process using the initial syndrome S1 to the controller control unit 12A.

  At this time, since a large bit error of 25 bits or more has occurred in the read data DT2, the correction circuit 14A cannot correct the error, and the data in the corrected data CD1 becomes unknown data DTxx. However, if the bit error of the read data DT2 is 28 bits or less (25 to 28), error bit information EB2 indicating the correct number of bit errors is included in the corrected data CD1.

  Therefore, the controller control unit 12A can accurately recognize that the read data DT2 is in an abnormal state of 25 bits or more based on the error bit information EB2. Hereinafter, the abnormal state determination process performed by executing steps ST21 to ST23 is referred to as a first abnormality determination process.

  Subsequently, in step ST24, the controller control unit 12A accesses the SRAM 13, and sets the flag information FG to “1” in the correction management data D51 having the address information AD indicating the address at the time of reading in the read data DT2. set.

  Thereafter, when the controller control unit 12A reads the read data DT at the address in which the flag information FG indicates “1”, the read data DT is immediately in an abnormal state without performing the above-described steps ST21 to ST23. Judge that there is.

  Therefore, although not shown in FIG. 2, prior to the processing of steps ST21 to ST23, the controller control unit 12A sets the address when reading the read data DT as the correction management data D52 in the SRAM management area R13. It is recognized whether or not the flag information FG of the correction management data D52 is set to “1”, and if it is set to “1”, it is immediately determined as an abnormal state. Hereinafter, the abnormal state determination process based on the contents of the flag information FG is referred to as a second abnormality determination process.

  When an abnormal state of the read data DT read is detected by the first or second abnormality determination process described above, the following two-stage correction process (first-stage correction process + second-stage correction process) in steps ST25 to ST29 is performed. Transition.

(3-2. First stage correction processing)
As for the address of the read data DT2, the second syndrome S2 has already been stored in the SRAM management area R13 of the SRAM 13 corresponding to the address information AD indicating the address of the read data DT2. This is because the number of bit errors in the read data DT is usually 16 to 24 bits, which is greater than the warning reference bit number, before the occurrence of a large number of bit errors in which the number of bit errors in the read data DT at the same address is 25 bits or more. It is.

  Therefore, in step ST25, the controller control unit 12A reads the second syndrome S2 associated with the address information AD indicating the address of the read data DT2 from the in-SRAM management area R13 of the SRAM 13.

  Next, in step ST26, the controller control unit 12A corrects the combination of the read data DT2 (user data D1 + initial syndrome S1) and the second syndrome S2, as shown in FIGS. 3 (d) and 4 (b). The data CT2 is output to the correction circuit 14A. At this time, the second syndrome S2 read in step ST25 is set as the correcting syndrome CS.

  Further, when the second abnormality determination process based on the flag information FG is executed, a part of the process of step ST26 can be executed in parallel with the process of step ST21. That is, the controller control unit 12A receives the data of the read data DT0 in step ST21, and immediately receives the second syndrome S2 in step ST25, and immediately executes the process of step ST26 without waiting for the completion of reception in step ST21. Also good.

  Then, in step ST27, the correction circuit 14A outputs the corrected data CD2 obtained by executing the bit error correction process using the second syndrome S2 to the controller control unit 12A. As shown in FIG. 3E, the post-correction data CD2 includes read data DT1 (user data portion; corrected user data D1c and initial syndrome portion S1; corrected initial syndrome S1c) having a bit error of 24 bits or less. It is.

  In this way, the first stage correction process is performed to return the read data DT2 having a bit error of 25 bits or more to the read data DT1 having a bit error of 24 bits or less.

(3-3. Second stage correction process)
Subsequently, in step ST28, the controller control unit 12A sets the read data DT1 (corrected user data D1c and corrected initial syndrome S1c) and dummy data MD included in the corrected data CD2 as correction target data CT1 to the correction circuit 14A. Output. At this time, the corrected initial syndrome S1c obtained in step ST27 is set as the correcting syndrome CS.

  Then, in step ST29, the correction circuit 14A outputs the corrected data CD1 obtained by executing the bit error correction process using the corrected initial syndrome S1c to the controller control unit 12A. The corrected data CD1 includes read data DT0 corrected to have no bit error as shown in FIG. 3 (f).

  In this way, the second-stage correction process is performed in which the read data DT1 having a bit error of 24 bits or less obtained by the first-stage correction process is returned to the read data DT0 having no bit error.

  As a result, the memory controller 1 can output the user data D1 included in the read data DT0 error-corrected by the error correction device 41 to the host 6 via the host I / F 11 as corrected read data.

(Correction management data D51 of SRAM 13)
The SRAM 13 stores the correction management data D51 in the SRAM management area R13 in units of addresses. When the second syndrome S2 is generated twice or more at the same address, the second syndrome S2 of the correction management data D51 is The latest second syndrome S2 is overwritten.

  When the contents stored in the SRAM management area R13 of the SRAM 13 are updated, the memory controller 1 transfers the contents of the SRAM management area R13 to the management area 71 of the NAND memory 7 at an arbitrary timing.

  As an initial operation when the memory system 51 is turned on (after reset is released), the memory controller 1 transfers the contents of the management area 71 of the NAND memory 7 to the management area R13 in the SRAM 13 of the SRAM 13 via the NAND control unit 15. Forward.

  Thus, data transfer is appropriately performed between the SRAM 13 and the NAND memory 7 so that the correction management data D51 has the latest contents.

  If the correction management data D52 from the SRAM 13 to the NAND memory 7 is reset before being updated and the content held in the SRAM 13 is erased, the difference information from before the update is lost.

  However, the warning reference bit number (16) for generating the second syndrome S2 is set to a value having a margin with the correctable bit number (24) of the correction circuit 14A. For this reason, when reading from the NAND memory 7 again, the correction management data D51 having the second syndrome S2 is almost certainly generated while satisfying the condition for generating the second syndrome S2, so that reading is performed when an abnormal state occurs. There is no substantial problem that the SRAM 13 does not hold the address information AD corresponding to the data DT2.

(Effects etc.)
As described above, when the error correction device 41 of the first embodiment in the memory controller 1 determines an abnormal state in which a large amount of bit errors occur in the read data DT by the first or second abnormal state determination process described above, the first stage The stage correction process by the correction process and the second stage correction process is executed.

  For this reason, the error correction device 41 is used even when the read data DT stored in the NAND memory 7 is read data DT2 having a large number of bit errors exceeding 24 bits, which is the correctable number of bits of the correction circuit 14A. Thus, normal read data DT0 corrected for bit errors can be obtained as post-correction read data.

  For example, if the second syndrome S2 corresponding to the read data DT stored in the SRAM 13 is at the time of occurrence of a 24-bit bit error, the read data DT2 having a bit error of 48 bits (24 + 24) is also bit Error correction can be performed on read data DT0 having no error.

  As a result, the error correction device 41 according to the first embodiment having the bit error correction capability exceeding the bit error correction capability of the built-in correction circuit 14A can be obtained with a relatively simple configuration including the single correction circuit 14A. it can.

  Further, the error correction device 41 receives a large number of bit errors, which are bit errors exceeding the correctable number of bits, from the correction circuit 14A as a large number of bit error determination information serving as a criterion for determining whether or not the read data DT has occurred. Information EB (EB0 to EB2) is acquired.

  Therefore, based on the error bit information EB, it is possible to efficiently execute the two-stage correction process by accurately determining that the read data DT that needs the two-stage correction process is in an abnormal state when a large number of bits are generated. it can.

  Further, since the correction circuit 14A can further output error bit information EB indicating a part of the number of error bits (25 to 28 bits) that causes a large bit error, a bit error detection that outputs a large amount of bit error determination information. Since the function of the circuit can be shared by the correction circuit 14A, the device configuration of the error correction device 41 can be simplified.

  Furthermore, when the controller control unit 12A determines the abnormal state of the read data DT once by the abnormal state determination process based on the error bit information EB, the correction management data having the address information AD indicating the address of the read data DT. By setting the flag information FG of D51 to “1”, the determination in the read data DT can be fixed in an abnormal state.

  For this reason, the determination process (first abnormality determination process) in which the read data DT is in an abnormal state based on the error bit information EB is completed only once for the read data DT at the same address, and thereafter the flag information FG As a result of the fact that the abnormality can be recognized by the second abnormality determination process based on “1” and “0”, the execution time of the abnormality determination process can be shortened.

<Embodiment 2>
(overall structure)
FIG. 5 is a block diagram showing a configuration of a memory system 52 according to the second embodiment of the present invention. As shown in the figure, the memory system 52 of the second embodiment includes a host 6, a memory controller 2, and a NAND memory 7. Hereinafter, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The NAND memory 7 stores correction management data D52, which will be described later, in the management area 71, and stores a combination of user data D1 and initial syndrome S1 in address units in the user data area 72.

  The memory controller 2 includes the error correction device 42 according to the second embodiment, and performs an erase operation, a write operation, and a read operation on the NAND memory 7 in response to a request for writing and reading by the host 6.

  The memory controller 2 includes a host I / F 11, a NAND control unit 15, and an error correction device 42. The error correction device 42 includes a controller control unit 12B, SRAM 13, and correction circuit 14B therein, and performs error correction when accessing the NAND memory 7.

  The SRAM 13 stores the second syndrome S2 as the correction management data D52 in association with the address, and functions as a temporary storage unit in the error correction device 42.

  Similarly to the correction circuit 14A of the first embodiment, the correction circuit 14B uses the correction syndrome CS to correct a bit error in the correction target data CT including the correction syndrome CS itself and obtain a corrected data CD. Perform error correction processing.

  Further, the correction circuit 14B has a bit error detection capability for outputting error bit information EB indicating the number of error bits of 24 bits or less. Thus, the correction circuit 14B has the same bit error detection capability (24 bits) as the bit error correction capability (24 bits).

  The controller control unit 12B (control unit) has an erase function, a write function, and a read function for controlling an erase operation, a write operation, and a read operation with respect to the NAND memory 7. The controller control unit 12B performs execution control of data correction read processing capable of bit error correction exceeding the bit error correction capability (24 bits) of the correction circuit 14B, using the SRAM 13 and the correction circuit 14B described above. doing.

(Correction circuit 14B)
As the correction circuit 14B, a correction circuit that performs a bit error correction process by using a BCH code can be considered. Hereinafter, a case where a BCH code is used will be described as an example.

  For example, when bit error correction processing is performed on user data D1 in units of 512 bytes (= 4092 bits), the irreducible polynomial of the Galois extension field GF (2 ^ 13) is {X ^ 13 + X ^ 4 + X ^ 3 + X + 1}, and when bit error correction processing is performed for user data D1 in 1024 bytes, the irreducible polynomial of Galois extension field GF (2 ^ 14) is {X ^ 14 + X ^ 10 + X ^ 6 + X + 1}. "^" Means factorial.

  When the user data D1 is 512 bytes (4096 bits), the initial syndrome S1 and the dummy data MD for performing a 24-bit bit error correction capability have a bit length of 312 bits. Therefore, 4720 bits (= 4096 + 312 + 312), which is the bit length obtained by adding the dummy data MD and the correction syndrome CS to the user data D1, is the bit length of the correction target data CT. On the other hand, if it is intended to have a 40-bit bit error correction capability under the above conditions, the bit length of the initial syndrome S1 needs to be 520 bits.

  On the other hand, when the user data D1 is 1024 bytes (8192 bits), the bit length of the initial syndrome S1 and the dummy data MD is 336 bits. Therefore, 8864 bits (= 8192 + 336 + 336), which is the bit length obtained by adding the correction syndrome CS and the dummy data MD to the user data D1, is the bit length of the correction target data CT. On the other hand, if it is intended to have a 40-bit bit error correction capability under the above conditions, the bit length of the initial syndrome S1 needs to be 560 bits.

  In the NAND memory 7, the user data area 72 is allocated to the user area for the user data D1 and the redundant area of the initial syndrome S1.

  Consider a specific example when the NAND memory 7 requires a bit correction capability of 40 bits per 1024 bytes.

  In this case, as a specific example 1, a mode in which the user area is set to 8192 bytes, the redundant area is set to 640 bytes, and the size of one page is set with a total of 8832 bytes. In this case, 80 bytes (640 bits) of redundant areas are provided per 1024 bytes, and 40 bytes (320 bits) of redundant areas are provided per 512 bytes.

  As specific example 2, a mode in which the user area is set to 16384 bytes, the redundant area is set to 1280 bytes, and the size of one page is set with a total of 17664 bytes can be considered. In this case as well, as in the first specific example, 80 bytes (640 bits) of redundant areas are provided per 1024 bytes, and 40 bytes (320 bits) of redundant areas are provided per 512 bytes.

  Therefore, in each of the specific example 1 and the specific example 2, when the above-described BCH code is used, for the initial syndrome S1 when the user data D1 is 1024 bytes, for the initial syndrome S1 when the user data D1 is 512 bytes, 312 bits can be stored in the redundant area.

(Operation)
FIG. 6 is an explanatory diagram showing the flow of data correction read processing of the error correction device 42 in the memory controller 2 of the second embodiment. FIG. 7 is an explanatory diagram showing the contents of read data and post-correction data when the error correction device 42 executes data correction read processing. FIG. 8 is an explanatory diagram showing the contents of the correction target data and the correction syndrome. Hereinafter, the contents of the data correction read processing by the error correction device 42 according to the second embodiment will be described with reference to FIGS.

(1. When there is no bit error in the read data (normal state))
First, when the read data DT is read data DT0 having no bit error, the data correction read processing for the read data DT0 in the read section PD0 in FIG. 6 is performed as in the read section PD0 in the first embodiment shown in FIG. Steps ST1 to ST3 are executed.

(2. When a bit error occurs in the read data and the number of bits is less than the correctable bit (24 bits))
(2-1. When the number of bit errors is less than the warning reference bit number (16 bits))
Next, when a bit error occurs in the read data DT and the number of bits is the read data DT1 less than the warning reference bit number (16 bits), as in steps ST11 to ST13 of the read section PD1 of the first embodiment. Steps ST11 to ST13 are executed in the read section PD1 in FIG. FIG. 7 (a) corresponds to FIG. 3 (a).

  Therefore, when the error bit information EB1 indicates 16 or more (24 or less), a warning state is required, and steps ST14 to ST16 described in the next item (2-2.) Are continued.

  Note that the processing of the items (1.) and (2-1.) Described above is processing in a normal state that is executed in a situation where it is not determined as an abnormal state.

(2-2. When the number of bit errors is in a cautionary state where the number of warning bits is 16 or more)
In step ST14, as shown in FIG. 7B, the controller control unit 12B outputs the read data DT1 (user data D1 + initial syndrome S1) to the correction circuit 14B as syndrome generation target data CTS.

  In step ST15, the correction circuit 14B generates a second syndrome S2 corresponding to the syndrome generation target data CTS, and outputs the second syndrome S2 to the controller control unit 12B.

  In step ST16, the controller control unit 12B sets the correction management data D52, which is a combination of the second syndrome S2 and the address information AD indicating the address at the time of reading the read data DT1, in the SRAM 13 management area. Store in R13. As shown on the right side of FIG. 7, the correction management data D52 is stored in the in-SRAM management area R13, which is a combination of only the second syndrome S2 and the address information AD. That is, the correction management data D52 is different from the correction management data D51 of the first embodiment in that it does not have the flag information FG.

  In the error correction apparatus 42 according to the second embodiment, when the read data DT reaches the warning reference bit number or more and the address information AD is registered in the SRAM 13 as the correction management data D52, the address information AD instructs thereafter. The address read data DT is determined to be in an abnormal state. For this reason, the second syndrome S2 is registered only once at the same address.

(3. When a bit error occurs in the read data and the number of bits exceeds the correctable number of bits (24 bits))
(3-1. Determination of presence or absence of abnormal state)
Next, a case where a bit error occurs in the read data DT and the read data DT2 has a large number of bit errors exceeding 24 bits will be described.

  Although not shown in FIG. 6, the controller control unit 12B determines whether the read data DT2 is in an abnormal state based on whether or not the address information AD indicating the address at the time of reading the read data DT2 is stored as the correction management data D52. Whether or not there is.

  Therefore, when the address information AD indicating the address of the read data DT2 exists in the correction management data D52, the controller control unit 12B immediately determines that the read data DT2 is in an abnormal state, and the following steps ST25 to ST29 are performed. The process proceeds to a two-stage correction process.

(3-2. First stage correction processing)
In step ST25, the controller control unit 12B reads out the second syndrome S2 associated with the address information AD indicating the address of the read data DT2 from the SRAM 13, as in the first embodiment.

  Thereafter, similarly to the first embodiment, steps ST26 and ST27 are executed, and the read data DT2 having a bit error of 25 bits or more is returned to the read data DT1 having a bit error of 24 bits or less. FIGS. 7C and 7D correspond to FIGS. 3D and 3E.

(3-3. Second stage correction process)
As in the first embodiment, steps ST28 and ST29 are executed, and the read data DT1 having a bit error of 24 bits or less obtained by the first stage correction process is returned to the read data DT0 having no bit error.

  As a result, the memory controller 2 can output the user data D1 included in the read data DT0 error-corrected by the error correction device 42 to the host 6 via the host I / F 11 as corrected read data. FIG. 7 (e) corresponds to FIG. 3 (f).

  For convenience of explanation, read data DT2 having a large amount of bit errors is used as an explanation of items (3-1. To 3-3.). However, even in the read data DT1 having a bit error that is not less than the warning reference bit number (16 bits) but less than the correctable bit number (24 bits), the corresponding address information AD is already managed in the SRAM as the correction management data D52. If it is registered in the region R13, it is determined as an abnormal state and can be subjected to a two-step correction process.

  Therefore, as shown in FIG. 8 (b), the read circuit DT1 and the second syndrome S2 are used as the correction target data CT2, and the second syndrome S2 is used as the correction syndrome CS. There is also a possibility.

  On the other hand, as shown in FIG. 8A, the read data DT included in the correction target data CT1 in the bit error correction processing in which the initial syndrome S1 is the correction syndrome CS is almost certainly the read data DT0 or the read data DT1. The possibility that the read data DT2 is included is extremely low. This is because, prior to the generation of the read data DT2, the read data DT1 exceeding the warning reference bit number is almost certainly generated when the same address is read, and the address information AD is registered in the management area R13 in the SRAM. .

(Correction management data D52 of SRAM 13)
The SRAM 13 stores the correction management data D52 in the SRAM management area R13 in units of addresses, and the second syndrome S2 is generated only once at the same address and is not overwritten.

  Also. Similar to the first embodiment, data transfer is appropriately performed between the SRAM 13 and the NAND memory 7 so that the correction management data D52 has the latest contents.

(Effects etc.)
As described above, the error correction device 42 according to the second embodiment provided in the memory controller 2 is in an abnormal state based on the presence / absence of the address information AD indicating the address of the read data DT in the management area R13 in the SRAM. When an abnormal state is determined by the determination process, a stage correction process by a first stage correction process and a second stage correction process is executed.

  For this reason, the error correction device 42 is normal in which the bit error is corrected as read data after correction even when the read data DT read from the NAND memory 7 is the read data DT2 having a large bit error of the correction circuit 14B. Read data DT0 can be obtained.

  For example, even if the second syndrome S2 corresponding to the read data DT is stored in the SRAM management area R13 when a 16-bit bit error occurs, the read data has a 40-bit (24 + 16) bit error. With respect to DT2, error correction can be performed to read data DT0 having no bit error.

  As a result, the error correction device 42 of the second embodiment having a bit error correction capability exceeding the bit error correction capability of the built-in correction circuit 14B can be obtained with a relatively simple configuration including a single correction circuit 14B. it can.

  Further, the error correction device 42 determines whether the read data DT is in an abnormal state based on the presence / absence of registration of the address information AD indicating the address at the time of reading the read data DT in the correction management data D52 in the SRAM management area R13. Judgment is made. Accordingly, since the read data DT at the address indicated by the address information AD registered in the correction management data D52 is always determined to be in an abnormal state, once it is determined as an abnormal state, the determination in the read data DT is fixed in the abnormal state. Is done.

  As described above, the error correction device 42 according to the second embodiment performs the presence / absence determination of the read data DT by referring to the contents of the management area R13 in the SRAM. Since the configuration corresponding to the bit error detection circuit (the function of generating the error bit information EB2 of the correction circuit 14A of the first embodiment or the correction availability calculation unit 16 of the second embodiment) is not required, the apparatus configuration is simplified. Can be achieved.

  Further, the correction circuit 14B used in the error correction device 42 of the second embodiment does not need to have a bit error detection capability exceeding the correctable number of bits unlike the correction circuit 14A of the first embodiment. In addition, the circuit configuration can be simplified.

<Embodiment 3>
(overall structure)
FIG. 9 is a block diagram showing a configuration of a memory system 53 according to the third embodiment of the present invention. As shown in the figure, the memory system 53 according to the third embodiment includes a host 6, a memory controller 3, and a NAND memory 7. Hereinafter, the same components as those in the first embodiment or the second embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The NAND memory 7 stores the correction management data D52 in the management area 71 as in the second embodiment, and the user data area 72 stores the combination of the user data D1 and the initial syndrome S1 in units of addresses.

  The memory controller 3 includes the error correction device 43 according to the third embodiment, and performs an erasing operation, a writing operation, and a reading operation on the NAND memory 7 in response to requests such as writing and reading by the host 6.

  The memory controller 3 includes a host I / F 11, a NAND control unit 15, and an error correction device 43. The error correction device 43 includes a controller control unit 12C, SRAM 13, and correction circuit 14B inside, and performs error correction when accessing the NAND memory 7.

  The SRAM 13 stores the second syndrome S2 as the correction management data D52 in association with the address, and functions as a temporary storage unit in the error correction device 43.

  Similarly to the correction circuit 14B of the second embodiment, the correction circuit 14B uses the correction syndrome CS to correct a bit error in the correction target data CT including the correction syndrome CS to obtain a corrected data CD. Perform correction processing. That is, the correction circuit 14B has the same bit error detection capability (24 bits) as the bit error correction capability (24 bits).

  The correctability calculation unit 16 performs CRC (Cyclic redundancy check) code generation calculation processing on the calculation target data JD, and generates a comparison CRC code CR16 (comparison error detection code) corresponding to the calculation target data JD. An error detection code generation process is executed.

  The controller control unit 12C (control unit) has an erase function, a write function, and a read function for controlling an erase operation, a write operation, and a read operation with respect to the NAND memory 7. Then, the controller control unit 12C uses the SRAM 13, the correction circuit 14B, and the correctability calculation unit 16 described above to perform a data correction read process capable of bit error correction exceeding the bit error correction capability (24 bits) of the correction circuit 14B. It is characterized by execution control.

(Operation)
FIG. 10 is an explanatory diagram showing the flow of data correction read processing of the error correction device 43 in the memory controller 3 of the third embodiment. FIG. 11 is an explanatory diagram showing the contents of read data and post-correction data when the error correction apparatus 43 executes data correction read processing. FIG. 12 is an explanatory diagram showing the contents of the correction target data and the correction syndrome. Hereinafter, the contents of the data correction read processing by the error correction device 43 according to the third embodiment will be described with reference to FIGS.

(1. When there is no bit error in the read data (normal state))
First, a case where the read data DT is read data DT0 having no bit error will be described. The read section PD0 in FIG. 8 shows the data correction read process for the read data DT0.

  First, in step ST51, the controller control unit 12C reads data as read data DT from the user data area 72 of the NAND memory 7 via the NAND control unit 15. As shown in FIG. 11 (a), the read data DT is read data DT0 with no bit error. Therefore, the user data D1 and the initial syndrome S1 corresponding to the user data D1 and the CRC code CR ( There is no bit error in any of the error detection codes. The CRC code CR is a code obtained by executing CRC code generation calculation processing by the correctability calculator 16 on the user data D1.

  Next, in step ST52, the controller control unit 12C outputs the combination of the read data DT0 and the dummy data MD as the correction target data CT1, and outputs the initial syndrome S1 as the correction syndrome CS to the correction circuit 14B. As a result, as shown in FIG. 12 (a), the user data D1, the CRC code CR, the dummy data MD, the initial syndrome S1, In this case, the initial syndrome S1 is set as the correcting syndrome CS. The dummy data MD has the same number of bits as the initial syndrome S1, and all are set to “0”. Further, the process of step ST52 can be partially executed in parallel with the process of step ST51.

  Thereafter, in step ST53, the correction circuit 14B outputs the corrected data CD1 obtained by executing the bit error correction process using the initial syndrome S1 to the controller control unit 12C. Since no bit error originally exists in the read data DT0, the corrected data CD1 includes the read data DT0 and error bit information EB0 indicating “0”.

  Subsequently, in step ST54, the controller control unit 12C outputs the user data D1 included in the corrected data CD1 to the correction availability calculation unit 16 as calculation target data JD.

  The correctability calculator 16 executes a CRC code generation calculation process on the user data D1 to generate a comparison CRC code CR16 corresponding to the user data D1.

  Subsequently, in step ST55, the controller control unit 12C compares the CRC code CR included in the corrected data CD1 with the comparison CRC code CR16, and since both match, a large bit error exceeding the correctable bit occurs. You can be sure that it is not.

(2. When a bit error occurs in the read data and the number of bits is less than the correctable bit (24 bits) (normal state))
(2-1. When the number of bit errors is less than the warning reference bit number (16 bits))
Next, a case where a bit error occurs in the read data DT and the number of bits is the read data DT1 having 24 bits or less will be described. The read section PD1 in FIG. 10 shows the data correction read processing for the read data DT1.

  First, in step ST61, the controller control unit 12C reads the read data DT from the NAND memory 7. The read data DT is composed of a combination of the read data DT1 in which a bit error exists and the initial syndrome S1.

  Next, in step ST62, the controller control unit 12C outputs the combination of the read data DT1 and the dummy data MD as the correction target data CT1, and outputs the initial syndrome S1 as the correction syndrome CS to the correction circuit 14B. Part of the process in step ST62 can be executed in parallel with the process in step S61.

  In step ST63, the correction circuit 14B outputs the corrected data CD1 obtained by executing the bit error correction process using the initial syndrome S1 to the controller control unit 12C. Since there is a bit error in the read data DT1, there is no bit error in the corrected data CD1, and error bit information indicating the number of bit errors in the corrected read data DT0 and the read data DT1 before correction EB1 is included.

  Thereafter, in steps ST64 and ST65, processing similar to that in steps ST54 and ST55 is executed, and it is confirmed whether or not a large bit error has occurred based on the comparison between the CRC code CR and the comparison CRC code CR16.

  When the error bit information EB1 obtained in step ST63 indicates 15 or less below “16”, which is the number of warning reference bits, the process ends in step ST65 described above. On the other hand, when the error bit information EB1 indicates 16 or more (24 or less), a warning state is required, and steps ST66 to ST68 described in the next item (2-2.) Are continued.

(2-2. When the number of bit errors is in a cautionary state where the number of warning bits is 16 or more)
In step ST66, the controller control unit 12C outputs the read data DT1 (user data D1 + CRC code CR + initial syndrome S1) to the correction circuit 14B as syndrome generation target data CTS as shown in FIG. 11B.

  In step ST67, the correction circuit 14B generates the second syndrome S2 corresponding to the syndrome generation target data CTS, and outputs the second syndrome S2 to the controller control unit 12C.

  In step ST68, the controller control unit 12C sets the correction management data D52, which is a combination of the second syndrome S2 and the address information AD indicating the address at the time of reading the read data DT1, in the SRAM 13 management area. Store in R13. That is, as shown on the right side of FIG. 11, correction management data D52 including a combination of the second syndrome S2 and the address information AD is stored in the management area R13 in the SRAM.

(3. When a bit error occurs in the read data and the number of bits exceeds the correctable number of bits (24 bits))
(3-1. Determination of presence or absence of abnormal state)
Next, a case where a bit error occurs in the read data DT and the read data DT2 has a large number of bit errors exceeding 24 bits will be described. The read section PD2 in FIG. 10 shows the data correction read processing for the read data DT2.

  First, in step ST71, the controller control unit 12C reads the read data DT from the NAND memory 7. As shown in FIG. 11 (c), the read data DT is read data DT2 in which a large number of bit errors exist, so that the user data D1, CRC code CR included in the read data DT2, and the bit error existing in the initial syndrome S1. The total number is 25 bits or more.

  Next, in step ST72, the controller control unit 12C outputs the combination of the read data DT2 and the dummy data MD as the correction target data CT1, and outputs the initial syndrome S1 as the correction syndrome CS to the correction circuit 14B. Part of the process in step ST72 can be executed in parallel with the process in step ST71.

  In step ST73, the correction circuit 14B outputs the corrected data CD1 obtained by executing the bit error correction process using the initial syndrome S1 to the controller control unit 12C.

  At this time, since the read data DT2 has a large bit error of 25 bits or more, the user data in the corrected data CD1 becomes unknown data DTxx.

  On the other hand, in step ST74, the controller control unit 12C outputs unknown user data D1xx, which is user data included in the corrected data CD1, to the correctability calculation unit 16 as calculation target data JD.

  The correctability calculator 16 performs a CRC code generation calculation process on the unknown user data D1xx, and generates a comparison CRC code CR16 corresponding to the unknown user data D1xx.

  Subsequently, in step ST75, the controller control unit 12C compares the CRC code CR included in the corrected data CD1 with the comparison CRC code CR16, and the two do not match. Therefore, a large number of bit errors exceeding the correctable bits occur. It is possible to accurately determine what has occurred.

  As described above, the error correction apparatus 43 according to the third embodiment performs the read data DT based on the comparison between the CRC code CR and the comparison CRC code CR16 by using the correctability calculator 16 by executing steps ST71 to ST75. An abnormality determination process is performed to determine whether there is an abnormal state.

  When the abnormal state of the read data DT read is detected by the abnormality determination process described above, the process proceeds to the following two-stage correction process (first-stage correction process + second-stage correction process) in steps ST76 to ST82.

(3-2. First stage correction processing)
Similar to the first embodiment, the second syndrome S2 is already stored in the SRAM management area R13 of the SRAM 13 corresponding to the address information AD indicating the address at the time of reading the read data DT2.

  Therefore, in step ST76, the controller control unit 12C reads from the SRAM 13 the second syndrome S2 associated with the address information AD indicating the address when reading the read data DT2.

  Next, in step ST77, the controller control unit 12C determines the combination of the read data DT2 (user data D1 + CRC code CR + initial syndrome S1) and the second syndrome S2 as shown in FIGS. 11 (d) and 12 (b). The correction target data CT2 is output to the correction circuit 14B. At this time, the second syndrome S2 read in step ST76 is set as the correcting syndrome CS.

  Then, in step ST78, the correction circuit 14B outputs the corrected data CD2 obtained by executing the bit error correction process using the second syndrome S2 to the controller control unit 12C. As shown in FIG. 11 (e), the corrected data CD2 is read data DT1 (user data portion; corrected user data D1c, CRC code portion (error correction code portion)) having a bit error of 24 bits or less; Code CRc (correction error detection code) and initial syndrome part; correction initial syndrome S1c) are included.

  In this way, the first stage correction process is performed to return the read data DT2 having a bit error of 25 bits or more to the read data DT1 having a bit error of 24 bits or less.

(3-3. Second stage correction process)
Subsequently, in step ST79, the controller control unit 12C converts the read data DT1 (corrected user data D1c, corrected CRC code CRc, and corrected initial syndrome S1c) and dummy data MD included in the corrected data CD2 to the correction target data CT1. To the correction circuit 14A. At this time, the corrected initial syndrome S1c obtained in step ST27 is set as the correcting syndrome CS.

  Then, in step ST80, the correction circuit 14B outputs the corrected data CD1 obtained by executing the bit error correction process using the initial syndrome S1 to the controller control unit 12C. The corrected data CD1 includes read data DT0 corrected to have no bit error as shown in FIG. 11 (f).

  Thereafter, in steps ST81 and ST82, as in steps ST54 and ST55, it is confirmed whether or not a large number of bit errors have occurred based on the comparison between the CRC code CR and the comparison CRC code CR16.

  In this way, the second-stage correction process is performed in which the read data DT1 having a bit error of 24 bits or less obtained by the first-stage correction process is returned to the read data DT0 having no bit error.

  As a result, the memory controller 3 can output the user data D1 included in the read data DT0 error-corrected by the error correction device 43 to the host 6 via the host I / F 11 as corrected read data.

  As described above, unlike the controller control unit 12A, the controller control unit 12C includes the CRC code CR in the correction target data CT1 when executing steps ST52, ST62, ST72, and ST79, and the correction target data CT2 when executing step ST77. Includes a CRC code CR.

  Further, the CRC code CR is included in the syndrome generation target data CTS at the time of execution of step ST66, the CRC code CR portion of the corrected data CD2 at the time of execution of step ST78 is set as the corrected CRC code CRc, and the corrected data at the time of execution of step S80. The corrected CRC code CRc is included in CD1.

(Correction management data D52 of SRAM 13)
The SRAM 13 stores the correction management data D52 in the SRAM management area R13 in units of addresses. When the second syndrome S2 is generated twice or more at the same address, the second syndrome S2 of the correction management data D52 is The latest second syndrome S2 is overwritten.

  Similarly to the first embodiment, data transfer is appropriately performed between the SRAM 13 and the NAND memory 7 so that the correction management data D52 has the latest contents.

(Effects etc.)
As described above, the error correction device 43 according to the third embodiment in the memory controller 1 causes a large number of bit errors in the read data DT by the abnormal state determination process using the dedicated correctability calculator 16 as a bit error detection circuit. When the abnormal state is determined, the stage correction process by the first stage correction process and the second stage correction process is executed.

  For this reason, the error correction device 43 is used even when the read data DT stored in the NAND memory 7 is read data DT2 having a large number of bit errors exceeding 24 bits, which is the correctable number of bits of the correction circuit 14B. Thus, normal read data DT0 corrected for bit errors can be obtained as post-correction read data.

  For example, if the second syndrome S2 corresponding to the read data DT stored in the SRAM 13 is at the time of occurrence of a 24-bit bit error, the read data DT2 having a bit error of 48 bits (24 + 24) is also bit Error correction can be performed on read data DT0 having no error.

  As a result, it is possible to obtain the error correction device 43 of the third embodiment having a bit error correction capability exceeding the bit error correction capability of the built-in correction circuit 14B with a relatively simple configuration including a single correction circuit 14B. it can.

  Further, the error correction device 43 receives a mass bit error that is a bit error exceeding the correctable number of bits as mass bit error determination information serving as a criterion for determining whether or not the read data DT is generated, from the correctability determination unit 16. The comparison CRC code CR16 is used.

  Therefore, based on the CRC code for comparison CR16, the two-stage correction process can be efficiently executed by accurately determining the occurrence of a mass bit error in the read data DT that requires the two-stage correction process as an abnormal state. Can do.

  As described above, the error correction apparatus 43 according to the third embodiment includes the correctability calculation unit 16 that executes a CRC code generation calculation process (error detection code generation process) as a bit error detection circuit. For this reason, the controller control unit 12C executes the above-described steps ST71 to ST75 while causing the correctability calculation unit 16 to execute the code generation calculation process, so that the controller control unit 12C is surely set to 2 only when a mass bit error occurs in the read data DT. A stage correction process can be performed. As a result, the above-described two-stage correction process can be performed most efficiently.

  Further, the correction circuit 14B used in the error correction device 43 of the third embodiment does not need to have a bit error detection capability exceeding the number of correctable bits unlike the correction circuit 14A of the first embodiment. In addition, the circuit configuration can be simplified.

  In addition, in the correction possibility calculation part 16 of the error correction apparatus 43 of Embodiment 3, although the case where the code generation calculation process for CRC was performed as an error detection code generation process was shown, it replaced with this and the Hush function was utilized. Code generation calculation processing may be performed.

<Consideration of Embodiments According to Characteristics of NAND Memory 7>
FIGS. 13 to 15 are graphs showing the number of bit errors associated with the number of readings per data length of the data to be corrected regarding the data read from the NAND memory 7, and FIG. 14 shows the case where the number of times of erasing and programming is 2000 times, and FIG. 15 shows the case where the number of times of erasing and programming is 3000 times.

  13 to 15, taking 64 NAND flash memories corresponding to the NAND memory 7 as samples, the horizontal axis indicates the number of reads (RN), and the vertical axis indicates the number of bit errors (BEN). The bit error numbers L1, L2, and L3 indicate the minimum value (Min), average value (Ave), and maximum value (Max) of the detected bit error number (BEN).

  As shown in FIGS. 13 and 14, when the number of erasures and programming is 2000 times or less and the number of readings is 4 million times or less, the maximum number of bit errors is about 20 bits. Even if the correction circuit 14A or the correction circuit 14B having a relatively small circuit scale of 24 bits is used, error correction can be sufficiently performed.

  That is, in the above case, the error correction apparatuses 41 to 43 can perform error correction by one correction process in the normal state using the initial syndrome S1, and thus two-stage correction processes that require a relatively long time are frequently performed. It is presumed that there is little concern that the operating efficiency will decrease due to the fact that it is executed immediately.

  On the other hand, as shown in FIGS. 14 and 15, when the number of erases and programs is 2000 times or more and the number of readings is 5 million times or more, the maximum value of the number of bit errors is a large number of bit errors exceeding 24 bits. It occurs almost certainly.

  However, the error correction apparatuses 41 to 43 according to the first to third embodiments reliably perform error using only the correction circuit 14A and the correction circuit 14B even when a large number of bit errors occur due to the two-stage correction processing. Corrections can be made.

  As described above, the error correction devices 41 to 43 according to the first to third embodiments are smaller than the correction circuit having a correctable bit number of about 40 bits, and the single circuit having a correctable bit number of 24 bits and a small circuit scale. High bit error correction capability capable of correcting a large number of bit errors exceeding 24 correctable bits without deteriorating the operation efficiency while simplifying the device configuration by using one correction circuit 14A or correction circuit 14B. Can have.

<Others>
In the first to third embodiments described above, the warning reference bit number is set to “16” with respect to the correctable bit number “24”. However, the present invention is not limited to this. It is desirable to set to an appropriate value.

  As main factors for determining the number of warning reference bits, an assumed number of rewrites (erase and program), an assumed number of reads, characteristics of NAND memory (including evaluation results as shown in FIGS. 13 to 15), and the like can be considered.

  For example, if the NAND memory 7 has the characteristics shown in FIGS. 13 to 15 and is assumed to be used when the number of rewrites is 2000 or less and the number of reads is 4 million or less, the warning reference bit number is a correctable bit. Setting to a value close to the number “24” is desirable because the bit error correction capability can be increased. Furthermore, in the error correction device 42 of the second embodiment, the execution efficiency of the two-stage correction process can be increased.

  On the other hand, when the NAND memory 7 has the characteristics as shown in FIGS. 13 to 15 and assumes that the number of rewrites is 3000 times or more and the number of reads is 3 million times or more, in order to reliably perform the two-stage correction process, It is desirable to set the warning reference bit number to about “16” in the first to third embodiments with a margin from the correctable bit number “24”.

  When new erase and program processing is executed on the NAND memory 7 and the user data D1 is rewritten with new contents, the contents of the initial syndrome S1 are also changed, and correction management data D51 (D52 for the user data D1) is changed. ) Is also cleared from the management area 71.

  The dummy data MD is used for adjusting the number of bits between the correction target data CT1 and CT2 in order to perform a two-step correction process using one correction circuit 14A (14B). When the number of bits of the correction target data of the correction circuit 14A (14B) can be variably set, the dummy data MD for adjusting the number of bits between the correction target data CT1 and CT2 can be eliminated.

  Each unit of the memory controllers 1 to 3 is basically configured by hardware, but may be executed by program processing using a CPU based on software except for the SRAM 13.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

1-3 Memory controller 6 Host 7 NAND memory 11 Host I / F
12A to 12C Controller control unit 13 SRAM
14A, 14B Correction circuit 15 NAND control unit 16 Correctability calculation unit 41-43 Error correction device 51-53 Memory system

Claims (5)

An error correction device that performs error correction at the time of reading from a semiconductor memory storing user data and initial syndrome in address units,
A correction circuit that executes a bit error correction process for correcting the bit error in the correction target data including the correction syndrome and obtaining corrected data using the correction syndrome, the correction circuit including the correction target data; It can be corrected when the number of bit errors is within the correctable number of bits,
A temporary storage unit for storing the second syndrome in association with the address;
The read data including the user data and the initial syndrome obtained from the semiconductor memory in an address unit is fetched, and the data correction read processing including the bit error correction processing by the correction circuit is executed and controlled. And a control unit to obtain,
The data correction read processing is
(a) In a normal state, the read data is the correction target data, the initial syndrome is the correction syndrome, the correction circuit performs the bit error correction process, and the data included in the corrected data is the data A step of setting the read data after correction;
(b) When the number of bit errors of the read data reaches a warning reference bit number that is set in advance with a value equal to or less than the correctable bit number, the read data is used as a syndrome generation target data, and the correction is performed. Causing the circuit to generate the second syndrome for the syndrome generation target data, and storing the second syndrome in the temporary storage unit in association with an address at the time of reading the read data;
(c) determining whether there is an abnormal state of the read data;
(d) performing a two-stage correction process when an abnormal state of the read data is determined in the step (c),
The step (d)
(d-1) The read error and the second syndrome stored in the temporary storage unit are used as the correction target data, the second syndrome is used as the correction syndrome, and the bit error correction process is performed in the correction circuit. And executing the user data portion in the corrected data as corrected user data and the initial syndrome portion as a corrected initial syndrome,
(d-2) The corrected user data and the corrected initial syndrome are set as the correction target data, the corrected initial syndrome is set as the correcting syndrome, and the correction circuit executes the bit error correction processing, and is included in the corrected data. The data to be read data after correction,
Error correction device. The error correction device according to claim 1,
A bit error detection circuit that outputs a large amount of bit error determination information serving as a determination criterion as to whether or not the read data has generated a large number of bit errors that are bit errors exceeding the correctable number of bits;
The control unit, in the step (c), determines the presence or absence of an abnormal state of the read data based on the mass bit error determination information.
Error correction device. The error correction device according to claim 2,
The correction circuit further outputs error bit information indicating the number of error bits generated in the correction target data during execution of the bit error correction processing as the mass bit error determination information, and the error bit information is the mass bit error Indicate at least part of the number of error bits in error,
The bit error detection circuit includes the correction circuit;
In the step (c), the control unit determines an abnormal state of the read data based on the error bit information, and thereafter fixes the determination in the read data in the abnormal state.
Error correction device. The error correction device according to claim 2,
In addition to the user data and the initial syndrome, the semiconductor memory further stores an error detection code, and the error detection code is a code obtained by performing a code generation calculation process on the user data, The read data includes the error detection code,
The control unit uses an error correction code portion in the corrected data at the time of execution of the step (d-1) as a correction error detection code, and the correction target data at the time of execution of the step (d-2) Including error detection code,
The bit error detection circuit includes a correction availability calculation unit that generates the comparison error detection code by performing the code generation calculation process on the operation target data,
Step (c)
(c-1) The read data is the correction target data, the initial syndrome is the correction syndrome, the correction circuit is caused to execute the bit error correction process, and the corrected data is obtained;
(c-2) Using the user data portion in the corrected data obtained in step (c-1) as the operation target data, causing the correction enable / disable calculation unit to execute the code generation calculation process, and for the comparison Obtaining an error detection code as the mass bit error determination information;
(c-3) Based on the comparison result between the error detection code in the corrected data obtained in step (c-1) and the comparison error detection code obtained in step (c-2), Determining whether there is an abnormal state of the read data,
Error correction device. The error correction device according to claim 1,
Step (c)
Based on the presence / absence of registration of corresponding address information in the temporary storage unit, the presence / absence of an abnormal state of the read data is determined,
Error correction device.

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