CN105471574A - Lorenz hyperchaotic system circuit with different feedbacks and convenient ultimate boundary estimation - Google Patents
Lorenz hyperchaotic system circuit with different feedbacks and convenient ultimate boundary estimation Download PDFInfo
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- CN105471574A CN105471574A CN201610005319.2A CN201610005319A CN105471574A CN 105471574 A CN105471574 A CN 105471574A CN 201610005319 A CN201610005319 A CN 201610005319A CN 105471574 A CN105471574 A CN 105471574A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/001—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using chaotic signals
Abstract
The invention provides a Lorenz hyperchaotic system circuit with different feedbacks and convenient ultimate boundary estimation. An operational amplifier U1, an operational amplifier U2, a resistor and a capacitor are used for realizing addition and integral operation, an operational amplifier U3 and the resistor are used for realizing inverse operation, a multiplier U4 and a multiplier U5 are used for realizing multiplication in the system, the operational amplifiers U1, U2, U3 and U6 adopt LF347BN, the multipliers U4 and U5 adopt AD633JN, and the selector adopts DG409; on the basis of the Lorenz hyperchaotic system, the invention designs a Lorenz hyperchaotic system construction method and a circuit construction method with different feedbacks and convenient ultimate boundary estimation and designs an analog circuit to realize the chaotic system, so as to provide a new hyperchaotic system signal source for the synchronization and control of chaos.
Description
Technical field
The present invention relates to a kind of chaos system and circuit, particularly a kind ofly feed back the different Lorenz type hyperchaotic system circuit be convenient to ultimate boundary and estimated.
Background technology
The control in chaos is estimated on the border of hyperchaotic system, the synchronous engineer applied aspect that waits has great importance, current, construct the method for four dimension ultra-chaos mainly on the basis of three-dimensional chaotic system, increase one dimension and form four-dimensional hyperchaotic system, but the hyperchaotic system formed is not easy to carry out ultimate boundary estimation, the feature that the hyperchaotic system that can carry out ultimate boundary estimation has is: the characteristic element of Jacobian matrix leading diagonal is all negative value, the characteristic element that the hyperchaotic system of the present invention's structure has a Jacobian matrix leading diagonal is all the feature of negative value, ultimate boundary estimation can be carried out, this is for the control of hyperchaos, synchronous etc. have important job applications prospect.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind ofly feeds back the different Lorenz type hyperchaotic system circuit be convenient to ultimate boundary and estimated:
1. the Lorenz type hyperchaotic system construction method being convenient to ultimate boundary estimation that feedback is different, is characterized in that, comprise the following steps:
(1) Lorenz type chaos system i is:
In formula, x, y, z are state variable, and a, b, c, d are system parameters;
(2) on chaos system i, one dimension variable w is increased:
dw/dt＝-ky-rwk＝5,r＝0.1ii
In formula, w is state variable, and k, r are system parameters;
(3) using variable i i as unidimensional system variable, be added on first equation of Lorenz type chaos system i, obtain a kind of be convenient to ultimate boundary estimate Lorenz type hyperchaotic system iii be:
In formula, x, y, z, w are state variable, parameter value a=12, b=23, c=1, d=2.1, k=5, r=0.1;
(4) using variable i i as unidimensional system variable, be added on second equation of Lorenz type chaos system i, obtain a kind of be convenient to ultimate boundary estimate Lorenz type hyperchaotic system iv be:
In formula, x, y, z, w are state variable, parameter value a=12, b=23, c=1, d=2.1, k=5, r=0.1;
(5) constructing choice function v and vi by a kind of for iii and iv composition Lorenz type switching hyperchaotic system vii being convenient to ultimate boundary estimation is:
In formula, x, y, z, w are state variable, and f (x), f (-x) are switching functions, and a, b, c, d, k, r are system parameters;
(6) based on the circuit of system vii structure, utilize operational amplifier U1, operational amplifier U2 and resistance, electric capacity realizes addition and integral operation, operational amplifier U3 and resistance is utilized to realize anti-phase computing, multiplier U4 and multiplier U5 realizes the multiplying in system, described operational amplifier U1 concatenation operation amplifier U3, operational amplifier U6 and multiplier U5, described operational amplifier U2 connects multiplier U4 and operational amplifier U3, described operational amplifier U3 concatenation operation amplifier U1, operational amplifier U2, operational amplifier U6 and multiplier U4, described multiplier U4 concatenation operation amplifier U1, described multiplier U5 concatenation operation amplifier U2, described operational amplifier U6 connects selector U7, described selector U7 concatenation operation amplifier U1, and described operational amplifier U1, U2, U3 and U6 adopt LF347BN, and described multiplier U4 and U5 adopts AD633JN, and described selector adopts ADG409,
1st pin of described operational amplifier U1 is connected with the 6th pin of operational amplifier U1 by resistance R2, 2nd pin of operational amplifier U1 is connected with the 1st pin of operational amplifier U1 by resistance Ry, 3rd pin of operational amplifier U1, 5th pin, 10th pin, 12nd pin ground connection, 4th pin of operational amplifier U1 meets VCC, 11st pin of operational amplifier U1 meets VEE, 6th pin of operational amplifier U1 is connected with the 7th pin of operational amplifier U1 by electric capacity Cy, 7th pin of operational amplifier U1 is connected with the 13rd pin of operational amplifier U1 by resistance Rx2, 7th pin of operational amplifier U1 connects with the 1st pin of multiplier U5, 7th pin of operational amplifier U1 is connected with the 6th pin of operational amplifier U3 by resistance R7, 7th pin of operational amplifier U1 connects and exports y, 8th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by electric capacity Cx, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance Ry1, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U3 by resistance R5, 8th pin of operational amplifier U1 connects with the 3rd pin of multiplier U5, 8th pin of operational amplifier U1 connects with the 2nd pin of operational amplifier U6, 8th pin of operational amplifier U1 connects and exports x, 13rd pin of operational amplifier U1 is connected with the 14th pin of operational amplifier U1 by resistance Rx, 14th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by resistance R1,
1st pin of described operational amplifier U2 is connected with the 6th pin of operational amplifier U2 by resistance R4, 2nd pin of operational amplifier U2 is connected with the 1st pin of operational amplifier U2 by resistance Rw, 3rd pin of operational amplifier U2, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U2 is connected with the 7th pin of operational amplifier U2 by electric capacity Cw, 7th pin of operational amplifier U2 connects with the 4th pin of selector U7 and the 12nd pin, 7th pin of operational amplifier U2 is connected with the 13rd pin of operational amplifier U3 by resistance R11, 7th pin of operational amplifier U2 connects and exports w, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by electric capacity Cz, 8th pin of operational amplifier U2 connects with the 3rd pin of multiplier U4, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U3 by resistance R9, 8th pin of operational amplifier U2 connects and exports z, 13rd pin of operational amplifier U2 is connected with the 14th pin of operational amplifier U2 by resistance Rz, 14th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by resistance R3,
1st pin of described operational amplifier U3 is connected with the 13rd pin of operational amplifier U1 by resistance Rx1, 1st pin of operational amplifier U3 connects with the 1st pin of multiplier U4, 2nd pin of operational amplifier U3 is connected with the 1st pin of operational amplifier U3 by resistance R6, 3rd pin of operational amplifier U3, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U3 is connected with the 7th pin of operational amplifier U3 by resistance R8, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U1 by resistance Ry2, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw1, 8th pin of operational amplifier U3 is connected with the 9th pin of operational amplifier U3 by resistance R10, 8th pin of operational amplifier U3 is connected with the 13rd pin of operational amplifier U2 by resistance Rz2, 13rd pin of operational amplifier U3 is connected with the 14th pin of operational amplifier U3 by resistance R12, 14th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw2,
2nd pin of described multiplier U4, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, and the 7th pin connects the 2nd pin of operational amplifier U1 by resistance Ry3, and the 8th pin meets VCC;
2nd pin of described multiplier U5, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, and the 7th pin connects operational amplifier U2 the 13rd pin by resistance Rz1, and the 8th pin meets VCC;
1st pin of described operational amplifier U6 is connected with the 1st pin of selector U7 by resistance R13,1st pin of operational amplifier U6 is connected with ground by resistance R13 and resistance R14,3rd pin of operational amplifier U6, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, and operational amplifier U6 the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled;
2nd pin and the 14th pin of described selector U7 meet VCC, 3rd pin of selector U7 meets VEE, 15th pin of selector U7 and the 16th pin ground connection, 8th pin of selector U7 is connected with the 2nd pin of operational amplifier U2 by resistance Rw1, and the 6th pin of selector U7, the 7th pin, the 9th pin, the 10th pin, the 11st pin, the 12nd pin, the 13rd pin are unsettled.
2. the Lorenz type hyperchaotic system circuit being convenient to ultimate boundary estimation that a feedback is different, it is characterized in that, utilize operational amplifier U1, operational amplifier U2 and resistance, electric capacity realizes addition and integral operation, operational amplifier U3 and resistance is utilized to realize anti-phase computing, multiplier U4 and multiplier U5 realizes the multiplying in system, described operational amplifier U1 concatenation operation amplifier U3, operational amplifier U6 and multiplier U5, described operational amplifier U2 connects multiplier U4 and operational amplifier U3, described operational amplifier U3 concatenation operation amplifier U1, operational amplifier U2, operational amplifier U6 and multiplier U4, described multiplier U4 concatenation operation amplifier U1, described multiplier U5 concatenation operation amplifier U2, described operational amplifier U6 connects selector U7, described selector U7 concatenation operation amplifier U1, and described operational amplifier U1, U2, U3 and U6 adopt LF347BN, and described multiplier U4 and U5 adopts AD633JN, and described selector adopts ADG409,
1st pin of described operational amplifier U1 is connected with the 6th pin of operational amplifier U1 by resistance R2, 2nd pin of operational amplifier U1 is connected with the 1st pin of operational amplifier U1 by resistance Ry, 3rd pin of operational amplifier U1, 5th pin, 10th pin, 12nd pin ground connection, 4th pin of operational amplifier U1 meets VCC, 11st pin of operational amplifier U1 meets VEE, 6th pin of operational amplifier U1 is connected with the 7th pin of operational amplifier U1 by electric capacity Cy, 7th pin of operational amplifier U1 is connected with the 13rd pin of operational amplifier U1 by resistance Rx2, 7th pin of operational amplifier U1 connects with the 1st pin of multiplier U5, 7th pin of operational amplifier U1 is connected with the 6th pin of operational amplifier U3 by resistance R7, 7th pin of operational amplifier U1 connects and exports y, 8th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by electric capacity Cx, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance Ry1, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U3 by resistance R5, 8th pin of operational amplifier U1 connects with the 3rd pin of multiplier U5, 8th pin of operational amplifier U1 connects with the 2nd pin of operational amplifier U6, 8th pin of operational amplifier U1 connects and exports x, 13rd pin of operational amplifier U1 is connected with the 14th pin of operational amplifier U1 by resistance Rx, 14th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by resistance R1,
1st pin of described operational amplifier U2 is connected with the 6th pin of operational amplifier U2 by resistance R4, 2nd pin of operational amplifier U2 is connected with the 1st pin of operational amplifier U2 by resistance Rw, 3rd pin of operational amplifier U2, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U2 is connected with the 7th pin of operational amplifier U2 by electric capacity Cw, 7th pin of operational amplifier U2 connects with the 4th pin of selector U7 and the 12nd pin, 7th pin of operational amplifier U2 is connected with the 13rd pin of operational amplifier U3 by resistance R11, 7th pin of operational amplifier U2 connects and exports w, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by electric capacity Cz, 8th pin of operational amplifier U2 connects with the 3rd pin of multiplier U4, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U3 by resistance R9, 8th pin of operational amplifier U2 connects and exports z, 13rd pin of operational amplifier U2 is connected with the 14th pin of operational amplifier U2 by resistance Rz, 14th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by resistance R3,
1st pin of described operational amplifier U3 is connected with the 13rd pin of operational amplifier U1 by resistance Rx1, 1st pin of operational amplifier U3 connects with the 1st pin of multiplier U4, 2nd pin of operational amplifier U3 is connected with the 1st pin of operational amplifier U3 by resistance R6, 3rd pin of operational amplifier U3, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U3 is connected with the 7th pin of operational amplifier U3 by resistance R8, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U1 by resistance Ry2, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw1, 8th pin of operational amplifier U3 is connected with the 9th pin of operational amplifier U3 by resistance R10, 8th pin of operational amplifier U3 is connected with the 13rd pin of operational amplifier U2 by resistance Rz2, 13rd pin of operational amplifier U3 is connected with the 14th pin of operational amplifier U3 by resistance R12, 14th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw2,
2nd pin of described multiplier U4, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, and the 7th pin connects the 2nd pin of operational amplifier U1 by resistance Ry3, and the 8th pin meets VCC;
2nd pin of described multiplier U5, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, and the 7th pin connects operational amplifier U2 the 13rd pin by resistance Rz1, and the 8th pin meets VCC;
1st pin of described operational amplifier U6 is connected with the 1st pin of selector U7 by resistance R13,1st pin of operational amplifier U6 is connected with ground by resistance R13 and resistance R14,3rd pin of operational amplifier U6, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, and operational amplifier U6 the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled;
2nd pin and the 14th pin of described selector U7 meet VCC, 3rd pin of selector U7 meets VEE, 15th pin of selector U7 and the 16th pin ground connection, 8th pin of selector U7 is connected with the 2nd pin of operational amplifier U2 by resistance Rw1, and the 6th pin of selector U7, the 7th pin, the 9th pin, the 10th pin, the 11st pin, the 12nd pin, the 13rd pin are unsettled.
Beneficial effect: the present invention is on the basis of Lorenz type chaos system, devise a kind of feedback different to be convenient to Lorenz type hyperchaotic system construction method that ultimate boundary estimates and to design an analog circuit carry out realizing this chaos system, for the synchronous of chaos and control to provide new hyperchaotic system signal source.
Accompanying drawing explanation
Fig. 1 is the circuit connection structure schematic diagram of the preferred embodiment of the present invention.
Fig. 2 is the actual connection layout of circuit of multiplier U4 and operational amplifier U1.
Fig. 3 is the actual connection layout of circuit of operational amplifier U3.
Fig. 4 is the actual connection layout of circuit of multiplier U5 and operational amplifier U2.
Fig. 5 is the actual connection layout of circuit of selector U7 and operational amplifier U6.
Embodiment
Below in conjunction with accompanying drawing and preferred embodiment, the present invention is further described in detail, see Fig. 1-Fig. 5.
1. the Lorenz type hyperchaotic system construction method being convenient to ultimate boundary estimation that feedback is different, is characterized in that, comprise the following steps:
(1) Lorenz type chaos system i is:
In formula, x, y, z are state variable, and a, b, c, d are system parameters;
(2) on chaos system i, one dimension variable w is increased:
dw/dt＝-ky-rwk＝5,r＝0.1ii
In formula, w is state variable, and k, r are system parameters;
(3) using variable i i as unidimensional system variable, be added on first equation of Lorenz type chaos system i, obtain a kind of be convenient to ultimate boundary estimate Lorenz type hyperchaotic system iii be:
In formula, x, y, z, w are state variable, parameter value a=12, b=23, c=1, d=2.1, k=5, r=0.1;
(4) using variable i i as unidimensional system variable, be added on second equation of Lorenz type chaos system i, obtain a kind of be convenient to ultimate boundary estimate Lorenz type hyperchaotic system iv be:
In formula, x, y, z, w are state variable, parameter value a=12, b=23, c=1, d=2.1, k=5, r=0.1;
(5) constructing choice function v and vi by a kind of for iii and iv composition Lorenz type switching hyperchaotic system vii being convenient to ultimate boundary estimation is:
In formula, x, y, z, w are state variable, and f (x), f (-x) are switching functions, and a, b, c, d, k, r are system parameters;
(6) based on the circuit of system vii structure, utilize operational amplifier U1, operational amplifier U2 and resistance, electric capacity realizes addition and integral operation, operational amplifier U3 and resistance is utilized to realize anti-phase computing, multiplier U4 and multiplier U5 realizes the multiplying in system, described operational amplifier U1 concatenation operation amplifier U3, operational amplifier U6 and multiplier U5, described operational amplifier U2 connects multiplier U4 and operational amplifier U3, described operational amplifier U3 concatenation operation amplifier U1, operational amplifier U2, operational amplifier U6 and multiplier U4, described multiplier U4 concatenation operation amplifier U1, described multiplier U5 concatenation operation amplifier U2, described operational amplifier U6 connects selector U7, described selector U7 concatenation operation amplifier U1, and described operational amplifier U1, U2, U3 and U6 adopt LF347BN, and described multiplier U4 and U5 adopts AD633JN, and described selector adopts ADG409,
1st pin of described operational amplifier U1 is connected with the 6th pin of operational amplifier U1 by resistance R2, 2nd pin of operational amplifier U1 is connected with the 1st pin of operational amplifier U1 by resistance Ry, 3rd pin of operational amplifier U1, 5th pin, 10th pin, 12nd pin ground connection, 4th pin of operational amplifier U1 meets VCC, 11st pin of operational amplifier U1 meets VEE, 6th pin of operational amplifier U1 is connected with the 7th pin of operational amplifier U1 by electric capacity Cy, 7th pin of operational amplifier U1 is connected with the 13rd pin of operational amplifier U1 by resistance Rx2, 7th pin of operational amplifier U1 connects with the 1st pin of multiplier U5, 7th pin of operational amplifier U1 is connected with the 6th pin of operational amplifier U3 by resistance R7, 7th pin of operational amplifier U1 connects and exports y, 8th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by electric capacity Cx, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance Ry1, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U3 by resistance R5, 8th pin of operational amplifier U1 connects with the 3rd pin of multiplier U5, 8th pin of operational amplifier U1 connects with the 2nd pin of operational amplifier U6, 8th pin of operational amplifier U1 connects and exports x, 13rd pin of operational amplifier U1 is connected with the 14th pin of operational amplifier U1 by resistance Rx, 14th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by resistance R1,
1st pin of described operational amplifier U2 is connected with the 6th pin of operational amplifier U2 by resistance R4, 2nd pin of operational amplifier U2 is connected with the 1st pin of operational amplifier U2 by resistance Rw, 3rd pin of operational amplifier U2, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U2 is connected with the 7th pin of operational amplifier U2 by electric capacity Cw, 7th pin of operational amplifier U2 connects with the 4th pin of selector U7 and the 12nd pin, 7th pin of operational amplifier U2 is connected with the 13rd pin of operational amplifier U3 by resistance R11, 7th pin of operational amplifier U2 connects and exports w, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by electric capacity Cz, 8th pin of operational amplifier U2 connects with the 3rd pin of multiplier U4, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U3 by resistance R9, 8th pin of operational amplifier U2 connects and exports z, 13rd pin of operational amplifier U2 is connected with the 14th pin of operational amplifier U2 by resistance Rz, 14th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by resistance R3,
1st pin of described operational amplifier U3 is connected with the 13rd pin of operational amplifier U1 by resistance Rx1, 1st pin of operational amplifier U3 connects with the 1st pin of multiplier U4, 2nd pin of operational amplifier U3 is connected with the 1st pin of operational amplifier U3 by resistance R6, 3rd pin of operational amplifier U3, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U3 is connected with the 7th pin of operational amplifier U3 by resistance R8, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U1 by resistance Ry2, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw1, 8th pin of operational amplifier U3 is connected with the 9th pin of operational amplifier U3 by resistance R10, 8th pin of operational amplifier U3 is connected with the 13rd pin of operational amplifier U2 by resistance Rz2, 13rd pin of operational amplifier U3 is connected with the 14th pin of operational amplifier U3 by resistance R12, 14th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw2,
2nd pin of described multiplier U4, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, and the 7th pin connects the 2nd pin of operational amplifier U1 by resistance Ry3, and the 8th pin meets VCC;
2nd pin of described multiplier U5, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, and the 7th pin connects operational amplifier U2 the 13rd pin by resistance Rz1, and the 8th pin meets VCC;
1st pin of described operational amplifier U6 is connected with the 1st pin of selector U7 by resistance R13,1st pin of operational amplifier U6 is connected with ground by resistance R13 and resistance R14,3rd pin of operational amplifier U6, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, and operational amplifier U6 the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled;
2nd pin and the 14th pin of described selector U7 meet VCC, 3rd pin of selector U7 meets VEE, 15th pin of selector U7 and the 16th pin ground connection, 8th pin of selector U7 is connected with the 2nd pin of operational amplifier U2 by resistance Rw1, and the 6th pin of selector U7, the 7th pin, the 9th pin, the 10th pin, the 11st pin, the 12nd pin, the 13rd pin are unsettled.
2. the Lorenz type hyperchaotic system circuit being convenient to ultimate boundary estimation that a feedback is different, it is characterized in that, utilize operational amplifier U1, operational amplifier U2 and resistance, electric capacity realizes addition and integral operation, operational amplifier U3 and resistance is utilized to realize anti-phase computing, multiplier U4 and multiplier U5 realizes the multiplying in system, described operational amplifier U1 concatenation operation amplifier U3, operational amplifier U6 and multiplier U5, described operational amplifier U2 connects multiplier U4 and operational amplifier U3, described operational amplifier U3 concatenation operation amplifier U1, operational amplifier U2, operational amplifier U6 and multiplier U4, described multiplier U4 concatenation operation amplifier U1, described multiplier U5 concatenation operation amplifier U2, described operational amplifier U6 connects selector U7, described selector U7 concatenation operation amplifier U1, and described operational amplifier U1, U2, U3 and U6 adopt LF347BN, and described multiplier U4 and U5 adopts AD633JN, and described selector adopts ADG409,
1st pin of described operational amplifier U1 is connected with the 6th pin of operational amplifier U1 by resistance R2, 2nd pin of operational amplifier U1 is connected with the 1st pin of operational amplifier U1 by resistance Ry, 3rd pin of operational amplifier U1, 5th pin, 10th pin, 12nd pin ground connection, 4th pin of operational amplifier U1 meets VCC, 11st pin of operational amplifier U1 meets VEE, 6th pin of operational amplifier U1 is connected with the 7th pin of operational amplifier U1 by electric capacity Cy, 7th pin of operational amplifier U1 is connected with the 13rd pin of operational amplifier U1 by resistance Rx2, 7th pin of operational amplifier U1 connects with the 1st pin of multiplier U5, 7th pin of operational amplifier U1 is connected with the 6th pin of operational amplifier U3 by resistance R7, 7th pin of operational amplifier U1 connects and exports y, 8th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by electric capacity Cx, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance Ry1, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U3 by resistance R5, 8th pin of operational amplifier U1 connects with the 3rd pin of multiplier U5, 8th pin of operational amplifier U1 connects with the 2nd pin of operational amplifier U6, 8th pin of operational amplifier U1 connects and exports x, 13rd pin of operational amplifier U1 is connected with the 14th pin of operational amplifier U1 by resistance Rx, 14th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by resistance R1,
1st pin of described operational amplifier U2 is connected with the 6th pin of operational amplifier U2 by resistance R4, 2nd pin of operational amplifier U2 is connected with the 1st pin of operational amplifier U2 by resistance Rw, 3rd pin of operational amplifier U2, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U2 is connected with the 7th pin of operational amplifier U2 by electric capacity Cw, 7th pin of operational amplifier U2 connects with the 4th pin of selector U7 and the 12nd pin, 7th pin of operational amplifier U2 is connected with the 13rd pin of operational amplifier U3 by resistance R11, 7th pin of operational amplifier U2 connects and exports w, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by electric capacity Cz, 8th pin of operational amplifier U2 connects with the 3rd pin of multiplier U4, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U3 by resistance R9, 8th pin of operational amplifier U2 connects and exports z, 13rd pin of operational amplifier U2 is connected with the 14th pin of operational amplifier U2 by resistance Rz, 14th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by resistance R3,
1st pin of described operational amplifier U3 is connected with the 13rd pin of operational amplifier U1 by resistance Rx1, 1st pin of operational amplifier U3 connects with the 1st pin of multiplier U4, 2nd pin of operational amplifier U3 is connected with the 1st pin of operational amplifier U3 by resistance R6, 3rd pin of operational amplifier U3, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U3 is connected with the 7th pin of operational amplifier U3 by resistance R8, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U1 by resistance Ry2, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw1, 8th pin of operational amplifier U3 is connected with the 9th pin of operational amplifier U3 by resistance R10, 8th pin of operational amplifier U3 is connected with the 13rd pin of operational amplifier U2 by resistance Rz2, 13rd pin of operational amplifier U3 is connected with the 14th pin of operational amplifier U3 by resistance R12, 14th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw2,
2nd pin of described multiplier U4, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, and the 7th pin connects the 2nd pin of operational amplifier U1 by resistance Ry3, and the 8th pin meets VCC;
2nd pin of described multiplier U5, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, and the 7th pin connects operational amplifier U2 the 13rd pin by resistance Rz1, and the 8th pin meets VCC;
1st pin of described operational amplifier U6 is connected with the 1st pin of selector U7 by resistance R13,1st pin of operational amplifier U6 is connected with ground by resistance R13 and resistance R14,3rd pin of operational amplifier U6, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, and operational amplifier U6 the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled;
2nd pin and the 14th pin of described selector U7 meet VCC, 3rd pin of selector U7 meets VEE, 15th pin of selector U7 and the 16th pin ground connection, 8th pin of selector U7 is connected with the 2nd pin of operational amplifier U2 by resistance Rw1, and the 6th pin of selector U7, the 7th pin, the 9th pin, the 10th pin, the 11st pin, the 12nd pin, the 13rd pin are unsettled.
Certainly, above-mentioned explanation is not to the restriction of invention, and the present invention is also not limited only to above-mentioned citing, and the change that those skilled in the art make in essential scope of the present invention, remodeling, interpolation or replacement, also belong to protection scope of the present invention.
Claims (1)
1. the Lorenz type hyperchaotic system circuit being convenient to ultimate boundary estimation that a feedback is different, it is characterized in that, utilize operational amplifier U1, operational amplifier U2 and resistance, electric capacity realizes addition and integral operation, operational amplifier U3 and resistance is utilized to realize anti-phase computing, multiplier U4 and multiplier U5 realizes the multiplying in system, described operational amplifier U1 concatenation operation amplifier U3, operational amplifier U6 and multiplier U5, described operational amplifier U2 connects multiplier U4 and operational amplifier U3, described operational amplifier U3 concatenation operation amplifier U1, operational amplifier U2, operational amplifier U6 and multiplier U4, described multiplier U4 concatenation operation amplifier U1, described multiplier U5 concatenation operation amplifier U2, described operational amplifier U6 connects selector U7, described selector U7 concatenation operation amplifier U1, and described operational amplifier U1, U2, U3 and U6 adopt LF347BN, and described multiplier U4 and U5 adopts AD633JN, and described selector adopts ADG409,
1st pin of described operational amplifier U1 is connected with the 6th pin of operational amplifier U1 by resistance R2, 2nd pin of operational amplifier U1 is connected with the 1st pin of operational amplifier U1 by resistance Ry, 3rd pin of operational amplifier U1, 5th pin, 10th pin, 12nd pin ground connection, 4th pin of operational amplifier U1 meets VCC, 11st pin of operational amplifier U1 meets VEE, 6th pin of operational amplifier U1 is connected with the 7th pin of operational amplifier U1 by electric capacity Cy, 7th pin of operational amplifier U1 is connected with the 13rd pin of operational amplifier U1 by resistance Rx2, 7th pin of operational amplifier U1 connects with the 1st pin of multiplier U5, 7th pin of operational amplifier U1 is connected with the 6th pin of operational amplifier U3 by resistance R7, 7th pin of operational amplifier U1 connects and exports y, 8th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by electric capacity Cx, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U1 by resistance Ry1, 8th pin of operational amplifier U1 is connected with the 2nd pin of operational amplifier U3 by resistance R5, 8th pin of operational amplifier U1 connects with the 3rd pin of multiplier U5, 8th pin of operational amplifier U1 connects with the 2nd pin of operational amplifier U6, 8th pin of operational amplifier U1 connects and exports x, 13rd pin of operational amplifier U1 is connected with the 14th pin of operational amplifier U1 by resistance Rx, 14th pin of operational amplifier U1 is connected with the 9th pin of operational amplifier U1 by resistance R1,
1st pin of described operational amplifier U2 is connected with the 6th pin of operational amplifier U2 by resistance R4, 2nd pin of operational amplifier U2 is connected with the 1st pin of operational amplifier U2 by resistance Rw, 3rd pin of operational amplifier U2, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U2 is connected with the 7th pin of operational amplifier U2 by electric capacity Cw, 7th pin of operational amplifier U2 connects with the 4th pin of selector U7 and the 12nd pin, 7th pin of operational amplifier U2 is connected with the 13rd pin of operational amplifier U3 by resistance R11, 7th pin of operational amplifier U2 connects and exports w, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by electric capacity Cz, 8th pin of operational amplifier U2 connects with the 3rd pin of multiplier U4, 8th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U3 by resistance R9, 8th pin of operational amplifier U2 connects and exports z, 13rd pin of operational amplifier U2 is connected with the 14th pin of operational amplifier U2 by resistance Rz, 14th pin of operational amplifier U2 is connected with the 9th pin of operational amplifier U2 by resistance R3,
1st pin of described operational amplifier U3 is connected with the 13rd pin of operational amplifier U1 by resistance Rx1, 1st pin of operational amplifier U3 connects with the 1st pin of multiplier U4, 2nd pin of operational amplifier U3 is connected with the 1st pin of operational amplifier U3 by resistance R6, 3rd pin of operational amplifier U3, 5th pin, 10th pin, 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin of operational amplifier U3 is connected with the 7th pin of operational amplifier U3 by resistance R8, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U1 by resistance Ry2, 7th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw1, 8th pin of operational amplifier U3 is connected with the 9th pin of operational amplifier U3 by resistance R10, 8th pin of operational amplifier U3 is connected with the 13rd pin of operational amplifier U2 by resistance Rz2, 13rd pin of operational amplifier U3 is connected with the 14th pin of operational amplifier U3 by resistance R12, 14th pin of operational amplifier U3 is connected with the 2nd pin of operational amplifier U2 by resistance Rw2,
2nd pin of described multiplier U4, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, and the 7th pin connects the 2nd pin of operational amplifier U1 by resistance Ry3, and the 8th pin meets VCC;
2nd pin of described multiplier U5, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, and the 7th pin connects operational amplifier U2 the 13rd pin by resistance Rz1, and the 8th pin meets VCC;
1st pin of described operational amplifier U6 is connected with the 1st pin of selector U7 by resistance R13,1st pin of operational amplifier U6 is connected with ground by resistance R13 and resistance R14,3rd pin of operational amplifier U6, the 5th pin, the 10th pin, the 12nd pin ground connection, 4th pin meets VCC, 11st pin meets VEE, and operational amplifier U6 the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled;
2nd pin and the 14th pin of described selector U7 meet VCC, 3rd pin of selector U7 meets VEE, 15th pin of selector U7 and the 16th pin ground connection, 8th pin of selector U7 is connected with the 2nd pin of operational amplifier U2 by resistance Rw1, and the 6th pin of selector U7, the 7th pin, the 9th pin, the 10th pin, the 11st pin, the 12nd pin, the 13rd pin are unsettled.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610005319.2A CN105471574B (en) | 2015-05-27 | 2015-05-27 | It is a kind of to feed back the different Lorenz type hyperchaotic system circuits convenient for ultimate boundary estimation |
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| CN201510279462.6A CN104836658B (en) | 2015-05-27 | 2015-05-27 | A kind of feedback different is easy to the Lorenz type hyperchaotic system construction method that ultimate boundary is estimated |
| CN201610005319.2A CN105471574B (en) | 2015-05-27 | 2015-05-27 | It is a kind of to feed back the different Lorenz type hyperchaotic system circuits convenient for ultimate boundary estimation |
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| CN201510279462.6A Division CN104836658B (en) | 2015-05-27 | 2015-05-27 | A kind of feedback different is easy to the Lorenz type hyperchaotic system construction method that ultimate boundary is estimated |
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| CN201610005319.2A Expired - Fee Related CN105471574B (en) | 2015-05-27 | 2015-05-27 | It is a kind of to feed back the different Lorenz type hyperchaotic system circuits convenient for ultimate boundary estimation |
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| CN105117600A (en) * | 2015-08-26 | 2015-12-02 | 王晓红 | Five-term spherical quasi-periodic oscillation system and circuit |
| CN105160167A (en) * | 2015-08-26 | 2015-12-16 | 王晓红 | Spherical quasi-periodic oscillator and circuit |
| CN105243257A (en) * | 2015-08-26 | 2016-01-13 | 韩敬伟 | Five-quasi-periodic spherical oscillator and circuit |
| CN105119714A (en) * | 2015-09-09 | 2015-12-02 | 韩敬伟 | Self-adaptive synchronization method and circuit for Lorenz type hyper-chaotic system convenient for ultimate boundary estimation |
| CN105119710A (en) * | 2015-09-09 | 2015-12-02 | 王春梅 | Lorenz type hyper-chaotic system adaptive synchronization method and circuit beneficial to ultimate edge estimation |
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| US5680462A (en) * | 1995-08-07 | 1997-10-21 | Sandia Corporation | Information encoder/decoder using chaotic systems |
| CN102332976B (en) * | 2011-09-15 | 2013-11-06 | 江西理工大学 | Different-dimensional switchable chaotic system design method and circuit |
| CN103217901A (en) * | 2013-01-31 | 2013-07-24 | 王少夫 | Chaotic system tracking control method |
| CN103856317A (en) * | 2014-02-22 | 2014-06-11 | 滨州学院 | Method and circuit for switching classic Lorenz type chaotic system with different fractional orders |
| CN105530085B (en) * | 2014-08-30 | 2018-05-11 | 新昌县无痕文化有限公司 | Different feedback automatic switchover hyperchaotic system building methods and analog circuit based on L ü systems |
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| CN104836658B (en) | 2016-10-12 |
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