WO2016187739A1

WO2016187739A1 - Construction method for hyperchaotic lorenz system of different feedbacks and facilitating ultimate boundary estimation and circuit

Info

Publication number: WO2016187739A1
Application number: PCT/CN2015/000572
Authority: WO
Inventors: 王忠林
Original assignee: 王忠林
Priority date: 2015-05-27
Filing date: 2015-08-07
Publication date: 2016-12-01
Also published as: CN104836658A; CN104836658B; CN105471574B; CN105471574A

Abstract

Provided in the present invention are a construction method for a hyperchaotic Lorenz system of different feedbacks and facilitating ultimate boundary estimation. Operational amplifier U1, operational amplifier U2, a resistor, and a capacitor are utilized to implement addition and integration operations. Operational amplifier U3 and a resistor are utilized to implement an inverting operation. Multiplier U4 and multiplier U5 implement multiplication operations in the system. Operational amplifiers U1, U2, U3, and U6 employ LF347BN. Multipliers U4 and U5 employ AD633JN. The selector employs ADG409. The present invention designs, on the basis of a chaotic Lorenz system, the construction method for the hyperchaotic Lorenz system of different feedbacks and facilitating ultimate boundary estimation and a circuit construction method, also designs one analog circuit for implementing this chaotic system, and provides chaotic synchronization and control with a novel hyperchaotic signal source.

Description

Method and circuit for constructing Lorenz type hyperchaotic system with different feedback for ultimate boundary estimation

Technical field

The invention relates to a chaotic system and a circuit, in particular to a method and a circuit for constructing a Lorenz type hyperchaotic system with different feedbacks for facilitating ultimate boundary estimation.

Background technique

The boundary estimation of hyperchaotic systems is of great significance in the application of chaos control and synchronization. At present, the method of constructing four-dimensional hyperchaos is based on the three-dimensional chaotic system, adding one-dimensional four-dimensional hyperchaotic systems. The hyperchaotic system is not easy to perform ultimate boundary estimation. The hyperchaotic system that can perform ultimate boundary estimation has the characteristic that the characteristic elements of the main diagonal of the Jacobian matrix are all negative, and the hyperchaotic system constructed by the present invention has ya The characteristic elements of the main diagonal of the comparable matrix are all negative, and the ultimate boundary estimation can be performed. This has important application prospects for the control and synchronization of hyperchaos.

Summary of the invention

The technical problem to be solved by the present invention is to provide a method and circuit for constructing a Lorenz type hyperchaotic system with different feedback for the ultimate boundary estimation:

A method for constructing a Lorenz type hyperchaotic system with different feedback for the ultimate boundary estimation, characterized in that it comprises the following steps:

(1) The Lorenz type chaotic system i is:

Where x, y, and z are state variables, and a, b, c, and d are system parameters;

(2) Add a one-dimensional variable w to the chaotic system i:

Dw/dt=-ky-rw k=5, r=0.1 ii

Where w is the state variable and k, r are the system parameters;

(3) The variable ii is used as a one-dimensional system variable and added to the first equation of the Lorenz-type chaotic system i. A Lorenz-type hyperchaotic system iii that facilitates the final boundary estimation is obtained:

Where x, y, z, w are state variables, parameter values a = 12, b = 23, c = 1, d = 2.1, k = 5, r = 0.1;

(4) The variable ii is used as a one-dimensional system variable and added to the second equation of the Lorenz-type chaotic system i. A Lorenz-type hyperchaotic system iv that facilitates the final boundary estimation is obtained:

Where x, y, z, w are state variables, parameter values a = 12, 6 = 23, c = 1, d = 2.1, k = 5, r = 0.1;

(5) Construct a selection function v and vi to form iii and iv into a Lorenz-type switched hyperchaotic system vii for the ultimate boundary estimation:

Where x, y, z, w are state variables, f(x), f(-x) are switching functions, and a, b, c, d, k, r are system parameters;

(6) Based on the circuit constructed by the system vii, the addition and integration operations are realized by the operational amplifier U1, the operational amplifier U2, and the resistors and capacitors, and the inverse operation is realized by the operational amplifier U3 and the resistor, and the multiplier U4 and the multiplier U5 are implemented in the system. In the multiplication operation, the operational amplifier U1 is connected to an operational amplifier U3, an operational amplifier U6, and a multiplier U5. The operational amplifier U2 is connected to a multiplier U4 and an operational amplifier U3. The operational amplifier U3 is connected to the operational amplifier U1 and the operational amplifier U2. An amplifier U6 and a multiplier U4, the multiplier U4 is connected to an operational amplifier U1, the multiplier U5 is connected to an operational amplifier U2; the operational amplifier U6 is connected to a selector U7, and the selector U7 is connected to an operational amplifier U1, the operation The amplifiers U1, U2, U3 and U6 adopt LF347BN, the multipliers U4 and U5 adopt AD633JN, and the selector adopts ADG409;

The first pin of the operational amplifier U1 is connected to the sixth pin of the operational amplifier U1 via the resistor R2, and the second pin of the operational amplifier U1 is connected to the first pin of the operational amplifier U1 via the resistor Ry. The third pin, the fifth pin, the tenth pin, and the twelfth pin of U1 are grounded, the fourth pin of the operational amplifier U1 is connected to VCC, the eleventh pin of the operational amplifier U1 is connected to VEE, and the operational amplifier U1 is The 6 pin is connected to the 7th pin of the operational amplifier U1 through the capacitor Cy, and the 7th pin of the operational amplifier U1 is connected to the 13th pin of the operational amplifier U1 through the resistor Rx2. The seventh pin of the operational amplifier U1 is connected to the first pin of the multiplier U5, and the seventh pin of the operational amplifier U1 is connected to the sixth pin of the operational amplifier U3 via the resistor R7, and the operational amplifier U1 is connected. The 7-pin is connected to the output y. The 8th pin of the operational amplifier U1 is connected to the 9th pin of the operational amplifier U1 through the capacitor Cx. The 8th pin of the operational amplifier U1 passes through the resistor Ry1 and the second pin of the operational amplifier U1. When connected, the eighth pin of the operational amplifier U1 is connected to the second pin of the operational amplifier U3 through the resistor R5, and the eighth pin of the operational amplifier U1 is connected to the third pin of the multiplier U5, and the operational amplifier U1 is connected. The 8th pin is connected to the 2nd pin of the operational amplifier U6, the 8th pin of the operational amplifier U1 is connected to the output x, and the 13th pin of the operational amplifier U1 is connected to the 14th pin of the operational amplifier U1 through the resistor Rx. The 14th pin of the operational amplifier U1 is connected to the 9th pin of the operational amplifier U1 through the resistor R1;

The first pin of the operational amplifier U2 is connected to the sixth pin of the operational amplifier U2 via the resistor R4, and the second pin of the operational amplifier U2 is connected to the first pin of the operational amplifier U2 via the resistor Rw. The 3rd pin, the 5th pin, the 10th pin, and the 12th pin of U2 are grounded, the 4th pin is connected to VCC, the 11th pin is connected to VEE, and the 6th pin of the operational amplifier U2 is connected to the capacitor Cw. The 7th pin of the amplifier U2 is connected, the 7th pin of the operational amplifier U2 is connected to the 4th pin and the 12th pin of the selector U7, and the 7th pin of the operational amplifier U2 is connected to the operational amplifier U3 through the resistor R11. The 13th pin is connected, the 7th pin of the operational amplifier U2 is connected to the output w, the 8th pin of the operational amplifier U2 is connected to the 9th pin of the operational amplifier U2 through the capacitor Cz, and the 8th lead of the operational amplifier U2 The pin is connected to the third pin of the multiplier U4, the eighth pin of the operational amplifier U2 is connected to the ninth pin of the operational amplifier U3 through the resistor R9, and the eighth pin of the operational amplifier U2 is connected to the output z, the operational amplifier The 13th pin of U2 is connected to the 14th pin of the operational amplifier U2 through the resistor Rz, and the 14th pin of the operational amplifier U2 is passed. The resistor R3 is connected to the ninth pin of the operational amplifier U2;

The first pin of the operational amplifier U3 is connected to the 13th pin of the operational amplifier U1 via the resistor Rx1, and the first pin of the operational amplifier U3 is connected to the first pin of the multiplier U4, and the first amplifier of the operational amplifier U3 The 2 pin is connected to the first pin of the operational amplifier U3 through the resistor R6, and the third pin, the fifth pin, the tenth pin, and the twelfth pin of the operational amplifier U3 are grounded, and the fourth pin is connected to VCC. The 11th pin is connected to VEE, the 6th pin of the operational amplifier U3 is connected to the 7th pin of the operational amplifier U3 through the resistor R8, and the 7th pin of the operational amplifier U3 is connected to the second pin of the operational amplifier U1 through the resistor Ry2. When connected, the seventh pin of the operational amplifier U3 is connected to the second pin of the operational amplifier U2 via the resistor Rw1, and the eighth pin of the operational amplifier U3 is connected to the ninth pin of the operational amplifier U3 via the resistor R10. The 8th pin of the amplifier U3 is connected to the 13th pin of the operational amplifier U2 through the resistor Rz2, and the 13th pin of the operational amplifier U3 is connected to the 14th pin of the operational amplifier U3 via the resistor R12, and the operational amplifier U3 is connected. The 14 pin is connected to the second pin of the operational amplifier U2 through the resistor Rw2;

The second pin, the fourth pin, and the sixth pin of the multiplier U4 are grounded, and the fifth pin is connected to VEE, and the seventh lead The pin is connected to the second pin of the operational amplifier U1 through the resistor Ry3, and the eighth pin is connected to VCC;

The second pin, the fourth pin, and the sixth pin of the multiplier U5 are grounded, the fifth pin is connected to VEE, and the seventh pin is connected to the 13th pin and the eighth pin of the operational amplifier U2 through the resistor Rz1. Connected to VCC;

The first pin of the operational amplifier U6 is connected to the first pin of the selector U7 via the resistor R13, and the first pin of the operational amplifier U6 is connected to the ground through the resistor R13 and the resistor R14, and the third of the operational amplifier U6. Pin, 5th pin, 10th pin, 12th pin are grounded, the 4th pin is connected to VCC, the 11th pin is connected to VEE, and the operational amplifier U6 is 6th, 7th, and 8th. The 9th pin, the 12th pin, the 13th pin, and the 14th pin are left floating.

The second pin of the selector U7 and the 14th pin stage VCC, the third pin of the selector U7 is connected to VEE, the fifteenth pin and the thirteenth pin of the selector U7 are grounded, and the eighth of the selector U7 The pin is connected to the second pin of the operational amplifier U2 through the resistor Rw1, and the sixth, seventh, ninth, tenth, eleventh, and twelfth pins of the selector U7. The 13th pin is left floating.

2. A Lorenz-type hyperchaotic system circuit with different feedback for the ultimate boundary estimation, which is characterized in that the operational amplifier U1, the operational amplifier U2, and the resistors and capacitors are used for addition and integration operations, and the operational amplifier U3 and the resistor are used for inversion. Operation, multiplier U4 and multiplier U5 implement multiplication in the system, the operational amplifier U1 is connected to an operational amplifier U3, an operational amplifier U6 and a multiplier U5, which is connected to a multiplier U4 and an operational amplifier U3, The operational amplifier U3 is connected to the operational amplifier U1, the operational amplifier U2, the operational amplifier U6, and the multiplier U4. The multiplier U4 is connected to the operational amplifier U1, and the multiplier U5 is connected to the operational amplifier U2. The operational amplifier U6 is connected to the selector U7. The selector U7 is connected to the operational amplifier U1, the operational amplifiers U1, U2, U3 and U6 adopt LF347BN, the multipliers U4 and U5 adopt AD633JN, and the selector adopts ADG409;

The first pin of the operational amplifier U1 is connected to the sixth pin of the operational amplifier U1 via the resistor R2, and the second pin of the operational amplifier U1 is connected to the first pin of the operational amplifier U1 via the resistor Ry. The third pin, the fifth pin, the tenth pin, and the twelfth pin of U1 are grounded, the fourth pin of the operational amplifier U1 is connected to VCC, the eleventh pin of the operational amplifier U1 is connected to VEE, and the operational amplifier U1 is The 6-pin is connected to the 7th pin of the operational amplifier U1 through the capacitor Cy. The 7th pin of the operational amplifier U1 is connected to the 13th pin of the operational amplifier U1 through the resistor Rx2, and the 7th pin of the operational amplifier U1 is connected. The first pin of the multiplier U5 is connected, the seventh pin of the operational amplifier U1 is connected to the sixth pin of the operational amplifier U3 through the resistor R7, and the seventh pin of the operational amplifier U1 is connected to the output y, and the operational amplifier U1 is The 8th pin is connected to the 9th pin of the operational amplifier U1 through the capacitor Cx. The 8th pin of the operational amplifier U1 is connected to the 2nd pin of the operational amplifier U1 through the resistor Ry1, and the 8th pin of the operational amplifier U1. Connected to the second pin of operational amplifier U3 through resistor R5, the eighth pin of operational amplifier U1 and Instruments used U5 third lead When the pin is connected, the 8th pin of the operational amplifier U1 is connected to the 2nd pin of the operational amplifier U6, the 8th pin of the operational amplifier U1 is connected to the output x, and the 13th pin of the operational amplifier U1 is connected to the operational amplifier by the resistor Rx. The 14th pin of U1 is connected, and the 14th pin of the operational amplifier U1 is connected to the 9th pin of the operational amplifier U1 through the resistor R1;

The second pin, the fourth pin, and the sixth pin of the multiplier U4 are grounded, the fifth pin is connected to VEE, and the seventh pin is connected to the second pin of the operational amplifier U1 through the resistor Ry3, and the eighth pin Foot connected to VCC;

The first pin of the operational amplifier U6 is connected to the first pin of the selector U7 via the resistor R13, and the first pin of the operational amplifier U6 is connected to the ground through the resistor R13 and the resistor R14, and the third of the operational amplifier U6. Pin, 5th lead Pin, pin 10, pin 12 are grounded, pin 4 is connected to VCC, pin 11 is connected to VEE, and op amp U6 is pin 6, pin 7, pin 8, pin 9, The 12th pin, the 13th pin, and the 14th pin are left floating.

Advantageous Effects: Based on the Lorenz-type chaotic system, the Lorenz-type hyperchaotic system with different feedback for the ultimate boundary estimation is designed and an analog circuit is designed to realize the chaotic system, which is the synchronization and control of chaos. A new hyperchaotic system signal source is provided.

DRAWINGS

FIG. 1 is a schematic diagram of a circuit connection structure according to a preferred embodiment of the present invention.

2 is a circuit actual connection diagram of the multiplier U4 and the operational amplifier U1.

FIG. 3 is a diagram showing the actual connection of the circuit of the operational amplifier U3.

4 is a circuit actual connection diagram of the multiplier U5 and the operational amplifier U2.

FIG. 5 is a circuit actual connection diagram of the selector U7 and the operational amplifier U6.

detailed description

The present invention will now be described in further detail with reference to the accompanying drawings and the preferred embodiments. FIG.

(1) The Lorenz type chaotic system i is:

(2) Add a one-dimensional variable w to the chaotic system i:

Dw/dt=-ky-rw k=5, r=0.1 ii

Where w is the state variable and k, r are the system parameters;

The first pin of the operational amplifier U1 is connected to the sixth pin of the operational amplifier U1 through the resistor R2, and is put into operation. The second pin of the U1 is connected to the first pin of the operational amplifier U1 via the resistor Ry, and the third, fifth, tenth, and twelfth pins of the operational amplifier U1 are grounded, and the operational amplifier The fourth pin of U1 is connected to VCC, the eleventh pin of operational amplifier U1 is connected to VEE, the sixth pin of operational amplifier U1 is connected to the seventh pin of operational amplifier U1 through capacitor Cy, and the seventh lead of operational amplifier U1. The pin is connected to the 13th pin of the operational amplifier U1 through the resistor Rx2, the 7th pin of the operational amplifier U1 is connected to the 1st pin of the multiplier U5, and the 7th pin of the operational amplifier U1 is connected to the operational amplifier by the resistor R7. The 6th pin of U3 is connected, the 7th pin of the operational amplifier U1 is connected to the output y, and the 8th pin of the operational amplifier U1 is connected to the 9th pin of the operational amplifier U1 through the capacitor Cx, and the 8th of the operational amplifier U1 The pin is connected to the second pin of the operational amplifier U1 through the resistor Ry1, and the eighth pin of the operational amplifier U1 is connected to the second pin of the operational amplifier U3 via the resistor R5, and the eighth pin of the operational amplifier U1 and multiplication The third pin of U5 is connected, and the eighth pin of operational amplifier U1 is connected to the second pin of operational amplifier U6. The 8th pin of the operational amplifier U1 is connected to the output x. The 13th pin of the operational amplifier U1 is connected to the 14th pin of the operational amplifier U1 through the resistor Rx. The 14th pin of the operational amplifier U1 passes through the resistor R1 and the operational amplifier U1. The 9th pin is connected;

The first pin of the operational amplifier U3 is connected to the 13th pin of the operational amplifier U1 via the resistor Rx1, and the first pin of the operational amplifier U3 is connected to the first pin of the multiplier U4, and the first amplifier of the operational amplifier U3 The 2 pin is connected to the first pin of the operational amplifier U3 through the resistor R6, and the third pin, the fifth pin, the tenth pin, and the twelfth pin of the operational amplifier U3 are grounded, and the fourth pin is connected to VCC. The 11th pin is connected to VEE, the 6th pin of the operational amplifier U3 is connected to the 7th pin of the operational amplifier U3 through the resistor R8, and the 7th pin of the operational amplifier U3 is connected to the second pin of the operational amplifier U1 through the resistor Ry2. When connected, the seventh pin of the operational amplifier U3 is connected to the second pin of the operational amplifier U2 through the resistor Rw1, and the eighth pin of the operational amplifier U3 is connected to the ninth pin of the operational amplifier U3 through the resistor R10. When connected, the 8th pin of the operational amplifier U3 is connected to the 13th pin of the operational amplifier U2 through the resistor Rz2, and the 13th pin of the operational amplifier U3 is connected to the 14th pin of the operational amplifier U3 through the resistor R12. The 14th pin of the amplifier U3 is connected to the second pin of the operational amplifier U2 through the resistor Rw2;

The first pin of the operational amplifier U1 is connected to the sixth pin of the operational amplifier U1 via the resistor R2, and the second pin of the operational amplifier U1 is connected to the first pin of the operational amplifier U1 via the resistor Ry. The third pin, the fifth pin, the tenth pin, and the twelfth pin of U1 are grounded, the fourth pin of the operational amplifier U1 is connected to VCC, the eleventh pin of the operational amplifier U1 is connected to VEE, and the operational amplifier U1 is The 6-pin is connected to the 7th pin of the operational amplifier U1 through the capacitor Cy. The 7th pin of the operational amplifier U1 is connected to the 13th pin of the operational amplifier U1 through the resistor Rx2, and the 7th pin of the operational amplifier U1 is connected. The first pin of the multiplier U5 is connected, and the seventh pin of the operational amplifier U1 Connected to the sixth pin of the operational amplifier U3 via the resistor R7, the seventh pin of the operational amplifier U1 is connected to the output y, and the eighth pin of the operational amplifier U1 is connected to the ninth pin of the operational amplifier U1 through the capacitor Cx. The eighth pin of the operational amplifier U1 is connected to the second pin of the operational amplifier U1 via the resistor Ry1, and the eighth pin of the operational amplifier U1 is connected to the second pin of the operational amplifier U3 via the resistor R5, and the operational amplifier U1 is connected. The 8th pin is connected to the 3rd pin of the multiplier U5, the 8th pin of the operational amplifier U1 is connected to the 2nd pin of the operational amplifier U6, and the 8th pin of the operational amplifier U1 is connected to the output x, the operational amplifier The 13th pin of U1 is connected to the 14th pin of the operational amplifier U1 through the resistor Rx, and the 14th pin of the operational amplifier U1 is connected to the 9th pin of the operational amplifier U1 through the resistor R1;

The above description is not intended to limit the invention, and the invention is not limited to the above examples, and variations, modifications, additions or substitutions made by those skilled in the art within the scope of the invention also belong to the invention. protected range.

Claims

A method for constructing a Lorenz type hyperchaotic system which is different for facilitating ultimate boundary estimation, and is characterized in that it comprises the following steps:

(1) The Lorenz type chaotic system i is:

Where x, y, and z are state variables, and a, b, c, and d are system parameters;

(2) Add a one-dimensional variable w to the chaotic system i:

Dw/dt=-ky-rw k=5, r=0.1 ii

Where w is the state variable and k, r are the system parameters;

(3) The variable ii is used as a one-dimensional system variable and added to the first equation of the Lorenz-type chaotic system i. A Lorenz-type hyperchaotic system iii that facilitates the final boundary estimation is obtained:

Where x, y, z, w are state variables, parameter values a = 12, b = 23, c = 1, d = 2.1, k = 5, r = 0.1;

(4) The variable ii is used as a one-dimensional system variable and added to the second equation of the Lorenz-type chaotic system i. A Lorenz-type hyperchaotic system iv that facilitates the final boundary estimation is obtained:

Where x, y, z, w are state variables, parameter values a = 12, b = 23, c = 1, d = 2.1, k = 5, r = 0.1;

(5) Construct a selection function v and vi to form iii and iv into a Lorenz-type switched hyperchaotic system vii for the ultimate boundary estimation:

Where x, y, z, w are state variables, f(x), f(-x) are switching functions, and a, b, c, d, k, r are system parameters;

(6) Based on the circuit constructed by the system vii, the addition and integration operations are realized by the operational amplifier U1, the operational amplifier U2, and the resistors and capacitors, and the inverse operation is realized by the operational amplifier U3 and the resistor, and the multiplier U4 and the multiplier U5 are implemented in the system. In the multiplication operation, the operational amplifier U1 is connected to an operational amplifier U3, an operational amplifier U6, and a multiplier U5. The operational amplifier U2 is connected to a multiplier U4 and an operational amplifier U3. The operational amplifier U3 is connected to the operational amplifier U1 and the operational amplifier U2. An amplifier U6 and a multiplier U4, the multiplier U4 is connected to an operational amplifier U1, the multiplier U5 is connected to an operational amplifier U2; the operational amplifier U6 is connected to a selector U7, and the selector U7 is connected to an operational amplifier U1, the operation The amplifiers U1, U2, U3 and U6 adopt LF347BN, the multipliers U4 and U5 adopt AD633JN, and the selector adopts ADG409;

The first pin of the operational amplifier U1 is connected to the sixth pin of the operational amplifier U1 via the resistor R2, and the second pin of the operational amplifier U1 is connected to the first pin of the operational amplifier U1 via the resistor Ry. The third pin, the fifth pin, the tenth pin, and the twelfth pin of U1 are grounded, the fourth pin of the operational amplifier U1 is connected to VCC, the eleventh pin of the operational amplifier U1 is connected to VEE, and the operational amplifier U1 is The 6-pin is connected to the 7th pin of the operational amplifier U1 through the capacitor Cy. The 7th pin of the operational amplifier U1 is connected to the 13th pin of the operational amplifier U1 through the resistor Rx2, and the 7th pin of the operational amplifier U1 is connected. The first pin of the multiplier U5 is connected, the seventh pin of the operational amplifier U1 is connected to the sixth pin of the operational amplifier U3 through the resistor R7, and the seventh pin of the operational amplifier U1 is connected to the output y, and the operational amplifier U1 is The 8th pin is connected to the 9th pin of the operational amplifier U1 through the capacitor Cx. The 8th pin of the operational amplifier U1 is connected to the 2nd pin of the operational amplifier U1 through the resistor Ry1, and the 8th pin of the operational amplifier U1. Connected to the second pin of operational amplifier U3 through resistor R5, the eighth pin of operational amplifier U1 and The third pin of the U5 is connected, the eighth pin of the operational amplifier U1 is connected to the second pin of the operational amplifier U6, the eighth pin of the operational amplifier U1 is connected to the output x, and the thirteenth lead of the operational amplifier U1 The pin is connected to the 14th pin of the operational amplifier U1 through the resistor Rx, and the 14th pin of the operational amplifier U1 is connected to the 9th pin of the operational amplifier U1 through the resistor R1;

The first pin of the operational amplifier U2 is connected to the sixth pin of the operational amplifier U2 via the resistor R4, and the second pin of the operational amplifier U2 is connected to the first pin of the operational amplifier U2 via the resistor Rw. The 3rd pin, the 5th pin, the 10th pin, and the 12th pin of U2 are grounded, the 4th pin is connected to VCC, the 11th pin is connected to VEE, and the 6th pin of the operational amplifier U2 is connected to the capacitor Cw. The 7th pin of amplifier U2 is connected, the 7th pin of operational amplifier U2 is connected to the 4th pin and the 12th pin of the selector U7, and the 7th pin of the operational amplifier U2 is connected through the resistor. R11 is connected to the 13th pin of the operational amplifier U3, the 7th pin of the operational amplifier U2 is connected to the output w, and the 8th pin of the operational amplifier U2 is connected to the 9th pin of the operational amplifier U2 through the capacitor Cz, the operational amplifier The 8th pin of U2 is connected to the 3rd pin of the multiplier U4, the 8th pin of the operational amplifier U2 is connected to the 9th pin of the operational amplifier U3 through the resistor R9, and the 8th pin of the operational amplifier U2 is connected. Output z, the 13th pin of the operational amplifier U2 is connected to the 14th pin of the operational amplifier U2 through the resistor Rz, and the 14th pin of the operational amplifier U2 is connected to the 9th pin of the operational amplifier U2 through the resistor R3;

The first pin of the operational amplifier U3 is connected to the 13th pin of the operational amplifier U1 via the resistor Rx1, and the first pin of the operational amplifier U3 is connected to the first pin of the multiplier U4, and the first amplifier of the operational amplifier U3 The 2 pin is connected to the first pin of the operational amplifier U3 through the resistor R6, and the third pin, the fifth pin, the tenth pin, and the twelfth pin of the operational amplifier U3 are grounded, and the fourth pin is connected to VCC. The 11th pin is connected to VEE, the 6th pin of the operational amplifier U3 is connected to the 7th pin of the operational amplifier U3 through the resistor R8, and the 7th pin of the operational amplifier U3 is connected to the second pin of the operational amplifier U1 through the resistor Ry2. When connected, the seventh pin of the operational amplifier U3 is connected to the second pin of the operational amplifier U2 via the resistor Rw1, and the eighth pin of the operational amplifier U3 is connected to the ninth pin of the operational amplifier U3 via the resistor R10. The 8th pin of the amplifier U3 is connected to the 13th pin of the operational amplifier U2 through the resistor Rz2, and the 13th pin of the operational amplifier U3 is connected to the 14th pin of the operational amplifier U3 via the resistor R12, and the operational amplifier U3 is connected. The 14 pin is connected to the second pin of the operational amplifier U2 through the resistor Rw2;

The second pin, the fourth pin, and the sixth pin of the multiplier U4 are grounded, the fifth pin is connected to VEE, and the seventh pin is connected to the second pin of the operational amplifier U1 through the resistor Ry3, and the eighth pin Foot connected to VCC;

The second pin, the fourth pin, and the sixth pin of the multiplier U5 are grounded, the fifth pin is connected to VEE, and the seventh pin is connected to the 13th pin and the eighth pin of the operational amplifier U2 through the resistor Rz1. Connected to VCC;

The first pin of the operational amplifier U6 is connected to the first pin of the selector U7 via the resistor R13, and the first pin of the operational amplifier U6 is connected to the ground through the resistor R13 and the resistor R14, and the third of the operational amplifier U6. Pin, 5th pin, 10th pin, 12th pin are grounded, the 4th pin is connected to VCC, the 11th pin is connected to VEE, and the operational amplifier U6 is 6th, 7th, and 8th. The 9th pin, the 12th pin, the 13th pin, and the 14th pin are left floating.

The second pin of the selector U7 and the 14th pin stage VCC, the third pin of the selector U7 is connected to VEE, the fifteenth pin and the thirteenth pin of the selector U7 are grounded, and the eighth of the selector U7 The pin is connected to the second pin of the operational amplifier U2 through the resistor Rw1, and the sixth, seventh, ninth, tenth, eleventh, and twelfth pins of the selector U7. The 13th pin is left floating.
A Lorenz type hyperchaotic system circuit which is different in feedback for the ultimate boundary estimation, is characterized in that an operational amplifier U1, an operational amplifier U2, a resistor and a capacitor are used for addition and integration operations, and an operational amplifier U3 and a resistor are used to realize an inversion operation. Multiplier U4 and multiplier U5 implement multiplication in the system, the operational amplifier U1 Connected to an operational amplifier U3, an operational amplifier U6, and a multiplier U5, the operational amplifier U2 is connected to a multiplier U4 and an operational amplifier U3, the operational amplifier U3 is connected to an operational amplifier U1, an operational amplifier U2, an operational amplifier U6 and a multiplier U4, The multiplier U4 is connected to an operational amplifier U1, which is connected to an operational amplifier U2; the operational amplifier U6 is connected to a selector U7, which is connected to an operational amplifier U1, the operational amplifiers U1, U2, U3 and U6 Using LF347BN, the multipliers U4 and U5 adopt AD633JN, and the selector adopts ADG409;

The first pin of the operational amplifier U1 is connected to the sixth pin of the operational amplifier U1 via the resistor R2, and the second pin of the operational amplifier U1 is connected to the first pin of the operational amplifier U1 via the resistor Ry. The third pin, the fifth pin, the tenth pin, and the twelfth pin of U1 are grounded, the fourth pin of the operational amplifier U1 is connected to VCC, the eleventh pin of the operational amplifier U1 is connected to VEE, and the operational amplifier U1 is The 6-pin is connected to the 7th pin of the operational amplifier U1 through the capacitor Cy. The 7th pin of the operational amplifier U1 is connected to the 13th pin of the operational amplifier U1 through the resistor Rx2, and the 7th pin of the operational amplifier U1 is connected. The first pin of the multiplier U5 is connected, the seventh pin of the operational amplifier U1 is connected to the sixth pin of the operational amplifier U3 through the resistor R7, and the seventh pin of the operational amplifier U1 is connected to the output y, and the operational amplifier U1 is The 8th pin is connected to the 9th pin of the operational amplifier U1 through the capacitor Cx. The 8th pin of the operational amplifier U1 is connected to the 2nd pin of the operational amplifier U1 through the resistor Ry1, and the 8th pin of the operational amplifier U1. Connected to the second pin of operational amplifier U3 through resistor R5, the eighth pin of operational amplifier U1 and The third pin of the U5 is connected, the eighth pin of the operational amplifier U1 is connected to the second pin of the operational amplifier U6, the eighth pin of the operational amplifier U1 is connected to the output x, and the thirteenth lead of the operational amplifier U1 The pin is connected to the 14th pin of the operational amplifier U1 through the resistor Rx, and the 14th pin of the operational amplifier U1 is connected to the 9th pin of the operational amplifier U1 through the resistor R1;

The first pin of the operational amplifier U2 is connected to the sixth pin of the operational amplifier U2 via the resistor R4, and the second pin of the operational amplifier U2 is connected to the first pin of the operational amplifier U2 via the resistor Rw. The 3rd pin, the 5th pin, the 10th pin, and the 12th pin of U2 are grounded, the 4th pin is connected to VCC, the 11th pin is connected to VEE, and the 6th pin of the operational amplifier U2 is connected to the capacitor Cw. The 7th pin of the amplifier U2 is connected, the 7th pin of the operational amplifier U2 is connected to the 4th pin and the 12th pin of the selector U7, and the 7th pin of the operational amplifier U2 is connected to the operational amplifier U3 through the resistor R11. The 13th pin is connected, the 7th pin of the operational amplifier U2 is connected to the output w, the 8th pin of the operational amplifier U2 is connected to the 9th pin of the operational amplifier U2 through the capacitor Cz, and the 8th lead of the operational amplifier U2 The pin is connected to the third pin of the multiplier U4, the eighth pin of the operational amplifier U2 is connected to the ninth pin of the operational amplifier U3 through the resistor R9, and the eighth pin of the operational amplifier U2 is connected to the output z, the operational amplifier The 13th pin of U2 is connected to the 14th pin of the operational amplifier U2 through the resistor Rz, and the 14th pin of the operational amplifier U2 is passed. The resistor R3 is connected to the ninth pin of the operational amplifier U2;

The first pin of the operational amplifier U3 is connected to the 13th pin of the operational amplifier U1 through the resistor Rx1, and the operation is performed. The first pin of the amplifier U3 is connected to the first pin of the multiplier U4, and the second pin of the operational amplifier U3 is connected to the first pin of the operational amplifier U3 via the resistor R6, and the third pin of the operational amplifier U3. The 5th pin, the 10th pin, and the 12th pin are grounded. The 4th pin is connected to VCC, the 11th pin is connected to VEE, and the 6th pin of the operational amplifier U3 is connected to the 7th lead of the operational amplifier U3 through the resistor R8. When the pin is connected, the seventh pin of the operational amplifier U3 is connected to the second pin of the operational amplifier U1 via the resistor Ry2, and the seventh pin of the operational amplifier U3 is connected to the second pin of the operational amplifier U2 via the resistor Rw1. The eighth pin of the operational amplifier U3 is connected to the ninth pin of the operational amplifier U3 via the resistor R10, and the eighth pin of the operational amplifier U3 is connected to the thirteenth pin of the operational amplifier U2 via the resistor Rz2, and the operational amplifier U3 is connected. The 13th pin is connected to the 14th pin of the operational amplifier U3 through the resistor R12, and the 14th pin of the operational amplifier U3 is connected to the second pin of the operational amplifier U2 through the resistor Rw2;

The second pin, the fourth pin, and the sixth pin of the multiplier U4 are grounded, the fifth pin is connected to VEE, and the seventh pin is connected to the second pin of the operational amplifier U1 through the resistor Ry3, and the eighth pin Foot connected to VCC;

The second pin, the fourth pin, and the sixth pin of the multiplier U5 are grounded, the fifth pin is connected to VEE, and the seventh pin is connected to the 13th pin and the eighth pin of the operational amplifier U2 through the resistor Rz1. Connected to VCC;

The first pin of the operational amplifier U6 is connected to the first pin of the selector U7 via the resistor R13, and the first pin of the operational amplifier U6 is connected to the ground through the resistor R13 and the resistor R14, and the third of the operational amplifier U6. Pin, 5th pin, 10th pin, 12th pin are grounded, the 4th pin is connected to VCC, the 11th pin is connected to VEE, and the operational amplifier U6 is 6th, 7th, and 8th. The 9th pin, the 12th pin, the 13th pin, and the 14th pin are left floating.

The second pin of the selector U7 and the 14th pin stage VCC, the third pin of the selector U7 is connected to VEE, the fifteenth pin and the thirteenth pin of the selector U7 are grounded, and the eighth of the selector U7 The pin is connected to the second pin of the operational amplifier U2 through the resistor Rw1, and the sixth, seventh, ninth, tenth, eleventh, and twelfth pins of the selector U7. The 13th pin is left floating.