WO2016187739A1 - Procédé de construction pour système de lorenz hyper-chaotique de différentes rétroactions et de facilitation de l'estimation de limite ultime et circuit - Google Patents

Procédé de construction pour système de lorenz hyper-chaotique de différentes rétroactions et de facilitation de l'estimation de limite ultime et circuit Download PDF

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Publication number
WO2016187739A1
WO2016187739A1 PCT/CN2015/000572 CN2015000572W WO2016187739A1 WO 2016187739 A1 WO2016187739 A1 WO 2016187739A1 CN 2015000572 W CN2015000572 W CN 2015000572W WO 2016187739 A1 WO2016187739 A1 WO 2016187739A1
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pin
operational amplifier
resistor
multiplier
selector
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PCT/CN2015/000572
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English (en)
Chinese (zh)
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王忠林
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王忠林
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Publication of WO2016187739A1 publication Critical patent/WO2016187739A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/001—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using chaotic signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols

Definitions

  • the invention relates to a chaotic system and a circuit, in particular to a method and a circuit for constructing a Lorenz type hyperchaotic system with different feedbacks for facilitating ultimate boundary estimation.
  • the boundary estimation of hyperchaotic systems is of great significance in the application of chaos control and synchronization.
  • the method of constructing four-dimensional hyperchaos is based on the three-dimensional chaotic system, adding one-dimensional four-dimensional hyperchaotic systems.
  • the hyperchaotic system is not easy to perform ultimate boundary estimation.
  • the hyperchaotic system that can perform ultimate boundary estimation has the characteristic that the characteristic elements of the main diagonal of the Jacobian matrix are all negative, and the hyperchaotic system constructed by the present invention has ya The characteristic elements of the main diagonal of the comparable matrix are all negative, and the ultimate boundary estimation can be performed. This has important application prospects for the control and synchronization of hyperchaos.
  • a method for constructing a Lorenz type hyperchaotic system with different feedback for the ultimate boundary estimation characterized in that it comprises the following steps:
  • x, y, and z are state variables, and a, b, c, and d are system parameters;
  • variable ii is used as a one-dimensional system variable and added to the first equation of the Lorenz-type chaotic system i.
  • a Lorenz-type hyperchaotic system iii that facilitates the final boundary estimation is obtained:
  • variable ii is used as a one-dimensional system variable and added to the second equation of the Lorenz-type chaotic system i.
  • a Lorenz-type hyperchaotic system iv that facilitates the final boundary estimation is obtained:
  • x, y, z, w are state variables, f(x), f(-x) are switching functions, and a, b, c, d, k, r are system parameters;
  • the addition and integration operations are realized by the operational amplifier U1, the operational amplifier U2, and the resistors and capacitors, and the inverse operation is realized by the operational amplifier U3 and the resistor, and the multiplier U4 and the multiplier U5 are implemented in the system.
  • the operational amplifier U1 is connected to an operational amplifier U3, an operational amplifier U6, and a multiplier U5.
  • the operational amplifier U2 is connected to a multiplier U4 and an operational amplifier U3.
  • the operational amplifier U3 is connected to the operational amplifier U1 and the operational amplifier U2.
  • An amplifier U6 and a multiplier U4 is connected to an operational amplifier U1, the multiplier U5 is connected to an operational amplifier U2; the operational amplifier U6 is connected to a selector U7, and the selector U7 is connected to an operational amplifier U1, the operation
  • the amplifiers U1, U2, U3 and U6 adopt LF347BN, the multipliers U4 and U5 adopt AD633JN, and the selector adopts ADG409;
  • the first pin of the operational amplifier U1 is connected to the sixth pin of the operational amplifier U1 via the resistor R2, and the second pin of the operational amplifier U1 is connected to the first pin of the operational amplifier U1 via the resistor Ry.
  • the third pin, the fifth pin, the tenth pin, and the twelfth pin of U1 are grounded, the fourth pin of the operational amplifier U1 is connected to VCC, the eleventh pin of the operational amplifier U1 is connected to VEE, and the operational amplifier U1 is The 6 pin is connected to the 7th pin of the operational amplifier U1 through the capacitor Cy, and the 7th pin of the operational amplifier U1 is connected to the 13th pin of the operational amplifier U1 through the resistor Rx2.
  • the seventh pin of the operational amplifier U1 is connected to the first pin of the multiplier U5, and the seventh pin of the operational amplifier U1 is connected to the sixth pin of the operational amplifier U3 via the resistor R7, and the operational amplifier U1 is connected.
  • the 7-pin is connected to the output y.
  • the 8th pin of the operational amplifier U1 is connected to the 9th pin of the operational amplifier U1 through the capacitor Cx.
  • the 8th pin of the operational amplifier U1 passes through the resistor Ry1 and the second pin of the operational amplifier U1.
  • the eighth pin of the operational amplifier U1 is connected to the second pin of the operational amplifier U3 through the resistor R5, and the eighth pin of the operational amplifier U1 is connected to the third pin of the multiplier U5, and the operational amplifier U1 is connected.
  • the 8th pin is connected to the 2nd pin of the operational amplifier U6, the 8th pin of the operational amplifier U1 is connected to the output x, and the 13th pin of the operational amplifier U1 is connected to the 14th pin of the operational amplifier U1 through the resistor Rx.
  • the 14th pin of the operational amplifier U1 is connected to the 9th pin of the operational amplifier U1 through the resistor R1;
  • the first pin of the operational amplifier U2 is connected to the sixth pin of the operational amplifier U2 via the resistor R4, and the second pin of the operational amplifier U2 is connected to the first pin of the operational amplifier U2 via the resistor Rw.
  • the 3rd pin, the 5th pin, the 10th pin, and the 12th pin of U2 are grounded, the 4th pin is connected to VCC, the 11th pin is connected to VEE, and the 6th pin of the operational amplifier U2 is connected to the capacitor Cw.
  • the 7th pin of the amplifier U2 is connected, the 7th pin of the operational amplifier U2 is connected to the 4th pin and the 12th pin of the selector U7, and the 7th pin of the operational amplifier U2 is connected to the operational amplifier U3 through the resistor R11.
  • the 13th pin is connected, the 7th pin of the operational amplifier U2 is connected to the output w, the 8th pin of the operational amplifier U2 is connected to the 9th pin of the operational amplifier U2 through the capacitor Cz, and the 8th lead of the operational amplifier U2
  • the pin is connected to the third pin of the multiplier U4, the eighth pin of the operational amplifier U2 is connected to the ninth pin of the operational amplifier U3 through the resistor R9, and the eighth pin of the operational amplifier U2 is connected to the output z, the operational amplifier
  • the 13th pin of U2 is connected to the 14th pin of the operational amplifier U2 through the resistor Rz, and the 14th pin of the operational amplifier U2 is passed.
  • the resistor R3 is connected to the ninth pin of the operational amplifier U2;
  • the first pin of the operational amplifier U3 is connected to the 13th pin of the operational amplifier U1 via the resistor Rx1, and the first pin of the operational amplifier U3 is connected to the first pin of the multiplier U4, and the first amplifier of the operational amplifier U3
  • the 2 pin is connected to the first pin of the operational amplifier U3 through the resistor R6, and the third pin, the fifth pin, the tenth pin, and the twelfth pin of the operational amplifier U3 are grounded, and the fourth pin is connected to VCC.
  • the 11th pin is connected to VEE
  • the 6th pin of the operational amplifier U3 is connected to the 7th pin of the operational amplifier U3 through the resistor R8, and the 7th pin of the operational amplifier U3 is connected to the second pin of the operational amplifier U1 through the resistor Ry2.
  • the seventh pin of the operational amplifier U3 is connected to the second pin of the operational amplifier U2 via the resistor Rw1
  • the eighth pin of the operational amplifier U3 is connected to the ninth pin of the operational amplifier U3 via the resistor R10.
  • the 8th pin of the amplifier U3 is connected to the 13th pin of the operational amplifier U2 through the resistor Rz2
  • the 13th pin of the operational amplifier U3 is connected to the 14th pin of the operational amplifier U3 via the resistor R12, and the operational amplifier U3 is connected.
  • the 14 pin is connected to the second pin of the operational amplifier U2 through the resistor Rw2;
  • the second pin, the fourth pin, and the sixth pin of the multiplier U4 are grounded, and the fifth pin is connected to VEE, and the seventh lead The pin is connected to the second pin of the operational amplifier U1 through the resistor Ry3, and the eighth pin is connected to VCC;
  • the second pin, the fourth pin, and the sixth pin of the multiplier U5 are grounded, the fifth pin is connected to VEE, and the seventh pin is connected to the 13th pin and the eighth pin of the operational amplifier U2 through the resistor Rz1. Connected to VCC;
  • the first pin of the operational amplifier U6 is connected to the first pin of the selector U7 via the resistor R13, and the first pin of the operational amplifier U6 is connected to the ground through the resistor R13 and the resistor R14, and the third of the operational amplifier U6.
  • Pin, 5th pin, 10th pin, 12th pin are grounded, the 4th pin is connected to VCC, the 11th pin is connected to VEE, and the operational amplifier U6 is 6th, 7th, and 8th.
  • the 9th pin, the 12th pin, the 13th pin, and the 14th pin are left floating.
  • the pin is connected to the second pin of the operational amplifier U2 through the resistor Rw1, and the sixth, seventh, ninth, tenth, eleventh, and twelfth pins of the selector U7.
  • the 13th pin is left floating.
  • a Lorenz-type hyperchaotic system circuit with different feedback for the ultimate boundary estimation which is characterized in that the operational amplifier U1, the operational amplifier U2, and the resistors and capacitors are used for addition and integration operations, and the operational amplifier U3 and the resistor are used for inversion.
  • Operation, multiplier U4 and multiplier U5 implement multiplication in the system, the operational amplifier U1 is connected to an operational amplifier U3, an operational amplifier U6 and a multiplier U5, which is connected to a multiplier U4 and an operational amplifier U3,
  • the operational amplifier U3 is connected to the operational amplifier U1, the operational amplifier U2, the operational amplifier U6, and the multiplier U4.
  • the multiplier U4 is connected to the operational amplifier U1, and the multiplier U5 is connected to the operational amplifier U2.
  • the operational amplifier U6 is connected to the selector U7.
  • the selector U7 is connected to the operational amplifier U1, the operational amplifiers U1, U2, U3 and U6 adopt LF347BN, the multipliers U4 and U5 adopt AD633JN, and the selector adopts ADG409;
  • the first pin of the operational amplifier U1 is connected to the sixth pin of the operational amplifier U1 via the resistor R2, and the second pin of the operational amplifier U1 is connected to the first pin of the operational amplifier U1 via the resistor Ry.
  • the third pin, the fifth pin, the tenth pin, and the twelfth pin of U1 are grounded, the fourth pin of the operational amplifier U1 is connected to VCC, the eleventh pin of the operational amplifier U1 is connected to VEE, and the operational amplifier U1 is The 6-pin is connected to the 7th pin of the operational amplifier U1 through the capacitor Cy.
  • the 7th pin of the operational amplifier U1 is connected to the 13th pin of the operational amplifier U1 through the resistor Rx2, and the 7th pin of the operational amplifier U1 is connected.
  • the first pin of the multiplier U5 is connected, the seventh pin of the operational amplifier U1 is connected to the sixth pin of the operational amplifier U3 through the resistor R7, and the seventh pin of the operational amplifier U1 is connected to the output y, and the operational amplifier U1 is The 8th pin is connected to the 9th pin of the operational amplifier U1 through the capacitor Cx.
  • the 8th pin of the operational amplifier U1 is connected to the 2nd pin of the operational amplifier U1 through the resistor Ry1, and the 8th pin of the operational amplifier U1.
  • the first pin of the operational amplifier U2 is connected to the sixth pin of the operational amplifier U2 via the resistor R4, and the second pin of the operational amplifier U2 is connected to the first pin of the operational amplifier U2 via the resistor Rw.
  • the 3rd pin, the 5th pin, the 10th pin, and the 12th pin of U2 are grounded, the 4th pin is connected to VCC, the 11th pin is connected to VEE, and the 6th pin of the operational amplifier U2 is connected to the capacitor Cw.
  • the 7th pin of the amplifier U2 is connected, the 7th pin of the operational amplifier U2 is connected to the 4th pin and the 12th pin of the selector U7, and the 7th pin of the operational amplifier U2 is connected to the operational amplifier U3 through the resistor R11.
  • the 13th pin is connected, the 7th pin of the operational amplifier U2 is connected to the output w, the 8th pin of the operational amplifier U2 is connected to the 9th pin of the operational amplifier U2 through the capacitor Cz, and the 8th lead of the operational amplifier U2
  • the pin is connected to the third pin of the multiplier U4, the eighth pin of the operational amplifier U2 is connected to the ninth pin of the operational amplifier U3 through the resistor R9, and the eighth pin of the operational amplifier U2 is connected to the output z, the operational amplifier
  • the 13th pin of U2 is connected to the 14th pin of the operational amplifier U2 through the resistor Rz, and the 14th pin of the operational amplifier U2 is passed.
  • the resistor R3 is connected to the ninth pin of the operational amplifier U2;
  • the first pin of the operational amplifier U3 is connected to the 13th pin of the operational amplifier U1 via the resistor Rx1, and the first pin of the operational amplifier U3 is connected to the first pin of the multiplier U4, and the first amplifier of the operational amplifier U3
  • the 2 pin is connected to the first pin of the operational amplifier U3 through the resistor R6, and the third pin, the fifth pin, the tenth pin, and the twelfth pin of the operational amplifier U3 are grounded, and the fourth pin is connected to VCC.
  • the 11th pin is connected to VEE
  • the 6th pin of the operational amplifier U3 is connected to the 7th pin of the operational amplifier U3 through the resistor R8, and the 7th pin of the operational amplifier U3 is connected to the second pin of the operational amplifier U1 through the resistor Ry2.
  • the seventh pin of the operational amplifier U3 is connected to the second pin of the operational amplifier U2 via the resistor Rw1
  • the eighth pin of the operational amplifier U3 is connected to the ninth pin of the operational amplifier U3 via the resistor R10.
  • the 8th pin of the amplifier U3 is connected to the 13th pin of the operational amplifier U2 through the resistor Rz2
  • the 13th pin of the operational amplifier U3 is connected to the 14th pin of the operational amplifier U3 via the resistor R12, and the operational amplifier U3 is connected.
  • the 14 pin is connected to the second pin of the operational amplifier U2 through the resistor Rw2;
  • the second pin, the fourth pin, and the sixth pin of the multiplier U4 are grounded, the fifth pin is connected to VEE, and the seventh pin is connected to the second pin of the operational amplifier U1 through the resistor Ry3, and the eighth pin Foot connected to VCC;
  • the second pin, the fourth pin, and the sixth pin of the multiplier U5 are grounded, the fifth pin is connected to VEE, and the seventh pin is connected to the 13th pin and the eighth pin of the operational amplifier U2 through the resistor Rz1. Connected to VCC;
  • the first pin of the operational amplifier U6 is connected to the first pin of the selector U7 via the resistor R13, and the first pin of the operational amplifier U6 is connected to the ground through the resistor R13 and the resistor R14, and the third of the operational amplifier U6.
  • Pin, 5th lead Pin, pin 10, pin 12 are grounded, pin 4 is connected to VCC, pin 11 is connected to VEE, and op amp U6 is pin 6, pin 7, pin 8, pin 9, The 12th pin, the 13th pin, and the 14th pin are left floating.
  • the pin is connected to the second pin of the operational amplifier U2 through the resistor Rw1, and the sixth, seventh, ninth, tenth, eleventh, and twelfth pins of the selector U7.
  • the 13th pin is left floating.
  • the Lorenz-type hyperchaotic system with different feedback for the ultimate boundary estimation is designed and an analog circuit is designed to realize the chaotic system, which is the synchronization and control of chaos.
  • a new hyperchaotic system signal source is provided.
  • FIG. 1 is a schematic diagram of a circuit connection structure according to a preferred embodiment of the present invention.
  • FIG. 3 is a diagram showing the actual connection of the circuit of the operational amplifier U3.
  • FIG. 5 is a circuit actual connection diagram of the selector U7 and the operational amplifier U6.
  • a method for constructing a Lorenz type hyperchaotic system with different feedback for the ultimate boundary estimation characterized in that it comprises the following steps:
  • x, y, and z are state variables, and a, b, c, and d are system parameters;
  • variable ii is used as a one-dimensional system variable and added to the first equation of the Lorenz-type chaotic system i.
  • a Lorenz-type hyperchaotic system iii that facilitates the final boundary estimation is obtained:
  • variable ii is used as a one-dimensional system variable and added to the second equation of the Lorenz-type chaotic system i.
  • a Lorenz-type hyperchaotic system iv that facilitates the final boundary estimation is obtained:
  • x, y, z, w are state variables, f(x), f(-x) are switching functions, and a, b, c, d, k, r are system parameters;
  • the addition and integration operations are realized by the operational amplifier U1, the operational amplifier U2, and the resistors and capacitors, and the inverse operation is realized by the operational amplifier U3 and the resistor, and the multiplier U4 and the multiplier U5 are implemented in the system.
  • the operational amplifier U1 is connected to an operational amplifier U3, an operational amplifier U6, and a multiplier U5.
  • the operational amplifier U2 is connected to a multiplier U4 and an operational amplifier U3.
  • the operational amplifier U3 is connected to the operational amplifier U1 and the operational amplifier U2.
  • An amplifier U6 and a multiplier U4 is connected to an operational amplifier U1, the multiplier U5 is connected to an operational amplifier U2; the operational amplifier U6 is connected to a selector U7, and the selector U7 is connected to an operational amplifier U1, the operation
  • the amplifiers U1, U2, U3 and U6 adopt LF347BN, the multipliers U4 and U5 adopt AD633JN, and the selector adopts ADG409;
  • the first pin of the operational amplifier U1 is connected to the sixth pin of the operational amplifier U1 through the resistor R2, and is put into operation.
  • the second pin of the U1 is connected to the first pin of the operational amplifier U1 via the resistor Ry, and the third, fifth, tenth, and twelfth pins of the operational amplifier U1 are grounded, and the operational amplifier
  • the fourth pin of U1 is connected to VCC
  • the eleventh pin of operational amplifier U1 is connected to VEE
  • the sixth pin of operational amplifier U1 is connected to the seventh pin of operational amplifier U1 through capacitor Cy
  • the pin is connected to the 13th pin of the operational amplifier U1 through the resistor Rx2, the 7th pin of the operational amplifier U1 is connected to the 1st pin of the multiplier U5, and the 7th pin of the operational amplifier U1 is connected to the operational amplifier by the resistor R7.
  • the 6th pin of U3 is connected, the 7th pin of the operational amplifier U1 is connected to the output y, and the 8th pin of the operational amplifier U1 is connected to the 9th pin of the operational amplifier U1 through the capacitor Cx, and the 8th of the operational amplifier U1
  • the pin is connected to the second pin of the operational amplifier U1 through the resistor Ry1, and the eighth pin of the operational amplifier U1 is connected to the second pin of the operational amplifier U3 via the resistor R5, and the eighth pin of the operational amplifier U1 and multiplication
  • the third pin of U5 is connected, and the eighth pin of operational amplifier U1 is connected to the second pin of operational amplifier U6.
  • the 8th pin of the operational amplifier U1 is connected to the output x.
  • the 13th pin of the operational amplifier U1 is connected to the 14th pin of the operational amplifier U1 through the resistor Rx.
  • the 14th pin of the operational amplifier U1 passes through the resistor R1 and the operational amplifier U1.
  • the 9th pin is connected;
  • the first pin of the operational amplifier U2 is connected to the sixth pin of the operational amplifier U2 via the resistor R4, and the second pin of the operational amplifier U2 is connected to the first pin of the operational amplifier U2 via the resistor Rw.
  • the 3rd pin, the 5th pin, the 10th pin, and the 12th pin of U2 are grounded, the 4th pin is connected to VCC, the 11th pin is connected to VEE, and the 6th pin of the operational amplifier U2 is connected to the capacitor Cw.
  • the 7th pin of the amplifier U2 is connected, the 7th pin of the operational amplifier U2 is connected to the 4th pin and the 12th pin of the selector U7, and the 7th pin of the operational amplifier U2 is connected to the operational amplifier U3 through the resistor R11.
  • the 13th pin is connected, the 7th pin of the operational amplifier U2 is connected to the output w, the 8th pin of the operational amplifier U2 is connected to the 9th pin of the operational amplifier U2 through the capacitor Cz, and the 8th lead of the operational amplifier U2
  • the pin is connected to the third pin of the multiplier U4, the eighth pin of the operational amplifier U2 is connected to the ninth pin of the operational amplifier U3 through the resistor R9, and the eighth pin of the operational amplifier U2 is connected to the output z, the operational amplifier
  • the 13th pin of U2 is connected to the 14th pin of the operational amplifier U2 through the resistor Rz, and the 14th pin of the operational amplifier U2 is passed.
  • the resistor R3 is connected to the ninth pin of the operational amplifier U2;
  • the first pin of the operational amplifier U3 is connected to the 13th pin of the operational amplifier U1 via the resistor Rx1, and the first pin of the operational amplifier U3 is connected to the first pin of the multiplier U4, and the first amplifier of the operational amplifier U3
  • the 2 pin is connected to the first pin of the operational amplifier U3 through the resistor R6, and the third pin, the fifth pin, the tenth pin, and the twelfth pin of the operational amplifier U3 are grounded, and the fourth pin is connected to VCC.
  • the 11th pin is connected to VEE
  • the 6th pin of the operational amplifier U3 is connected to the 7th pin of the operational amplifier U3 through the resistor R8, and the 7th pin of the operational amplifier U3 is connected to the second pin of the operational amplifier U1 through the resistor Ry2.
  • the seventh pin of the operational amplifier U3 is connected to the second pin of the operational amplifier U2 through the resistor Rw1
  • the eighth pin of the operational amplifier U3 is connected to the ninth pin of the operational amplifier U3 through the resistor R10.
  • the 8th pin of the operational amplifier U3 is connected to the 13th pin of the operational amplifier U2 through the resistor Rz2
  • the 13th pin of the operational amplifier U3 is connected to the 14th pin of the operational amplifier U3 through the resistor R12.
  • the 14th pin of the amplifier U3 is connected to the second pin of the operational amplifier U2 through the resistor Rw2;
  • the second pin, the fourth pin, and the sixth pin of the multiplier U4 are grounded, the fifth pin is connected to VEE, and the seventh pin is connected to the second pin of the operational amplifier U1 through the resistor Ry3, and the eighth pin Foot connected to VCC;
  • the second pin, the fourth pin, and the sixth pin of the multiplier U5 are grounded, the fifth pin is connected to VEE, and the seventh pin is connected to the 13th pin and the eighth pin of the operational amplifier U2 through the resistor Rz1. Connected to VCC;
  • the first pin of the operational amplifier U6 is connected to the first pin of the selector U7 via the resistor R13, and the first pin of the operational amplifier U6 is connected to the ground through the resistor R13 and the resistor R14, and the third of the operational amplifier U6.
  • Pin, 5th pin, 10th pin, 12th pin are grounded, the 4th pin is connected to VCC, the 11th pin is connected to VEE, and the operational amplifier U6 is 6th, 7th, and 8th.
  • the 9th pin, the 12th pin, the 13th pin, and the 14th pin are left floating.
  • the pin is connected to the second pin of the operational amplifier U2 through the resistor Rw1, and the sixth, seventh, ninth, tenth, eleventh, and twelfth pins of the selector U7.
  • the 13th pin is left floating.
  • a Lorenz-type hyperchaotic system circuit with different feedback for the ultimate boundary estimation which is characterized in that the operational amplifier U1, the operational amplifier U2, and the resistors and capacitors are used for addition and integration operations, and the operational amplifier U3 and the resistor are used for inversion.
  • Operation, multiplier U4 and multiplier U5 implement multiplication in the system, the operational amplifier U1 is connected to an operational amplifier U3, an operational amplifier U6 and a multiplier U5, which is connected to a multiplier U4 and an operational amplifier U3,
  • the operational amplifier U3 is connected to the operational amplifier U1, the operational amplifier U2, the operational amplifier U6, and the multiplier U4.
  • the multiplier U4 is connected to the operational amplifier U1, and the multiplier U5 is connected to the operational amplifier U2.
  • the operational amplifier U6 is connected to the selector U7.
  • the selector U7 is connected to the operational amplifier U1, the operational amplifiers U1, U2, U3 and U6 adopt LF347BN, the multipliers U4 and U5 adopt AD633JN, and the selector adopts ADG409;
  • the first pin of the operational amplifier U1 is connected to the sixth pin of the operational amplifier U1 via the resistor R2, and the second pin of the operational amplifier U1 is connected to the first pin of the operational amplifier U1 via the resistor Ry.
  • the third pin, the fifth pin, the tenth pin, and the twelfth pin of U1 are grounded, the fourth pin of the operational amplifier U1 is connected to VCC, the eleventh pin of the operational amplifier U1 is connected to VEE, and the operational amplifier U1 is The 6-pin is connected to the 7th pin of the operational amplifier U1 through the capacitor Cy.
  • the 7th pin of the operational amplifier U1 is connected to the 13th pin of the operational amplifier U1 through the resistor Rx2, and the 7th pin of the operational amplifier U1 is connected.
  • the first pin of the multiplier U5 is connected, and the seventh pin of the operational amplifier U1 Connected to the sixth pin of the operational amplifier U3 via the resistor R7, the seventh pin of the operational amplifier U1 is connected to the output y, and the eighth pin of the operational amplifier U1 is connected to the ninth pin of the operational amplifier U1 through the capacitor Cx.
  • the eighth pin of the operational amplifier U1 is connected to the second pin of the operational amplifier U1 via the resistor Ry1, and the eighth pin of the operational amplifier U1 is connected to the second pin of the operational amplifier U3 via the resistor R5, and the operational amplifier U1 is connected.
  • the 8th pin is connected to the 3rd pin of the multiplier U5, the 8th pin of the operational amplifier U1 is connected to the 2nd pin of the operational amplifier U6, and the 8th pin of the operational amplifier U1 is connected to the output x, the operational amplifier
  • the 13th pin of U1 is connected to the 14th pin of the operational amplifier U1 through the resistor Rx, and the 14th pin of the operational amplifier U1 is connected to the 9th pin of the operational amplifier U1 through the resistor R1;
  • the first pin of the operational amplifier U2 is connected to the sixth pin of the operational amplifier U2 via the resistor R4, and the second pin of the operational amplifier U2 is connected to the first pin of the operational amplifier U2 via the resistor Rw.
  • the 3rd pin, the 5th pin, the 10th pin, and the 12th pin of U2 are grounded, the 4th pin is connected to VCC, the 11th pin is connected to VEE, and the 6th pin of the operational amplifier U2 is connected to the capacitor Cw.
  • the 7th pin of the amplifier U2 is connected, the 7th pin of the operational amplifier U2 is connected to the 4th pin and the 12th pin of the selector U7, and the 7th pin of the operational amplifier U2 is connected to the operational amplifier U3 through the resistor R11.
  • the 13th pin is connected, the 7th pin of the operational amplifier U2 is connected to the output w, the 8th pin of the operational amplifier U2 is connected to the 9th pin of the operational amplifier U2 through the capacitor Cz, and the 8th lead of the operational amplifier U2
  • the pin is connected to the third pin of the multiplier U4, the eighth pin of the operational amplifier U2 is connected to the ninth pin of the operational amplifier U3 through the resistor R9, and the eighth pin of the operational amplifier U2 is connected to the output z, the operational amplifier
  • the 13th pin of U2 is connected to the 14th pin of the operational amplifier U2 through the resistor Rz, and the 14th pin of the operational amplifier U2 is passed.
  • the resistor R3 is connected to the ninth pin of the operational amplifier U2;
  • the first pin of the operational amplifier U3 is connected to the 13th pin of the operational amplifier U1 via the resistor Rx1, and the first pin of the operational amplifier U3 is connected to the first pin of the multiplier U4, and the first amplifier of the operational amplifier U3
  • the 2 pin is connected to the first pin of the operational amplifier U3 through the resistor R6, and the third pin, the fifth pin, the tenth pin, and the twelfth pin of the operational amplifier U3 are grounded, and the fourth pin is connected to VCC.
  • the 11th pin is connected to VEE
  • the 6th pin of the operational amplifier U3 is connected to the 7th pin of the operational amplifier U3 through the resistor R8, and the 7th pin of the operational amplifier U3 is connected to the second pin of the operational amplifier U1 through the resistor Ry2.
  • the seventh pin of the operational amplifier U3 is connected to the second pin of the operational amplifier U2 via the resistor Rw1
  • the eighth pin of the operational amplifier U3 is connected to the ninth pin of the operational amplifier U3 via the resistor R10.
  • the 8th pin of the amplifier U3 is connected to the 13th pin of the operational amplifier U2 through the resistor Rz2
  • the 13th pin of the operational amplifier U3 is connected to the 14th pin of the operational amplifier U3 via the resistor R12, and the operational amplifier U3 is connected.
  • the 14 pin is connected to the second pin of the operational amplifier U2 through the resistor Rw2;
  • the second pin, the fourth pin, and the sixth pin of the multiplier U4 are grounded, the fifth pin is connected to VEE, and the seventh pin is connected to the second pin of the operational amplifier U1 through the resistor Ry3, and the eighth pin Foot connected to VCC;
  • the second pin, the fourth pin, and the sixth pin of the multiplier U5 are grounded, the fifth pin is connected to VEE, and the seventh pin is connected to the 13th pin and the eighth pin of the operational amplifier U2 through the resistor Rz1. Connected to VCC;
  • the first pin of the operational amplifier U6 is connected to the first pin of the selector U7 via the resistor R13, and the first pin of the operational amplifier U6 is connected to the ground through the resistor R13 and the resistor R14, and the third of the operational amplifier U6.
  • Pin, 5th pin, 10th pin, 12th pin are grounded, the 4th pin is connected to VCC, the 11th pin is connected to VEE, and the operational amplifier U6 is 6th, 7th, and 8th.
  • the 9th pin, the 12th pin, the 13th pin, and the 14th pin are left floating.
  • the pin is connected to the second pin of the operational amplifier U2 through the resistor Rw1, and the sixth, seventh, ninth, tenth, eleventh, and twelfth pins of the selector U7.
  • the 13th pin is left floating.

Abstract

La présente invention porte sur un procédé de construction d'un système de Lorenz hyperchaotique de différentes rétroactions et sur la facilitation d'estimation de limite finale. Un amplificateur opérationnel (U1), un amplificateur opérationnel (U2), une résistance, et un condensateur sont utilisés pour mettre en œuvre des opérations d'ajout et d'intégration. Un amplificateur opérationnel (U3) et une résistance sont utilisés pour mettre en œuvre une opération d'inversion. Un multiplicateur (U4) et un multiplicateur (U5) mettent en œuvre des opérations de multiplication dans le système. Les amplificateurs opérationnels U1, U2, U3, et U6 utilisent LF347BN. Les multiplicateurs U4 et U5 utilisent AD633JN. Le sélecteur utilise ADG409. La présente invention conçoit, sur la base d'un système chaotique de Lorenz, le procédé de construction pour le système de Lorenz hyper-chaotique de différentes rétroactions et la facilitation de l'estimation de limite finale et un procédé de construction de circuit, conçoit également un circuit analogique pour mettre en œuvre ce système chaotique, et fournit la synchronisation et commande chaotique avec un nouvelle source de signal hyper-chaotique.
PCT/CN2015/000572 2015-05-27 2015-08-07 Procédé de construction pour système de lorenz hyper-chaotique de différentes rétroactions et de facilitation de l'estimation de limite ultime et circuit WO2016187739A1 (fr)

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CN105119714A (zh) * 2015-09-09 2015-12-02 韩敬伟 一种便于终极边界估计的Lorenz型超混沌系统自适应同步方法及电路
CN105119710A (zh) * 2015-09-09 2015-12-02 王春梅 一种利于终极边界估计的Lorenz型超混沌系统自适应同步方法及电路

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5680462A (en) * 1995-08-07 1997-10-21 Sandia Corporation Information encoder/decoder using chaotic systems
CN102332976A (zh) * 2011-09-15 2012-01-25 江西理工大学 异维可切换混沌系统设计方法及电路
CN103856317A (zh) * 2014-02-22 2014-06-11 滨州学院 一种分数阶次不同的经典Lorenz型混沌切换系统方法及电路

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103217901A (zh) * 2013-01-31 2013-07-24 王少夫 一种混沌系统跟踪控制方法
CN105530085B (zh) * 2014-08-30 2018-05-11 新昌县无痕文化有限公司 基于Lü系统的不同反馈自动切换超混沌系统构造方法及模拟电路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5680462A (en) * 1995-08-07 1997-10-21 Sandia Corporation Information encoder/decoder using chaotic systems
CN102332976A (zh) * 2011-09-15 2012-01-25 江西理工大学 异维可切换混沌系统设计方法及电路
CN103856317A (zh) * 2014-02-22 2014-06-11 滨州学院 一种分数阶次不同的经典Lorenz型混沌切换系统方法及电路

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