ZA814971B - Pcm regenerators - Google Patents

Abstract

1. Arrangement for monitoring a regenerator which includes a code rule infringement checking device connected to an error counter, for PCM signals occurring in AMI code, which regenerator generates, at a minimum of two inner terminals, two unipolar pulse trains which are regenerated in terms of amplitude and time and of which one represents the positive and one the negative input pulses, wherein, for the code rule infringement checking there is additionally provided an RS flip-flop (RSFF) whose reset input (R) and whose set input (S) are respectively separately connected to an output of the pulsed D flip-flop (DF1, DF2), and the outputs of the RS flip-flop produce the push-pull signal output (SA) for the regenerated signal so that a unipolar pulse train which contains the total information can be obtained from each output terminal, where two gate arrangements are provided each of which has two inputs, and the first input of the first gate arrangement is connected to the non-inverting output (Q) of the RS flip-flop (RSFF) and the other input of the first gate arrangement is connected to an output of the particular pulsed D flip-flop which is connected to the reset input (R) of the RS flip-flop (RSFF), where furthermore the first input of the second gate arrangement is connected to the inverting output (~Q) of the RS flip-flop (RSFF) and the other input of the second gate arrangement is connected to an output of the particular pulsed D flip-flop which is connected to the set input (S) of the RS flip-flop (RSFF), and where the outputs of the gate arrangements are connected to one another and to an output (F) for an error signal, and where the generation of checking sequences in the course of operation is effected in that respective ones of the outputs of the D flip-flops (DF1, DF2) are connected to voltage detectors (Det) whose output terminals are connected to the inputs of an analysis circuit (ASW), and where the control outputs of this analysis circuit are respectively connected to the base terminal of one of two switching transistors (T1, T2) whose emitter terminals are each connected to reference potential (Uo ), whose collector terminals are each connected via a protective resistor (R1, R2) to one of the outputs of the assigned D flip-flops, to one of the inputs of the assigned gate arrangement, and via a further resistor (R3, R4) to operating voltage (-Ub ) and, in accordance with the polarity of the connected output of the D flip-flop, in both cases an npn-transistor (T1, T2) is provided.