WO2025246700A1 - 数据处理装置、电子装置和数据处理装置的制备方法 - Google Patents

数据处理装置、电子装置和数据处理装置的制备方法

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Publication number
WO2025246700A1
WO2025246700A1 PCT/CN2025/089055 CN2025089055W WO2025246700A1 WO 2025246700 A1 WO2025246700 A1 WO 2025246700A1 CN 2025089055 W CN2025089055 W CN 2025089055W WO 2025246700 A1 WO2025246700 A1 WO 2025246700A1
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Prior art keywords
layer
memory
array
random access
data processing
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English (en)
French (fr)
Inventor
王钰言
原剑
李怡均
唐建石
高滨
钱鹤
吴华强
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Tsinghua University
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Tsinghua University
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell

Definitions

  • Embodiments of this disclosure relate to a data processing apparatus, an electronic device, and a method for manufacturing the data processing apparatus.
  • Memristor-based in-memory computing systems can effectively perform matrix-vector multiplication in neural networks, but the input and output data need to be cached, and the efficiency of data transfer becomes a performance bottleneck. Cache bandwidth is limited by the bus interconnection under the two-dimensional integrated architecture, resulting in low transmission efficiency within a single operation and limiting parallel computing capabilities. Even with multi-level bus optimization, it is still constrained by the inefficiency of two-dimensional connections.
  • traditional memristor chips are based on analog resistive switching characteristics. Although they have multiple resistive states that can be used for analog calculations, they are limited by non-ideal characteristics (such as conductance drift, high randomness, or limited erase/write cycles), making it difficult to achieve high-precision calculations.
  • At least one embodiment of this disclosure provides a data processing apparatus, including: a logic processing layer, an in-memory computing layer, and a storage array layer, wherein the logic processing layer, the in-memory computing layer, and the storage array layer are at least partially stacked; the logic processing layer is configured to perform logical operations and/or control processing; the in-memory computing layer is configured to perform neural network operations on received data; the storage array layer is configured to store data for the in-memory computing layer; the storage array layer includes a storage array, the storage array including a plurality of storage cells arranged in multiple rows and columns, each of the plurality of storage cells including a transistor and a magnetic random access storage device electrically connected to the transistor.
  • the magnetic random access storage device includes a first electrode layer, a free layer, a barrier layer, a pinning layer, and a second electrode layer stacked sequentially.
  • the free layer includes an antiferromagnetic layer and a ferromagnetic layer stacked sequentially.
  • the in-memory computing layer includes at least one in-memory computing array, each of the in-memory computing arrays including at least one memristor array, the memristor array including a plurality of memristors arranged in multiple rows and columns;
  • the magnetic random access storage device includes a magnetic tunnel junction, the magnetic tunnel junction being placed at a offset position from the memristors.
  • the transistor includes at least one of a carbon nanotube transistor, an indium oxide transistor, or a low-temperature polycrystalline silicon transistor.
  • the magnetic random access memory device includes a spin-transfer torque magnetic random access memory device or a spin-orbit torque magnetic random access memory device.
  • At least one embodiment of this disclosure provides an electronic device, including a data processing device provided in any embodiment of this disclosure.
  • At least one embodiment of this disclosure provides a method for fabricating a data processing device, comprising: fabricating an in-memory computing layer and fabricating a memory array layer at least partially stacked with the in-memory computing layer using a semiconductor fabrication process, wherein the in-memory computing layer is configured to perform neural network operations on received data, and the memory array layer is configured to store data for the in-memory computing layer; the memory array layer is configured to store data for the in-memory computing layer, the memory array layer includes a memory array, the memory array includes a plurality of memory cells arranged in multiple rows and columns, each of the plurality of memory cells includes a transistor and a magnetic random access memory device electrically connected to the transistor.
  • the fabrication of a magnetic random access memory device includes: fabricating a mask to define a patterned region of the magnetic random access memory device, wherein the mask includes a photoresist mask or a hard mask; and using the mask to fabricate a magnetic tunnel junction.
  • the fabrication of a mask to define a patterned region of the magnetic random access memory device includes: defining the pattern of the magnetic tunnel junction region using a double-layer adhesive process.
  • the fabrication of a magnetic tunnel junction using the mask includes: etching areas other than the patterned area of the magnetic random access memory device using a dry etching process to preserve the patterned area of the magnetic random access memory device.
  • the in-memory computing layer includes at least one in-memory computing array, each of the in-memory computing arrays includes at least one memristor array, the memristor array includes multiple memristors arranged in multiple rows and columns; the fabrication of the magnetic random access memory device further includes: selecting a region on the surface of the memristor with a root mean square roughness of less than 1 nm or 0.2 nm to arrange a magnetic tunnel junction, and placing the magnetic tunnel junction at a position offset from the memristor.
  • one embodiment of the present disclosure provides a fabrication method that further includes: providing a silicon substrate; fabricating a logic processing layer on the silicon substrate using a semiconductor fabrication process, wherein the logic processing layer is configured to perform logic operations and/or control processing, the in-memory computing layer is formed on the side of the logic processing layer away from the silicon substrate, and the memory array layer is formed on the side of the in-memory computing layer away from the silicon substrate.
  • Figure 1 shows a schematic diagram of an MRAM memory cell
  • Figure 2 shows a schematic diagram of the structure of an SOT-MRAM memory cell
  • Figure 3 shows a schematic diagram of an STT-MRAM memory cell
  • Figure 4 shows a schematic diagram of the working principle of an in-memory computing array
  • Figure 5 shows a schematic diagram of the architecture of a data processing apparatus provided in at least one embodiment of the present disclosure
  • Figure 6 shows a schematic block diagram of a data processing apparatus provided in at least one embodiment of the present disclosure
  • Figure 7 shows a schematic diagram of a method for fabricating a magnetic random access storage device according to at least one embodiment of the present disclosure
  • Figure 8 shows a schematic flowchart of a method for preparing a magnetoresistive random access device according to at least one embodiment of this disclosure.
  • Figure 9 shows a schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure.
  • Figure 1 shows a schematic diagram of an MRAM memory cell.
  • Figure 1 shows an MRAM magnetic random access memory with a 2T1M (Two Transistor One Magnetic Tunnel Junction) structure, which includes two transistors (2T) and one MRAM memory device (1M).
  • 2T1M Tro Transistor One Magnetic Tunnel Junction
  • an exemplary MRAM memory device includes a heavy metal layer (HM), a free layer (FL), a barrier layer (TBL, such as magnesium oxide MgO), and a pinned layer (PL) stacked sequentially.
  • HM heavy metal layer
  • FL free layer
  • TBL barrier layer
  • PL pinned layer
  • the two transistors (2T) include a first transistor and a second transistor.
  • the first transistor is connected to the read word line (RWL) and the bit line (BL) to the pinned layer (PL) of the MRAM memory device.
  • the second transistor is connected to the write word line (WWL) and the bit line (BL) to the heavy metal layer (HM) of the MRAM memory device.
  • the bit line (BL) is connected to both the pinned layer (PL) and the heavy metal layer (HM) of the MRAM memory device via the two transistors.
  • the source line (SL) is connected to the heavy metal layer (HM) of the MRAM memory device.
  • the first transistor is configured to control data reading from the MRAM memory cell via the read word line (RWL), and the second transistor is configured to control data writing to the MRAM memory cell via the write word line (WWL).
  • the 2T1M structure of MRAM memory cells improves the reliability and selectivity of data access and reduces crosstalk between adjacent cells through dual transistor control and the magnetoresistance effect of magnetic tunnel junction. It achieves non-volatile, high-speed, and high-density storage, and effectively performs data reading and writing by finely controlling current and magnetic field, with good anti-interference ability and data stability.
  • FIG. 2 shows a schematic diagram of a SOT-MRAM memory cell.
  • the MRAM memory cell in a 2T1M memory cell based on SOT-MRAM (Spin-Orbit Torque Magnetic Random Access Memory), the MRAM memory cell includes a heavy metal layer (HM), a free layer (FL), a barrier layer (TBL), and a pinning layer (PL) stacked sequentially.
  • the bit line (BL) is connected to the heavy metal layer (HM) of the MRAM memory cell through a transistor, and the source line (SL) is connected to the heavy metal layer (HM) of the MRAM memory cell to provide read current or write current.
  • the read word line (RWL) is connected to the gate of the transistor connected between the bit line and the pinning layer (PL) of the MRAM memory cell
  • the write word line (WWL) is connected to the gate of the transistor connected between the bit line and the heavy metal layer (HM) of the MRAM memory cell.
  • the transistor controlled by the enable signal on the write word line, connects the bit line to the heavy metal layer (HM) of the MRAM memory device.
  • Current can be supplied through the bit line and source line to reverse the magnetization direction of the free layer.
  • the magnetization direction of the free layer can be switched.
  • the transistor controlled by the enable signal on the read word line, connects to the pinned layer (PL) of the MRAM memory device.
  • Current is supplied via the bit lines and source lines to prevent the magnetization direction of the free layer from flipping.
  • Data is then read by detecting the magnetization direction of the free layer.
  • the stored bit is 0; when the magnetization direction of the free layer is opposite to that of the pinned layer, the stored bit is 1.
  • FIG. 3 shows a schematic diagram of an STT-MRAM memory cell.
  • the MRAM memory device in an STT-MRAM (Spin-Transfer Torque Magnetic Random Access Memory) memory cell, the MRAM memory device includes a stacked free layer (FL), a barrier layer, and a pinned layer (PL).
  • the bit line (BL) is connected to the free layer of the MRAM memory device to provide read or write current;
  • the source line (SL) is connected to the pinned layer of the MRAM memory device through a transistor to provide read or write current;
  • the word line (WL) is connected to the gate of the transistor to select the cell to be read or written.
  • control signals on the word line can turn on transistors to provide corresponding current flowing through the MRAM memory device via the bit lines and source lines.
  • the resulting current component passes through the barrier layer, causing the magnetization direction of the free layer to flip.
  • the magnetization direction of the free layer can be flipped from top to bottom or from bottom to top. Therefore, different data can be written by changing the direction of the current.
  • transistors are turned on via control signals on the word lines to provide corresponding currents flowing through the MRAM memory device via the bit lines and source lines, ensuring that the magnetization direction of the free layer does not reverse.
  • the magnetization direction of the free layer is then determined by detecting voltage changes on the bit lines. If the magnetization direction of the free layer is the same as that of the pinned layer, the voltage on the bit line is lower; if the magnetization direction of the free layer is opposite to that of the pinned layer, the voltage on the bit line is higher. Therefore, the data stored in the MRAM memory device can be determined by reading the voltage on the bit lines.
  • FIG 4 illustrates a schematic diagram of the working principle of an in-memory computing array.
  • the in-memory computing array i.e., the memory computing array
  • the memristor units include memristors (such as resistive random access memory (RRAM), phase-change memory (PRAM), etc.).
  • This in-memory computing array can perform matrix-vector multiplication operations according to Kirchhoff's laws.
  • the data to be weighted matrix can be mapped to the resistance values of each memristor and written into the in-memory computing array.
  • the input vector is mapped to the input signal (voltage signal) of each row of the in-memory computing array, and the output signal (current signal) of each column is the product of the input voltage and the resistive random access conductance, which is the output vector.
  • I represents the output current of each column in the in-memory computing array
  • V represents the input voltage of each row in the in-memory computing array
  • G represents the conductance of the memristor in the memristor cell. Therefore, the aforementioned in-memory computing array can be used for neural network computation.
  • in-memory computing offers advantages such as faster processing speed, lower power consumption, and higher integration density.
  • In-memory computing integrates computational functions into storage units, reducing the frequent data transfer between data storage and computation modules and minimizing data transmission latency. Furthermore, by integrating computation and storage functions onto the same chip, it reduces the need for external connections and wiring, resulting in higher chip integration and enabling applications in smaller, thinner electronic devices.
  • Neural networks are a key technology in fields such as deep learning, requiring massive computational resources and extremely high efficiency. In-memory computing not only meets the computational demands of neural networks but also achieves high-performance computing under low power consumption conditions.
  • in-memory computing chips face technical challenges related to cache capacity and chip area, cache bandwidth, and single-precision computing.
  • a cache of at least 512 bits is required (i.e., for a 1k array, 0.5k data needs to be cached).
  • 6T-SRAM to achieve the same capacity cache, the number of transistors required in the cache is three times that of a memristor array (using a 1T1R structure), resulting in a cache area that significantly exceeds that of the in-memory computing array, thus limiting the integration density.
  • the cache capacity may need to be increased by another 2-3 times.
  • the memristor array and the cache are interconnected through a bus, which leads to bandwidth limitations. For example, for a 128bit/200MHz bus, only about three 32 ⁇ 32 arrays can be supported for parallel computing in one operation cycle, which restricts the overall computing efficiency of multi-memristor array chips.
  • MRAM based on binary magnetic tunnel junctions
  • advantages such as stability and unlimited erase/write cycles
  • At least one embodiment of this disclosure provides a data processing apparatus and a method for preparing the data processing apparatus.
  • the data processing device includes a logic processing layer, an in-memory computing layer, and a memory array layer.
  • the logic processing layer, in-memory computing layer, and memory array layer are at least partially stacked.
  • the logic processing layer is configured to perform logic operations and/or control processing.
  • the in-memory computing layer is configured to perform neural network operations on received data.
  • the memory array layer is configured to store data for the in-memory computing layer.
  • the memory array layer includes a memory array comprising multiple memory cells arranged in multiple rows and columns. Each memory cell includes a transistor and a magnetic random access memory device electrically connected to the transistor.
  • This data processing device integrates in-memory computing and back-end compatible transistor technologies, and in at least one embodiment, it can also be used to implement mixed-precision computing, breaking through the von Neumann bottleneck, significantly improving data processing efficiency and integration, and achieving a chip design that combines high computing power and versatility.
  • This data processing device can also be, for example, a chip, semiconductor device, or integrated circuit device employing three-dimensional integration technology; the embodiments disclosed herein are not limited in this regard.
  • Figure 5 shows a schematic block diagram of a data processing apparatus provided in at least one embodiment of the present disclosure.
  • the data processing apparatus may include a logic processing layer, an in-memory computing layer, and a storage array layer.
  • the logic processing layer, the in-memory computing layer, and the storage array layer are at least partially stacked.
  • the logic processing layer is configured to perform logical operations and/or control processing
  • the in-memory computing layer is configured to perform neural network operations on the received data
  • the storage array layer is configured to store data for the in-memory computing layer.
  • the logic processing layer can perform operations such as combining, comparing, and filtering on data from the in-memory computing layer, the storage array layer, or other input sources to generate new logic signals or data streams to support the corresponding data processing tasks.
  • data and/or control signals can be transmitted between the logic processing layer, the memory array layer, and the in-memory computing layer through interlayer metal interconnects.
  • the in-memory computing layer can perform neural network operations such as matrix multiplication on data received from external input or provided by the memory array layer, through the in-memory computing array (e.g., memristors) included within the in-memory computing layer. It can also perform operations such as convolution, pooling, and activation functions as needed. For example, refer to the description of the working principle of the in-memory computing array in the foregoing embodiments; it will not be repeated here.
  • the in-memory computing layer can significantly reduce data transfer overhead, thereby greatly improving computational efficiency, and is particularly suitable for large-scale parallel computing scenarios.
  • the in-memory computing layer may include at least one in-memory computing array, which includes at least one memristor array.
  • the memristor array may include multiple memristor cells arranged in multiple rows and columns, and each memristor cell includes a memristor and a switching element (e.g., a transistor).
  • the material structure of at least one of the memristors may include a stacked structure of TiN/HfAlO x /TaO x /TiN, TiN/HfO 2 /TaO x /TiN, TiN/HfO 2 /TiN, TiN/HfZrO x /TaO x /TiN, TiN/HfAlZrO x /TaO x /TiN, TiN/SiO 2 /TiN, or TiN/HfO x /TaO x /TiN, etc.
  • the embodiments of this disclosure are not limited to this.
  • X is not necessarily an integer, and the metal oxides may have different oxygen contents or oxygen ratios.
  • the oxygen content in each layer can be determined based on the amount of oxygen introduced during the manufacturing process.
  • the actual manufacturing process may include metal oxides with variable oxygen contents, such as a mixture of Ta 2O 5 and TaO, etc. The embodiments of this disclosure are not limited to this.
  • the storage array layer can cache the data used by the in-memory computing layer.
  • a memory array layer may include a memory array that may include multiple memory cells arranged in multiple rows and columns, each of the multiple memory cells may include a transistor and a magnetic random access memory (MRAM) device electrically connected to the transistor.
  • MRAM magnetic random access memory
  • a transistor can be configured to perform access control. By applying an appropriate control voltage signal to the gate of the transistor, the transistor can be precisely turned on or off, thereby performing operations on the connected MRAM memory device to read, write, or erase stored data.
  • the transistor may include at least one of carbon nanotube (CNT) transistors, indium oxide transistors, or low-temperature polycrystalline silicon (LTPS) transistors, and the embodiments disclosed herein are not limited thereto.
  • CNT carbon nanotube
  • LTPS low-temperature polycrystalline silicon
  • indium oxide transistors can include IGZO transistors, IGO transistors, or In2O3 transistors .
  • each of the multiple storage units may include a 2T1M storage unit.
  • the specific details of the 2T1M storage unit can be found in the description of the foregoing embodiments, and will not be repeated here.
  • multiple 2T1M storage cells arranged in multiple rows and columns can form a storage array, thereby forming a storage array layer.
  • magnetic random access memory devices may include spin-transfer torque magnetic random access memory devices (STT-MRAM) or spin-orbit torque magnetic random access memory devices (SOT-MRAM), and the embodiments disclosed herein are not limited thereto.
  • STT-MRAM spin-transfer torque magnetic random access memory devices
  • SOT-MRAM spin-orbit torque magnetic random access memory devices
  • the storage array layer can quickly and reliably store neural network model parameters, training data, or intermediate calculation results in the in-memory computing layer under the premise of high density and low power consumption, providing corresponding data storage support for the in-memory computing layer.
  • the magnetic random access storage device may include a first electrode layer, a free layer, a barrier layer (i.e., a tunneling layer), a pinning layer, and a second electrode layer stacked sequentially.
  • the first electrode layer can be a metal with a strong spin-orbit coupling effect (such as Pt, W, or Ta, or an alloy material).
  • the thickness of the first electrode layer can be, for example, 0–6 nm.
  • a free layer may include an antiferromagnetic layer and a ferromagnetic layer stacked sequentially (i.e., an antiferromagnetic/ferromagnetic exchange-coupled layer).
  • the antiferromagnetic layer in the free layer can also be used directly as the first electrode of the magnetic random access memory device.
  • the material of the antiferromagnetic layer in the free layer may include collinear antiferromagnetic materials (e.g., Mn2Au ), non-collinear antiferromagnetic materials (e.g., IrMn3 , PtMn3 , or Mn3Sn ), or spin-splitting antiferromagnetic materials (e.g., RuO2 , Mn5Si3 ), etc., and the embodiments of this disclosure are not limited thereto.
  • the film thickness of the antiferromagnetic layer in the free layer may , for example, be 4-8 nm.
  • the material of the ferromagnetic layer in the free layer may include CoFeB or Co materials, etc., and the embodiments of this disclosure are not limited thereto.
  • the film thickness of the ferromagnetic layer in the free layer may be, for example, 0.8-1.4 nm, to obtain perpendicular magnetic anisotropy, that is, the easy magnetization direction is perpendicular or approximately perpendicular to the film surface.
  • the antiferromagnetic layer exhibits zero magnetic moment due to the opposite alignment of adjacent magnetic moments.
  • the magnetization direction of the antiferromagnetic layer is extremely stable and not easily altered by external influences.
  • the magnetic moments within the ferromagnetic layer can align in the same direction, forming a net magnetic moment.
  • the magnetization direction of the ferromagnetic layer can be modulated by external stimuli (such as electric current or magnetic field).
  • the antiferromagnetic layer is in close contact with the ferromagnetic layer, an exchange coupling occurs between them, which is a direct magnetic interaction between adjacent magnetic moments. This interaction can cause the magnetization direction of the ferromagnetic layer to be pinned to a specific direction by the antiferromagnetic moment, generating an exchange bias magnetic field inside even in the absence of an external magnetic field.
  • the magnetization direction of the free layer can be stabilized in a specific state due to the constraint of the pinned layer (with a fixed magnetization direction) and the influence of the exchange bias magnetic field provided by the antiferromagnetic layer/ferromagnetic layer. For example, it can store a binary bit ("0" or "1").
  • the exchange bias magnetic field is generated within the free layer, the symmetry of the spin-orbit torque (SOT) magnetization reversal is broken.
  • SOT spin-orbit torque
  • the spin-orbit torque (SOT) generated by the current can more effectively drive the vertical magnetization direction of the ferromagnetic layer to reverse along that specific direction, rather than the aimless reversal that might occur without bias. This allows the magnetization reversal process of the free layer to be directionally controlled by the current direction, without relying on an external magnetic field.
  • a current in a specific direction is applied to the first electrode layer.
  • the strong spin-orbit coupling effect in the metal electrode material generates the SOT effect.
  • the SOT effect produces an effective torque within the ferromagnetic layer, acting on the magnetization vector and causing it to rotate. Due to the presence of the exchange bias magnetic field, the current only needs to overcome the coercivity of the ferromagnetic layer itself (i.e., the minimum energy required to maintain the magnetization state) to directionally flip the magnetization direction from one stable state to another, thus completing the data writing process.
  • the magnetization state can be determined by measuring the change in tunneling resistance between the free layer and the pinned layer.
  • the tunneling resistance is low, which can indicate that the stored binary bit is "0"; when the magnetization directions of the two layers are antiparallel (out of the same direction), the tunneling resistance is high, which can indicate that the stored binary bit is "1".
  • the free layer By introducing an antiferromagnetic/ferromagnetic exchange coupling layer, the free layer obtains a strong in-plane exchange bias magnetic field, which enables directional magnetization reversal to be achieved solely by current in the absence of an external magnetic field. This improves the operational efficiency of data storage, reduces power consumption, and enhances the adaptability of MRAM in specific application environments.
  • the material of the barrier layer can be an insulating layer, such as MgO, and the film thickness of the barrier layer can be 1-2 nm.
  • the pinning layer may include an artificial antiferromagnetic structure.
  • the pinning layer may include a ferromagnetic layer, a non-magnetic metal layer, a ferromagnetic layer, and an antiferromagnetic layer stacked sequentially.
  • the material of the ferromagnetic layer in the pinning layer may include CoFeB or Co materials, etc., and the embodiments of this disclosure are not limited thereto.
  • the film thickness of the ferromagnetic layer in the pinning layer may be, for example, 0.8-1.4 nm.
  • the material of the antiferromagnetic layer in the pinning layer may include IrMn3 or PtMn3 , etc., and the embodiments disclosed herein are not limited thereto.
  • the film thickness of the antiferromagnetic layer in the pinning layer may, for example, be 5-10 nm.
  • the material of the non-magnetic metal layer in the pinning layer may include Ru or Ta, etc., and the embodiments of this disclosure are not limited thereto.
  • the film thickness of the non-magnetic metal layer in the pinning layer may be, for example, 0.4-1.5 nm.
  • the easy magnetization axis of the free layer and the pinned layer can be perpendicular or approximately perpendicular to the film surface of the free layer and the pinned layer.
  • the material of the second electrode can include metallic materials such as Pt, W, or Ta, or alloy materials.
  • the film thickness of the second electrode can be, for example, 5-20 nm.
  • the actual film thickness may have an error of 5-10 nm.
  • the film thickness of the second electrode can also range from 1-30 nm.
  • the magnetic random access storage device includes a magnetic tunnel junction (MTJ).
  • MTJ magnetic tunnel junction
  • a magnetic tunnel junction can consist of a series of stacked ferromagnetic layers, an insulating layer, and another ferromagnetic layer.
  • An insulating layer e.g., a tunnel barrier layer
  • two ferromagnetic layers e.g., one ferromagnetic layer with a fixed magnetization direction, and the other with a switchable magnetization direction.
  • the magnetization directions of the two ferromagnetic layers are parallel, electrons can efficiently tunnel through the insulating layer, resulting in a low-resistance state.
  • the tunneling effect weakens, resulting in a high-resistance state. This change in resistance can correspond to the storage of binary data "0" and "1".
  • the inventors of this disclosure have noted that the surface roughness of the in-memory computing layer can affect the performance of magnetic random access memory (MRAM) devices.
  • MRAM magnetic random access memory
  • a rough surface of the in-memory computing layer can lead to structural inhomogeneities in the magnetic tunnel junction (MTJ), affecting the precise control of electron tunneling efficiency, magnetic anisotropy, or spin-orbit torque effects, thereby impacting key performance indicators of MRAM devices such as stability, read/write speed, power consumption, and data retention capabilities.
  • MRAM magnetic random access memory
  • a location with a root mean square roughness (RMS) of less than or equal to 1 nanometer (or 0.2 nanometer) on the surface of the memory computing layer can be selected to ensure the high-performance operation of the MRAM magnetic tunnel junction.
  • RMS root mean square roughness
  • the memristors in the in-memory computing layer can be placed in offset positions from the magnetic tunnel junctions of the MRAM.
  • staggering the magnetic tunnel junctions of the memristor and MRAM helps avoid mutual process interference, ensuring high-quality manufacturing of each device. It also ensures that the magnetic tunnel junction is positioned within a specific region that meets its surface roughness requirements, while the memristor can be integrated into a suitable region based on its surface quality requirements. Furthermore, since both the memristor and MRAM generate electric and magnetic fields during operation, although both are non-volatile, their electrical behavior may interfere with each other if they are too close, leading to read/write errors, signal crosstalk, or increased power consumption. Therefore, staggering the magnetic tunnel junctions of the memristor and MRAM avoids direct electrical coupling, maintaining the independence of their read/write operations and data integrity.
  • the memristor and MRAM have different heat dissipation requirements, they may generate different heat distributions during data read/write operations. Staggering their positions also helps optimize thermal management, prevent the formation of localized hot spots, and maintain the stability and reliability of the data processing device. Furthermore, staggering the magnetic tunnel junctions of memristors and MRAMs allows for more flexible layout of the data processing device, enabling space to be allocated rationally according to the needs of each circuit layer and process limitations, which helps to improve the integration density of the data processing device.
  • Figure 6 shows a schematic block diagram of a data processing apparatus provided in at least one embodiment of the present disclosure.
  • the data processing apparatus 100 may include a logic processing layer 101, an in-memory computing layer 102, and a memory array layer 103.
  • the logic processing layer 101, the in-memory computing layer 102, and the memory array layer 103 are at least partially stacked.
  • the logic processing layer 101 can be disposed on the silicon substrate
  • the in-memory computing layer 102 can be disposed on the side of the logic processing layer 101 away from the silicon substrate
  • the memory array layer 103 can be disposed on the side of the in-memory computing layer 102 away from the silicon substrate.
  • the data processing device 100 also includes an interlayer medium layer disposed between the logic processing layer 101, the in-memory computing layer 102 and the storage array layer 103.
  • the interlayer medium layer includes a plurality of vias, and the logic processing layer 101, the in-memory computing layer 102 and the storage array layer 103 communicate through the plurality of vias.
  • an interlayer medium 1 is provided between the logic processing layer 101 and the in-memory computing layer 102
  • an interlayer medium 2 is provided between the in-memory computing layer 102 and the storage array layer 103.
  • the logic processing layer 101 can be configured to perform logic operations and/or control processing
  • the in-memory computing layer 102 can be configured to perform neural network operations on the received data
  • the memory array layer 103 can be configured to store data for the in-memory computing layer.
  • the logic processing layer 101 can perform operations such as combining, comparing, and filtering on data from the in-memory computing layer 102, the storage array layer 103, or other input sources to generate new logic signals or data streams to support the corresponding data processing tasks.
  • the in-memory computing layer 102 may include at least one in-memory computing array, each of which includes at least one memristor array, and the memristor array may include multiple memristors arranged in multiple rows and columns.
  • the memory array layer 103 may include a memory array that may include multiple memory cells arranged in multiple rows and columns, each of the multiple memory cells may include a transistor and a magnetic random access memory device electrically connected to the transistor.
  • transistors and magnetic random access memory devices can be arranged in a stacked manner in the memory array layer 103, or they can be arranged in a planar manner in the memory array layer 103.
  • the embodiments of this disclosure through the stacked design of the logic processing layer 101, the in-memory computing layer 102, and the storage array layer 103, not only help to reduce the size of the data processing device and improve the integration, but also reduce the data transmission distance and latency between each circuit layer and improve the data processing speed.
  • At least one embodiment of this disclosure also provides a method for fabricating a data processing device.
  • the method includes: fabricating an in-memory computing layer using a semiconductor fabrication process and fabricating a memory array layer at least partially stacked with the in-memory computing layer, wherein the memory array layer includes a memory array, the memory array including a plurality of memory cells arranged in multiple rows and columns, each of the plurality of memory cells including a transistor and a magnetic random access memory device electrically connected to the transistor.
  • an in-memory computing layer is fabricated using semiconductor fabrication technology
  • a memory array layer is fabricated using semiconductor fabrication technology, wherein the memory array layer and the in-memory computing layer are at least partially stacked.
  • an in-memory computing array in an in-memory computing layer is fabricated using semiconductor fabrication technology.
  • Each in-memory computing array includes at least one memristor array, and the memristor array includes multiple memristors arranged in multiple rows and columns.
  • transistors can be fabricated first and then magnetic random access memory devices can be fabricated, or magnetic random access memory devices can be fabricated first and then transistors can be fabricated.
  • the embodiments of this disclosure do not limit the order of fabrication of magnetic random access memory devices and transistors.
  • a low-temperature back-end transistor fabrication process can be used, for example.
  • the fabrication temperature can be, for example, a low-temperature process of 300 degrees Celsius or less (or 400 degrees Celsius).
  • the transistor can, for example, include at least one of carbon nanotube transistors, indium oxide transistors, or low-temperature polycrystalline silicon transistors.
  • the method for fabricating the data processing device further includes providing a silicon substrate, fabricating a logic processing layer on the silicon substrate using a semiconductor fabrication process, forming an in-memory computing layer on the side of the logic processing layer away from the silicon substrate, and forming a memory array layer on the side of the in-memory computing layer away from the silicon substrate.
  • the logic processing layer can be fabricated using CMOS logic circuit fabrication technology (or silicon-based CMOS technology) to manufacture CMOS transistors and other components to create the logic processing circuit.
  • CMOS logic circuit fabrication technology or silicon-based CMOS technology
  • fabricating a magnetic random access memory (MRMH) device in a memory array layer may include fabricating a mask to define a patterned region of the MRMH device and using the mask to fabricate a magnetic tunnel junction.
  • MRMH magnetic random access memory
  • a mask may include a photoresist mask or a hard mask.
  • the material of the mask can include metal or an insulating medium.
  • a hard mask can be prepared using a double-layer photoresist through photolithography, deposition of metal or insulating medium, and a stripping process to define the patterned area of the magnetic random access memory device.
  • a two-layer adhesive process can be used to define the pattern of the magnetic tunnel junction region.
  • a base adhesive and a top adhesive can be sequentially coated on the substrate where the magnetic tunnel junction region is prepared.
  • the base adhesive is patterned into a predetermined shape, wherein the top adhesive, after processing, can form a partially suspended "eaves" structure above the edge of the pattern defined by the base adhesive.
  • an insulating medium can be deposited, and then the photoresist can be dissolved and stripped away by soaking in a photoresist remover. The insulating medium attached above the photoresist can also be stripped away, thereby creating interconnects for a magnetic tunnel junction.
  • the undercoat refers to the photoresist first coated on the substrate of the magnetic tunnel junction region
  • the topcoat refers to the photoresist coated on top of the undercoat
  • various micro- and nano-sized photoresist masks can be prepared by methods such as ultraviolet lithography, direct write lithography (DWL), electron beam lithography (EBL), and ion beam lithography (IBL).
  • DWL direct write lithography
  • EBL electron beam lithography
  • IBL ion beam lithography
  • a double-layer photoresist mask can also be fabricated using a double-layer photoresist process, where a top resist is applied to the substrate in the magnetic tunnel junction region to form a double-layer photoresist mask with an upper suspended layer.
  • a dry etching process can be used to etch areas outside the patterned regions of the magnetic random access memory (MRMemory) device to preserve the patterned regions of the MRMemory device.
  • MRMemory magnetic random access memory
  • the dry etching process used in the embodiments of this disclosure may include: ion beam etching (IBE), atomic layer etching (ALE), reactive ion etching (RIE), or inductively coupled plasma etching (ICP), etc.
  • IBE ion beam etching
  • ALE atomic layer etching
  • RIE reactive ion etching
  • ICP inductively coupled plasma etching
  • Figure 7 illustrates a schematic diagram of a method for fabricating a magnetic random access memory device according to at least one embodiment of this disclosure.
  • the magnetic tunnel junction can first be etched using a vertical angular component, for example, a larger angle can be used for etching (e.g., the ion beam is at a 60-degree angle to the surface of the magnetic tunnel junction). This can quickly remove most of the material to be etched, but this step may still produce a certain amount of burrs.
  • sidewall angular component etching is performed, for example, etching at a smaller angle (e.g., the ion beam is at a 30-degree angle to the magnetic tunnel junction surface).
  • the ion beam bombardment of the sidewalls is more effective, which can specifically remove the burrs generated during the previous etching process, while further smoothing the sidewalls.
  • the etching can be paused and the sample allowed to cool for a period of time (e.g., 3 minutes). Cooling can help reduce the probability of secondary sputtering of material due to thermal effects during the etching process, and it is also beneficial to the stability of the sample structure and prevents morphology deterioration caused by overheating.
  • the etching steps at the two angles shown in Figure 7 can be repeated several times to gradually optimize the surface quality and sidewall morphology of the magnetic tunnel junction until the desired etching effect is achieved.
  • variable-angle etching technology can effectively reduce or even eliminate burrs at the top edge of the magnetic tunnel junction, improving the device's flatness, insulation, and magnetoresistance change rate, thereby enhancing the overall device performance and yield.
  • the etching characteristics of the ion beam at different angles and its effect on removing burrs are cleverly utilized, achieving precise control over the magnetic tunnel junction fabrication process.
  • fabricating a magnetic random access memory device further includes: selecting a region on the surface of the internal computing layer with a root mean square roughness of less than 1 nm or 0.2 nm to arrange a magnetic tunnel junction, and placing the magnetic tunnel junction at a position offset from the memristor.
  • a polishing operation e.g., chemical mechanical polishing (CMP)
  • CMP chemical mechanical polishing
  • the undulations of the in-memory computing layer are removed to ensure extremely low surface roughness (e.g., root mean square roughness below 1 nm, or even below 0.2 nm).
  • CMOS transistors and other components can be fabricated on a silicon substrate using CMOS logic circuit fabrication technology (or silicon-based CMOS technology) to prepare logic processing circuits.
  • CMOS logic circuit fabrication technology or silicon-based CMOS technology
  • the RRAM in-memory computing layer can be fabricated using a low-temperature (e.g., less than or equal to 400 degrees Celsius) back-end integration process.
  • a low-temperature (e.g., less than or equal to 400 degrees Celsius) back-end integration process e.g., an exemplary method for fabricating a memory computing circuit layer may include the following steps:
  • the stack is selectively etched using photolithography and dry etching processes to achieve the patterning of the resistive random access memory device.
  • a layer of tungsten (W) is deposited by electroplating, and then chemical mechanical polishing is used to grind the W clean except for the SiO2 pores (forming metal vias).
  • FIG 8 shows a schematic flowchart of a method for fabricating a magnetoresistive random access memory (MRAM) cell according to at least one embodiment of the present disclosure. As shown in Figure 8, the method for fabricating the MRAM memory device may include steps S210-S250.
  • MRAM magnetoresistive random access memory
  • a multilayer thin film stack consisting of an insulating dielectric layer, a first electrode layer, a free layer, a barrier layer, a pinned layer, and a second electrode layer can be deposited sequentially using techniques such as magnetron sputtering or molecular beam epitaxy (MBE).
  • MBE molecular beam epitaxy
  • the material of the first electrode layer can include metals with strong spin-orbit coupling effects (such as Pt, W, Ta, or alloys), and the film thickness of the first electrode layer can be 0-6 nm; for example, the antiferromagnetic layer in the free layer can be used as the first electrode layer.
  • metals with strong spin-orbit coupling effects such as Pt, W, Ta, or alloys
  • the film thickness of the first electrode layer can be 0-6 nm; for example, the antiferromagnetic layer in the free layer can be used as the first electrode layer.
  • the free layer may comprise an exchange-coupled layer formed by sequentially stacked antiferromagnetic and ferromagnetic layers.
  • the ferromagnetic layer material may be CoFeB or Co, and its thickness may be 0.8-1.4 nm.
  • the antiferromagnetic layer material in the free layer may include collinear antiferromagnetic materials (e.g., Mn2Au ), non-collinear antiferromagnetic materials (e.g., IrMn3 , PtMn3 , or Mn3Sn ), or spin-splitting antiferromagnetic materials (e.g., RuO2 , Mn5Si3 ), etc.
  • the thickness of the antiferromagnetic layer in the free layer may be, for example, 4-8 nm.
  • the barrier layer can be made of an insulating material, such as MgO.
  • the thickness of the barrier layer can be 1-2 nm.
  • the pinning layer may include an artificial antiferromagnetic structure.
  • the pinning layer may include a ferromagnetic layer, a non-magnetic metal layer, a ferromagnetic layer, and an antiferromagnetic layer stacked sequentially.
  • the material of the ferromagnetic layer in the pinning layer may include CoFeB or Co, etc.
  • the film thickness of the ferromagnetic layer in the pinning layer may be, for example, 0.8-1.4 nm.
  • the material of the antiferromagnetic layer in the pinning layer may include IrMn3 or PtMn3, etc.
  • the film thickness of the antiferromagnetic layer in the pinning layer may be, for example, 5-10 nm.
  • the material of the non-magnetic metal layer in the pinning layer may include Ru or Ta, etc.
  • the film thickness of the non-magnetic metal layer in the pinning layer may be, for example, 0.4-1.5 nm.
  • the material of the second electrode may include metals such as Pt, W, or Ta, or alloys.
  • the film thickness of the second electrode may be, for example, 5-20 nm.
  • various micro- and nano-sized photoresist masks can be fabricated using processes such as ultraviolet lithography, laser direct writing, electron beam lithography, and ion beam lithography.
  • a hard mask can be fabricated using a double-layer photoresist layer through photolithography, deposition, and lift-off processes to define the patterned regions of the MRAM.
  • Another approach is to use a double-layer photoresist layer process to fabricate the photoresist mask, where the top resist forms a partially suspended magnetic tunnel junction structure on the bottom resist layer.
  • dry etching processes such as ion beam etching, atomic layer etching, reactive ion etching, or inductively coupled plasma etching are used to etch away the areas outside the MRAM pattern, preserving the MRAM patterned regions. It is important to note that if a photoresist mask is used to fabricate the magnetic tunnel junction, the photoresist mask must be removed at the end.
  • insulating layer e.g., silicon oxide SiO2 or aluminum oxide Al2O3 thin film
  • photolithography can be used to define the opening area pattern of the second electrode and the first electrode, and then dry etching or wet etching can be used to etch the insulating layer to complete the opening, expose the connection hole of the two first electrodes and the first electrode, form the interconnect connection point, and finally remove the photoresist.
  • a conductive layer such as tungsten (W) can be deposited using electroplating or chemical vapor deposition. Then, chemical mechanical polishing (CMP) is used for planarization, cleaning away the conductive layer (e.g., tungsten W) outside the opening, leaving only the conductive layer inside the opening, thus forming a metal via. Next, physical vapor deposition (PVD) is used to deposit a conductive layer, such as aluminum (Al). Finally, dry etching processes such as photolithography or integrated circuit etching (ICP) are used to selectively etch the conductive layer (Al) to form conductive interconnects.
  • CMP chemical mechanical polishing
  • PVD physical vapor deposition
  • ICP integrated circuit etching
  • a double-layer photoresist lithography process can be used to define the wire region pattern first, enabling conductive interconnection between the MRAM second and first electrodes and external devices or circuits. Because this photolithography uses a double-layer photoresist process, the top resist forms a double-layer photoresist structure with suspended edges on the bottom resist of the magnetic tunnel junction. Subsequently, a conductive layer (such as gold (Au), platinum (Pt), palladium (Pd), aluminum (Al), copper (Cu), tungsten (W), or titanium nitride (TiN)) is deposited using electron beam evaporation or magnetron sputtering.
  • an adhesion layer such as titanium (Ti), chromium (Cr), or tantalum (Ta)
  • Ti titanium
  • Cr chromium
  • Ta tantalum
  • the thickness of the deposited conductive layer can, for example, be less than half the thickness of the bottom resist.
  • the conductive layer regions supported by the photoresist can be removed in acetone or other resist-removing solutions, retaining the conductive layer pattern without photoresist. Furthermore, this step can be aided by prolonged immersion, ultrasonic treatment, or heating.
  • an annealing operation is required to crystallize the MgO barrier layer, improve the interface quality between the ferromagnetic layer and the barrier layer, and thus increase the magnetoresistance of the tunnel junction.
  • This annealing operation can be performed, for example, in a high-temperature combined magnetic field environment.
  • the annealing temperature can be set to, for example, 200-350 degrees Celsius
  • the magnetic field direction can be set to the easy axis direction of the SOT-MRAM free layer, for example, perpendicular (or approximately perpendicular) to the thin film surface.
  • the magnetic field strength can be set, for example, to 500-10000 Oersted.
  • the transistor used for MRAM in step (5) above can be fabricated using a low-temperature (less than or equal to 400 degrees Celsius) back-end integration method.
  • the channel material of the transistor can include semiconductor channel materials such as carbon nanotubes, indium gallium zinc oxide, low-temperature polycrystalline silicon, and indium oxide ( In2O3 ) .
  • the fabrication method of carbon nanotube transistors may include the following steps:
  • a metal target Pd is deposited using photolithography and electron beam evaporation deposition, and then stripped to form a pattern, which serves as the back gate structure of a carbon nanotube transistor.
  • a layer of carbon nanotubes is deposited using a wet transfer process.
  • Photolithography is used to deposit 80nm Pd by electron beam evaporation, and then the pattern is stripped to form the source and drain electrodes of the carbon nanotube transistor.
  • Atomic layer deposition was used to grow 45nm Al2O3 as a passivation layer .
  • a metal interconnect pattern is formed by using a subsequent passivation process and a metal interconnect process.
  • Figure 9 shows a schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure.
  • the electronic device 300 includes a data processing device 400.
  • the data processing device 400 can be any of the data processing device devices provided in the above embodiments.
  • the electronic device 300 may further include other devices, such as a central processing unit (CPU), a data bus, memory, etc.
  • the electronic device 300 can be a signal processing device, a computing device, etc., and can be used as a controller, terminal device, or server device, etc.

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Abstract

一种数据处理装置、电子装置和数据处理装置的制备方法。该数据处理装置包括逻辑处理层、存内计算层和存储阵列层。其中，逻辑处理层、存内计算层和存储阵列层至少部分层叠；逻辑处理层被配置为进行逻辑运算和/或控制处理；存内计算层被配置为对接收的数据进行神经网络运算，存储阵列层被配置为存储用于存内计算层的数据；存储阵列层包括存储阵列，存储阵列包括排列为多行多列的多个存储单元，多个存储单元每个包括晶体管以及与晶体管电连接的磁随机存储器件。该数据处理装置可以提高数据处理效率以及集成度。

Description

数据处理装置、电子装置和数据处理装置的制备方法
本申请要求于2024年5月29日递交的中国专利申请第202410683155.3号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种数据处理装置、电子装置和数据处理装置的制备方法。
背景技术
忆阻器存算一体系统可有效执行神经网络中的矩阵-向量乘法，但输入输出数据需缓存，其搬运效率成为性能瓶颈。缓存带宽受限于二维集成架构下的总线互连，因此一次运算时间内传输效率较低，导致并行计算能力受限，即使通过多级总线优化，仍受二维连接低效制约。此外，传统忆阻器芯片基于模拟阻变特性，虽有多电阻状态可用于模拟计算，但受制于非理想特性(如电导漂移、随机性大或擦写次数有限等)的影响，难以实现高精度计算。
发明内容
本公开至少一个实施例提供一种数据处理装置，包括：逻辑处理层、存内计算层和存储阵列层，其中，所述逻辑处理层、所述存内计算层和所述存储阵列层至少部分层叠；所述逻辑处理层被配置为进行逻辑运算和/或控制处理；所述存内计算层被配置为对接收的数据进行神经网络运算，所述存储阵列层被配置为存储用于所述存内计算层的数据；所述存储阵列层包括存储阵列，所述存储阵列包括排列为多行多列的多个存储单元，所述多个存储单元每个包括晶体管以及与所述晶体管电连接的磁随机存储器件。
例如，在本公开一实施例提供的数据处理装置中，所述磁随机存储器件包括依次层叠设置的第一电极层、自由层、势垒层、钉扎层和第二电极层。
例如，在本公开一实施例提供的数据处理装置中，所述自由层包括依次层叠的反铁磁层和铁磁层。
例如，在本公开一实施例提供的数据处理装置中，所述存内计算层包括至少一个存内计算阵列，所述存内计算阵列每个包括至少一个忆阻器阵列，所述忆阻器阵列包括排列为多行多列的多个忆阻器；所述磁随机存储器件包括磁性隧道结，所述磁性隧道结与所述忆阻器错开位置放置。
例如，在本公开一实施例提供的数据处理装置中，所述晶体管包括碳纳米管晶体管、铟基氧化物晶体管或低温多晶硅晶体管中的至少一种。
例如，在本公开一实施例提供的数据处理装置中，所述磁随机存储器件包括自旋转移力矩磁随机存储器件或自旋轨道矩磁随机存储器件。
本公开至少一个实施例提供一种电子装置，包括本公开任一实施例提供的数据处理装置。
本公开至少一个实施例提供一种数据处理装置的制备方法，包括：采用半导体制备工艺制备存内计算层和制备与所述存内计算层至少部分层叠设置的存储阵列层，其中，所述存内计算层被配置为对接收的数据进行神经网络运算，所述存储阵列层被配置为存储用于所述存内计算层的数据；所述存储阵列层被配置为存储用于所述存内计算层的数据，所述存储阵列层包括存储阵列，所述存储阵列包括排列为多行多列的多个存储单元，所述多个存储单元每个包括晶体管以及与所述晶体管电连接的磁随机存储器件。
例如，在本公开一实施例提供的制备方法中，所述制备磁随机存储器件包括：制备掩膜以定义出所述磁随机存储器件的图形区域，其中，所述掩膜包括光刻胶掩膜或硬掩膜；使用所述掩模制备磁性隧道结。
例如，在本公开一实施例提供的制备方法中，所述制备掩膜以定义出所述磁随机存储器件的图形区域，包括：采用双层胶工艺定义出所述磁性隧道结区域的图形。
例如，在本公开一实施例提供的制备方法中，所述使用所述掩模制备磁性隧道结，包括：通过干法刻蚀工艺，对所述磁随机存储器件的图形区域之外的其他区域进行刻蚀，以保留所述磁随机存储器件的图形区域。
例如，在本公开一实施例提供的制备方法中，所述存内计算层包括至少一个存内计算阵列，所述存内计算阵列每个包括至少一个忆阻器阵列，所述忆阻器阵列包括排列为多行多列的多个忆阻器；所述制备磁随机存储器件，还包括：选择所述忆阻器表面的均方根粗糙度小于1nm或0.2nm的区域布置磁性隧道结，并将所述磁性隧道结与所述忆阻器错开位置放置。
例如，本公开一实施例提供的制备方法，还包括：提供硅衬底；在所述硅衬底上采用半导体制备工艺制备逻辑处理层，其中，所述逻辑处理层被配置为进行逻辑运算和/或控制处理，所述存内计算层形成在所述逻辑处理层远离硅衬底的一侧，所述存储阵列层形成在所述存内计算层远离硅衬底的一侧。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1示出了一种MRAM存储单元的结构示意图；
图2示出了一种SOT-MRAM存储单元的结构示意图；
图3示出了一种STT-MRAM存储单元的结构示意图；
图4示出了一种存内计算阵列的工作原理示意图；
图5示出了本公开至少一个实施例提供的一种数据处理装置的架构示意图；
图6示出了本公开至少一个实施例提供的一种数据处理装置的示意框图；
图7示出了本公开至少一个实施例提供的一种磁随机存储器件的制备方法示意图；
图8示出了本公开至少一个实施例提供的一种磁阻随机存取的制备方法的流程示意图；以及
图9示出了本公开至少一个实施例提供的一种电子装置的示意框图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1示出了一种MRAM存储单元的结构示意图。图1示出了具有2T1M(Two Transistor One Magnetic Tunnel Junction)结构的MRAM磁随机(Magnetic Random Access Memory)，该2T1M存储单元包括2个晶体管(2T)和1个MRAM存储器件(1M)。
如图1所示，示例性的MRAM存储器件包括依次层叠的重金属层(HM，Heavy Metal Layer)、自由层(FL，Free Layer)、势垒层(TBL，Tunnel Barrier Layer，例如氧化镁MgO)、钉扎层(PL，Pinned Layer)。
两个晶体管(2T)包括第一晶体管和第二晶体管，其中，第一晶体管连接读取字线(RWL，Read Word Line)，且连接位线(BL)与MRAM存储器件的钉扎层(PL)，第二晶体管连接写入字线(WWL，Write Word Line)，且连接位线(BL)与MRAM存储器件的重金属层(HM)，由此位线(BL，Bit Line)分别通过两个晶体管与MRAM存储器件的钉扎层(PL)以及重金属层(HM)连接，源线(SL，Source Line)与MRAM存储器件的重金属层(HM)连接。第一晶体管被配置为由读取字线(RWL)控制MRAM存储单元的数据读取，第二晶体管被配置为由写入字线(WWL)控制MRAM存储单元的数据写入。
2T1M结构的MRAM存储单元通过双晶体管控制与磁隧道结磁电阻效应，可以提升数据访问的可靠性与选择性，减少相邻单元串扰，实现非易失性、高速、高密度存储，通过精细调控电流和磁场有效进行数据读写，具备良好抗干扰能力和数据稳定性。
图2示出了一种SOT-MRAM存储单元的结构示意图。如图2所示，在基于SOT-MRAM(Spin-Orbit Torque Magnetic Random Access Memory，自旋轨道矩磁随机存储器件)的2T1M存储单元中，MRAM存储器件包括依次层叠的重金属层(HM)、自由层(FL)、势垒层(TBL)、钉扎层(PL)，位线(BL)通过晶体管与MRAM存储器件的重金属层(HM)相连，源线(SL)与MRAM存储器件的重金属层(HM)相连，用于提供读取电流或写入电流；读取字线(RWL)与连接在位线和MRAM存储器件的钉扎层(PL)之间的晶体管的栅极连接，写入字线(WWL)与连接在位线和MRAM存储器件的重金属层(HM)之间的晶体管的栅极连接。
在写入操作中，晶体管在写入字线上的开启信号的控制下将位线与MRAM存储器件的重金属层(HM)的连接，可以通过位线和源线提供相应的电流，使得自由层的磁化方向发生翻转。通过调节电流的方向和大小，可以实现自由层磁化方向的切换。当自由层的磁化方向与钉扎层的磁化方向一致时，表示写入的比特为0；当自由层的磁化方向与钉扎层的磁化方向相反时，表示写入的比特为1。
在读取操作中，晶体管在读取字线上的开启信号的控制下与MRAM存储器件的钉扎层(PL)的连接，可以通过位线和源线提供相应的电流，使得自由层的磁化方向不会翻转。然后，通过检测自由层的磁化方向来读取数据。当自由层的磁化方向与定扎层的磁化方向一致时，表示存储的比特为0；当自由层的磁化方向与定扎层的磁化方向相反时，表示存储的比特为1。
图3示出了一种STT-MRAM存储单元的结构示意图。如图3所示，在STT-MRAM(Spin-Transfer Torque Magnetic Random Access Memory，自旋转移力矩磁随机存储器件)存储单元中，MRAM存储器件包括层叠的自由层(FL)、势垒层、钉扎层(PL)，位线(BL)与MRAM存储器件的自由层相连，用于提供读取或写入电流；源线(SL)通过晶体管与MRAM存储器件的钉扎层相连，用于提供读取或写入电流；字线(WL)晶体管的栅极连接，用于选择要读取或写入的单元。
在写入操作中，可以通过字线上控制信号控制晶体管导通，以通过位线和源线提供流过MRAM存储器件的相应的电流，产生的电流分量通过势垒层，使得自由层的磁化方向翻转。可以根据电流的方向，使得自由层的磁化方向从上向下翻转，或者从下向上翻转。因此，可以通过改变电流的方向来写入不同的数据。
在读取操作中，可以通过字线上控制信号控制晶体管导通，以通过位线和源线提供流过MRAM存储器件的相应的电流，使得自由层的磁化方向不会翻转。然后，通过检测位线上的电压变化来确定自由层的磁化方向。如果自由层的磁化方向与钉扎层的磁化方向相同，则位线上的电压较低；如果自由层的磁化方向与钉扎层的磁化方向相反，则位线上的电压较高。因此，可以通过读取位线上的电压来确定存储在MRAM存储器件中的数据。
图4示出了一种存内计算阵列的工作原理示意图。如图4所示，存算一体阵列(即存内计算阵列)包括呈行列布置的忆阻器单元，忆阻器单元包括忆阻器(例如阻变存储器件(RRAM)、相变存储器件(PRAM)等)，该存算一体阵列可以根据基尔霍夫定律，完成矩阵-向量乘的运算过程。可以将待权重矩阵数据映射为各个忆阻器的阻值并写入存算一体阵列中，输入向量被映射为存算一体阵列各行的输入信号(电压信号)，各列的输出信号(电流信号)，即为输入电压与阻变电导的乘积，为输出向量，即：
∑I＝∑V*G，
其中，I表示存算一体阵列中各列的输出电流，V表示存算一体阵列中各行的输入电压，G表示忆阻器单元中的忆阻器的电导。由此，上述存算一体阵列可以用于神经网络计算。
与冯·诺依曼架构相比，存内计算架构具有运算速度快、功耗低、集成密度高等优势，存内计算将计算功能融入存储单元，减少了数据在数据存储模块和计算模块之间的频繁搬运，也减少了数据传输的延迟，此外，存内计算将计算和存储功能集成在同一芯片上，减少了外部连接和布线的需求，使得芯片的集成度更高，可以应用于更小、更轻薄的电子设备。神经网络是深度学习等领域的关键技术，其计算量巨大且对计算效率要求极高，存内计算不仅能够满足神经网络的计算需求，还能在低功耗的条件下实现高性能的计算。
但是，本公开的发明人注意到，存算一体芯片面临着缓存容量与芯片面积、缓存带宽以及单一精度计算的技术问题，例如对于32×32存内计算阵列，所需缓存至少为512bit(即对于1k阵列，需要缓存0.5k数据)，而采用6T-SRAM实现同等容量缓存，缓存中所需的晶体管数量是忆阻器阵列(采用1T1R结构)的三倍，从而导致缓存的面积显著大大超过存内计算阵列，限制了集成度。
并且，实际应用中，考虑到神经网络中残差连接的需求，缓存容量可能还需要再扩大2-3倍。此外，二维集成方式下，忆阻器阵列与缓存通过总线互连，导致带宽受限，例如，对于一个128bit/200MHz总线，一次运算周期内仅能支持约3个32×32阵列的并行计算，制约了多忆阻器阵列芯片的整体计算效率。
此外，本公开的发明人还注意到，忆阻器芯片基于模拟阻变特性，虽然能实现多电阻状态以完成模拟计算，但由于非理想特性(如电导漂移、随机性或擦写次数限制等)的影响，难以进行高精度计算。而MRAM基于二值磁隧道结，虽具有稳定、无限擦写次数等优点，但仅能实现两电阻态，虽适合高精度计算，而不适合高算力矩阵计算。因此，如何构建混合精度高算力芯片成为亟待解决的问题。
本公开至少一个实施例提供了一种数据处理装置以及提供一种该数据处理装置的制备方法。
该数据处理装置包括逻辑处理层、存内计算层和存储阵列层。其中，逻辑处理层、存内计算层和存储阵列层至少部分层叠；逻辑处理层被配置为进行逻辑运算和/或控制处理；存内计算层被配置为对接收的数据进行神经网络运算，存储阵列层被配置为存储用于存内计算层的数据；存储阵列层包括存储阵列，存储阵列包括排列为多行多列的多个存储单元，多个存储单元每个包括晶体管以及与晶体管电连接的磁随机存储器件。该数据处理装置融合存内计算与后道兼容晶体管等技术，并且在至少一个实施例中还可以用于实现混合精度计算，突破了冯·诺伊曼瓶颈，大幅提高数据处理效率与集成度，实现高算力与通用性兼备的芯片设计。该数据处理装置例如还可以为采用三维集成技术的芯片、半导体器件、集成电路装置等，本公开的实施例对此并不限制。
下面结合附图对本公开的实施例进行详细说明，但是，本公开并不限于这些具体的实施例。
图5示出了本公开至少一个实施例提供的数据处理装置的示意框图。
在本公开的一些实施例中，如图5所示，数据处理装置可以包括逻辑处理层、存内计算层以及存储阵列层。逻辑处理层、存内计算层和存储阵列层至少部分层叠。逻辑处理层被配置为进行逻辑运算和/或控制处理，存内计算层被配置为对接收的数据进行神经网络运算，存储阵列层被配置为存储用于存内计算层的数据。
例如，逻辑处理层可以对来自存内计算层、存储阵列层或者其他输入源的数据进行组合、比较、筛选等操作，生成新的逻辑信号或数据流，以支持对应的数据处理任务。
例如，逻辑处理层、存储阵列层与存内计算层之间可以通过层间金属互联，进行数据和/或控制信号的传输。
例如，存内计算层可以对接收的外部输入或存储阵列层提供的数据，通过存内计算层内包括的存内计算阵列(例如忆阻器等)执行矩阵乘法等神经网络操作，根据需要还可以执行诸如卷积、池化、激活函数等操作。例如，可以参考前述实施例中关于存内计算阵列的工作原理的相关描述，此处不再赘述。相较于先从中取出数据再送入处理器进行计算的模式，存内计算层能够显著减少数据搬运的开销，从而大幅提升计算效率，特别适用于大规模并行计算场景。
例如，存内计算层可以包括至少一个存内计算阵列，存内计算阵列包括至少一个忆阻器阵列，忆阻器阵列可以包括排列为多行多列的多个忆阻器单元，每个忆阻器单元包括忆阻器以及开关元件(例如晶体管)。
例如，忆阻器至少之一的材料结构可以包括：TiN/HfAlOx/TaOx/TiN或TiN/HfO2/TaOx/TiN或TiN/HfO2/TiN或TiN/HfZrOx/TaOx/TiN或TiN/HfAlZrOx/TaOx/TiN或TiN/SiO2/TiN或TiN/HfOx/TaOx/TiN等的层叠结构，本公开的实施例对此并不限制。需要说明的是，在本公开的实施例中，上述的X不一定是整数，金属氧化物可以具有不同的氧含量或含氧比例。例如可以根据制造过程中通入氧气量的多少来确定各层中的氧含量。例如，实际制作过程中可以包括氧含量不固定的金属氧化物，例如可以是Ta2O5与TaO混合物等，本公开的实施例对此并不限定。
例如，存储阵列层可以对用于存内计算层的数据进行缓存。
例如，存储阵列层可以包括存储阵列，该存储阵列可以包括排列为多行多列的多个存储单元，多个存储单元每个可以包括晶体管以及与晶体管电连接的磁随机存储器件(MRAM)。
例如，晶体管可以被配置为起访问控制的作用，通过对晶体管的栅极施加适当的控制电压信号，可以精准地开启或关闭晶体管，从而执行对相连的MRAM存储器件的操作，实现对存储数据的读取、写入或擦除操作。
例如，晶体管可以包括碳纳米管(CNT，Carbon Nanotube)晶体管、铟基氧化物晶体管或低温多晶硅晶体管(LTPS，Low-Temperature Polycrystalline Silicon)中的至少一种，本公开的实施例对此并不限制。
例如，铟基氧化物晶体管可以包括IGZO晶体管、IGO晶体管或In2O3晶体管等。
例如多个存储单元每个可以包括2T1M存储单元。2T1M存储单元的具体内容例如可以参照前述实施例的相关描述，此处不再赘述。
例如，排列为多行多列的多个2T1M存储单元可以形成存储阵列，从而形成存储阵列层。
例如，磁随机存储器件可以包括自旋转移力矩磁随机存储器件(STT-MRAM)或自旋轨道矩磁随机存储器件(SOT-MRAM)等，本公开的实施例对此并不限制。对于自旋转移力矩磁随机存储器件和自旋轨道矩磁随机存储器件的相关描述例如可以参照前述实施例中对于STT-MRAM和SOT-MRAM的相关描述，此处不再赘述。
存储阵列层可以在高密度、低能耗的前提下，快速、可靠地存储存内计算层中神经网络模型参数、训练数据或中间计算结果等，为存内计算层提供相应的数据存储支持。
在本公开的一些实施例中，磁随机存储器件可以包括依次层叠设置的第一电极层、自由层、势垒层(即，隧穿层)、钉扎层和第二电极层。
例如，第一电极层可以为自旋轨道耦合效应比较强的金属(如Pt、W或Ta等金属材料，或者合金材料)。第一电极层的膜层厚度例如可以为0～6nm。
例如，自由层可以包括依次层叠的反铁磁层和铁磁层(即反铁磁/铁磁交换耦合层)。
例如，还可以采用自由层中的反铁磁层直接作为磁随机存储器件的第一电极。
例如，自由层中的反铁磁层的材料可以包括共线反铁磁材料(例如Mn2Au)、非共线反铁磁材料(例如IrMn3、PtMn3或Mn3Sn)或自旋劈裂反铁磁材料(例如，RuO2、Mn5Si3)等，本公开的实施例对此并不限定。自由层中的反铁磁层的膜层厚度例如可以为4-8nm。
例如，自由层中的铁磁层的材料可以包括CoFeB或Co材料等，本公开的实施例对此并不限定。自由层中的铁磁层的膜层厚度例如可以为0.8-1.4nm，以获得垂直磁各向异性，即易磁化方向垂直或近似垂直于薄膜表面。
对于自由层，反铁磁层由于具有相邻磁矩反向排列的特点，整体对外表现为零磁矩，反铁磁层的磁化方向极其稳定，不易受外部影响而改变。铁磁层内部磁矩可以沿同一方向排列，形成净磁矩，可以通过外部刺激(如电流或磁场)来调控铁磁层的磁化方向。
由于反铁磁层与铁磁层紧密接触，使得反铁磁层与铁磁层之间会发生交换耦合作用，即相邻磁矩之间的直接磁相互作用。这种相互作用可以导致铁磁层的磁化方向被反铁磁磁矩钉扎在特定方向，即使在没有外部磁场的情况下，内部也会产生交换偏置磁场。
在无电流或磁场作用时，自由层由于受到钉扎层(具有固定磁化方向)的约束和反铁磁层/铁磁层提供的交换偏置磁场的影响，自由层的磁化方向可以稳定在一个特定状态，例如可以对应存储一个二进制位(“0”或“1”)。
由于交换偏置磁场在自由层内部产生，打破了自旋轨道扭矩(SOT)磁化翻转的对称性。当施加特定方向的电流时，电流产生的自旋轨道扭矩(SOT)可以更有效地驱动铁磁层的垂直磁化方向沿着特定方向翻转，而不是在没有偏置时可能发生的无定向翻转。这使得自由层的磁化翻转过程可以通过电流方向来定向控制，且无需依赖外加磁场。
在进行数据写入操作时，通过向第一电极层施加特定方向的电流，电流流过第一电极层时由于金属电极材料中的强自旋轨道耦合效应产生SOT效应。SOT效应会在铁磁层内产生一个有效的扭矩，作用于磁化矢量，使其发生旋转。由于有交换偏置磁场的存在，电流只需要可以克服铁磁层自身的矫顽力(即保持磁化状态所需的最小能量)，就可以定向地将磁化方向从一个稳定状态翻转到另一个稳定状态，从而完成数据的写入。
在进行读取数据操作时，可以通过测量自由层与钉扎层之间隧穿电阻的变化来确定磁化状态。当两层磁化方向平行(同向)时，隧穿电阻较低，可以表示存储的二进制位为“0”；当两层磁化方向反平行(异向)时，隧穿电阻较高，可以表示存储的二进制位为“1”。
通过引入反铁磁/铁磁交换耦合层，自由层获得了较强的面内交换偏置磁场，从而在无外磁场条件下，可以仅依靠电流即可实现定向的磁化翻转，提高了数据存储的操作效率、降低了功耗，并增强了MRAM在特定应用环境下的适应性。
例如，势垒层的材料可以为绝缘层，例如包括MgO，势垒层的膜层厚度可以为1-2nm。
例如，钉扎层可以包括人工反铁磁结构。钉扎层可以包括依次层叠的铁磁层、非磁金属层、铁磁层以及反铁磁层。
例如，钉扎层中的铁磁层的材料可以包括CoFeB或Co材料等，本公开的实施例对此并不限定。钉扎层中的铁磁层的膜层厚度例如可以为0.8-1.4nm。
例如，钉扎层中的反铁磁层的材料可以包括IrMn3或PtMn3等，本公开的实施例对此并不限制。钉扎层中的反铁磁层的膜层厚度例如可以为5-10nm。
例如，钉扎层中的非磁金属层的材料可以包括Ru或Ta等，本公开的实施例对此并不限制。钉扎层中的非磁金属层的膜层厚度例如可以为0.4-1.5nm。
此外，自由层和钉扎层的易磁化轴方向可以垂直或者近似垂直于自由层和钉扎层的膜层表面。
例如，第二电极的材料可以包括Pt、W或Ta等金属材料，或者合金材料。第二电极的膜层厚度例如可以为5-20nm。
需要说明的是，考虑到量产工艺误差，实际的膜层厚度可以存在5-10nm的误差。示例性的，第二电极的膜层厚度的范围还可以是1-30nm。
在本公开的一些实施例中，磁随机存储器件包括磁性隧道结(MTJ，Magnetic Tunnel Junction)。
磁性隧道结可以包括依次层叠的铁磁层、绝缘层、铁磁层。可以由两个铁磁层(例如一个铁磁层固定磁化方向，另一个铁磁层可以切换磁化方向)夹着绝缘层(例如隧道势垒层)。当上下两个铁磁层的磁化方向平行时，电子可以通过隧穿效应高效地穿越绝缘层，表现为低电阻状态；当上下两个铁磁层的磁化方向反平行时，隧穿效应减弱，表现为高电阻状态，电阻状态的变化可以对应于二进制数据“0”和“1”的存储。
此外，本公开的发明人还注意到，存内计算层的表面粗糙度可能对磁随机存储器件的性能产生影响。粗糙的存内计算层的表面可能导致磁性隧道结(MTJ)的结构不均匀，影响电子隧穿效率、磁各向异性或者自旋轨道转矩效应的精确控制，从而影响MRAM存储器件的稳定性、读写速度、功耗以及数据保持能力等关键性能指标。
因此，在选择MRAM的磁性隧道结的设置区域时，可以选择存内计算层表面的均方根粗糙度(RMS,Root Mean Square Roughness)小于等于1纳米(或0.2纳米)的位置，以确保MRAM磁性隧道结的高性能运作。
例如，还可以将存内计算层中的忆阻器与MRAM的磁性隧道结二者错开位置放置。
在本公开的至少一实施例中，将忆阻器与MRAM的磁性隧道结错开位置放置，可以有助于避免相互间的工艺干扰，确保各自器件的高质量制造，还可以确保磁性隧道结设置在经过满足其粗糙度要求的特定区域，而忆阻器则可以根据其自身对表面质量的需求选择合适的区域进行集成。并且，由于忆阻器与MRAM在工作时都会产生电场和磁场，虽然忆阻器与MRAM都是非易失性件，但如果二者过于靠近，彼此的电学行为可能相互干扰，导致读写错误、信号串扰或功耗增加等问题，因此，将忆阻器与MRAM的磁性隧道结错开位置，可以避免直接的电学耦合，保持各自的读写操作独立性和数据完整性。由于忆阻器与MRAM有不同的散热需求，二者在数据读写过程中可能产生不同的热分布，将二者错开位置还可以有助于优化热管理，防止局部热点的形成，维持数据处理装置的稳定性和可靠性。此外，将忆阻器与MRAM的磁性隧道结错开位置放置，可以使得数据处理装置的布局更加灵活，可以根据各电路层的需求以及工艺限制来合理分配空间，有助于提高数据处理装置的集成密度。
图6示出了本公开至少一个实施例提供的一种数据处理装置的示意框图。如图6所示，在本公开的一些实施例中，数据处理装置100可以包括逻辑处理层101、存内计算层102以及存储阵列层103。逻辑处理层101和存内计算层102以及存储阵列层103至少部分层叠设置。
例如，逻辑处理层101可以设置在硅衬底上，存内计算层102设置在逻辑处理层101远离硅衬底的一侧，存储阵列层103设置在存内计算层102远离硅衬底的一侧。
例如，数据处理装置100还包括设置在逻辑处理层101、存内计算层102以及存储阵列层103之间的层间介质层，层间介质层包括有多个过孔，逻辑处理层101、存内计算层102以及存储阵列层103分别通过多个过孔通信。
例如，逻辑处理层101与存内计算层102之间设置有层间介质1，存内计算层102与存储阵列层103之间设置有层间介质2。
例如，逻辑处理层101可以被配置为进行逻辑运算和/或控制处理，存内计算层102可以被配置为对接收的数据进行神经网络运算，存储阵列层103可以被配置为存储用于存内计算层的数据。
例如，逻辑处理层101可以对来自存内计算层102、存储阵列层103或者其他输入源的数据进行组合、比较、筛选等操作，生成新的逻辑信号或数据流，以支持对应的数据处理任务。
例如，存内计算层102可以包括至少一个存内计算阵列，存内计算阵列每个包括至少一个忆阻器阵列，忆阻器阵列可以包括排列为多行多列的多个忆阻器。
例如，存储阵列层103可以包括存储阵列，该存储阵列可以包括排列为多行多列的多个存储单元，多个存储单元每个可以包括晶体管以及与晶体管电连接的磁随机存储器件。
又例如，晶体管与磁随机存储器件可以以层叠的形式设置在存储阵列层103，还可以以平面的形式设置在存储阵列层103。
本公开的实施例通过逻辑处理层101与存内计算层102、存储阵列层103的层叠设计，不仅有利于缩小数据处理装置的体积，提高集成度，还能够减少各电路层间的数据传输距离与延迟，提升数据处理速度。
在本公开的至少一个实施例还提供一种数据处理装置的制备方法。该数据处理装置的制备方法包括：采用半导体制备工艺制备存内计算层和制备与存内计算层至少部分层叠设置的存储阵列层，其中，存储阵列层包括存储阵列，存储阵列包括排列为多行多列的多个存储单元，多个存储单元每个包括晶体管以及与晶体管电连接的磁随机存储器件。
例如，采用半导体制备工艺制备存内计算层，以及采用半导体制备工艺制备存储阵列层，存储阵列层与存内计算层至少部分层叠设置。
例如，采用半导体制备工艺制备存内计算层中的存内计算阵列，存内计算阵列每个包括至少一个忆阻器阵列，忆阻器阵列包括排列为多行多列的多个忆阻器。
例如，采用半导体制备工艺制备存储阵列层中的存储阵列的过程中，既可以先制备晶体管再制备磁随机存储器件，还可以先制备磁随机存储器件再制备晶体管，本公开的实施例对于磁随机存储器件以及晶体管的制备先后顺序并不限定。
对于制备晶体管，例如可以采用低温后道晶体管制备工艺制备晶体管。这里，制备温度例如可以为小于等于300摄氏度(或者400摄氏度)的低温工艺。该晶体管例如可以包括碳纳米管晶体管、铟基氧化物晶体管或低温多晶硅晶体管中的至少一种。
在本公开的一些实施例中，数据处理装置的制备方法还包括提供硅衬底，在硅衬底上采用半导体制备工艺制备逻辑处理层，存内计算层形成在逻辑处理层远离硅衬底的一侧，存储阵列层形成在存内计算层远离硅衬底的一侧。
例如，制备逻辑处理层可以采用CMOS逻辑电路制备工艺(或硅基CMOS工艺)实现CMOS晶体管和其他元件的制造，以制造逻辑处理电路。
在本公开的一些实施例中，制备存储阵列层中的磁随机存储器件，可以包括制备掩膜以定义出磁随机存储器件的图形区域，并且使用掩模制备磁性隧道结。
例如，掩膜可以包括光刻胶掩膜或硬掩膜。
例如，掩膜的材料可以包括金属或者绝缘介质。
为了制备硬掩膜，例如，可以采用双层光刻胶通过光刻、沉积金属或者绝缘介质、剥离工艺制作硬掩膜，定义出磁随机存储器件的图形区域。
例如，还可以采用双层胶工艺定义出磁性隧道结区域的图形。示例性的，可以在制备磁性隧道结区域的基底上依次涂覆底胶和顶胶，并通过控制曝光和显影过程，使得底胶被图形化为预定设计的形状，其中，顶胶经处理后可以在底胶已定义的图形边缘上方形成部分悬空的“屋檐”结构。
例如，在这种“屋檐”双层胶结构的基础上，还可以沉积绝缘介质，然后在去胶液中浸泡以溶解剥离掉光刻胶，并且还可以连带剥离掉光刻胶上方附着的绝缘介质，从而制作出磁性隧道结的互连孔。
需要说明的是，本公开的实施例中的底胶是指在磁性隧道结区域的基底上首先涂覆的光刻胶，顶胶是指在底胶之上再涂覆的光刻胶。
对于制备光刻胶掩膜，例如，可以紫外光刻(Ultraviolet Lithography)、激光直写(DWL，Direct Write Lithography)、电子束曝光(EBL，Electron Beam Lithography)、离子束曝光(IBL，Ion Beam Lithography)等方法制备多种微纳米尺寸的光刻胶掩膜。
例如，还可以采用双层胶工艺制作光刻胶掩膜，采用顶胶在磁性隧道结区域的基底上涂覆底胶，以形成上层悬空的双层光刻胶掩膜。
对于使用掩模制备磁性隧道结，例如，可以通过干法刻蚀工艺，对磁随机存储器件的图形区域之外的其他区域进行刻蚀，以保留磁随机存储器件的图形区域。
例如，本公开的实施例采用的干法刻蚀工艺可以包括：离子束刻蚀(IBE,Ion Beam Etching)、原子层刻蚀(ALE,Atomic Layer Etching)、反应离子刻蚀(RIE,Reactive Ion Etching)或电感耦合等离子体刻蚀(ICP,Inductively Coupled Plasma Etching)等，本公开的实施例对于具体采用的干法刻蚀工艺并不限制。
需要注意的是，在采用离子束刻蚀(IBE)工艺制备磁性隧道结的过程中，如果采用垂直刻蚀方式，即离子束流与磁性隧道结表面呈90度直角(或接近90度)时，可能会导致制作出的磁性隧道结顶部边缘存在大量突出的“毛刺”，这些“毛刺”可能会对后续工艺和器件性能会产生负面影响。因此，可以采用变角度刻蚀方法，通过垂直角度分量刻蚀磁性隧道结，之后通过其他角度分量刻蚀磁性隧道结侧壁(即侧壁角度分量刻蚀)，以减小甚至消除“毛刺”现象，并且还可以降低离子束刻蚀带来的二次溅射效应，从而提高磁性隧道结的平整度、绝缘性和磁阻变化率，避免器件失效。
图7示出了本公开至少一个实施例提供的一种磁随机存储器件的制备方法示意图。如图7所示，可以首先通过垂直角度分量刻蚀磁性隧道结，例如可以使用较大角度进行刻蚀(例如离子束流与磁性隧道结表面呈60度)。可以快速去除大部分待刻蚀材料，但该步骤可能仍会产生一定量的毛刺。
之后进行侧壁角度分量刻蚀，例如可以采用较小角度进行刻蚀(例如离子束流与磁性隧道结表面呈30度)。该步骤中离子束对侧壁的轰击更为有效，可以针对性地去除先前刻蚀过程中产生的毛刺，同时进一步平滑侧壁。
此外，还需要注意刻蚀过程中的循环与冷却问题，例如上述不同角度中的每个角度刻蚀一段时间(例如1分钟)后可以暂停刻蚀，并让样品冷却(例如3分钟)一段时间。冷却可以有助于降低刻蚀过程中材料因热效应而产生的二次溅射概率，同时也有利于样品结构稳定，防止过热导致的形貌恶化。
例如，可以按照图7所示的两个角度的刻蚀步骤反复循环数次，逐步优化磁性隧道结的表面质量和侧壁形态，直至达到需要的刻蚀效果。
在本公开的至少一个实施例中，通过变角度刻蚀技术，可以有效地减小甚至消除磁性隧道结顶部边缘的毛刺，改善器件的平整度、绝缘性和磁阻变化率，从而提高器件的整体性能和良率。通过调控离子束入射角度和刻蚀步骤，巧妙地利用不同角度下离子束对材料的刻蚀特性和对已生成毛刺的去除效果，实现了对磁性隧道结制备过程的精准控制。
在本公开的一些实施例中，制备磁随机存储器件还包括：选择存内计算层表面的均方根粗糙度小于1nm或0.2nm的区域布置磁性隧道结，并将磁性隧道结与忆阻器错开位置放置。
这里，在制备存内计算层时，需要进行抛光操作(例如化学机械抛光(CMP,Chemical Mechanical Polishing))，通过化学腐蚀和机械研磨的协同作用，来去除存内计算层起伏，确保得到极低的表面粗糙度(例如，均方根粗糙度低于1nm，甚至低于0.2nm)。
在制备磁随机存储器件的过程中，对于布置磁性隧道结具体位置的方法和有益效果例如还可以参考前述实施例的相关描述，此处不再赘述。
以下以RRAM和SOT-MRAM堆叠形成的数据处理装置的制备方法为例，对数据处理装置的制备方法进行示例性描述，例如该制备方法如下的步骤(1)～(5)：
(1)提供硅衬底。
(2)在硅衬底上制备逻辑电路层。
(3)在逻辑电路层上制备存内计算层。
(4)在存内计算层上制备MRAM存储器件。
(5)在存内计算层上制备用于MRAM存储器件的晶体管。
例如，可以在硅衬底上采用CMOS逻辑电路制备工艺(或硅基CMOS工艺)实现CMOS晶体管和其他元件的制造，以制备逻辑处理电路。
例如，可以采用低温(例如小于等于400摄氏度)的后端集成工艺制备RRAM存内计算层，例如，一种示例性的制备存储计算电路层的方法可以包括如下步骤：
(a)、沉积“下电极层/阻变层/热增强层/上电极层”叠层。
(b)、采用光刻、干法刻蚀工艺，选择性刻蚀该叠层，实现阻变存储器件的图形化。
(c)、采用等离子增强化学气相沉积，沉积钝化层(如SiO2薄膜)。
(d)、采用光刻、干法刻蚀或湿法刻蚀工艺，刻蚀钝化层，形成互连线连接点开孔。
(e)、采用电镀沉积一层钨(W)，然后利用化学机械抛光，除了SiO2孔之外的W研磨干净(形成金属过孔)。
(f)、采用物理气相沉积，沉积金属Al。
(g)、采用光刻、干法刻蚀工艺，选择性刻蚀Al，形成Al金属互连线。
图8示出了本公开至少一个实施例提供的一种磁阻随机存取存储单元的制备方法的流程示意图。如图8所示，MRAM存储器件的制备方法可以包括步骤S210-S250。
(a)S210，制备SOT-MRAM叠层。
例如，可以采用磁控溅射工艺或者分子束外延工艺(MBE)等技术依次沉积：绝缘介质层、第一电极层、自由层、势垒层、钉扎层、第二电极层的多层薄膜叠层。
第一电极层的材料例如可以包括自旋轨道耦合效应比较强的金属(如Pt、W、Ta或者合金等)，第一电极层的膜层厚度可以为0-6nm；例如可以将自由层中的反铁磁层作为第一电极层。
自由层可以包括依次层叠的反铁磁层和铁磁层形成的交换耦合层，铁磁层材料可采用CoFeB或Co材料体系，铁磁层的膜层厚度可以为0.8-1.4nm。自由层中的反铁磁层的材料可以包括共线反铁磁材料(例如Mn2Au)、非共线反铁磁材料(例如IrMn3、PtMn3或Mn3Sn)或自旋劈裂反铁磁材料(例如，RuO2、Mn5Si3)等。自由层中的反铁磁层的膜层厚度例如可以为4-8nm。
势垒层的材料可以为绝缘材料，例如可以包括MgO。势垒层的膜层厚度可以为1-2nm。
钉扎层可以包括人工反铁磁结构。钉扎层可以包括依次层叠的铁磁层、非磁金属层、铁磁层以及反铁磁层。钉扎层中的铁磁层的材料可以包括CoFeB或Co材料等。钉扎层中的铁磁层的膜层厚度例如可以为0.8-1.4nm。钉扎层中的反铁磁层的材料可以包括IrMn3或PtMn3等。钉扎层中的反铁磁层的膜层厚度例如可以为5-10nm。钉扎层中的非磁金属层的材料可以包括Ru或Ta等。钉扎层中的非磁金属层的膜层厚度例如可以为0.4-1.5nm。第二电极的材料可以包括Pt、W或Ta等金属材料，或者合金材料。第二电极的膜层厚度例如可以为5-20nm。
(b)S220，制备SOT-MRAM磁性隧道结。
例如，可以先采用紫外光刻工艺、激光直写工艺、电子束曝光工艺、离子束曝光工艺等工艺方法制备多种微纳米尺寸的光刻胶掩膜，或者采用双层光刻胶通过光刻、沉积、剥离等工艺制作硬掩膜，以定义出MRAM的图形区域。另外，还可以采用双层胶工艺制作光刻胶掩膜，顶胶在磁性隧道结的底胶上形成部分悬空的磁性隧道结结构。之后再通过离子束刻蚀工艺、原子层刻蚀工艺、反应离子刻蚀工艺或者电感耦合等离子体刻蚀工艺等干法刻蚀工艺，将该MRAM图形之外的区域刻蚀掉，保留MRAM图形区域。需要注意的是，如果采用光刻胶掩膜制备磁性隧道结，最后还需要去除该光刻胶掩膜。
(c)S230，制备绝缘层。
例如，可以采用磁控溅射工艺、化学气相沉积工艺、等离子体增强化学气相沉积工艺或者原子层沉积工艺等方法，在器件表面整体沉积绝缘层(例如，氧化硅SiO2或者氧化铝Al2O3等绝缘介质薄膜)。
(d)S240，制备互连孔。
例如，可以先采用光刻工艺定义出第二电极和第一电极的开孔区域图形，再采用干法刻蚀工艺或者湿法刻蚀工艺刻蚀绝缘层，以完成开孔，暴露出两个第一电极和一个第二电极的连接孔，形成互连线连接点，最后去除光刻胶。
在本公开的一些实施例中，还可以选择在制作SOT-MRAM磁性隧道结的过程中，例如在进行光刻、刻蚀工艺后，不去除光刻胶掩膜，直接进行绝缘层的沉积，之后再通过相应的去胶工艺剥离光刻胶掩膜并制作出互连孔。
(e)S250，制备互连电极和导线。
例如，可以采用电镀工艺或者化学气相沉积工艺沉积一层导电层，例如沉积金属钨(W)，然后利用化学机械抛光工艺(CMP)进行平坦化加工，将开孔之外的导电层如金属钨W研磨干净，只保留开孔内部的导电层如金属钨W，形成金属过孔。之后采用物理气相沉积工艺(PVD)，沉积导电层如金属铝Al。再采用光刻、ICP等干法刻蚀工艺，选择性刻蚀导电层如金属铝Al，形成导电互连引线。
需要注意的是，制作互连电极和导线时，还可以先采用双层胶光刻工艺定义出导线区域的图形，用以实现MRAM第二电极和第一电极与外部器件或电路的导电互连。由于该光刻采用双层胶工艺实现，因此，顶胶在磁性隧道结的底胶上会形成顶胶边缘悬空的双层光刻胶结构。之后，再采用电子束蒸发镀膜工艺或磁控溅射工艺等技术沉积一层导电层(如金Au、铂Pt、钯Pd、铝Al、铜Cu、钨W或者氮化钛TiN等)。如果该导电层的粘附性差，还可以先沉积一层粘附层(例如钛Ti、铬Cr或者钽Ta等)，再沉积导电层。所沉积导电层的厚度例如可以小于底胶厚度的一半。然后可以选择在丙酮或者其他去胶溶液中，去除被光刻胶支撑的导电层区域，保留没有光刻胶区域的导电层图形。此外，该步骤还可以可辅助采用长时间浸泡、超声波处理、或者加热等辅助操作。
(f)退火操作。
例如，在SOT-MRAM多层薄膜沉积完成后，还需要进行退火操作，以实现MgO势垒层的晶化，提高铁磁层和势垒层的界面质量，从而提高隧道结的磁电阻值。该退火操作操作例如可以在高温结合磁场环境下进行，退火的温度例如可以设置为200-350摄氏度，磁场方向可以设置为SOT-MRAM自由层的易轴方向，例如可以为垂直(或者近似垂直)于薄膜表面，磁场强度例如可以设置为500-10000奥斯特。
例如上述步骤(5)中用于MRAM的晶体管，可以采用低温(小于等于四百摄氏度)的后端集成制备方法。这里，晶体管的沟道材料可以包括：碳纳米管、铟镓氧化锌、低温多晶硅、氧化铟In2O3等半导体沟道材料。
以下以碳纳米管晶体管的制备方法为例对制备后道晶体管的方法进行示例性描述，例如碳纳米管晶体管的制备方法可以包括以下步骤：
(a)、采用光刻工艺，电子束蒸发镀膜沉积工艺沉积金属靶Pd，然后剥离形成图形，作为碳纳米晶体管的背栅结构。
(b)、采用原子层淀积技术生长Al2O3和HfO2绝缘层作为栅氧介质。
(c)、采用光刻、湿法刻蚀工艺，选择性地刻蚀Al2O3与HfO2区域实现栅氧开孔。
(d)、采用湿法转移工艺，沉积一层碳纳米管。
(e)、采用光刻，电子束蒸镀80nm Pd，然后剥离形成图形，作为碳纳米晶体管的源、漏电极。
(f)、采用光刻、氧等离子体刻蚀工艺，选择性刻蚀碳纳米管，隔离不同器件。
(g)、采用原子层淀积生长45nm Al2O3作为钝化层。
(h)、采用光刻、湿法刻蚀工艺，选择性刻蚀Al2O3，形成电极接触孔。
(i)、采用后续钝化工艺与金属互连工艺形成金属互连图形。
图9示出了本公开至少一个实施例提供的一种电子装置的示意框图。如图9所示，该电子装置300包括数据处理装置400。
例如，数据处理装置400可以是上述任一实施例提供的数据处理装置装置。例如，该电子装置300还可以进一步包括其他装置，例如中央处理器(CPU)、数据总线、内存等。该电子装置300可以为信号处理装置、计算装置等，例如，可以用于控制器、终端设备或服务端设备等。
除了上述示例性说明之外，本公开还有以下几点需要说明：
(1)本公开的附图只涉及到本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
(3)应理解，在本公开的实施例中，上述各步骤的序号的大小并不意味着执行顺序的先后，各步骤的执行顺序应以其功能和内在逻辑确定，而不应对本公开实施例的实施过程构成任何限定。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种数据处理装置，包括：逻辑处理层、存内计算层和存储阵列层，
    其中，所述逻辑处理层、所述存内计算层和所述存储阵列层至少部分层叠；
    所述逻辑处理层被配置为进行逻辑运算和/或控制处理；
    所述存内计算层被配置为对接收的数据进行神经网络运算，所述存储阵列层被配置为存储用于所述存内计算层的数据；
    所述存储阵列层包括存储阵列，所述存储阵列包括排列为多行多列的多个存储单元，所述多个存储单元每个包括晶体管以及与所述晶体管电连接的磁随机存储器件。
  2. 根据权利要求1所述的数据处理装置，其中，所述磁随机存储器件包括依次层叠设置的第一电极层、自由层、势垒层、钉扎层和第二电极层。
  3. 根据权利要求2所述的数据处理装置，其中，所述自由层包括依次层叠的反铁磁层和铁磁层。
  4. 根据权利要求1-3任一所述的数据处理装置，其中，所述存内计算层包括至少一个存内计算阵列，所述存内计算阵列每个包括至少一个忆阻器阵列，所述忆阻器阵列包括排列为多行多列的多个忆阻器；
    所述磁随机存储器件包括磁性隧道结，所述磁性隧道结与所述忆阻器错开位置放置。
  5. 根据权利要求1-4任一所述的数据处理装置，其中，所述晶体管包括碳纳米管晶体管、铟基氧化物晶体管或低温多晶硅晶体管中的至少一种。
  6. 根据权利要求1-5任一所述的数据处理装置，其中，所述磁随机存储器件包括自旋转移力矩磁随机存储器件或自旋轨道矩磁随机存储器件。
  7. 一种电子装置，包括如权利要求1-6任一所述的数据处理装置。
  8. 一种数据处理装置的制备方法，包括：
    采用半导体制备工艺制备存内计算层和制备与所述存内计算层至少部分层叠设置的存储阵列层，
    其中，所述存内计算层被配置为对接收的数据进行神经网络运算，所述存储阵列层被配置为存储用于所述存内计算层的数据；
    所述存储阵列层包括存储阵列，所述存储阵列包括排列为多行多列的多个存储单元，所述多个存储单元每个包括晶体管以及与所述晶体管电连接的磁随机存储器件。
  9. 根据权利要求8所述的制备方法，其中，所述制备磁随机存储器件包括：
    制备掩膜以定义出所述磁随机存储器件的图形区域，其中，所述掩膜包括光刻胶掩膜或硬掩膜；
    使用所述掩模制备磁性隧道结。
  10. 根据权利要求9所述的制备方法，其中，所述制备掩膜以定义出所述磁随机存储器件的图形区域，包括：
    采用双层胶工艺定义出所述磁性隧道结区域的图形。
  11. 根据权利要求9或10所述的制备方法，其中，所述使用所述掩模制备磁性隧道结，包括：
    通过干法刻蚀工艺，对所述磁随机存储器件的图形区域之外的其他区域进行刻蚀，以保留所述磁随机存储器件的图形区域。
  12. 根据权利要求8-11任一项所述的制备方法，其中，所述存内计算层包括至少一个存内计算阵列，所述存内计算阵列每个包括至少一个忆阻器阵列，所述忆阻器阵列包括排列为多行多列的多个忆阻器；
    所述制备磁随机存储器件，还包括：
    选择所述忆阻器表面的均方根粗糙度小于1nm或0.2nm的区域布置磁性隧道结，并将所述磁性隧道结与所述忆阻器错开位置放置。
  13. 根据权利要求8-12任一项所述的制备方法，还包括：
    提供硅衬底；
    在所述硅衬底上采用半导体制备工艺制备逻辑处理层，
    其中，所述逻辑处理层被配置为进行逻辑运算和/或控制处理，所述存内计算层形成在所述逻辑处理层远离硅衬底的一侧，所述存储阵列层形成在所述存内计算层远离硅衬底的一侧。
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