WO2025200830A1 - 移位寄存器及其驱动方法、栅极驱动电路、显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路、显示装置

Info

Publication number
WO2025200830A1
WO2025200830A1 PCT/CN2025/077129 CN2025077129W WO2025200830A1 WO 2025200830 A1 WO2025200830 A1 WO 2025200830A1 CN 2025077129 W CN2025077129 W CN 2025077129W WO 2025200830 A1 WO2025200830 A1 WO 2025200830A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
electrically connected
node
electrode
signal terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/077129
Other languages
English (en)
French (fr)
Inventor
陈文波
于子阳
蒋志亮
吴建鹏
王梦奇
胡明
邱海军
韩宏达
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Publication of WO2025200830A1 publication Critical patent/WO2025200830A1/zh
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2380/00—Specific applications
    • G09G2380/02—Flexible displays

Definitions

  • This article relates to the field of display technology, and in particular to a shift register and a driving method thereof, a gate driving circuit, and a display device.
  • OLEDs Organic light-emitting diodes
  • QLEDs quantum-dot light-emitting diodes
  • advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost.
  • TFTs thin-film transistors
  • the present disclosure provides a shift register, comprising: a cascade output subcircuit, a drive output subcircuit, and a node control subcircuit;
  • the cascade output subcircuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitor, a second capacitor, and a third capacitor;
  • the control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the second power supply terminal, and the second electrode of the second transistor is electrically connected to the second node;
  • the control electrode of the third transistor is electrically connected to the first end of the third capacitor, the first electrode of the third transistor is electrically connected to the second clock signal end, and the second electrode of the third transistor is electrically connected to the second node;
  • the control electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first node;
  • the control electrode of the seventh transistor is electrically connected to the third node, the first electrode of the seventh transistor is electrically connected to the second clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the cascade output signal terminal;
  • control electrode of the eighth transistor electrically connected to the second power supply terminal, a first electrode of the eighth transistor electrically connected to the first node, and a second electrode of the eighth transistor electrically connected to the third node;
  • control electrode of the ninth transistor electrically connected to the first node, a first electrode of the ninth transistor electrically connected to the second power supply terminal, and a second electrode of the ninth transistor electrically connected to the first terminal of the third capacitor;
  • a first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the first power supply end.
  • a first end of the fourth capacitor is electrically connected to the first power supply end, and a second end of the fourth capacitor is electrically connected to the cascade output signal end.
  • the first control input signal terminal includes: a second clock signal terminal and a mask signal terminal
  • the second control input signal terminal includes: a second clock signal terminal
  • the driving output sub-circuit includes: a tenth transistor, an eleventh transistor, and a fifth capacitor
  • the node control sub-circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitor;
  • control electrode of the tenth transistor electrically connected to the fifth node, a first electrode of the tenth transistor electrically connected to the second clock signal terminal, and a second electrode of the tenth transistor electrically connected to the drive output signal terminal;
  • the control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the driving output signal terminal;
  • the control electrode of the twelfth transistor is electrically connected to the fourth node, the first electrode of the twelfth transistor is electrically connected to the masking signal terminal, and the second electrode of the twelfth transistor is electrically connected to the fifth node;
  • control electrode of the thirteenth transistor electrically connected to the second clock signal terminal, a first electrode of the thirteenth transistor electrically connected to the second electrode of the fourteenth transistor, and a second electrode of the thirteenth transistor electrically connected to the fifth node;
  • a first end of the fifth capacitor is electrically connected to the fifth node, and a second end of the fifth capacitor is electrically connected to the driving output signal terminal;
  • the first control input signal terminal includes: a second clock signal terminal, and the second control input signal terminal includes: a mask signal terminal;
  • the cascade output subcircuit is provided with a first node, a second node and a third node;
  • the node control subcircuit is electrically connected to the first node, the second node, the second clock signal terminal, the first power terminal, the second power terminal, and the fifth node, respectively, and is configured to provide a signal from the first power terminal or the second clock signal terminal to the fifth node under the control of the signals from the first node, the second node, the second clock signal terminal, and the second power terminal;
  • the drive output sub-circuit is electrically connected to the second node, the fifth node, the first power supply terminal, the masking signal terminal and the drive output signal terminal, respectively, and is configured to provide a signal from the first power supply terminal or the masking signal terminal to the drive output signal terminal under the control of signals configured as the second node and the fifth node.
  • the driving output sub-circuit includes: a tenth transistor, an eleventh transistor, and a fifth capacitor
  • the node control sub-circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitor;
  • the control electrode of the tenth transistor is electrically connected to the fifth node, the first electrode of the tenth transistor is electrically connected to the masking signal terminal, and the second electrode of the tenth transistor is electrically connected to the driving output signal terminal;
  • the control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the driving output signal terminal;
  • the node control subcircuit is electrically connected to the second node, the third node, the mask signal terminal, the second clock signal terminal, the first power terminal, the second power terminal, and the fifth node, respectively, and is configured to provide a signal from the first power terminal or the mask signal terminal to the fifth node under the control of signals from the second node, the third node, the mask signal terminal, the second clock signal terminal, and the second power terminal;
  • control electrode of the tenth transistor electrically connected to the fifth node, a first electrode of the tenth transistor electrically connected to the second clock signal terminal, and a second electrode of the tenth transistor electrically connected to the drive output signal terminal;
  • the drive output sub-circuit is electrically connected to the second node, the fifth node, the first power supply terminal, the masking signal terminal and the drive output signal terminal, respectively, and is configured to provide a signal from the first power supply terminal or the masking signal terminal to the drive output signal terminal under the control of signals configured as the second node and the fifth node.
  • the driving output sub-circuit includes: a tenth transistor, an eleventh transistor, and a fifth capacitor
  • the node control sub-circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitor;
  • the control electrode of the tenth transistor is electrically connected to the fifth node, the first electrode of the tenth transistor is electrically connected to the masking signal terminal, and the second electrode of the tenth transistor is electrically connected to the driving output signal terminal;
  • the control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the driving output signal terminal;
  • a first end of the fifth capacitor is electrically connected to the fifth node, and a second end of the fifth capacitor is electrically connected to the driving output signal terminal;
  • a first end of the sixth capacitor is electrically connected to the fourth node, and a second end of the sixth capacitor is electrically connected to the fifth node.
  • the control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the second node;
  • the control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor;
  • the control electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first node;
  • a control electrode of the seventh transistor is electrically connected to the third node, a first electrode of the seventh transistor is electrically connected to the second clock signal terminal, and a second electrode of the seventh transistor is electrically connected to the cascade output signal terminal;
  • control electrode of the eighth transistor electrically connected to the second power supply terminal, a first electrode of the eighth transistor electrically connected to the first node, and a second electrode of the eighth transistor electrically connected to the third node;
  • control electrode of the tenth transistor electrically connected to the fifth node, a first electrode of the tenth transistor electrically connected to one of the masking signal terminal and the second clock signal terminal, and a second electrode of the tenth transistor electrically connected to the driving output signal terminal;
  • a control electrode of the twelfth transistor is electrically connected to the fourth node, a first electrode of the twelfth transistor is electrically connected to the other of the mask signal terminal and the second clock signal terminal, and a second electrode of the twelfth transistor is electrically connected to the fifth node;
  • control electrode of the fifteenth transistor electrically connected to the second power supply terminal, a first electrode of the fifteenth transistor electrically connected to one of the first node and the third node, and a second electrode of the fifteenth transistor electrically connected to the fourth node;
  • a first end of the first capacitor is electrically connected to the third node, and a second end of the first capacitor is electrically connected to the cascade output signal terminal;
  • a first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the first power supply terminal;
  • a first end of the fifth capacitor is electrically connected to the fifth node, and a second end of the fifth capacitor is electrically connected to the driving output signal terminal;
  • a first end of the sixth capacitor is electrically connected to the fourth node, and a second end of the sixth capacitor is electrically connected to the fifth node.
  • the cascade output sub-circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor, a second capacitor, and a fourth capacitor;
  • the driver output sub-circuit includes: a tenth transistor, an eleventh transistor, and a fifth capacitor;
  • the node control sub-circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitor.
  • the control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node;
  • a control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is electrically connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the second node;
  • the control electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first node;
  • a control electrode of the twelfth transistor is electrically connected to the fourth node, a first electrode of the twelfth transistor is electrically connected to the other of the mask signal terminal and the second clock signal terminal, and a second electrode of the twelfth transistor is electrically connected to the fifth node;
  • a first end of the first capacitor is electrically connected to the third node, and a second end of the first capacitor is electrically connected to the cascade output signal terminal;
  • a first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the first power supply terminal;
  • a first end of the fourth capacitor is electrically connected to the first power supply terminal, and a second end of the fourth capacitor is electrically connected to the cascade output signal terminal;
  • a first end of the fifth capacitor is electrically connected to the fifth node, and a second end of the fifth capacitor is electrically connected to the driving output signal terminal;
  • a first end of the sixth capacitor is electrically connected to the fourth node, and a second end of the sixth capacitor is electrically connected to the fifth node.
  • the cascade output sub-circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitor, a second capacitor, and a third capacitor;
  • the driver output sub-circuit includes: a tenth transistor, an eleventh transistor, and a fifth capacitor;
  • the node control sub-circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitor.
  • the control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the second power supply terminal, and the second electrode of the second transistor is electrically connected to the second node;
  • the control electrode of the third transistor is electrically connected to the first end of the third capacitor, the first electrode of the third transistor is electrically connected to the second clock signal end, and the second electrode of the third transistor is electrically connected to the second node;
  • the control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the second power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor;
  • the control electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first node;
  • the control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the cascade output signal terminal;
  • a control electrode of the seventh transistor is electrically connected to the third node, a first electrode of the seventh transistor is electrically connected to the second clock signal terminal, and a second electrode of the seventh transistor is electrically connected to the cascade output signal terminal;
  • control electrode of the ninth transistor electrically connected to the first node, a first electrode of the ninth transistor electrically connected to the second power supply terminal, and a second electrode of the ninth transistor electrically connected to the first terminal of the third capacitor;
  • control electrode of the tenth transistor electrically connected to the fifth node, a first electrode of the tenth transistor electrically connected to one of the masking signal terminal and the second clock signal terminal, and a second electrode of the tenth transistor electrically connected to the driving output signal terminal;
  • the control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the driving output signal terminal;
  • a control electrode of the twelfth transistor is electrically connected to the fourth node, a first electrode of the twelfth transistor is electrically connected to the other of the mask signal terminal and the second clock signal terminal, and a second electrode of the twelfth transistor is electrically connected to the fifth node;
  • control electrode of the thirteenth transistor electrically connected to the second clock signal terminal, a first electrode of the thirteenth transistor electrically connected to the second electrode of the fourteenth transistor, and a second electrode of the thirteenth transistor electrically connected to the fifth node;
  • the control electrode of the fourteenth transistor is electrically connected to the second node, and the first electrode of the fourteenth transistor is electrically connected to the first power supply terminal;
  • control electrode of the fifteenth transistor electrically connected to the second power supply terminal, a first electrode of the fifteenth transistor electrically connected to one of the first node and the third node, and a second electrode of the fifteenth transistor electrically connected to the fourth node;
  • a first end of the first capacitor is electrically connected to the third node, and a second end of the first capacitor is electrically connected to the cascade output signal terminal;
  • a first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the first power supply terminal;
  • the second end of the third capacitor is electrically connected to the second clock signal end
  • a first end of the fifth capacitor is electrically connected to the fifth node, and a second end of the fifth capacitor is electrically connected to the driving output signal terminal;
  • a first end of the sixth capacitor is electrically connected to the fourth node, and a second end of the sixth capacitor is electrically connected to the fifth node.
  • the cascade output sub-circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor;
  • the driver output sub-circuit includes: a tenth transistor, an eleventh transistor, and a fifth capacitor;
  • the node control sub-circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitor.
  • the control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node;
  • the control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the second power supply terminal, and the second electrode of the second transistor is electrically connected to the second node;
  • the control electrode of the third transistor is electrically connected to the first end of the third capacitor, the first electrode of the third transistor is electrically connected to the second clock signal end, and the second electrode of the third transistor is electrically connected to the second node;
  • the control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the second power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor;
  • the control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the cascade output signal terminal;
  • a control electrode of the seventh transistor is electrically connected to the third node, a first electrode of the seventh transistor is electrically connected to the second clock signal terminal, and a second electrode of the seventh transistor is electrically connected to the cascade output signal terminal;
  • control electrode of the eighth transistor electrically connected to the second power supply terminal, a first electrode of the eighth transistor electrically connected to the first node, and a second electrode of the eighth transistor electrically connected to the third node;
  • control electrode of the tenth transistor electrically connected to the fifth node, a first electrode of the tenth transistor electrically connected to one of the masking signal terminal and the second clock signal terminal, and a second electrode of the tenth transistor electrically connected to the driving output signal terminal;
  • the control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the driving output signal terminal;
  • a control electrode of the twelfth transistor electrically connected to the fourth node, a first electrode of the twelfth transistor electrically connected to the other of the mask signal terminal and the second clock signal terminal, and a second electrode of the twelfth transistor electrically connected to the fifth node;
  • control electrode of the thirteenth transistor electrically connected to the second clock signal terminal, a first electrode of the thirteenth transistor electrically connected to the second electrode of the fourteenth transistor, and a second electrode of the thirteenth transistor electrically connected to the fifth node;
  • the control electrode of the fourteenth transistor is electrically connected to the second node, and the first electrode of the fourteenth transistor is electrically connected to the first power supply terminal;
  • control electrode of the fifteenth transistor electrically connected to the second power supply terminal, a first electrode of the fifteenth transistor electrically connected to one of the first node and the third node, and a second electrode of the fifteenth transistor electrically connected to the fourth node;
  • a first end of the first capacitor is electrically connected to the third node, and a second end of the first capacitor is electrically connected to the cascade output signal terminal;
  • a first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the first power supply terminal;
  • the second end of the third capacitor is electrically connected to the second clock signal end
  • a first end of the fourth capacitor is electrically connected to the first power supply terminal, and a second end of the fourth capacitor is electrically connected to the cascade output signal terminal;
  • a first end of the sixth capacitor is electrically connected to the fourth node, and a second end of the sixth capacitor is electrically connected to the fifth node.
  • the signal at the masking signal terminal in the first display mode, is a first signal, and in the second display mode, the signal at the masking signal terminal is the first signal during at least a portion of the time period and is the second signal during at least a portion of the time period;
  • the time period when the signal of the masked signal terminal is the first signal does not overlap with the time period when the cascade output signal terminal outputs the signal, and the time period when the signal of the masked signal terminal is the second signal at least partially overlaps with the time period when the cascade output signal terminal outputs the signal;
  • a voltage value of at least one of the first signal and the second signal is constant, and the voltage value of the first signal is smaller than the voltage value of the second signal.
  • a time period during which the cascade output signal terminal outputs a signal is within a time period during which the signal of the masking signal terminal is the second signal.
  • the moment when the signal at the masking signal terminal changes from the first signal to the second signal is before the output time period, wherein the output time period is the time period during which the cascade output signal terminal outputs a signal.
  • the present disclosure further provides a gate drive circuit, comprising: a plurality of the above-mentioned shift registers;
  • the cascade output signal terminal of at least one stage of the shift register is electrically connected to the signal input terminal of at least one stage of the shift register.
  • the present disclosure further provides a display device, comprising: the above-mentioned gate driving circuit.
  • the device further comprises: sub-pixels arranged in an array, a plurality of first scan signal lines, and a plurality of data signal lines, wherein at least one sub-pixel is electrically connected to each of the first scan signal line and the data signal line;
  • At least one sub-pixel includes: a pixel driving circuit, the pixel driving circuit of at least one sub-pixel includes: a write transistor, the write transistor being electrically connected to the first scan signal line and the data signal line connected to the sub-pixel;
  • the driving output signal terminal of at least one stage of the shift register is electrically connected to the first scanning signal line connected to at least one row of pixel driving circuits.
  • the present invention further comprises: a plurality of second reset signal lines and a plurality of second initial signal lines, and at least one sub-pixel is further electrically connected to the second reset signal line and the second initial signal line, respectively;
  • the driving output signal terminal of at least one stage of the shift register is electrically connected to a second reset signal line connected to at least one row of pixel driving circuits;
  • the first scanning signal line and the second reset signal line connected to at least one row of pixel driving circuits are independently provided, or the second reset signal line connected to at least one row of pixel driving circuits is the same signal line as the first scanning signal line connected to the next row of pixel driving circuits.
  • the present disclosure further provides a shift register driving method, which is configured to drive the above-mentioned shift register, the method comprising:
  • the cascade output subcircuit provides the signal of the first power supply terminal or the second clock signal terminal to the cascade output signal terminal under the control of the signal of the signal input terminal, the first clock signal terminal, the second clock signal terminal and the second power supply terminal;
  • the node control subcircuit provides a signal to the drive output subcircuit under the control of the signals from the cascade output subcircuit, the first power supply terminal, the second power supply terminal and the first control input signal terminal;
  • FIG5 is an equivalent circuit diagram 1 of the cascade output subcircuit
  • FIG6 is a second equivalent circuit diagram of the cascade output sub-circuit
  • FIG9 is a third equivalent circuit diagram of the drive output subcircuit and the node control subcircuit
  • FIG10 is a fourth equivalent circuit diagram of the drive output subcircuit and the node control subcircuit
  • FIG11 is an equivalent circuit diagram 1 of a shift register
  • FIG12 is a second equivalent circuit diagram of a shift register
  • FIG13 is a third equivalent circuit diagram of a shift register
  • FIG14 is a fourth equivalent circuit diagram of a shift register
  • FIG15 is a fifth equivalent circuit diagram of a shift register
  • FIG17 is an equivalent circuit diagram of a shift register
  • FIG18 is an equivalent circuit diagram 8 of a shift register
  • the scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such.
  • the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values shown in the figures.
  • the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa.
  • the functions of “source electrode” and “drain electrode” may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced with “conductive film.”
  • insulating film may be replaced with “insulating layer.”
  • the circuit unit may include a pixel driver circuit, and the pixel driver circuit may be respectively connected to the scan signal lines and the data signal lines.
  • the timing controller may provide grayscale values and control signals suitable for the specifications of the source driver circuit to the source driver circuit, may provide clock signals, scan start signals, etc. suitable for the specifications of the gate driver circuit to the gate driver circuit, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver.
  • the source driver circuit can generate a data voltage to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller.
  • the first subpixel P1 may be a red subpixel (R) emitting red light
  • the second subpixel P2 may be a blue subpixel (B) emitting blue light
  • the third subpixel P3 may be a green subpixel (G) emitting green light.
  • the shape of the sub-pixel may be rectangular, diamond, pentagonal, or hexagonal, and the plurality of sub-pixels may be arranged in parallel horizontally, vertically, or in a herringbone pattern, which is not limited in the present disclosure.
  • the light emitting device may be an OLED, which may include a first electrode (anode), a second electrode (cathode), and an organic light emitting layer between the first electrode and the second electrode.
  • the organic light-emitting layer may include an emissive layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).
  • HIL hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • HBL hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be a common layer connected together, and the emissive layers of adjacent sub-pixels may have a small overlap or may be isolated.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure.
  • the pixel driving circuit may be connected to 11 signal lines (data signal line Data, first scan signal line Gate1, second scan signal line Gate2, first reset signal line Reset1, second reset signal line Reset2, light emitting signal line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, first power line VDD and second power line VSS).
  • data signal line Data data signal line Data
  • a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2 , ie, the second end of the storage capacitor C is connected to the control electrode of the third transistor M3 .
  • the control electrode of the first transistor M1 is connected to the first reset signal line Reset1, the first electrode of the first transistor M1 is connected to the first initialization signal line INIT1, and the second electrode of the first transistor is connected to the third node N3.
  • the first transistor T1 can be referred to as a first node reset transistor.
  • the first transistor M1 transmits an initialization voltage to the third node N3 to initialize the charge of the third node N3.
  • the control electrode of the second transistor M2 is connected to the second scan signal line Gate2, the first electrode of the second transistor M2 is connected to the second node N2, and the second electrode of the second transistor M2 is connected to the third node N3.
  • the second transistor M2 can be called a compensation transistor.
  • the second transistor M2 connects the control electrode of the third transistor M3 to the second electrode to compensate or reset the control electrode of the third transistor M3.
  • the control electrode of the third transistor M3 is connected to the second node N2, the first electrode of the third transistor M3 is connected to the first node N1, and the second electrode of the third transistor M3 is connected to the third node N3.
  • the third transistor M3 can be called a driving transistor.
  • the third transistor M3 determines the magnitude of the driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between the control electrode and the first electrode of the third transistor M3.
  • the control electrode of the fourth transistor M4 is connected to the first scan signal line Gate1, the first electrode of the fourth transistor M4 is connected to the data signal line Data, and the second electrode of the fourth transistor M4 is connected to the first node N1.
  • the fourth transistor M4 can be called a write transistor. When an on-level scan signal is applied to the first scan signal line Gate1, the fourth transistor M4 inputs the data voltage of the data signal line Data to the pixel driving circuit.
  • the control electrode of the fifth transistor M5 is connected to the light-emitting signal line EM, the first electrode of the fifth transistor M5 is connected to the first power line VDD, and the second electrode of the fifth transistor M5 is connected to the first node N1.
  • the control electrode of the sixth transistor M6 is connected to the light-emitting signal line EM, the first electrode of the sixth transistor M6 is connected to the third node N3, and the second electrode of the sixth transistor M6 is connected to the first electrode of the light-emitting device.
  • the fifth transistor M5 and the sixth transistor M6 can be referred to as light-emitting transistors.
  • the fifth transistor M5 and the sixth transistor M6 form a drive current path between the first power line VDD and the second power line VSS, thereby causing the light-emitting device to emit light.
  • the control electrode of the seventh transistor M7 is connected to the second reset signal line Reset2, the first electrode of the seventh transistor M7 is connected to the second initialization signal line INIT2, and the second electrode of the seventh transistor M7 is connected to the first electrode of the light-emitting device.
  • the seventh transistor M7 can be referred to as an anode reset transistor. When an on-level scan signal is applied to the second reset signal line Reset2, the seventh transistor M7 transmits an initialization voltage to the first electrode of the light-emitting device to initialize or release the charge accumulated in the first electrode of the light-emitting device.
  • the second electrode of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a high level signal.
  • Transistors can be divided into N-type transistors and P-type transistors according to their characteristics.
  • the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages)
  • the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages).
  • the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages)
  • the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).
  • the first transistor M1 and the second transistor M2 may be N-type transistors
  • the third transistor M3 to the seventh transistor M7 may be P-type transistors.
  • the second reset signal line connected to the sub-pixels in this row and the first scan signal line connected to the sub-pixels in the next row may be the same signal line, or may be the same signal or different signals.
  • Figure 3A is an operating timing diagram of the pixel driving circuit provided in Figure 2A.
  • the following illustrates exemplary embodiments of the present disclosure using the operating process of the pixel driving circuit illustrated in Figure 2A.
  • the pixel driving circuit in Figure 2A includes eight transistors (first transistor M1 to eighth transistor M8) and one storage capacitor C.
  • the second transistor M2 is an N-type transistor, and the first transistor M1 and the third transistor M3 to the eighth transistor M8 are all P-type transistors.
  • the operation process of the pixel driving circuit may include:
  • the signal on the first scanning signal line Gate1 is a low-level signal
  • the signals on the first reset signal line Reset1, the second reset signal line Reset2, the second scanning signal line Reset2, and the emission signal line EM are high-level signals
  • the data signal line Data outputs a data voltage.
  • the second end of the storage capacitor C is a low-level signal, so the third transistor M3 is turned on.
  • the fourth transistor M4 is turned on, and when the signal on the second scan signal line Reset2 is high, the second transistor M2 is turned on.
  • the second and fourth transistors M2 and M4 are turned on, so that the data voltage output by the data signal line Data is provided to the second node N2 via the first node N1, the turned-on third transistor M3, the third node N3, and the turned-on second transistor M2.
  • the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is charged into the storage capacitor C.
  • the voltage at the second end (second node N2) of the storage capacitor C is Vd-
  • the signals on the first reset signal line Reset1, the second reset signal line Reset2, and the emission signal line EM are high, turning off the first transistor M1, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8.
  • the signals on the emission signal line EM and the second scan signal terminal Gate2 are low-level signals, while the signals on the first scan signal line Gate1, the first reset signal line Reset1, and the second reset signal line Reset2 are high-level signals.
  • the low-level signal on the emission signal line EM turns on the fifth transistor M5 and the sixth transistor M6.
  • the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor M5, the third transistor M3, and the sixth transistor M6, driving the OLED to emit light.
  • the driving current of the third transistor M3 is no longer affected by the threshold voltage of the third transistor M3, thereby eliminating the influence of the threshold voltage of the third transistor M3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.
  • Figure 3B is an operating timing diagram of the pixel driving circuit provided in Figure 2B.
  • the following describes an exemplary embodiment of the present disclosure using the operating process of the pixel driving circuit illustrated in Figure 2B.
  • the pixel driving circuit in Figure 2B includes seven transistors (first transistor M1 to seventh transistor M7) and one storage capacitor C.
  • the first transistor M1 and the second transistor M2 are N-type transistors, and the third transistor M3 to the seventh transistor M7 are P-type transistors.
  • the operation process of the pixel driving circuit may include:
  • the first phase B1 is called the first reset phase.
  • the signals on the first reset signal line Reset1, the second reset signal line Reset2, the first scan signal line Gate1, the second scan signal line Gate2, and the light-emitting signal line EM are high-level signals.
  • the signal on the first reset signal line Reset is low-level, the first transistor M1 is turned on, and the signal on the first initial signal line INIT1 is written to the third node N3, initializing (resetting) the third node N3 and clearing the existing charge in the third node N3.
  • the signal on the second scan signal line Gate2 is high-level, the second transistor M2 is turned on, and the signal on the third node N3 is provided to the second node N2, initializing (resetting) the storage capacitor C and clearing the existing charge in the storage capacitor.
  • the signal on the second reset signal line Reset2 is low-level, and the signals on the first scan signal line Gate1, the second reset signal line Reset2, and the light-emitting signal line EM are high-level signals, turning off the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor T7. During this phase, the OLED does not emit light.
  • the signals on the first reset signal line Reset1 and the first scan signal line Gate1 are low-level signals, while the signals on the second reset signal line Reset2, the second scan signal line Reset2, and the luminescence signal line EM are high-level signals.
  • the data signal line Data outputs a data voltage.
  • the second end of the storage capacitor C is at a low-level signal, so the third transistor M3 is turned on.
  • the signal on the first scan signal line Gate1 is low, the fourth transistor M4 is turned on, the signal on the second scan signal line Reset2 is high, and the second transistor M2 is turned on.
  • the second and fourth transistors M2 and M4 are turned on, so that the data voltage output by the data signal line Data is provided to the second node N2 via the first node N1, the turned-on third transistor M3, the third node N3, and the turned-on second transistor M2.
  • the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is charged into the storage capacitor C.
  • the voltage at the second end (second node N2) of the storage capacitor C is Vd-
  • the signal on the first reset signal line Reset1 is low, and the signals on the second reset signal line Reset2 and the emission signal line EM are high, turning off the first transistor M1, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7.
  • the third phase B3 is characterized by low-level signals on the first reset signal line Reset1, the second reset signal line Reset2, and the second scan signal line Gate2, while high-level signals on the first scan signal line Gate1 and the light-emitting signal line EM.
  • the seventh transistor M7 is turned on, allowing the signal on the second initialization signal line INIT2 to be supplied to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED and clearing the pre-stored voltage within it.
  • the signals on the first reset signal line Reset1 and the second scan signal line Gate2 are low-level signals, while the signals on the first scan signal line Gate1 and the light-emitting signal line EM are high-level signals.
  • the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are turned off.
  • the signals on the first reset signal line Reset1, the light-emitting signal line EM, and the second scanning signal terminal Gate2 are low-level signals, while the signals on the first scanning signal line Gate1 and the second reset signal line Reset2 are high-level signals.
  • the low-level signal on the light-emitting signal line EM turns on the fifth transistor M5 and the sixth transistor M6.
  • the power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor M5, third transistor M3, and sixth transistor M6, driving the OLED to emit light.
  • the signals on the first scanning signal line Gate1 and the second scanning signal terminal Gate2 are low-level signals, while the signals on the first reset signal line Reset1 and the second reset signal line Reset2 are high-level signals, turning off the first transistor M1, the second transistor M2, the fourth transistor M4, and the seventh transistor M7.
  • the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • )-Vth] 2 K*[(Vdd-Vd] 2
  • I is the driving current flowing through the third transistor M3, that is, the driving current driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor M3
  • Vth is the threshold voltage of the third transistor M3
  • Vd is the data voltage output by the data signal line D
  • Vdd is the power supply voltage output by the first power supply line VDD.
  • the driving current of the third transistor M3 is no longer affected by the threshold voltage of the third transistor M3, thereby eliminating the influence of the threshold voltage of the third transistor M3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.
  • the display device When the display device displays a picture, a driving signal is generated by the gate driving circuit, and the pixel driving circuit is initialized and data is written under the control of the driving signal, thereby realizing display.
  • the picture displayed by the display device may include a normal picture and a special picture (for example: an off-screen display picture, a static picture or a picture that is less updated, etc.).
  • a normal picture When the display device displays a normal picture, it refreshes the picture in each frame, that is, the pixel driving circuit needs to be initialized and data written in each display frame.
  • the display device displays some special pictures, the original brightness can be maintained by a low-leakage pixel driving circuit.
  • the gate driving circuit When the display device displays a special picture, the gate driving circuit generates a driving signal in each frame, and writing data to the pixel driving circuit will cause crosstalk in the picture of the display device, affecting the display effect of the display device.
  • Figure 4 is a schematic diagram of the structure of a shift register provided by an embodiment of the present disclosure.
  • the shift register provided by an embodiment of the present disclosure may include: a cascade output subcircuit, a scan output subcircuit, and a node control subcircuit.
  • the cascade output sub-circuit is electrically connected to the signal input terminal IN, the first clock signal terminal CK, the second clock signal terminal CB, the first power supply terminal VGH, the second power supply terminal VGL and the cascade output signal terminal OUT1, and is configured to provide the signal of the first power supply terminal VGH or the second clock signal terminal CB to the cascade output signal terminal OUT1 under the control of the signals of the signal input terminal IN, the first clock signal terminal CK, the second clock signal terminal CB and the second power supply terminal VGL; the node control sub-circuit is electrically connected to the cascade output sub-circuit, the drive output sub-circuit, the first power supply terminal VGH, the second power supply terminal VGL and the first power supply terminal VGL, respectively.
  • a control input signal terminal IN1 is electrically connected and configured to provide a signal to the driver output subcircuit under the control of a signal from the cascade output subcircuit, the first power supply terminal VGH, the second power supply terminal VGL, and the first control input signal terminal IN1.
  • the driver output subcircuit is electrically connected to the cascade output subcircuit, the node control subcircuit, the first power supply terminal VGH, the second control input signal terminal IN2, and the driver output signal terminal OUT2, respectively, and configured to provide a signal from the first power supply terminal VGH or the second control input signal terminal IN2 to the driver output signal terminal OUT2 under the control of signals from the cascade output subcircuit and the node control subcircuit.
  • the first control input signal terminal IN1 includes a second clock signal terminal CB
  • the second control input signal terminal IN2 includes a mask signal terminal MS.
  • the first control input signal terminal includes the second clock signal terminal CB and the mask signal terminal MS
  • the second control input signal terminal IN2 includes the second clock signal terminal CB.
  • the signal at the signal input terminal IN is a single pulse signal.
  • the signal at either the first clock signal terminal CK1 or the second clock signal terminal CB may be a square wave signal that repeats a high voltage and a low voltage.
  • the signal at the first clock signal terminal CK1 and the second clock signal terminal CK2 may have the same period and may be configured as phase-shifted signals.
  • the signal at the second clock signal terminal CK2 may be phase-shifted by half a period compared to the signal at the first clock signal terminal CK1.
  • the high voltage period in each period of the signal at either the first clock signal terminal CK1 or the second clock signal terminal CK2 may be set to be longer than the low voltage period.
  • the high voltage period of the signal of the first clock signal terminal CK1 can be set so that its width overlaps with the low voltage period of the signal of the second clock signal terminal CK2, and the low voltage period of the signal of the first clock signal terminal CK1 can be set so that its width overlaps with the high voltage period of the signal of the second clock signal terminal CK2.
  • the signal of the first power supply terminal VGH is a constant voltage signal and a high level signal.
  • the signal of the second power terminal VGL is a constant voltage signal and a low level signal.
  • the shift register is provided in a display device, and the content displayed by the display device includes multiple display frames.
  • the driving output subcircuit provided in the embodiment of the present disclosure can control whether the shift register outputs a driving signal to a sub-pixel in the display device within a display frame.
  • the display mode of the display device may include a first display mode and a second display mode, and a refresh rate of the first display mode is greater than a refresh rate of the second display mode.
  • the signal of the cascade output signal terminal OUT1 and the signal of the driving output signal terminal OUT2 of the shift register are the same.
  • the signal at the cascade output signal terminal OUT1 and the signal at the driving output signal terminal OUT2 of the shift register are inverted signals to each other at least partially.
  • the cascade output sub-circuit may be 8T2C, 8T3C, 9T3C, or 9T4C, which is not limited in the present disclosure.
  • FIG5 is an equivalent circuit diagram of a cascade output subcircuit.
  • the cascade output subcircuit may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a first capacitor C1, and a second capacitor C2.
  • the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1;
  • the control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK, and the second electrode of the second transistor T2 is electrically connected to the second node N2;
  • the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal VGL, and the second electrode of the third transistor T3 is electrically connected to the second node N2;
  • the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to the first power supply terminal VGH, and the second electrode of the fourth transistor T4 is electrical
  • a second electrode of the sixth transistor T6 is electrically connected to the first node N1; a control electrode of the sixth transistor T6 is electrically connected to the second node N2, a first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal VGH, and a second electrode of the sixth transistor T6 is electrically connected to the cascade output signal terminal OUT1; a control electrode of the seventh transistor T7 is electrically connected to the third node N3, a first electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CB, and a second electrode of the seventh transistor T7 is electrically connected to the cascade output signal terminal OUT1; a control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal VGL, a first electrode of the eighth transistor T8 is electrically connected to the first node N1, and a second electrode of the eighth transistor T8 is electrically connected to the third node N3; a first end of the first capacitor C1 is electrically connected to the third node N3, and a second
  • FIG6 is a second equivalent circuit diagram of the cascade output sub-circuit.
  • the cascade output sub-circuit may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor C1, a second capacitor C2, and a third capacitor C3.
  • the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1;
  • the control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the second power supply terminal VGL, and the second electrode of the second transistor T2 is electrically connected to the second node N2;
  • the control electrode of the third transistor T3 is electrically connected to the first end of the third capacitor C3, the first electrode of the third transistor T3 is electrically connected to the second clock signal terminal CB, and the second electrode of the third transistor T3 is electrically connected to the second node N2;
  • the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to the second power supply terminal VGL, and the second electrode of the fourth transistor T4 is
  • a first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal VGH, and a second electrode of the sixth transistor T6 is electrically connected to the cascade output signal terminal OUT1;
  • a control electrode of the seventh transistor T7 is electrically connected to the third node N3, a first electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CB, and a second electrode of the seventh transistor T7 is electrically connected to the cascade output signal terminal OUT1;
  • a control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal VGL, a first electrode of the eighth transistor T8 is electrically connected to the first node N1, and a second electrode of the eighth transistor T8 is electrically connected to the third node N3;
  • a control electrode of the ninth transistor T9 is electrically connected to the first node N1, a first electrode of the ninth transistor T9 is electrically connected to the second power supply terminal VGL, and a second electrode of the ninth transistor T9 is electrically connected to a
  • the cascade output sub-circuit may further include a fourth capacitor C4 , wherein a first terminal of the fourth capacitor C4 is electrically connected to the first power supply terminal VGH, and a second terminal of the fourth capacitor C4 is electrically connected to the cascade output signal terminal OUT1 .
  • the provision of the fourth capacitor C4 in the present disclosure can ensure the stability of the signal at the cascade output signal terminal, thereby improving the reliability of the shift register.
  • the sixth transistor T6 and the seventh transistor T7 in Figures 5 and 6 may be referred to as output transistors.
  • a capacitance between a control electrode and a source electrode of at least one of the sixth transistor T6 and the seventh transistor T7 is greater than a capacitance between a control electrode and a source electrode of other transistors in the cascade output sub-circuit except the sixth transistor T6 and the seventh transistor T7.
  • FIG5 and FIG6 show two exemplary structures of the cascade output sub-circuit, and the implementation of the cascade output sub-circuit in the present disclosure is not limited thereto.
  • a first node N1 , a second node N2 , and a third node N3 are provided in the cascade output sub-circuit.
  • the first control input signal terminal includes: a second clock signal terminal CB and a mask signal terminal MS
  • the second control input signal terminal includes: the second clock signal terminal CB
  • the node control sub-circuit can be electrically connected to one of the first node N1 and the third node N3, the second node N2, the mask signal terminal MS, the second clock signal terminal CB, the first power supply terminal VGH, the second power supply terminal VGL, and the fifth node N5, respectively, and is configured to provide a signal of the first power supply terminal VGH or the mask signal terminal MS to the fifth node N5 under the control of signals of one of the first node N1 and the third node N3, the second node N2, the mask signal terminal MS, the second clock signal terminal CB, and the second power supply terminal VGL.
  • the drive output sub-circuit is electrically connected to the second node N2, the fifth node N5, the second clock signal terminal CB, the first power supply terminal VGH, and the drive output signal terminal OUT2, respectively, and is configured to provide the first power supply terminal VG to the drive output signal terminal OUT2 under the control of signals of the second node N2 and the fifth node N5.
  • the first control input signal terminal includes: the second clock signal terminal CB
  • the second control input signal terminal includes: when the mask signal terminal MS is masked, the node control sub-circuit is electrically connected to one of the first node N1 and the third node N3, the second node N2, the second clock signal terminal CB, the first power supply terminal VGH, the second power supply terminal VGL and the fifth node N5, and is configured to provide the signal of the first power supply terminal VGH or the second clock signal terminal CB to the fifth node N5 under the control of the signal of one of the first node N1 and the third node N3, the second node N2, the second clock signal terminal CB and the second power supply terminal VGL.
  • the drive output sub-circuit is electrically connected to the second node N2, the fifth node N5, the first power supply terminal VGH, the mask signal terminal MS and the drive output signal terminal OUT2, and is configured to provide the signal of the first power supply terminal VGH or the mask signal terminal MS to the drive output signal terminal OUT2 under the control of the signal configured to be the second node N2 and the fifth node N5.
  • Figures 5 and 6 are explained using the drive output sub-circuit and the first node N1 as an example.
  • Figure 7 is an equivalent circuit diagram of the driver output subcircuit and the node control subcircuit.
  • the driver output subcircuit includes: a tenth transistor T10, an eleventh transistor T11, and a fifth capacitor C5
  • the node control subcircuit includes: a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a sixth capacitor C6.
  • the control electrode of the tenth transistor T10 is electrically connected to the fifth node N5, the first electrode of the tenth transistor T10 is electrically connected to the second clock signal terminal CB, and the second electrode of the tenth transistor T10 is electrically connected to the drive output signal terminal OUT2;
  • the control electrode of the eleventh transistor T11 is electrically connected to the second node N2, the first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VGH, and the second electrode of the eleventh transistor T11 is electrically connected to the drive output signal terminal OUT2;
  • the control electrode of the twelfth transistor T12 is electrically connected to the fourth node N4, the first electrode of the twelfth transistor T12 is electrically connected to the mask signal terminal MS, and the second electrode of the twelfth transistor T12 is electrically connected to the fifth node N5;
  • the control electrode of the thirteenth transistor T13 is electrically connected to the second clock signal terminal CB, and the thirteenth transistor T13 is electrically
  • a first electrode of the transistor T13 is electrically connected to the second electrode of the fourteenth transistor T14, and the second electrode of the thirteenth transistor T13 is electrically connected to the fifth node N5; a control electrode of the fourteenth transistor T14 is electrically connected to the second node N2, and a first electrode of the fourteenth transistor T14 is electrically connected to the first power supply terminal VGH; a control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VGL, a first electrode of the fifteenth transistor T15 is electrically connected to the first node N1, and a second electrode of the fifteenth transistor T15 is electrically connected to the fourth node N4; a first end of the fifth capacitor C5 is electrically connected to the fifth node N5, and a second end of the fifth capacitor C5 is electrically connected to the drive output signal terminal OUT2; a first end of the sixth capacitor C6 is electrically connected to the fourth node N4, and a second end of the sixth capacitor C6 is electrically connected to the fifth node N5.
  • Figure 7 is an example of a node control sub-circuit electrically connected to the first node N1, the second node N2, the mask signal terminal MS, the second clock signal terminal CB, the first power supply terminal VGH, the second power supply terminal VGL and the fifth node N5, and a driver output sub-circuit electrically connected to the second node N2, the fifth node N5, the second clock signal terminal CB, the first power supply terminal VGH and the driver output signal terminal OUT2.
  • FIG8 is a second equivalent circuit diagram of the driver output subcircuit and the node control subcircuit.
  • the driver output subcircuit may include: a tenth transistor T10, an eleventh transistor T11, and a fifth capacitor C5;
  • the node control subcircuit may include: a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a sixth capacitor C6.
  • the control electrode of the tenth transistor T10 is electrically connected to the fifth node N5, the first electrode of the tenth transistor T10 is electrically connected to the mask signal terminal MS, and the second electrode of the tenth transistor T10 is electrically connected to the drive output signal terminal OUT2;
  • the control electrode of the eleventh transistor T11 is electrically connected to the second node N2, the first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VGH, and the second electrode of the eleventh transistor T11 is electrically connected to the drive output signal terminal OUT2;
  • the control electrode of the twelfth transistor T12 is electrically connected to the fourth node N4, the first electrode of the twelfth transistor T12 is electrically connected to the second clock signal terminal CB, and the second electrode of the twelfth transistor T12 is electrically connected to the fifth node N5;
  • the control electrode of the thirteenth transistor T13 is electrically connected to the second clock signal terminal CB, and the control electrode of the thirteenth transistor T
  • a first electrode of the transistor T13 is electrically connected to the second electrode of the fourteenth transistor T14, and the second electrode of the thirteenth transistor T13 is electrically connected to the fifth node N5; a control electrode of the fourteenth transistor T14 is electrically connected to the second node N2, and a first electrode of the fourteenth transistor T14 is electrically connected to the first power supply terminal VGH; a control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VGL, a first electrode of the fifteenth transistor T15 is electrically connected to the first node N1, and a second electrode of the fifteenth transistor T15 is electrically connected to the fourth node N4; a first end of the fifth capacitor C5 is electrically connected to the fifth node N5, and a second end of the fifth capacitor C5 is electrically connected to the drive output signal terminal OUT2; a first end of the sixth capacitor C6 is electrically connected to the fourth node N4, and a second end of the sixth capacitor C6 is electrically connected to the fifth node N5.
  • Figure 8 is an example of a node control sub-circuit electrically connected to the first node N1, the second node N2, the second clock signal terminal CB, the first power supply terminal VGH, the second power supply terminal VGL and the fifth node N5, and a driver output sub-circuit electrically connected to the second node N2, the fifth node N5, the masking signal terminal MS, the first power supply terminal VGH and the driver output signal terminal OUT2.
  • FIG9 is a third equivalent circuit diagram of the driver output subcircuit and the node control subcircuit.
  • the driver output subcircuit includes a tenth transistor T10, an eleventh transistor T11, and a fifth capacitor C5
  • the node control subcircuit includes a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a sixth capacitor C6.
  • the control electrode of the tenth transistor T10 is electrically connected to the fifth node N5, the first electrode of the tenth transistor T10 is electrically connected to the second clock signal terminal CB, and the second electrode of the tenth transistor T10 is electrically connected to the drive output signal terminal OUT2;
  • the control electrode of the eleventh transistor T11 is electrically connected to the second node N2, the first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VGH, and the second electrode of the eleventh transistor T11 is electrically connected to the drive output signal terminal OUT2;
  • the control electrode of the twelfth transistor T12 is electrically connected to the fourth node N4, the first electrode of the twelfth transistor T12 is electrically connected to the mask signal terminal MS, and the second electrode of the twelfth transistor T12 is electrically connected to the fifth node N5;
  • the control electrode of the thirteenth transistor T13 is electrically connected to the second clock signal terminal CB, and the thirteenth transistor T13 is electrically
  • a first electrode of the body transistor T13 is electrically connected to the second electrode of the fourteenth transistor T14, and the second electrode of the thirteenth transistor T13 is electrically connected to the fifth node N5; a control electrode of the fourteenth transistor T14 is electrically connected to the second node N2, and a first electrode of the fourteenth transistor T14 is electrically connected to the first power supply terminal VGH; a control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VGL, a first electrode of the fifteenth transistor T15 is electrically connected to the third node N3, and a second electrode of the fifteenth transistor T15 is electrically connected to the fourth node N4; a first end of the fifth capacitor C5 is electrically connected to the fifth node N5, and a second end of the fifth capacitor C5 is electrically connected to the drive output signal terminal OUT2; a first end of the sixth capacitor C6 is electrically connected to the fourth node N4, and a second end of the sixth capacitor C6 is electrically connected to the fifth node N5.
  • Figure 9 is an example of a node control sub-circuit electrically connected to the third node N3, the second node N2, the second clock signal terminal CB, the mask signal terminal MS, the first power supply terminal VGH, the second power supply terminal VGL and the fifth node N5, and a driver output sub-circuit electrically connected to the second node N2, the fifth node N5, the second clock signal terminal CB, the first power supply terminal VGH and the driver output signal terminal OUT2.
  • FIG10 is a fourth equivalent circuit diagram of the driver output subcircuit and the node control subcircuit.
  • the driver output subcircuit may include: a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a fifth capacitor C5, and a sixth capacitor C6.
  • the control electrode of the tenth transistor T10 is electrically connected to the fifth node N5, the first electrode of the tenth transistor T10 is electrically connected to the mask signal terminal MS, and the second electrode of the tenth transistor T10 is electrically connected to the drive output signal terminal OUT2;
  • the control electrode of the eleventh transistor T11 is electrically connected to the second node N2, the first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VGH, and the second electrode of the eleventh transistor T11 is electrically connected to the drive output signal terminal OUT2;
  • the control electrode of the twelfth transistor T12 is electrically connected to the fourth node N4, the first electrode of the twelfth transistor T12 is electrically connected to the second clock signal terminal CB, and the second electrode of the twelfth transistor T12 is electrically connected to the fifth node N5;
  • the control electrode of the thirteenth transistor T13 is electrically connected to the second clock signal terminal CB, and the control electrode of the thirteenth transistor T
  • the output signal of the driving output signal terminal OUT2 in Figures 7 and 9 can be the signal of the second clock signal terminal CB, and the signal of the driving output signal terminal OUT2 in Figures 8 and 10 can be the signal of the mask signal terminal MS. Because the signal of the mask signal terminal MS does not frequently jump like the clock signal of the second clock signal terminal CB, the fifth capacitor C5 is charged by the signal of the mask signal terminal MS in Figures 8 and 10, which can reduce the power consumption of the shift register.
  • the driver output subcircuit includes: a tenth transistor T10, an eleventh transistor T11, and a fifth capacitor C5.
  • the node control sub-circuit includes a twelfth transistor T12 , a thirteenth transistor T13 , a fourteenth transistor T14 , a fifteenth transistor T15 and a sixth capacitor C6 .
  • the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1;
  • the control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK, and the second electrode of the second transistor T2 is electrically connected to the second node N2;
  • the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal VGL, and the second electrode of the third transistor T3 is electrically connected to the second node N2;
  • the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to the first power supply terminal VGH, and the second electrode of the fourth transistor T4 is
  • FIG11 illustrates an example in which the tenth transistor T10 is electrically connected to the second clock signal terminal CB, the first electrode of the twelfth transistor T12 is electrically connected to the mask signal terminal MS, and the first electrode of the fifteenth transistor T15 is electrically connected to the first node N1.
  • FIG12 illustrates an example in which the tenth transistor T10 is electrically connected to the second clock signal terminal CB, the first electrode of the twelfth transistor T12 is electrically connected to the mask signal terminal MS, and the first electrode of the fifteenth transistor T15 is electrically connected to the third node N3.
  • FIG13 illustrates an example in which the tenth transistor T10 is electrically connected to the mask signal terminal MS, the first electrode of the twelfth transistor T12 is electrically connected to the second clock signal terminal CB, and the first electrode of the fifteenth transistor T15 is electrically connected to the first node N1.
  • FIG14 illustrates an example in which the tenth transistor T10 is electrically connected to the mask signal terminal MS, the first electrode of the twelfth transistor T12 is electrically connected to the second clock signal terminal CB, and the first electrode of the fifteenth transistor T15 is electrically connected to the third node N3.
  • At least one of the first to eighth transistors T1 to T8 and the ninth to fifteenth transistors T9 to T15 may be a P-type transistor.
  • the driver output subcircuit includes: a tenth transistor T10, an eleventh transistor T11, and a fifth capacitor C5.
  • the node control sub-circuit includes a twelfth transistor T12 , a thirteenth transistor T13 , a fourteenth transistor T14 , a fifteenth transistor T15 and a sixth capacitor C6 .
  • the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1;
  • the control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the second power supply terminal VGL, and the second electrode of the second transistor T2 is electrically connected to the second node N2;
  • the control electrode of the third transistor T3 is electrically connected to the first end of the third capacitor C3, the first electrode of the third transistor T3 is electrically connected to the second clock signal terminal CB, and the second electrode of the third transistor T3 is electrically connected to the second node N2;
  • the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to the second power supply terminal VGL, and the second electrode of the fourth transistor T4
  • a control electrode of the eleventh transistor T11 is electrically connected to the second node N2, a first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VGH, and a second electrode of the eleventh transistor T11 is electrically connected to the drive output signal terminal OUT2;
  • a control electrode of the twelfth transistor T12 is electrically connected to the fourth node N4, a first electrode of the twelfth transistor T12 is electrically connected to the other of the mask signal terminal MS and the second clock signal terminal CB, and a second electrode of the twelfth transistor T12 is electrically connected to the fifth node N5;
  • a control electrode of the thirteenth transistor T13 is electrically connected to the second clock signal terminal CB, a first electrode of the thirteenth transistor T13 is electrically connected to the second electrode of the fourteenth transistor T14, and a second electrode of the
  • FIG15 illustrates an example in which the tenth transistor T10 is electrically connected to the second clock signal terminal CB, the first electrode of the twelfth transistor T12 is electrically connected to the mask signal terminal MS, and the first electrode of the fifteenth transistor T15 is electrically connected to the first node N1.
  • FIG16 illustrates an example in which the tenth transistor T10 is electrically connected to the second clock signal terminal CB, the first electrode of the twelfth transistor T12 is electrically connected to the mask signal terminal MS, and the first electrode of the fifteenth transistor T15 is electrically connected to the third node N3.
  • FIG17 illustrates an example in which the tenth transistor T10 is electrically connected to the mask signal terminal MS, the first electrode of the twelfth transistor T12 is electrically connected to the second clock signal terminal CB, and the first electrode of the fifteenth transistor T15 is electrically connected to the first node N1.
  • FIG18 illustrates an example in which the tenth transistor T10 is electrically connected to the mask signal terminal MS, the first electrode of the twelfth transistor T12 is electrically connected to the second clock signal terminal CB, and the first electrode of the fifteenth transistor T15 is electrically connected to the third node N3.
  • any capacitor among the first capacitor C1 to the sixth capacitor C6 can be a capacitor device made by a process.
  • a capacitor device can be realized by making a special capacitor electrode, and multiple capacitor electrodes of the capacitor can be realized by a metal layer, a semiconductor layer (such as doped polysilicon), etc.
  • any capacitor among the first capacitor C1 to the sixth capacitor C6 can be a parasitic capacitance between multiple devices, which can be realized by the transistor itself and other devices and circuits.
  • the connection method of any capacitor among the first capacitor C1 to the sixth capacitor C6 includes but is not limited to the method described above, and can be other applicable connection methods, and the level of the corresponding node can be stored.
  • the exemplary embodiment of the present disclosure is not limited to this.
  • Figure 19 is a timing diagram of the operation of the shift register provided in Figures 11 to 18 in the first display mode
  • Figure 20 is a timing diagram of the operation of the shift register provided in Figures 11 to 18 in the second display mode.
  • Figures 19 and 20 are described using the example that all transistors in the shift register are P-type transistors.
  • the signal at the masking signal terminal MS is the first signal V1 .
  • the signal at the masking signal terminal MS is the first signal V1 for at least a portion of the time period, and is the second signal V2 for at least a portion of the time period.
  • the time period during which the masking signal terminal MS is the first signal V1 does not overlap with the time period during which the cascade output signal terminal OUT1 outputs a signal, while the time period during which the masking signal terminal MS is the second signal at least partially overlaps with the time period during which the cascade output signal terminal OUT1 outputs a signal.
  • the voltage value of at least one of the first signal V1 and the second signal V2 is constant, and the voltage value of the first signal V1 is lower than the voltage value of the second signal V2.
  • the time t at which the signal at the masking signal terminal MS changes from the first signal to the second signal occurs before the output time period, where the output time period is the time period during which the cascade output signal terminal outputs the signal.
  • the time t at which the signal at the masking signal terminal MS changes from the first signal to the second signal may be within the first time period t1 or the second time period t2, wherein during the first time period t1, the signal at the first clock signal terminal CK is a low-level signal, the first time period t1 occurs before the output time period, the second time period t2 occurs between the first time period t1 and the output time period, and the duration of the second time period t2 is less than the duration of at least one of the first time period t1 or the output time period.
  • FIG20 illustrates the case where the time t at which the signal at the masking signal terminal MS changes from the first signal to the second signal is within the first time period t1.
  • the eighth transistor T8 and the fifteenth transistor T15 are continuously turned on.
  • the difference between the shift register provided in FIG11 and the shift register provided in FIG12 is that the first electrode of the fifteenth transistor T15 is connected to different nodes.
  • the signal of the first node N1 is written to the fourth node N4
  • the signal of the third node N3 is written to the fourth node N4. Since the fifteenth transistor T15 is continuously turned on, the signals at the first node N1 and the third node N3 are the same. Therefore, the operation process of the shift register provided in FIG11 and the shift register provided in FIG12 is the same.
  • the first clock signal terminal CK, the signal input terminal IN and the mask signal terminal MS are low-level signals
  • the signal of the second clock signal terminal CB is a high-level signal
  • the first transistor T1 and the third transistor T3 are turned on
  • the fifth transistor T5 and the thirteenth transistor T13 are turned off.
  • the first transistor T1 is turned on, and the low-level signal of the signal input terminal IN is written into the first node N1.
  • the low-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8.
  • the seventh transistor T7 is turned on, and the high-level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1.
  • the low-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15.
  • the twelfth transistor T12 is turned on, and the low-level signal of the mask signal terminal MS is written into the fifth node N5.
  • the tenth transistor T10 is turned on, and the high-level signal of the second clock signal terminal CB is written into the drive output signal terminal OUT2.
  • the signal at the first node N1 is a low-level signal
  • the second transistor T2 is turned on, the low-level signal of the first clock signal terminal CK is written into the second node N2
  • the third transistor T3 is turned on, the low-level signal of the second power supply terminal VGL is written into the second node N2
  • the signal at the second node N2 is a low-level signal
  • the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned on, and the high-level signal of the first power supply terminal VGH is written into the node connecting the fourth transistor T4 and the fifth transistor T5, the node connecting the thirteenth transistor T13 and the fourteenth transistor T14, the cascade output signal terminal OUT1 and the drive output signal terminal OUT2.
  • the signals of the first node N1, the second node N2, the third node N3, the fourth node N4 and the fifth node N5 are all low level signals, and the signals of the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are high level signals.
  • the signals at the second clock signal terminal CB and the mask signal terminal MS are low-level signals
  • the signals at the first clock signal terminal CK and the signal input terminal IN are high-level signals
  • the first transistor T1 and the third transistor T3 are turned off
  • the fifth transistor T5 and the thirteenth transistor T13 are turned on.
  • the first transistor T1 is disconnected, and the high-level signal of the signal input terminal IN cannot be written to the first node N1.
  • the signal of the first node N1 maintains the low-level signal of the previous stage.
  • the low-level signal of the first node N1 is written to the third node N3 through the conductive eighth transistor T8.
  • the seventh transistor T7 is turned on, and the low-level signal of the second clock signal terminal CB is written to the cascade output signal terminal OUT1.
  • the signal of the cascade output signal terminal OUT1 is a low-level signal. Under the action of the first capacitor C1, the signal of the third node N3 is continuously pulled low.
  • the low-level signal of the third node N3 is written to the first node N1 through the conductive eighth transistor T8.
  • the first node N1 is continuously pulled low.
  • the low-level signal of the first node N1 or the third node N3 is written to the fourth node N4 through the conductive fifteenth transistor T15.
  • the twelfth transistor T12 is turned on, and the low-level signal of the mask signal terminal MS is written to the fifth node N5.
  • the tenth transistor T10 is turned on, and the low-level signal of the second clock signal terminal CB is written to the drive output signal terminal OUT2.
  • the signal at the first node N1 is a low-level signal
  • the second transistor T2 is turned on
  • the high-level signal of the first clock signal terminal CK is written into the second node N2
  • the third transistor T3 is turned off
  • the low-level signal of the second power supply terminal VGL cannot be written into the second node N2
  • the signal at the second node N2 is a high-level signal
  • the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned off, and the high-level signal of the first power supply terminal VGH cannot be written into the node connecting the fourth transistor T4 and the fifth transistor T5, the node connecting the thirteenth transistor T13 and the fourteenth transistor T14, the cascade output signal terminal OUT1 and the drive output signal terminal OUT2.
  • the signals at the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all low level signals
  • the signal at the second node N2 is high level signal
  • the signals at the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are low level signals.
  • the signals at the first clock signal terminal CK and the mask signal terminal MS are low-level signals
  • the signals at the signal input terminal IN and the second clock signal terminal CB are high-level signals
  • the first transistor T1 and the third transistor T3 are turned on
  • the fifth transistor T5 and the thirteenth transistor T13 are turned off.
  • the first transistor T1 is turned on, and the high-level signal at the signal input terminal IN is written to the first node N1.
  • the high-level signal at the first node N1 is written to the third node N3 via the turned-on eighth transistor T8.
  • the seventh transistor T7 is turned off, and the high-level signal at the first node N1 or the third node N3 is written to the fourth node N4 via the turned-on fifteenth transistor T15.
  • the twelfth transistor T12 is turned off, and the low-level signal at the masked signal terminal MS cannot be written to the fifth node N5.
  • the signal at the fourth node N4 is pulled high in this stage, the signal at the fifth node N5 is also pulled high by the action of the sixth capacitor C6, and the signal at the fifth node N5 is a high-level signal.
  • the tenth transistor T10 is turned off.
  • the signal at the first node N1 is a high-level signal
  • the second transistor T2 is turned off, the low-level signal at the first clock signal terminal CK cannot be written into the second node N2
  • the third transistor T3 is turned on, the low-level signal at the second power supply terminal VGL is written into the second node N2
  • the signal at the second node N2 is a low-level signal
  • the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned on
  • the high-level signal at the first power supply terminal VGH is written into the node connecting the fourth transistor T4 and the fifth transistor T5, the node connecting the thirteenth transistor T13 and the fourteenth transistor T14, the cascade output signal terminal OUT1 and the drive output signal terminal OUT2.
  • the signal at the second node N2 remains low at the previous stage.
  • the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned on, and the high-level signal at the first power supply terminal VGH is written to the node connecting the fourth transistor T4 and the fifth transistor T5, the node connecting the thirteenth transistor T13 and the fourteenth transistor T14, the cascade output signal terminal OUT1, and the driver output signal terminal OUT2.
  • the high level signal of the first power supply terminal VGH is written into the fifth node N5 through the turned-on thirteenth transistor T13, and the tenth transistor T10 is turned off.
  • the signals at the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all high level signals
  • the signal at the second node N2 is low level signal
  • the signals at the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are high level signals.
  • the difference between the shift register provided in FIG13 and the shift register provided in FIG14 is that the first electrode of the fifteenth transistor T15 is connected to different nodes.
  • the signal of the first node N1 is written to the fourth node N4
  • the signal of the third node N3 is written to the fourth node N4. Since the fifteenth transistor T15 is continuously turned on, the signals at the first node N1 and the third node N3 are the same. Therefore, the operation process of the shift register provided in FIG13 and the shift register provided in FIG14 is the same.
  • the signals at the second clock signal terminal CB and the mask signal terminal MS are low-level signals
  • the signals at the first clock signal terminal CK and the signal input terminal IN are high-level signals
  • the first transistor T1 and the third transistor T3 are turned off
  • the fifth transistor T5 and the thirteenth transistor T13 are turned on.
  • the first transistor T1 is disconnected, and the high-level signal of the signal input terminal IN cannot be written into the first node N1.
  • the signal of the first node N1 maintains the low-level signal of the previous stage.
  • the low-level signal of the first node N1 is written into the third node N3 through the conductive eighth transistor T8.
  • the seventh transistor T7 is turned on, and the low-level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1.
  • the signal of the cascade output signal terminal OUT1 is a low-level signal. Under the action of the first capacitor C1, the signal of the third node N3 is continuously pulled low.
  • the low-level signal of the third node N3 is written into the first node N1 through the conductive eighth transistor T8.
  • the signal at the first node N1 is a low-level signal
  • the second transistor T2 is turned on
  • the high-level signal of the first clock signal terminal CK is written into the second node N2
  • the third transistor T3 is turned off
  • the low-level signal of the second power supply terminal VGL cannot be written into the second node N2
  • the signal at the second node N2 is a high-level signal
  • the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned off, and the high-level signal of the first power supply terminal VGH cannot be written into the node connecting the fourth transistor T4 and the fifth transistor T5, the node connecting the thirteenth transistor T13 and the fourteenth transistor T14, the cascade output signal terminal OUT1 and the drive output signal terminal OUT2.
  • the signals at the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all low level signals
  • the signal at the second node N2 is high level signal
  • the signals at the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are low level signals.
  • the signals at the first clock signal terminal CK and the mask signal terminal MS are low-level signals
  • the signals at the signal input terminal IN and the second clock signal terminal CB are high-level signals
  • the first transistor T1 and the third transistor T3 are turned on
  • the fifth transistor T5 and the thirteenth transistor T13 are turned off.
  • the first transistor T1 is turned on, and the high-level signal at the signal input terminal IN is written into the first node N1.
  • the high-level signal at the first node N1 is written into the third node N3 via the turned-on eighth transistor T8.
  • the seventh transistor T7 is turned off, and the high-level signal at the first node N1 or the third node N3 is written into the fourth node N4 via the turned-on fifteenth transistor T15.
  • the twelfth transistor T12 is turned off, and the high-level signal at the second clock signal terminal CB cannot be written into the fifth node N5.
  • the signal at the fourth node N4 is pulled high in this stage, the signal at the fifth node N5 is also pulled high by the action of the sixth capacitor C6, and the signal at the fifth node N5 is a high-level signal.
  • the tenth transistor T10 is turned off.
  • the signal at the first node N1 is a high-level signal
  • the second transistor T2 is turned off, the low-level signal at the first clock signal terminal CK cannot be written into the second node N2
  • the third transistor T3 is turned on, the low-level signal at the second power supply terminal VGL is written into the second node N2
  • the signal at the second node N2 is a low-level signal
  • the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned on
  • the high-level signal at the first power supply terminal VGH is written into the node connecting the fourth transistor T4 and the fifth transistor T5, the node connecting the thirteenth transistor T13 and the fourteenth transistor T14, the cascade output signal terminal OUT1 and the drive output signal terminal OUT2.
  • the signals of the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all high-level signals
  • the signal of the second node N2 is a low-level signal
  • the signals of the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are high-level signals.
  • the signals of the second clock signal terminal CB and the mask signal terminal MS are low-level signals
  • the signals of the first clock signal terminal CK and the signal input terminal IN are high-level signals
  • the first transistor T1 and the third transistor T3 are turned off
  • the fifth transistor T5 and the thirteenth transistor T13 are turned on.
  • the first transistor T1 is turned off, and the signal at the first node N1 remains high at the previous stage.
  • the high-level signal at the first node N1 is written to the third node N3 via the conductive eighth transistor T8.
  • the seventh transistor T7 is turned off, and the high-level signal at the first node N1 or the third node N3 is written to the fourth node N4 via the conductive fifteenth transistor T15.
  • the twelfth transistor T12 is turned off, and the low-level signal at the second clock signal terminal CB cannot be written to the fifth node N5.
  • the signal at the first node N1 is high, and the second transistor T2 is turned off.
  • the high-level signal at the first clock signal terminal CK cannot be written to the second node N2.
  • the signal at the second node N2 remains low at the previous stage.
  • the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned on, and the high-level signal at the first power supply terminal VGH is written to the node connecting the fourth transistor T4 and the fifth transistor T5, the node connecting the thirteenth transistor T13 and the fourteenth transistor T14, the cascade output signal terminal OUT1, and the driver output signal terminal OUT2.
  • the high level signal of the first power supply terminal VGH is written into the fifth node N5 through the turned-on thirteenth transistor T13, and the tenth transistor T10 is turned off.
  • the signals at the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all high level signals
  • the signal at the second node N2 is low level signal
  • the signals at the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are high level signals.
  • the shift register continues to execute the third stage S13 and the fourth stage S14.
  • the tenth transistor T10 is turned off, and the low-level signal of the masked signal terminal MS cannot be written into the drive output signal terminal OUT2.
  • the signal at the first node N1 is a low-level signal
  • the second transistor T2 is turned on, the low-level signal of the first clock signal terminal CK is written into the second node N2
  • the third transistor T3 is turned on, the low-level signal of the second power supply terminal VGL is written into the second node N2
  • the signal at the second node N2 is a low-level signal
  • the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned on, and the high-level signal of the first power supply terminal VGH is written into the node connecting the fourth transistor T4 and the fifth transistor T5, the node connecting the thirteenth transistor T13 and the fourteenth transistor T14, the cascade output signal terminal OUT1 and the drive output signal terminal OUT2.
  • the signals of the first node N1, the second node N2, the third node N3, the fourth node N4 and the fifth node N5 are all low level signals, and the signals of the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are high level signals.
  • the first transistor T1 is turned off, and the signal of the first node N1 maintains the high-level signal of the previous stage.
  • the high-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8.
  • the seventh transistor T7 is turned off, and the high-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15.
  • the twelfth transistor T12 is turned off, and the low-level signal of the second clock signal terminal CB cannot be written into the fifth node N5.
  • the shift register Before the signal at the signal input terminal IN becomes a low level signal, the shift register continues to execute the third stage S23 and the fourth stage S24.
  • the difference between the shift register provided in FIG15 and the shift register provided in FIG16 is that the first electrode of the fifteenth transistor T15 is connected to different nodes.
  • the signal of the first node N1 is written to the fourth node N4
  • the signal of the third node N3 is written to the fourth node N4. Since the fifteenth transistor T15 is continuously turned on, the signals at the first node N1 and the third node N3 are the same. Therefore, the operation process of the shift register provided in FIG15 and the shift register provided in FIG16 is the same.
  • the first clock signal terminal CK, the signal input terminal IN and the mask signal terminal MS are low level signals
  • the signal of the second clock signal terminal CB is high level signal
  • the first transistor T1 is turned on
  • the fifth transistor T5 and the thirteenth transistor T13 are turned off.
  • the first transistor T1 is turned on, and the low-level signal of the signal input terminal IN is written into the first node N1.
  • the low-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8.
  • the seventh transistor T7 is turned on, and the high-level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1.
  • the low-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15.
  • the twelfth transistor T12 is turned on, and the low-level signal of the mask signal terminal MS is written into the fifth node N5.
  • the tenth transistor T10 is turned on, and the high-level signal of the second clock signal terminal CB is written into the drive output signal terminal OUT2.
  • the signal at the first node N1 is a low-level signal
  • the second transistor T2 and the ninth transistor T9 are turned on, the high-level signal at the first power supply terminal VGH is written into the first end of the third capacitor C3 through the turned-on ninth transistor T9, and the third capacitor C3 is charged.
  • the third transistor T3 is turned off, the high-level signal at the first power supply terminal VGH is written into the second node N2 through the turned-on second transistor T2, and the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned off.
  • the signals at the second clock signal terminal CB and the mask signal terminal MS are low level signals
  • the signals at the signal input terminal IN and the first clock signal terminal CK are high level signals
  • the first transistor T1 is turned off
  • the fifth transistor T5 and the thirteenth transistor T13 are turned on.
  • the first transistor T1 is turned off, so that the high-level signal of the signal input terminal IN cannot be written into the first node N1.
  • the signal of the first node N1 maintains the low-level signal of the previous stage.
  • the signal of the third node N3 is a low-level signal.
  • the seventh transistor T7 is turned on, and the low-level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1.
  • the low-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15.
  • the twelfth transistor T12 is turned on, and the low-level signal of the mask signal terminal MS is written into the fifth node N5.
  • the tenth transistor T10 is turned on, and the low-level signal of the second clock signal terminal CB is written into the drive output signal terminal OUT2.
  • the signal at the first node N1 is a low-level signal
  • the second transistor T2 and the ninth transistor T9 are turned on, the high-level signal at the first power supply terminal VGH is still written into the first end of the third capacitor C3 through the turned-on ninth transistor T9, and the third capacitor C3 is charged.
  • the third transistor T3 is turned off, and the high-level signal at the first power supply terminal VGH is written into the second node N2 through the turned-on second transistor T2.
  • the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned off.
  • the signals at the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all low level signals
  • the signal at the second node N2 is high level signal
  • the signals at the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are low level signals.
  • the signals at the first clock signal terminal CK and the mask signal terminal MS are low level signals
  • the signals at the signal input terminal IN and the second clock signal terminal CB are high level signals
  • the first transistor T1 is turned on
  • the fifth transistor T5 and the thirteenth transistor T13 are turned off.
  • the first transistor T1 is turned on, and the high-level signal of the signal input terminal IN is written into the first node N1.
  • the high-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8.
  • the seventh transistor T7 is turned off. Under the coupling action of the first capacitor C1, the signal of the cascade output signal terminal OUT becomes a high-level signal.
  • the high-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15.
  • the twelfth transistor T12 is turned off, and the low-level signal of the masked signal terminal MS cannot be written into the fifth node N5.
  • the signal of the fifth node N5 becomes a high-level signal.
  • the tenth transistor T10 is turned off.
  • the signal of the output signal terminal OUT2 is driven to become a high-level signal.
  • the signal at the first node N1 is a high-level signal
  • the second transistor T2 and the ninth transistor T9 are disconnected, and the second end of the third capacitor C3 is floating. Due to the high-level signal at the second clock signal terminal CB, the signal at the second end of the third capacitor C3 is a high-level signal under the coupling effect of the third capacitor C3.
  • the signals of the first node N1, the second node N2, the third node N3, the fourth node N4 and the fifth node N5 are all high level signals, and the signals of the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are high level signals.
  • the signals at the second clock signal terminal CB and the mask signal terminal MS are low level signals
  • the signals at the signal input terminal IN and the first clock signal terminal CK are high level signals
  • the first transistor T1 is turned off
  • the fifth transistor T5 and the thirteenth transistor T13 are turned on.
  • the first transistor T1 is disconnected, so that the high-level signal of the signal input terminal IN cannot be written to the first node N1.
  • the signal of the first node N1 maintains the high-level signal of the previous stage.
  • the high-level signal of the first node N1 is written to the third node N3 through the conductive eighth transistor T8.
  • the seventh transistor T7 is disconnected, and the high-level signal of the first node N1 or the third node N3 is written to the fourth node N4 through the conductive fifteenth transistor T15.
  • the twelfth transistor T12 is disconnected, and the low-level signal of the masked signal terminal MS cannot be written to the fifth node N5.
  • the fifth node N5 maintains the high-level signal of the previous stage.
  • the tenth transistor T10 is disconnected.
  • the signal at the first node N1 is a high-level signal
  • the second transistor T2 and the ninth transistor T9 are disconnected, and the second end of the third capacitor C3 is floating. Due to the low-level signal of the signal at the second clock signal terminal CB, the signal at the second end of the third capacitor C3 is a low-level signal under the coupling effect of the third capacitor C3.
  • the third transistor T3 is turned on, and the low-level signal at the second clock signal terminal CB is written to the second node N2.
  • the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned on, and the high-level signal of the first power supply terminal VGH is written to the cascade output signal terminal OUT1, the drive output signal terminal OUT2, the node connecting the fourth transistor T4 and the fifth transistor T5, and the node connecting the thirteenth transistor T13 and the fourteenth transistor T14. Since the fourth transistor T4 and the fifth transistor T5 are turned on, the high-level signal of the first power supply terminal VGH is written into the first node N1, so that the signal of the first node N1 remains at a high-level signal. Since the thirteenth transistor T13 and the fourteenth transistor T14 are turned on, the high-level signal of the first power supply terminal VGH is written into the fifth node N5, so that the signal of the fifth node N5 remains at a high-level signal.
  • the signals of the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all high level signals
  • the signal of the second node N2 is low level signal
  • the signals of the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are all high level signals.
  • the signals at the first clock signal terminal CK and the signal input terminal IN are low-level signals
  • the signal at the masked signal terminal MS is a low-level signal in at least part of the time period and a high-level signal in at least part of the time period
  • the time period in which the signal at the masked signal terminal MS is a low-level signal occurs before the time period in which the signal at the masked signal terminal MS is a high-level signal
  • the signal at the second clock signal terminal CB is a high-level signal
  • the first transistor T1 is turned on
  • the fifth transistor T5 and the thirteenth transistor T13 are turned off.
  • the tenth transistor T10 is turned on, and the high-level signal at the second clock signal terminal CB is written to the drive output signal terminal OUT2. During the time period when the signal at the mask signal terminal MS is a high-level signal, the high-level signal at the mask signal terminal MS is written to the fifth node N5. The tenth transistor T10 is turned off. The signal at the first node N1 is a low-level signal, the second transistor T2 and the ninth transistor T9 are turned on, the high-level signal at the first power supply terminal VGH is written into the first end of the third capacitor C3 through the turned-on ninth transistor T9, and the third capacitor C3 is charged.
  • the signals at the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all low level signals
  • the signal at the second node N2 is high level signal
  • the signals at the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are high level signals.
  • the signal at the second clock signal terminal CB is a low level signal
  • the signals at the signal input terminal IN, the first clock signal terminal CK and the mask signal terminal MS are high level signals
  • the first transistor T1 is turned off
  • the fifth transistor T5 and the thirteenth transistor T13 are turned on.
  • the first transistor T1 is turned off, so that the high-level signal of the signal input terminal IN cannot be written to the first node N1.
  • the signal of the first node N1 remains the low-level signal in the previous stage.
  • the signal of the third node N3 is a low-level signal.
  • the seventh transistor T7 is turned on, and the low-level signal of the second clock signal terminal CB is written to the cascade output signal terminal OUT1.
  • the low-level signal of the first node N1 or the third node N3 is written to the fourth node N4 through the turned-on fifteenth transistor T15.
  • the twelfth transistor T12 is turned on, and the high-level signal of the masked signal terminal MS is written to the fifth node N5.
  • the tenth transistor T10 is turned off, and the low-level signal of the second clock signal terminal CB cannot be written to the drive output signal terminal OUT2. Under the coupling action of the fifth capacitor C5, the signal of the drive output signal terminal OUT2 remains the high-level signal in the previous stage.
  • the signal at the first node N1 is a low-level signal
  • the second transistor T2 and the ninth transistor T9 are turned on, the high-level signal at the first power supply terminal VGH is still written into the first end of the third capacitor C3 through the turned-on ninth transistor T9, and the third capacitor C3 is charged.
  • the third transistor T3 is turned off, and the high-level signal at the first power supply terminal VGH is written into the second node N2 through the turned-on second transistor T2.
  • the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned off.
  • the signals at the first, third, fourth, and fifth nodes N1, N3, N4, and N5 are all low-level signals, while the signal at the second node N2 is high-level.
  • the signal at the cascade output signal terminal OUT1 is low-level, driving the output signal terminal OUT2 to float and maintain the high-level signal from the previous phase.
  • the signal at the first clock signal terminal CK is a low level signal
  • the signals at the signal input terminal IN, the second clock signal terminal CB and the mask signal terminal MS are high level signals
  • the first transistor T1 is turned on
  • the fifth transistor T5 and the thirteenth transistor T13 are turned off.
  • the signal of the fifth node N5 becomes a high-level signal.
  • the tenth transistor T10 is turned off.
  • the signal of the output signal terminal OUT2 is driven to become a high-level signal.
  • the signal at the first node N1 is a high-level signal
  • the second transistor T2 and the ninth transistor T9 are disconnected, and the second end of the third capacitor C3 is floating. Due to the high-level signal at the second clock signal terminal CB, the signal at the second end of the third capacitor C3 is a high-level signal under the coupling effect of the third capacitor C3.
  • the third transistor T3 is disconnected, and the second capacitor C2 is discharged, so that the signal at the second node N2 remains a high-level signal in the previous stage.
  • the high-level signal at the first power supply terminal VGH cannot be written to the second node N2 through the conductive second transistor T2.
  • the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are disconnected.
  • the signals of the first node N1, the second node N2, the third node N3, the fourth node N4 and the fifth node N5 are all high-level signals
  • the signal of the cascade output signal terminal OUT1 is a high-level signal, driving the output signal terminal OUT2 to float and maintain the high-level signal of the previous stage.
  • the signal at the second clock signal terminal CB is a low level signal
  • the signals at the signal input terminal IN, the first clock signal terminal CK and the mask signal terminal MS are high level signals
  • the first transistor T1 is turned off
  • the fifth transistor T5 and the thirteenth transistor T13 are turned on.
  • the first transistor T1 is disconnected, so that the high-level signal of the signal input terminal IN cannot be written into the first node N1.
  • the signal of the first node N1 maintains the high-level signal of the previous stage.
  • the high-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8.
  • the seventh transistor T7 is disconnected, and the high-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15.
  • the twelfth transistor T12 is disconnected, and the high-level signal of the masked signal terminal MS cannot be written into the fifth node N5.
  • the tenth transistor T10 is disconnected.
  • the signal at the first node N1 is a high-level signal
  • the second transistor T2 and the ninth transistor T9 are disconnected, and the second end of the third capacitor C3 is floating. Due to the low-level signal of the signal at the second clock signal terminal CB, the signal at the second end of the third capacitor C3 is a low-level signal under the coupling effect of the third capacitor C3.
  • the third transistor T3 is turned on, and the low-level signal at the second clock signal terminal CB is written to the second node N2.
  • the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned on, and the high-level signal of the first power supply terminal VGH is written to the cascade output signal terminal OUT1, the drive output signal terminal OUT2, the node connecting the fourth transistor T4 and the fifth transistor T5, and the node connecting the thirteenth transistor T13 and the fourteenth transistor T14. Since the fourth transistor T4 and the fifth transistor T5 are turned on, the high-level signal of the first power supply terminal VGH is written into the first node N1, so that the signal of the first node N1 remains at a high-level signal. Since the thirteenth transistor T13 and the fourteenth transistor T14 are turned on, the high-level signal of the first power supply terminal VGH is written into the fifth node N5, so that the signal of the fifth node N5 remains at a high-level signal.
  • the signals of the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all high level signals
  • the signal of the second node N2 is low level signal
  • the signals of the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are all high level signals.
  • the difference between the shift register provided in FIG17 and the shift register provided in FIG18 is that the first electrode of the fifteenth transistor T15 is connected to different nodes.
  • the signal of the first node N1 is written to the fourth node N4
  • the signal of the third node N3 is written to the fourth node N4. Since the fifteenth transistor T15 is continuously turned on, the signals at the first node N1 and the third node N3 are the same. Therefore, the operation process of the shift register provided in FIG17 and the shift register provided in FIG18 is the same.
  • the first clock signal terminal CK, the signal input terminal IN and the mask signal terminal MS are low level signals
  • the signal of the second clock signal terminal CB is high level signal
  • the first transistor T1 is turned on
  • the fifth transistor T5 and the thirteenth transistor T13 are turned off.
  • the first transistor T1 is turned on, and the low-level signal of the signal input terminal IN is written into the first node N1.
  • the low-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8.
  • the seventh transistor T7 is turned on, and the high-level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1.
  • the low-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15.
  • the twelfth transistor T12 is turned on, and the high-level signal of the second clock signal terminal CB is written into the fifth node N5.
  • the tenth transistor T10 is turned off, and the low-level signal of the masked signal terminal MS cannot be written into the drive output signal terminal OUT2.
  • the signal at the first node N1 is a low-level signal
  • the second transistor T2 and the ninth transistor T9 are turned on, the high-level signal at the first power supply terminal VGH is written into the first end of the third capacitor C3 through the turned-on ninth transistor T9, and the third capacitor C3 is charged.
  • the third transistor T3 is turned off, the high-level signal at the first power supply terminal VGH is written into the second node N2 through the turned-on second transistor T2, and the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned off.
  • the signals at the first, third, and fourth nodes N1, N3, and N4 are all low-level signals, while the signals at the second and fifth nodes N2 and N5 are high-level signals.
  • the signal at the cascade output signal terminal OUT1 is high-level, driving the output signal terminal OUT2 to float and maintain the high-level signal from the previous phase.
  • the signals at the second clock signal terminal CB and the mask signal terminal MS are low level signals
  • the signals at the signal input terminal IN and the first clock signal terminal CK are high level signals
  • the first transistor T1 is turned off
  • the fifth transistor T5 and the thirteenth transistor T13 are turned on.
  • the first transistor T1 is turned off, so that the high-level signal of the signal input terminal IN cannot be written into the first node N1.
  • the signal of the first node N1 maintains the low-level signal of the previous stage.
  • the signal of the third node N3 is a low-level signal.
  • the signal of the third node N3 is a low-level signal.
  • the seventh transistor T7 is turned on, and the low-level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1.
  • the signal of the cascade output signal terminal OUT1 is a low-level signal.
  • the low-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15.
  • the signals at the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all low level signals
  • the signal at the second node N2 is high level signal
  • the signals at the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are low level signals.
  • the signals at the first clock signal terminal CK and the mask signal terminal MS are low level signals
  • the signals at the signal input terminal IN and the second clock signal terminal CB are high level signals
  • the first transistor T1 is turned on
  • the fifth transistor T5 and the thirteenth transistor T13 are turned off.
  • the first transistor T1 is turned on, and the high-level signal of the signal input terminal IN is written into the first node N1.
  • the high-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8.
  • the seventh transistor T7 is turned off. Under the coupling effect of the first capacitor C1, the signal of the cascade output signal terminal OUT becomes a high-level signal.
  • the high-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15.
  • the twelfth transistor T12 is turned off, and the high-level signal of the second clock signal terminal CB cannot be written into the fifth node N5.
  • the signal of the fifth node N5 becomes a high-level signal.
  • the tenth transistor T10 is turned off.
  • the signal of the output signal terminal OUT2 is driven to become a high-level signal.
  • the signal at the first node N1 is a high-level signal
  • the second transistor T2 and the ninth transistor T9 are disconnected, and the second end of the third capacitor C3 is floating. Due to the high-level signal at the second clock signal terminal CB, the signal at the second end of the third capacitor C3 is a high-level signal under the coupling effect of the third capacitor C3.
  • the third transistor T3 is disconnected, and the second capacitor C2 is discharged, so that the signal at the second node N2 remains a high-level signal in the previous stage.
  • the high-level signal at the first power supply terminal VGH cannot be written to the second node N2 through the conductive second transistor T2.
  • the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are disconnected.
  • the signals of the first node N1, the second node N2, the third node N3, the fourth node N4 and the fifth node N5 are all high-level signals
  • the cascade output signal terminal OUT1 is floating and maintains the high-level signal of the previous stage
  • the drive output signal terminal OUT2 is floating and maintains the high-level signal of the previous stage.
  • the signals at the second clock signal terminal CB and the mask signal terminal MS are low level signals
  • the signals at the signal input terminal IN and the first clock signal terminal CK are high level signals
  • the first transistor T1 is turned off
  • the fifth transistor T5 and the thirteenth transistor T13 are turned on.
  • the first transistor T1 is turned off, so that the high-level signal of the signal input terminal IN cannot be written to the first node N1.
  • the signal of the first node N1 maintains the high-level signal of the previous stage.
  • the high-level signal of the first node N1 is written to the third node N3 through the conductive eighth transistor T8.
  • the seventh transistor T7 is turned off, the first capacitor C1 is discharged, the signal of the cascade output signal terminal OUT1 is a high-level signal, the high-level signal of the first node N1 or the third node N3 is written to the fourth node N4 through the conductive fifteenth transistor T15, the twelfth transistor T12 is turned off, the low-level signal of the second clock signal terminal CB cannot be written to the fifth node N5, the fifth node N5 maintains the high-level signal of the previous stage, and the tenth transistor T10 is turned off.
  • the signal at the first node N1 is a high-level signal
  • the second transistor T2 and the ninth transistor T9 are disconnected, and the second end of the third capacitor C3 is floating.
  • the signal at the second end of the third capacitor C3 is a low-level signal under the coupling effect of the third capacitor C3.
  • the third transistor T3 is turned on, and the low-level signal at the second clock signal terminal CB is written to the second node N2.
  • the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned on, and the high-level signal of the first power supply terminal VGH is written to the cascade output signal terminal OUT1, the drive output signal terminal OUT2, the node connecting the fourth transistor T4 and the fifth transistor T5, and the node connecting the thirteenth transistor T13 and the fourteenth transistor T14.
  • the fourth transistor T4 and the fifth transistor T5 are turned on, the high-level signal of the first power supply terminal VGH is written into the first node N1, so that the signal of the first node N1 remains at a high-level signal. Since the thirteenth transistor T13 and the fourteenth transistor T14 are turned on, the high-level signal of the first power supply terminal VGH is written into the fifth node N5, so that the signal of the fifth node N5 remains at a high-level signal.
  • the first clock signal terminal CK and the signal input terminal IN are low-level signals
  • the signal of the masked signal terminal MS is a low-level signal in at least part of the time period and a high-level signal in at least part of the time period
  • the time period when the signal of the masked signal terminal MS is a low-level signal occurs before the time period when the signal of the masked signal terminal MS is a high-level signal
  • the signal of the second clock signal terminal CB is a high-level signal
  • the first transistor T1 is turned on
  • the fifth transistor T5 and the thirteenth transistor T13 are turned off.
  • the tenth transistor T10 is turned off, and the low-level signal of the masked signal terminal MS cannot be written into the drive output signal terminal OUT2.
  • the signal at the first node N1 is a low-level signal
  • the second transistor T2 and the ninth transistor T9 are turned on, the high-level signal at the first power supply terminal VGH is written into the first end of the third capacitor C3 through the turned-on ninth transistor T9, and the third capacitor C3 is charged.
  • the third transistor T3 is turned off, the high-level signal at the first power supply terminal VGH is written into the second node N2 through the turned-on second transistor T2, and the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned off.
  • the signals at the first, third, and fourth nodes N1, N3, and N4 are all low-level signals, while the signals at the second and fifth nodes N2 and N5 are high-level signals.
  • the signal at the cascade output signal terminal OUT1 is high-level, driving the output signal terminal OUT2 to float and maintain the high-level signal from the previous phase.
  • the signal at the second clock signal terminal CB is a low level signal
  • the signals at the signal input terminal IN, the first clock signal terminal CK and the mask signal terminal MS are high level signals
  • the first transistor T1 is turned off
  • the fifth transistor T5 and the thirteenth transistor T13 are turned on.
  • the first transistor T1 is turned off, so that the high-level signal of the signal input terminal IN cannot be written into the first node N1.
  • the signal of the first node N1 maintains the low-level signal of the previous stage.
  • the signal of the third node N3 is a low-level signal.
  • the seventh transistor T7 is turned on, and the low-level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1.
  • the signal of the cascade output signal terminal OUT1 is a low-level signal.
  • the low-level signal of the third node N3 is written into the first node N1 through the turned-on eighth transistor T8.
  • the low-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15.
  • the twelfth transistor T12 is turned on, and the low-level signal of the second clock signal terminal CB is written into the fifth node N5.
  • the tenth transistor T10 is turned on, and the high-level signal of the masked signal terminal MS is written into the drive output signal terminal OUT2.
  • the signal at the first node N1 is a low-level signal
  • the second transistor T2 and the ninth transistor T9 are turned on, the high-level signal at the first power supply terminal VGH is written into the first end of the third capacitor C3 through the turned-on ninth transistor T9, and the third capacitor C3 is charged.
  • the third transistor T3 is turned off, the high-level signal at the first power supply terminal VGH is written into the second node N2 through the turned-on second transistor T2, and the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned off.
  • the signals at the first node N1, the third node N3, the fourth node N4, and the fifth node N5 are all low-level signals
  • the signal at the second node N2 is high-level signal
  • the signal at the cascade output signal terminal OUT1 is low-level signal
  • the signal at the drive output signal terminal OUT2 is high-level signal.
  • the signal at the first clock signal terminal CK is a low level signal
  • the signals at the signal input terminal IN, the second clock signal terminal CB and the mask signal terminal MS are high level signals
  • the first transistor T1 is turned on
  • the fifth transistor T5 and the thirteenth transistor T13 are turned off.
  • the first transistor T1 is turned on, and the high-level signal of the signal input terminal IN is written into the first node N1.
  • the high-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8.
  • the seventh transistor T7 is turned off. Under the coupling effect of the first capacitor C1, the signal of the cascade output signal terminal OUT becomes a high-level signal.
  • the high-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15.
  • the twelfth transistor T12 is turned off, and the high-level signal of the second clock signal terminal CB cannot be written into the fifth node N5.
  • the signal of the fifth node N5 becomes a high-level signal.
  • the tenth transistor T10 is turned off, and the high-level signal of the masked signal terminal MS cannot be written into the drive output signal terminal OUT2.
  • the signal of the drive output signal terminal OUT2 becomes a high-level signal.
  • the signal at the first node N1 is a high-level signal
  • the second transistor T2 and the ninth transistor T9 are disconnected, and the second end of the third capacitor C3 is floating. Due to the high-level signal at the second clock signal terminal CB, the signal at the second end of the third capacitor C3 is a high-level signal under the coupling effect of the third capacitor C3.
  • the third transistor T3 is disconnected, and the second capacitor C2 is discharged, so that the signal at the second node N2 remains a high-level signal in the previous stage.
  • the high-level signal at the first power supply terminal VGH cannot be written to the second node N2 through the conductive second transistor T2.
  • the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are disconnected.
  • the signals of the first node N1, the second node N2, the third node N3, the fourth node N4 and the fifth node N5 are all high-level signals
  • the signal of the cascade output signal terminal OUT1 is a high-level signal, driving the output signal terminal OUT2 to float and maintain the high-level signal of the previous stage.
  • the signal at the second clock signal terminal CB is a low level signal
  • the signals at the signal input terminal IN, the first clock signal terminal CK and the mask signal terminal MS are high level signals
  • the first transistor T1 is turned off
  • the fifth transistor T5 and the thirteenth transistor T13 are turned on.
  • the first transistor T1 is disconnected, so that the high-level signal of the signal input terminal IN cannot be written into the first node N1.
  • the signal of the first node N1 maintains the high-level signal of the previous stage.
  • the high-level signal of the first node N1 is written into the third node N3 through the conductive eighth transistor T8.
  • the seventh transistor T7 is disconnected, and the low-level signal of the second clock signal terminal CB cannot be written into the cascade output signal terminal OUT1.
  • the high-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the conductive fifteenth transistor T15.
  • the twelfth transistor T12 is disconnected, and the low-level signal of the second clock signal terminal CB cannot be written into the fifth node N5.
  • the tenth transistor T10 is disconnected.
  • the signal at the first node N1 is a high-level signal
  • the second transistor T2 and the ninth transistor T9 are disconnected, and the second end of the third capacitor C3 is floating. Due to the low-level signal of the signal at the second clock signal terminal CB, the signal at the second end of the third capacitor C3 is a low-level signal under the coupling effect of the third capacitor C3.
  • the third transistor T3 is turned on, and the low-level signal at the second clock signal terminal CB is written to the second node N2.
  • the signals at the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all high level signals
  • the signal at the second node N2 is low level signal
  • the signals at the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are high level signals.
  • An embodiment of the present disclosure further provides a shift register driving method, which is configured to drive the shift register provided by any of the aforementioned embodiments, and the method includes:

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Abstract

一种移位寄存器及其驱动方法、栅极驱动电路和显示装置，移位寄存器包括：节点控制子电路被配置为在级联输出子电路、第一电源端、第二电源端和第一控制输入信号端的信号的控制下，向驱动输出子电路提供信号；驱动输出子电路被配置为在级联输出子电路和节点控制子电路的信号的控制下，向驱动输出信号端提供第一电源端或者第二控制输入信号端的信号；第一控制输入信号端包括：第二时钟信号端，第二控制输入信号端包括：掩蔽信号端，或者，第一控制输入信号端包括：第二时钟信号端和掩蔽信号端，第二控制输入信号端包括：第二时钟信号端。

Description

移位寄存器及其驱动方法、栅极驱动电路、显示装置
本申请要求于2024年3月26日提交的、申请号为202410354593.5、发明名称为“移位寄存器及其驱动方法、栅极驱动电路、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本文涉及显示技术领域，具体涉及一种移位寄存器及其驱动方法、栅极驱动电路、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种移位寄存器，包括：级联输出子电路、驱动输出子电路和节点控制子电路；
所述级联输出子电路，分别与信号输入端、第一时钟信号端、第二时钟信号端、第一电源端、第二电源端和级联输出信号端电连接，被配置为在信号输入端、第一时钟信号端、第二时钟信号端和第二电源端的信号的控制下，向级联输出信号端提供第一电源端或者第二时钟信号端的信号；
所述节点控制子电路，分别与所述级联输出子电路、所述驱动输出子电路、第一电源端、第二电源端和第一控制输入信号端电连接，被配置为在所述级联输出子电路、第一电源端、第二电源端和第一控制输入信号端的信号的控制下，向驱动输出子电路提供信号；
所述驱动输出子电路，分别与所述级联输出子电路、所述节点控制子电路、第第一电源端、第二控制输入信号端和驱动输出信号端电连接，被配置为在级联输出子电路和节点控制子电路的信号的控制下，向驱动输出信号端提供第一电源端或者第二控制输入信号端的信号；
所述第一控制输入信号端包括：第二时钟信号端，所述第二控制输入信号端包括：掩蔽信号端，或者，所述第一控制输入信号端包括：第二时钟信号端和掩蔽信号端，所述第二控制输入信号端包括：第二时钟信号端。
在示例性实施方式中，所述移位寄存器设置在显示装置中，所述显示装置所显示内容包括多个显示帧，所述显示装置的显示模式包括：第一显示模式和第二显示模式，所述第一显示模式的刷新率大于所述第二显示模式的刷新率；
在所述第一显示模式下，移位寄存器的级联输出信号端的信号和驱动输出信号端的信号相同；
在所述第二显示模式下，移位寄存器的级联输出信号端的信号和驱动输出信号端的信号在至少部分时间互为反相信号。
在示例性实施方式中，所述级联输出子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第一电容和第二电容；
第一晶体管的控制极与第一时钟信号端电连接，第一晶体管的第一极与信号输入端电连接，第一晶体管的第二极与第一节点电连接；
第二晶体管的控制极与第一节点电连接，第二晶体管的第一极与第一时钟信号端电连接，第二晶体管的第二极与第二节点电连接；
第三晶体管的控制极与第一时钟信号端电连接，第三晶体管的第一极与第二电源端电连接，第三晶体管的第二极与第二节点电连接；
第四晶体管的控制极与第二节点电连接，第四晶体管的第一极与第一电源端电连接，第四晶体管的第二极与第五晶体管的第一极电连接；
第五晶体管的控制极与第二时钟信号端电连接，第五晶体管的第二极与第一节点电连接；
第六晶体管的控制极与第二节点电连接，第六晶体管的第一极与第一电源端电连接，第六晶体管的第二极与级联输出信号端电连接；
第七晶体管的控制极与第三节点电连接，第七晶体管的第一极与第二时钟信号端电连接，第七晶体管的第二极与级联输出信号端电连接；
第八晶体管的控制极与第二电源端电连接，第八晶体管的第一极与第一节点电连接，第八晶体管的第二极与第三节点电连接；
第一电容的第一端与第三节点电连接，第一电容的第二端与级联输出信号端电连接；
第二电容的第一端与第二节点电连接，第二电容的第二端与第一电源端电连接。
在示例性实施方式中，所述级联输出子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第一电容、第二电容和第三电容；
第一晶体管的控制极与第一时钟信号端电连接，第一晶体管的第一极与信号输入端电连接，第一晶体管的第二极与第一节点电连接；
第二晶体管的控制极与第一节点电连接，第二晶体管的第一极与第二电源端电连接，第二晶体管的第二极与第二节点电连接；
第三晶体管的控制极与第三电容的第一端电连接，第三晶体管的第一极与第二时钟信号端电连接，第三晶体管的第二极与第二节点电连接；
第四晶体管的控制极与第二节点电连接，第四晶体管的第一极与第二电源端电连接，第四晶体管的第二极与第五晶体管的第一极电连接；
第五晶体管的控制极与第二时钟信号端电连接，第五晶体管的第二极与第一节点电连接；
第六晶体管的控制极与第二节点电连接，第六晶体管的第一极与第一电源端电连接，第六晶体管的第二极与级联输出信号端电连接；
第七晶体管的控制极与第三节点电连接，第七晶体管的第一极与第二时钟信号端电连接，第七晶体管的第二极与级联输出信号端电连接；
第八晶体管的控制极与第二电源端电连接，第八晶体管的第一极与第一节点电连接，第八晶体管的第二极与第三节点电连接；
第九晶体管的控制极与第一节点电连接，第九晶体管的第一极与第二电源端电连接，第九晶体管的第二极与第三电容的第一端电连接；
第一电容的第一端与第三节点电连接，第一电容的第二端与级联输出信号端电连接；
第二电容的第一端与第二节点电连接，第二电容的第二端与第一电源端电连接。
第三电容的第二端与第二时钟信号端电连接。
在示例性实施方式中，所述级联输出子电路还包括：第四电容；
第四电容的第一端与第一电源端电连接，第四电容的第二端与级联输出信号端电连接。
在示例性实施方式中，所述第一控制输入信号端包括：第二时钟信号端和掩蔽信号端，所述第二控制输入信号端包括：第二时钟信号端；
所述级联输出子电路中设置有第一节点、第二节点和第三节点；
所述节点控制子电路，分别与所述第一节点、所述第二节点、掩蔽信号端、第二时钟信号端、第一电源端、第二电源端和第五节点电连接，被配置为在第一节点、第二节点、掩蔽信号端、第二时钟信号端和第二电源端的信号的控制下，向第五节点提供第一电源端或者掩蔽信号端的信号；
所述驱动输出子电路，分别与所述第二节点、所述第五节点、第二时钟信号端、第一电源端和驱动输出信号端电连接，被配置为在第二节点和第五节点的信号的控制下，向驱动输出信号端提供第一电源端或者第二时钟信号端的信号。
在示例性实施方式中，所述驱动输出子电路包括：第十晶体管、第十一晶体管和第五电容，所述节点控制子电路包括：第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管和第六电容；
第十晶体管的控制极与第五节点电连接，第十晶体管的第一极与第二时钟信号端电连接，第十晶体管的第二极与驱动输出信号端电连接；
第十一晶体管的控制极与第二节点电连接，第十一晶体管的第一极与第一电源端电连接，第十一晶体管的第二极与驱动输出信号端电连接；
第十二晶体管的控制极与第四节点电连接，第十二晶体管的第一极与掩蔽信号端电连接，第十二晶体管的第二极与第五节点电连接；
第十三晶体管的控制极与第二时钟信号端电连接，第十三晶体管的第一极与第十四晶体管的第二极电连接，第十三晶体管的第二极与第五节点电连接；
第十四晶体管的控制极与第二节点电连接，第十四晶体管的第一极与第一电源端电连接；
第十五晶体管的控制极与第二电源端电连接，第十五晶体管的第一极与第一节点电连接，第十五晶体管的第二极与第四节点电连接；
第五电容的第一端与第五节点电连接，第五电容的第二端与驱动输出信号端电连接；
第六电容的第一端与第四节点电连接，第六电容的第二端与第五节点电连接。
在示例性实施方式中，所述第一控制输入信号端包括：第二时钟信号端，所述第二控制输入信号端包括：掩蔽信号端；
所述级联输出子电路中设置有第一节点、第二节点和第三节点；
所述节点控制子电路，分别与所述第一节点、所述第二节点、第二时钟信号端、第一电源端、第二电源端和第五节点电连接，被配置为在第一节点、第二节点、第二时钟信号端和第二电源端的信号的控制下，向第五节点提供第一电源端或者第二时钟信号端的信号；
所述驱动输出子电路，分别与所述第二节点、所述第五节点、第一电源端、掩蔽信号端和驱动输出信号端电连接，被配置为在被配置为在第二节点和第五节点的信号的控制下，向驱动输出信号端提供第一电源端或者掩蔽信号端的信号。
在示例性实施方式中，所述驱动输出子电路包括：第十晶体管、第十一晶体管和第五电容，所述节点控制子电路包括：第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管和第六电容；
第十晶体管的控制极与第五节点电连接，第十晶体管的第一极与掩蔽信号端电连接，第十晶体管的第二极与驱动输出信号端电连接；
第十一晶体管的控制极与第二节点电连接，第十一晶体管的第一极与第一电源端电连接，第十一晶体管的第二极与驱动输出信号端电连接；
第十二晶体管的控制极与第四节点电连接，第十二晶体管的第一极与第二时钟信号端电连接，第十二晶体管的第二极与第五节点电连接；
第十三晶体管的控制极与第二时钟信号端电连接，第十三晶体管的第一极与第十四晶体管的第二极电连接，第十三晶体管的第二极与第五节点电连接；
第十四晶体管的控制极与第二节点电连接，第十四晶体管的第一极与第一电源端电连接；
第十五晶体管的控制极与第二电源端电连接，第十五晶体管的第一极与第一节点电连接，第十五晶体管的第二极与第四节点电连接；
第五电容的第一端与第五节点电连接，第五电容的第二端与驱动输出信号端电连接；
第六电容的第一端与第四节点电连接，第六电容的第二端与第五节点电连接。
在示例性实施方式中，所述第一控制输入信号端包括：第二时钟信号端和掩蔽信号端，所述第二控制输入信号端包括：第二时钟信号端；
所述级联输出子电路中设置有第一节点、第二节点和第三节点；
所述节点控制子电路，分别与所述第二节点、所述第三节点、掩蔽信号端、第二时钟信号端、第一电源端、第二电源端和第五节点电连接，被配置为在第二节点、第三节点、掩蔽信号端、第二时钟信号端和第二电源端的信号的控制下，向第五节点提供第一电源端或者掩蔽信号端的信号；
所述驱动输出子电路，分别与所述第二节点、所述第五节点、第二时钟信号端、第一电源端和驱动输出信号端电连接，被配置为在第二节点和第五节点的信号的控制下，向驱动输出信号端提供第一电源端或者第二时钟信号端的信号。
在示例性实施方式中，所述驱动输出子电路包括：第十晶体管、第十一晶体管和第五电容，所述节点控制子电路包括：第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管和第六电容；
第十晶体管的控制极与第五节点电连接，第十晶体管的第一极与第二时钟信号端电连接，第十晶体管的第二极与驱动输出信号端电连接；
第十一晶体管的控制极与第二节点电连接，第十一晶体管的第一极与第一电源端电连接，第十一晶体管的第二极与驱动输出信号端电连接；
第十二晶体管的控制极与第四节点电连接，第十二晶体管的第一极与掩蔽信号端电连接，第十二晶体管的第二极与第五节点电连接；
第十三晶体管的控制极与第二时钟信号端电连接，第十三晶体管的第一极与第十四晶体管的第二极电连接，第十三晶体管的第二极与第五节点电连接；
第十四晶体管的控制极与第二节点电连接，第十四晶体管的第一极与第一电源端电连接；
第十五晶体管的控制极与第二电源端电连接，第十五晶体管的第一极与第三节点电连接，第十五晶体管的第二极与第四节点电连接；
第五电容的第一端与第五节点电连接，第五电容的第二端与驱动输出信号端电连接；
第六电容的第一端与第四节点电连接，第六电容的第二端与第五节点电连接。
在示例性实施方式中，所述第一控制输入信号端包括：第二时钟信号端，所述第二控制输入信号端包括：掩蔽信号端；
所述级联输出子电路中设置有第一节点、第二节点和第三节点；
所述节点控制子电路，分别与所述第二节点、所述第三节点、第二时钟信号端、第一电源端、第二电源端和第五节点电连接，被配置为在第二节点、第三节点、第二时钟信号端和第二电源端的信号的控制下，向第五节点提供第一电源端或者第二时钟信号端的信号；
所述驱动输出子电路，分别与所述第二节点、所述第五节点、第一电源端、掩蔽信号端和驱动输出信号端电连接，被配置为在被配置为在第二节点和第五节点的信号的控制下，向驱动输出信号端提供第一电源端或者掩蔽信号端的信号。
在示例性实施方式中，所述驱动输出子电路包括：第十晶体管、第十一晶体管和第五电容，所述节点控制子电路包括：第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管和第六电容；
第十晶体管的控制极与第五节点电连接，第十晶体管的第一极与掩蔽信号端电连接，第十晶体管的第二极与驱动输出信号端电连接；
第十一晶体管的控制极与第二节点电连接，第十一晶体管的第一极与第一电源端电连接，第十一晶体管的第二极与驱动输出信号端电连接；
第十二晶体管的控制极与第四节点电连接，第十二晶体管的第一极与第二时钟信号端电连接，第十二晶体管的第二极与第五节点电连接；
第十三晶体管的控制极与第二时钟信号端电连接，第十三晶体管的第一极与第十四晶体管的第二极电连接，第十三晶体管的第二极与第五节点电连接；
第十四晶体管的控制极与第二节点电连接，第十四晶体管的第一极与第一电源端电连接；
第十五晶体管的控制极与第二电源端电连接，第十五晶体管的第一极与第三节点电连接，第十五晶体管的第二极与第四节点电连接；
第五电容的第一端与第五节点电连接，第五电容的第二端与驱动输出信号端电连接；
第六电容的第一端与第四节点电连接，第六电容的第二端与第五节点电连接。
在示例性实施方式中，所述级联输出子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第一电容和第二电容，所述驱动输出子电路包括：第十晶体管、第十一晶体管和第五电容；所述节点控制子电路包括：第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管和第六电容；
第一晶体管的控制极与第一时钟信号端电连接，第一晶体管的第一极与信号输入端电连接，第一晶体管的第二极与第一节点电连接；
第二晶体管的控制极与第一节点电连接，第二晶体管的第一极与第一时钟信号端电连接，第二晶体管的第二极与第二节点电连接；
第三晶体管的控制极与第一时钟信号端电连接，第三晶体管的第一极与第二电源端电连接，第三晶体管的第二极与第二节点电连接；
第四晶体管的控制极与第二节点电连接，第四晶体管的第一极与第一电源端电连接，第四晶体管的第二极与第五晶体管的第一极电连接；
第五晶体管的控制极与第二时钟信号端电连接，第五晶体管的第二极与第一节点电连接；
第六晶体管的控制极与第二节点电连接，第六晶体管的第一极与第一电源端电连接，第六晶体管的第二极与级联输出信号端电连接；
第七晶体管的控制极与第三节点电连接，第七晶体管的第一极与第二时钟信号端电连接，第七晶体管的第二极与级联输出信号端电连接；
第八晶体管的控制极与第二电源端电连接，第八晶体管的第一极与第一节点电连接，第八晶体管的第二极与第三节点电连接；
第十晶体管的控制极与第五节点电连接，第十晶体管的第一极与掩蔽信号端和第二时钟信号端的其中一个信号端电连接，第十晶体管的第二极与驱动输出信号端电连接；
第十一晶体管的控制极与第二节点电连接，第十一晶体管的第一极与第一电源端电连接，第十一晶体管的第二极与驱动输出信号端电连接；
第十二晶体管的控制极与第四节点电连接，第十二晶体管的第一极与掩蔽信号端和第二时钟信号端中的另一个信号端电连接，第十二晶体管的第二极与第五节点电连接；
第十三晶体管的控制极与第二时钟信号端电连接，第十三晶体管的第一极与第十四晶体管的第二极电连接，第十三晶体管的第二极与第五节点电连接；
第十四晶体管的控制极与第二节点电连接，第十四晶体管的第一极与第一电源端电连接；
第十五晶体管的控制极与第二电源端电连接，第十五晶体管的第一极与第一节点和第三节点中的其中一个节点电连接，第十五晶体管的第二极与第四节点电连接；
第一电容的第一端与第三节点电连接，第一电容的第二端与级联输出信号端电连接；
第二电容的第一端与第二节点电连接，第二电容的第二端与第一电源端电连接；
第五电容的第一端与第五节点电连接，第五电容的第二端与驱动输出信号端电连接；
第六电容的第一端与第四节点电连接，第六电容的第二端与第五节点电连接。
在示例性实施方式中，所述级联输出子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第一电容、第二电容和第四电容，所述驱动输出子电路包括：第十晶体管、第十一晶体管和第五电容，所述节点控制子电路包括：第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管和第六电容；
第一晶体管的控制极与第一时钟信号端电连接，第一晶体管的第一极与信号输入端电连接，第一晶体管的第二极与第一节点电连接；
第二晶体管的控制极与第一节点电连接，第二晶体管的第一极与第一时钟信号端电连接，第二晶体管的第二极与第二节点电连接；
第三晶体管的控制极与第一时钟信号端电连接，第三晶体管的第一极与第二电源端电连接，第三晶体管的第二极与第二节点电连接；
第四晶体管的控制极与第二节点电连接，第四晶体管的第一极与第一电源端电连接，第四晶体管的第二极与第五晶体管的第一极电连接；
第五晶体管的控制极与第二时钟信号端电连接，第五晶体管的第二极与第一节点电连接；
第六晶体管的控制极与第二节点电连接，第六晶体管的第一极与第一电源端电连接，第六晶体管的第二极与级联输出信号端电连接；
第七晶体管的控制极与第三节点电连接，第七晶体管的第一极与第二时钟信号端电连接，第七晶体管的第二极与级联输出信号端电连接；
第八晶体管的控制极与第二电源端电连接，第八晶体管的第一极与第一节点电连接，第八晶体管的第二极与第三节点电连接；
第十晶体管的控制极与第五节点电连接，第十晶体管的第一极与掩蔽信号端和第二时钟信号端的其中一个信号端电连接，第十晶体管的第二极与驱动输出信号端电连接；
第十一晶体管的控制极与第二节点电连接，第十一晶体管的第一极与第一电源端电连接，第十一晶体管的第二极与驱动输出信号端电连接；
第十二晶体管的控制极与第四节点电连接，第十二晶体管的第一极与掩蔽信号端和第二时钟信号端中的另一个信号端电连接，第十二晶体管的第二极与第五节点电连接；
第十三晶体管的控制极与第二时钟信号端电连接，第十三晶体管的第一极与第十四晶体管的第二极电连接，第十三晶体管的第二极与第五节点电连接；
第十四晶体管的控制极与第二节点电连接，第十四晶体管的第一极与第一电源端电连接；
第十五晶体管的控制极与第二电源端电连接，第十五晶体管的第一极与第一节点和第三节点中的其中一个节点电连接，第十五晶体管的第二极与第四节点电连接；
第一电容的第一端与第三节点电连接，第一电容的第二端与级联输出信号端电连接；
第二电容的第一端与第二节点电连接，第二电容的第二端与第一电源端电连接；
第四电容的第一端与第一电源端电连接，第四电容的第二端与级联输出信号端电连接；
第五电容的第一端与第五节点电连接，第五电容的第二端与驱动输出信号端电连接；
第六电容的第一端与第四节点电连接，第六电容的第二端与第五节点电连接。
在示例性实施方式中，所述级联输出子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第一电容、第二电容和第三电容，所述驱动输出子电路包括：第十晶体管、第十一晶体管和第五电容，所述节点控制子电路包括：第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管和第六电容；
第一晶体管的控制极与第一时钟信号端电连接，第一晶体管的第一极与信号输入端电连接，第一晶体管的第二极与第一节点电连接；
第二晶体管的控制极与第一节点电连接，第二晶体管的第一极与第二电源端电连接，第二晶体管的第二极与第二节点电连接；
第三晶体管的控制极与第三电容的第一端电连接，第三晶体管的第一极与第二时钟信号端电连接，第三晶体管的第二极与第二节点电连接；
第四晶体管的控制极与第二节点电连接，第四晶体管的第一极与第二电源端电连接，第四晶体管的第二极与第五晶体管的第一极电连接；
第五晶体管的控制极与第二时钟信号端电连接，第五晶体管的第二极与第一节点电连接；
第六晶体管的控制极与第二节点电连接，第六晶体管的第一极与第一电源端电连接，第六晶体管的第二极与级联输出信号端电连接；
第七晶体管的控制极与第三节点电连接，第七晶体管的第一极与第二时钟信号端电连接，第七晶体管的第二极与级联输出信号端电连接；
第八晶体管的控制极与第二电源端电连接，第八晶体管的第一极与第一节点电连接，第八晶体管的第二极与第三节点电连接；
第九晶体管的控制极与第一节点电连接，第九晶体管的第一极与第二电源端电连接，第九晶体管的第二极与第三电容的第一端电连接；
第十晶体管的控制极与第五节点电连接，第十晶体管的第一极与掩蔽信号端和第二时钟信号端的其中一个信号端电连接，第十晶体管的第二极与驱动输出信号端电连接；
第十一晶体管的控制极与第二节点电连接，第十一晶体管的第一极与第一电源端电连接，第十一晶体管的第二极与驱动输出信号端电连接；
第十二晶体管的控制极与第四节点电连接，第十二晶体管的第一极与掩蔽信号端和第二时钟信号端中的另一个信号端电连接，第十二晶体管的第二极与第五节点电连接；
第十三晶体管的控制极与第二时钟信号端电连接，第十三晶体管的第一极与第十四晶体管的第二极电连接，第十三晶体管的第二极与第五节点电连接；
第十四晶体管的控制极与第二节点电连接，第十四晶体管的第一极与第一电源端电连接；
第十五晶体管的控制极与第二电源端电连接，第十五晶体管的第一极与第一节点和第三节点中的其中一个节点电连接，第十五晶体管的第二极与第四节点电连接；
第一电容的第一端与第三节点电连接，第一电容的第二端与级联输出信号端电连接；
第二电容的第一端与第二节点电连接，第二电容的第二端与第一电源端电连接；
第三电容的第二端与第二时钟信号端电连接；
第五电容的第一端与第五节点电连接，第五电容的第二端与驱动输出信号端电连接；
第六电容的第一端与第四节点电连接，第六电容的第二端与第五节点电连接。
在示例性实施方式中，所述级联输出子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第一电容、第二电容、第三电容和第四电容，所述驱动输出子电路包括：第十晶体管、第十一晶体管和第五电容，所述节点控制子电路包括：第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管和第六电容；
第一晶体管的控制极与第一时钟信号端电连接，第一晶体管的第一极与信号输入端电连接，第一晶体管的第二极与第一节点电连接；
第二晶体管的控制极与第一节点电连接，第二晶体管的第一极与第二电源端电连接，第二晶体管的第二极与第二节点电连接；
第三晶体管的控制极与第三电容的第一端电连接，第三晶体管的第一极与第二时钟信号端电连接，第三晶体管的第二极与第二节点电连接；
第四晶体管的控制极与第二节点电连接，第四晶体管的第一极与第二电源端电连接，第四晶体管的第二极与第五晶体管的第一极电连接；
第五晶体管的控制极与第二时钟信号端电连接，第五晶体管的第二极与第一节点电连接；
第六晶体管的控制极与第二节点电连接，第六晶体管的第一极与第一电源端电连接，第六晶体管的第二极与级联输出信号端电连接；
第七晶体管的控制极与第三节点电连接，第七晶体管的第一极与第二时钟信号端电连接，第七晶体管的第二极与级联输出信号端电连接；
第八晶体管的控制极与第二电源端电连接，第八晶体管的第一极与第一节点电连接，第八晶体管的第二极与第三节点电连接；
第九晶体管的控制极与第一节点电连接，第九晶体管的第一极与第二电源端电连接，第九晶体管的第二极与第三电容的第一端电连接；
第十晶体管的控制极与第五节点电连接，第十晶体管的第一极与掩蔽信号端和第二时钟信号端的其中一个信号端电连接，第十晶体管的第二极与驱动输出信号端电连接；
第十一晶体管的控制极与第二节点电连接，第十一晶体管的第一极与第一电源端电连接，第十一晶体管的第二极与驱动输出信号端电连接；
第十二晶体管的控制极与第四节点电连接，第十二晶体管的第一极与掩蔽信号端和第二时钟信号端中的另一个信号端电连接，第十二晶体管的第二极与第五节点电连接；
第十三晶体管的控制极与第二时钟信号端电连接，第十三晶体管的第一极与第十四晶体管的第二极电连接，第十三晶体管的第二极与第五节点电连接；
第十四晶体管的控制极与第二节点电连接，第十四晶体管的第一极与第一电源端电连接；
第十五晶体管的控制极与第二电源端电连接，第十五晶体管的第一极与第一节点和第三节点中的其中一个节点电连接，第十五晶体管的第二极与第四节点电连接；
第一电容的第一端与第三节点电连接，第一电容的第二端与级联输出信号端电连接；
第二电容的第一端与第二节点电连接，第二电容的第二端与第一电源端电连接；
第三电容的第二端与第二时钟信号端电连接；
第四电容的第一端与第一电源端电连接，第四电容的第二端与级联输出信号端电连接；
第五电容的第一端与第五节点电连接，第五电容的第二端与驱动输出信号端电连接；
第六电容的第一端与第四节点电连接，第六电容的第二端与第五节点电连接。
在示例性实施方式中，在所述第一显示模式下，所述掩蔽信号端的信号为第一信号，在所述第二显示模式下，所述掩蔽信号端的信号在至少部分时间段内为第一信号，且在至少部分时间段内为第二信号；
所述掩蔽信号端的信号为第一信号的时间段与级联输出信号端输出信号的时间段不交叠，所述掩蔽信号端的信号为第二信号的时间段与级联输出信号端输出信号的时间段至少部分交叠；
所述第一信号与所述第二信号中的至少一个信号的电压值恒定，且所述第一信号的电压值小于所述第二信号的电压值。
在示例性实施方式中，在所述第二显示模式下，所述级联输出信号端输出信号的时间段位于所述掩蔽信号端的信号为第二信号的时间段内。
在示例性实施方式中，所述掩蔽信号端的信号由第一信号变为第二信号的时刻位于输出时间段之前，其中，所述输出时间段为所述级联输出信号端输出信号的时间段。
第二方面，本公开还提供了一种栅极驱动电路，包括：多个上述移位寄存器；
至少一级移位寄存器的级联输出信号端与至少一级移位寄存器的信号输入端电连接。
第三方面，本公开还提供了一种显示装置，包括：上述栅极驱动电路。
在示例性实施方式中，还包括：阵列排布的子像素、多条第一扫描信号线和多条数据信号线，至少一个子像素分别与第一扫描信号线和数据信号线电连接；
至少一个子像素包括：像素驱动电路，至少一个子像素的像素驱动电路包括：写入晶体管，所述写入晶体管分别与所在子像素所连接的所述第一扫描信号线和所述数据信号线电连接；
至少一级移位寄存器的驱动输出信号端与至少一行像素驱动电路所连接的第一扫描信号线电连接。
在示例性实施方式中，还包括：多条第二复位信号线和多条第二初始信号线，至少一个子像素还分别与第二复位信号线和第二初始信号线电连接；
至少一个子像素的像素驱动电路还包括：阳极复位晶体管，所述阳极复位晶体管分别与所在子像素连接的所述第二复位信号线和所述第二初始信号线电连接；
至少一级移位寄存器的驱动输出信号端与至少一行像素驱动电路所连接的第二复位信号线电连接；
至少一行像素驱动电路所连接的第一扫描信号线和第二复位信号线独立设置，或者至少一行像素驱动电路所连接的第二复位信号线与下一行像素驱动电路所连接的第一扫描信号线为同一信号线。
第四方面，本公开还提供了一种移位寄存器的驱动方法，被配置为驱动上述移位寄存器，所述方法包括：
级联输出子电路在信号输入端、第一时钟信号端、第二时钟信号端和第二电源端的信号的控制下，向级联输出信号端提供第一电源端或者第二时钟信号端的信号；
节点控制子电路在级联输出子电路、第一电源端、第二电源端和第一控制输入信号端的信号的控制下，向驱动输出子电路提供信号；
驱动输出子电路在级联输出子电路和节点控制子电路的信号的控制下，向驱动输出信号端提供第一电源端或者第二控制输入信号端的信号。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种显示装置的结构示意图；
图2A为一种像素驱动电路的等效电路示意图；
图2B为另一像素驱动电路的等效电路示意图；
图3A为图2A提供的像素驱动电路的工作时序图；
图3B为图2B提供的像素驱动电路的工作时序图；
图4为本公开实施例提供的移位寄存器的结构示意图；
图5为级联输出子电路的等效电路图一；
图6为级联输出子电路的等效电路图二；
图7为驱动输出子电路和节点控制子电路的等效电路图一；
图8为驱动输出子电路和节点控制子电路的等效电路图二；
图9为驱动输出子电路和节点控制子电路的等效电路图三；
图10为驱动输出子电路和节点控制子电路的等效电路图四；
图11为移位寄存器的等效电路图一；
图12为移位寄存器的等效电路图二；
图13为移位寄存器的等效电路图三；
图14为移位寄存器的等效电路图四；
图15为移位寄存器的等效电路图五；
图16为移位寄存器的等效电路图六；
图17为移位寄存器的等效电路图七；
图18为移位寄存器的等效电路图八；
图19为图11至图18提供的移位寄存器在第一显示模式下的工作时序图；
图20为图11至图18提供的移位寄存器在第二显示模式下的工作时序图。
详述
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、源极驱动电路、栅极驱动电路和像素阵列，时序控制器分别与源极驱动电路和栅极驱动电路连接，源极驱动电路分别与多个数据信号线(D1到Dn)连接，栅极驱动电路分别与多个扫描信号线(S1到Sm)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以包括像素驱动电路，像素驱动电路可以分别与扫描信号线和数据信号线连接。在示例性实施方式中，时序控制器可以将适合于源极驱动电路的规格的灰度值和控制信号提供到源极驱动电路，可以将适合于栅极驱动电路的规格的时钟信号、扫描起始信号等提供到栅极驱动电路，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。源极驱动电路可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，源极驱动电路可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。栅极驱动电路可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，栅极驱动电路可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，栅极驱动电路可以被构造为移位寄存器的形式，并且可以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。
在示例性实施方式中，子像素可以包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3，第一子像素P1、第二子像素P2和第三子像素P3均包括像素驱动电路和发光器件。第一子像素P1、第二子像素P2和第三子像素P3中的像素驱动电路分别与扫描信号线和数据信号线连接，像素驱动电路被配置为在扫描信号线的控制下，接收数据信号线传输的数据电压，向发光器件输出相应的电流。第一子像素P1、第二子像素P2和第三子像素P3中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3可以是出射绿色光线的绿色子像素(G)。
在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形，多个子像素可以采用水平并列、竖直并列或品字方式排列，本公开在此不做限定。
在示例性实施方式中，发光器件可以为OLED，OLED可以包括：第一电极(阳极)、第二电极(阴极)和位于第一电极和第二电极之间的有机发光层。
在示例性实施方式中，有机发光层可以包括发光层(EML)以及如下任意一层或多层：空穴注入层HIL)、空穴传输层(HTL)、电子阻挡层(EBL)、空穴阻挡层(HBL)、电子传输层(ETL)和电子注入层(EIL)。在示例性实施方式中，所有子像素的空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层中的一层或多层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的。
在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。
图2A为一种像素驱动电路的等效电路示意图。如图2A所示，像素驱动电路可以包括8个晶体管(第一晶体管M1到第八晶体管M8)、1个存储电容C，图2B为另一像素驱动电路的等效电路示意图。如图2B所示，像素驱动电路可以包括8个晶体管(第一晶体管M1到第七晶体管M7)、1个存储电容C。如图2A和图2B所示，像素驱动电路可以与11个信号线(数据信号线Data、第一扫描信号线Gate1、第二扫描信号线Gate2、第一复位信号线Reset1、第二复位信号线Reset2、发光信号线EM、第一初始信号线INIT1、第二初始信号线INIT2、第三初始信号线INIT3、第一电源线VDD和第二电源线VSS)连接。
在示例性实施方式中，存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第二节点N2连接，即存储电容C的第二端与第三晶体管M3的控制极连接。
第一晶体管M1的控制极与第一复位信号线Reset1连接，第一晶体管M1的第一极与第一初始信号线INIT1连接，第一晶体管的第二极与第三节点N3连接。第一晶体管T1可以称为第一节点复位晶体管。当导通电平扫描信号施加到第一复位信号线Reset1时，第一晶体管M1将初始化电压传输到第三节点N3，以使第三节点N3的电荷量初始化。
第二晶体管M2的控制极与第二扫描信号线Gate2连接，第二晶体管M2的第一极与第二节点N2连接，第二晶体管M2的第二极与第三节点N3连接。第二晶体管M2可以称为补偿晶体管。当导通电平扫描信号施加到第二扫描信号线Gate2时，第二晶体管M2使第三晶体管M3的控制极与第二极连接，以对第三晶体管M3的控制极进行补偿或者复位。
第三晶体管M3的控制极与第二节点N2连接，第三晶体管M3的第一极与第一节点N1连接，第三晶体管M3的第二极与第三节点N3连接。第三晶体管M3可以称为驱动晶体管，第三晶体管M3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的大小。
第四晶体管M4的控制极与第一扫描信号线Gate1连接，第四晶体管M4的第一极与数据信号线Data连接，第四晶体管M4的第二极与第一节点N1连接。第四晶体管M4可以称为写入晶体管，当导通电平扫描信号施加到第一扫描信号线Gate1时，第四晶体管M4使数据信号线Data的数据电压输入到像素驱动电路。
第五晶体管M5的控制极与发光信号线EM连接，第五晶体管M5的第一极与第一电源线VDD连接，第五晶体管M5的第二极与第一节点N1连接。第六晶体管M6的控制极与发光信号线EM连接，第六晶体管M6的第一极与第三节点N3连接，第六晶体管M6的第二极与发光器件的第一极连接。第五晶体管M5和第六晶体管M6可以称为发光晶体管。当导通电平发光信号施加到发光信号线EM时，第五晶体管M5和第六晶体管M6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
第七晶体管M7的控制极与第二复位信号线Reset2连接，第七晶体管M7的第一极与第二初始信号线INIT2连接，第七晶体管M7的第二极与发光器件的第一极连接。第七晶体管M7可以称为阳极复位晶体管。当导通电平扫描信号施加到第二复位信号线Reset2时，第七晶体管M7将初始化电压传输到发光器件的第一极，以使发光器件的第一极中累积的电荷量初始化或释放发光器件的第一极中累积的电荷量。
第八晶体管M8的控制极与第二复位信号线Reset2连接，第八晶体管M8的第一极与第三初始信号线INIT3连接，第八晶体管M8的第二极与第一节点N1连接。第八晶体管M8可以称为第二节点复位晶体管。当导通电平扫描信号施加到第二复位信号线Reset2时，第八晶体管M8将初始化电压传输到第一节点，以使第八晶体管M8中累积的电荷量初始化。
在示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为低电平信号，第一电源线VDD的信号为高电平信号。
按照晶体管的特性区分可以将晶体管分为N型晶体管和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)，关闭电压为高电平电压(例如，5V、10V或其它合适的电压)。当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其它合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)。
在示例性实施方式中，如图2A所示的像素驱动电路中，第二晶体管M2可以为N型晶体管，第一晶体管M1、第三晶体管M3至第八晶体管M8可以为P型晶体管。
在示例性实施方式中，如图2B所示的像素驱动电路中，第一晶体管M1和第二晶体管M2可以为N型晶体管，第三晶体管M3至第七晶体管M7可以为P型晶体管。
在示例性实施方式中，图2B提供的像素驱动电路中，本行子像素连接的第二复位信号线与下一行子像素连接的第一扫描信号线可以为同一信号线，或者可以为信号相同的，不同信号。
图3A为图2A提供的像素驱动电路的工作时序图。下面通过图2A示例的像素驱动电路的工作过程说明本公开示例性实施例，图2A中的像素驱动电路包括8个晶体管(第一晶体管M1到第八晶体管M8)和1个存储电容C，第二晶体管M2为N型晶体管，第一晶体管M1、第三晶体管M3至第八晶体管M8均为P型晶体管。
在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第一复位信号线Reset和第二复位信号线Reset2的信号为低电平信号，第一扫描信号线Gate1、第二扫描信号线Gate2和发光信号线EM的信号为高电平信号。第一复位信号线Reset的信号为低电平信号，第一晶体管M1导通，第一初始信号线INIT1的信号写入第三节点N3，对第三节点N3进行初始化(复位)，清除第三节点N3中原有电荷，第二扫描信号线Gate2的信号为高电平信号，第二晶体管M2导通，第三节点N3的信号提供至第二节点N2，对存储电容C进行初始化(复位)，清除存储电容中原有电荷。第二复位信号线Reset2的信号为低电平信号，第七晶体管M7和第八晶体管M8导通，使得第二初始信号线INIT2的信号提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，第三初始信号线INIT3的信号提供至第一节点N1，对第一节点N1进行初始化(复位)，清空其内部的预存电压。第一扫描信号线Gate1和发光信号线EM的信号为高电平信号，使第四晶体管M4、第五晶体管M5、第六晶体管M6断开，此阶段OLED不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线Gate1的信号为低电平信号，第一复位信号线Reset1、第二复位信号线Reset2、第二扫描信号线Reset2和发光信号线EM的信号为高电平信号，数据信号线Data输出数据电压。此阶段由于存储电容C的第二端为低电平信号，因此第三晶体管M3导通。第一扫描信号线Gate1的信号为低电平信号，第四晶体管M4导通，第二扫描信号线Reset2的信号为高电平信号，第二晶体管M2导通，第二晶体管M2和第四晶体管M4导通使得数据信号线Data输出的数据电压经过第一节点N1、导通的第三晶体管M3、第三节点N3、导通的第二晶体管M2提供至第二节点N2，并将数据信号线Data输出的数据电压与第三晶体管M3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线Data输出的数据电压，Vth为第三晶体管M3的阈值电压。第一复位信号线Reset1、第二复位信号线Reset2和发光信号线EM的信号为高电平信号，使得第一晶体管M1、第五晶体管M5、第六晶体管M6、第七晶体管M7和第八晶体管M8断开。
第三阶段A3、称为发光阶段，发光信号线EM和第二扫描信号端Gate2的信号为低电平信号，第一扫描信号线Gate1、第一复位信号线Reset1和第二复位信号线Reset2的信号为高电平信号。发光信号线EM的信号为低电平信号，使第五晶体管M5和第六晶体管M6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管M5、第三晶体管M3和第六晶体管M6向OLED的第一极提供驱动电压，驱动OLED发光。第二扫描信号端Gate2的信号为低电平信号，第一扫描信号线Gate1、第一复位信号线Reset1和第二复位信号线Reset2的信号为高电平信号，使得第一晶体管M1、第二晶体管M2、第四晶体管M4、第七晶体管M7和第八晶体管M8断开。
在像素驱动电路驱动过程中，流过第三晶体管M3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第三晶体管M3的驱动电流为：
I＝K*(Vgs-Vth)2＝K*[(Vdd-Vd+|Vth|)-Vth]2＝K*[(Vdd-Vd]2
其中，I为流过第三晶体管M3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管M3的栅电极和第一极之间的电压差，Vth为第三晶体管M3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
由上述电流公式的推导结果可以看出，在发光阶段，第三晶体管M3的驱动电流已经不受第三晶体管M3的阈值电压的影响，从而消除了第三晶体管M3的阈值电压对驱动电流的影响，可以保证显示产品的显示亮度均匀，提升了整个显示产品的显示效果。
图3B为图2B提供的像素驱动电路的工作时序图。下面通过图2B示例的像素驱动电路的工作过程说明本公开示例性实施例，图2B中的像素驱动电路包括7个晶体管(第一晶体管M1到第七晶体管M7)和1个存储电容C，第一晶体管M1和第二晶体管M2为N型晶体管，第三晶体管M3至第七晶体管M7均为P型晶体管。
在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段B1，称为第一复位阶段，第一复位信号线Reset1、第二复位信号线Reset2、第一扫描信号线Gate1、第二扫描信号线Gate2和发光信号线EM的信号为高电平信号。第一复位信号线Reset的信号为低电平信号，第一晶体管M1导通，第一初始信号线INIT1的信号写入第三节点N3，对第三节点N3进行初始化(复位)，清除第三节点N3中原有电荷，第二扫描信号线Gate2的信号为高电平信号，第二晶体管M2导通，第三节点N3的信号提供至第二节点N2，对存储电容C进行初始化(复位)，清除存储电容中原有电荷。第二复位信号线Reset2的信号为低电平信号，第一扫描信号线Gate1、第二复位信号线Reset2和发光信号线EM的信号为高电平信号，使第四晶体管M4、第五晶体管M5、第六晶体管M6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段B2、称为数据写入阶段或者阈值补偿阶段，第一复位信号线Reset1和第一扫描信号线Gate1的信号为低电平信号，第二复位信号线Reset2、第二扫描信号线Reset2和发光信号线EM的信号为高电平信号，数据信号线Data输出数据电压。此阶段由于存储电容C的第二端为低电平信号，因此第三晶体管M3导通。第一扫描信号线Gate1的信号为低电平信号，第四晶体管M4导通，第二扫描信号线Reset2的信号为高电平信号，第二晶体管M2导通，第二晶体管M2和第四晶体管M4导通使得数据信号线Data输出的数据电压经过第一节点N1、导通的第三晶体管M3、第三节点N3、导通的第二晶体管M2提供至第二节点N2，并将数据信号线Data输出的数据电压与第三晶体管M3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线Data输出的数据电压，Vth为第三晶体管M3的阈值电压。第一复位信号线Reset1的信号为低电平信号，第二复位信号线Reset2和发光信号线EM的信号为高电平信号，使得第一晶体管M1、第五晶体管M5、第六晶体管M6和第七晶体管M7断开。
第三阶段B3、称为阳极复位阶段，第一复位信号线Reset1、第二复位信号线Reset2和第二扫描信号线Gate2的信号为低电平信号，第一扫描信号线Gate1和发光信号线EM的信号为高电平信号。第七晶体管M7导通，使得第二初始信号线INIT2的信号提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压。第一复位信号线Reset1和第二扫描信号线Gate2的信号为低电平信号，第一扫描信号线Gate1和发光信号线EM的信号为高电平信号，第一晶体管M1、第二晶体管M2、第四晶体管M4、第五晶体管M5和第六晶体管M6断开。
第四阶段B4、称为发光阶段，第一复位信号线Reset1、发光信号线EM和第二扫描信号端Gate2的信号为低电平信号，第一扫描信号线Gate1和第二复位信号线Reset2的信号为高电平信号。发光信号线EM的信号为低电平信号，使第五晶体管M5和第六晶体管M6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管M5、第三晶体管M3和第六晶体管M6向OLED的第一极提供驱动电压，驱动OLED发光。第一扫描信号线Gate1和第二扫描信号端Gate2的信号为低电平信号，第一复位信号线Reset1和第二复位信号线Reset2的信号为高电平信号，使得第一晶体管M1、第二晶体管M2、第四晶体管M4和第七晶体管M7断开。
在像素驱动电路驱动过程中，流过第三晶体管M3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第三晶体管M3的驱动电流为：
I＝K*(Vgs-Vth)2＝K*[(Vdd-Vd+|Vth|)-Vth]2＝K*[(Vdd-Vd]2
其中，I为流过第三晶体管M3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管M3的栅电极和第一极之间的电压差，Vth为第三晶体管M3的阈值电压，Vd为数据信号线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
由上述电流公式的推导结果可以看出，在发光阶段，第三晶体管M3的驱动电流已经不受第三晶体管M3的阈值电压的影响，从而消除了第三晶体管M3的阈值电压对驱动电流的影响，可以保证显示产品的显示亮度均匀，提升了整个显示产品的显示效果。
显示装置显示画面时，由栅极驱动电路生成驱动信号，像素驱动电路在驱动信号的控制下，进行初始化和数据写入，从而实现显示。显示装置显示的画面可以包括正常画面和特殊画面(例如：熄屏显示画面、静态画面或较少更新的画面等)。显示装置在显示正常画面时会在每一帧刷新面面，即在每一显示帧都需要对像素驱动电路进行初始化和数据写入。显示装置在显示一些特殊画面时可以通过低漏电的像素驱动电路即可维持原有的亮度。显示装置在显示特殊画面时，栅极驱动电路在每一帧生成驱动信号，对像素驱动电路进行数据写入会使得显示装置的画面出现串扰，影响了显示装置的显示效果。
图4为本公开实施例提供的移位寄存器的结构示意图。如图4所示，本公开实施例提供的移位寄存器可以包括：级联输出子电路、扫描输出子电路和节点控制控制子电路。
如图4所示，级联输出子电路，分别与信号输入端IN、第一时钟信号端CK、第二时钟信号端CB、第一电源端VGH、第二电源端VGL和级联输出信号端OUT1电连接，被配置为在信号输入端IN、第一时钟信号端CK、第二时钟信号端CB和第二电源端VGL的信号的控制下，向级联输出信号端OUT1提供第一电源端VGH或者第二时钟信号端CB的信号；节点控制子电路，分别与级联输出子电路、驱动输出子电路、第一电源端VGH、第二电源端VGL和第一控制输入信号端IN1电连接，被配置为在级联输出子电路、第一电源端VGH、第二电源端VGL和第一控制输入信号端IN1的信号的控制下，向驱动输出子电路提供信号；驱动输出子电路，分别与级联输出子电路、节点控制子电路、第一电源端VGH、第二控制输入信号端IN2和驱动输出信号端OUT2电连接，被配置为在级联输出子电路和节点控制子电路的信号的控制下，向驱动输出信号端OUT2提供第一电源端VGH或者第二控制输入信号端IN2的信号。其中，第一控制输入信号端IN1包括：第二时钟信号端CB，第二控制输入信号端IN2包括：掩蔽信号端MS，或者，第一控制输入信号端包括：第二时钟信号端CB和掩蔽信号端MS，第二控制输入信号端IN2包括：第二时钟信号端CB。
在示例性实施方式中，信号输入端IN的信号为单次脉冲信号。
在示例性实施方式中，第一时钟信号端CK和第二时钟信号端CB中的任一信号端的信号可以为重复高电压和低电压的方波信号。示例性地，第一时钟信号端CK1的信号和第二时钟信号端CK2可以具有相同的周期，并且可以被配置为相移信号。此处，与第一时钟信号端CK1的信号相比，第二时钟信号端CK2的信号可相移半个周期。第一时钟信号端CK1和第二时钟信号端CK2中任一信号端的信号在的每个周期中的高电压时段可设置为长于低电压时段。
在示例性实施方式中，第一时钟信号端CK1的信号的高电压时段可以设置为使得其宽度与第二时钟信号端CK2的信号的低电压时段重叠，第一时钟信号端CK1的信号的低电压时段可以设置为使得其宽度与第二时钟信号端CK2的信号的高电压时段重叠。
在示例性实施方式中，第一电源端VGH的信号为恒压信号，且为高电平信号。
在示例性实施方式中，第二电源端VGL的信号为恒压信号，且为低电平信号。
在示例性实施方式中，移位寄存器设置在显示装置中，显示装置所显示内容包括多个显示帧。本公开实施例提供的驱动输出子电路可以控制移位寄存器在一个显示帧内是否向显示装置中的子像素输出驱动信号。
本公开实施例提供的移位寄存器中设置的节点控制子电路和驱动输出子电路，可以在显示正常画面时，在每一显示帧输出驱动信号，对像素驱动电路进行反复初始化和数据写入，保证正常显示，还可以在显示特殊画面时，在部分显示帧不输出驱动信号，避免了数据写入导致的显示装置出现的串扰现象，提升了显示装置的显示效果。
在示例性实施方式中，显示装置的显示模式可以包括：第一显示模式和第二显示模式，第一显示模式的刷新率大于第二显示模式的刷新率。
在示例性实施方式中，在第一显示模式下，移位寄存器的级联输出信号端OUT1的信号和驱动输出信号端OUT2的信号相同。
在示例性实施方式中，在第二显示模式下，移位寄存器的级联输出信号端OUT1的信号和驱动输出信号端OUT2的信号在至少部分时间互为反相信号。
在示例性实施方式中，级联输出子电路可以为8T2C、8T3C、9T3C或者9T4C，本公开对此不做任何限定。
图5为级联输出子电路的等效电路图一。如图5所示，在示例性实施方式中，级联输出子电路可以包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第一电容C1和第二电容C2。
如图5所示，第一晶体管T1的控制极与第一时钟信号端CK电连接，第一晶体管T1的第一极与信号输入端IN电连接，第一晶体管T1的第二极与第一节点N1电连接；第二晶体管T2的控制极与第一节点N1电连接，第二晶体管T2的第一极与第一时钟信号端CK电连接，第二晶体管T2的第二极与第二节点N2电连接；第三晶体管T3的控制极与第一时钟信号端CK电连接，第三晶体管T3的第一极与第二电源端VGL电连接，第三晶体管T3的第二极与第二节点N2电连接；第四晶体管T4的控制极与第二节点N2电连接，第四晶体管T4的第一极与第一电源端VGH电连接，第四晶体管T4的第二极与第五晶体管T5的第一极电连接；第五晶体管T5的控制极与第二时钟信号端CB电连接，第五晶体管T5的第二极与第一节点N1电连接；第六晶体管T6的控制极与第二节点N2电连接，第六晶体管T6的第一极与第一电源端VGH电连接，第六晶体管T6的第二极与级联输出信号端OUT1电连接；第七晶体管T7的控制极与第三节点N3电连接，第七晶体管T7的第一极与第二时钟信号端CB电连接，第七晶体管T7的第二极与级联输出信号端OUT1电连接；第八晶体管T8的控制极与第二电源端VGL电连接，第八晶体管T8的第一极与第一节点N1电连接，第八晶体管T8的第二极与第三节点N3电连接；第一电容C1的第一端与第三节点N3电连接，第一电容C1的第二端与级联输出信号端OUT1电连接；第二电容C2的第一端与第二节点N2电连接，第二电容C2的第二端与第一电源端VGH电连接。
图6为级联输出子电路的等效电路图二。在示例性实施方式中，如图6所示，级联输出子电路可以包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第一电容C1、第二电容C2和第三电容C3。
如图6所示，第一晶体管T1的控制极与第一时钟信号端CK电连接，第一晶体管T1的第一极与信号输入端IN电连接，第一晶体管T1的第二极与第一节点N1电连接；第二晶体管T2的控制极与第一节点N1电连接，第二晶体管T2的第一极与第二电源端VGL电连接，第二晶体管T2的第二极与第二节点N2电连接；第三晶体管T3的控制极与第三电容C3的第一端电连接，第三晶体管T3的第一极与第二时钟信号端CB电连接，第三晶体管T3的第二极与第二节点N2电连接；第四晶体管T4的控制极与第二节点N2电连接，第四晶体管T4的第一极与第二电源端VGL电连接，第四晶体管T4的第二极与第五晶体管T5的第一极电连接；第五晶体管T5的控制极与第二时钟信号端CB电连接，第五晶体管T5的第二极与第一节点N1电连接；第六晶体管T6的控制极与第二节点N2电连接，第六晶体管T6的第一极与第一电源端VGH电连接，第六晶体管T6的第二极与级联输出信号端OUT1电连接；第七晶体管T7的控制极与第三节点N3电连接，第七晶体管T7的第一极与第二时钟信号端CB电连接，第七晶体管T7的第二极与级联输出信号端OUT1电连接；第八晶体管T8的控制极与第二电源端VGL电连接，第八晶体管T8的第一极与第一节点N1电连接，第八晶体管T8的第二极与第三节点N3电连接；第九晶体管T9的控制极与第一节点N1电连接，第九晶体管T9的第一极与第二电源端VGL电连接，第九晶体管T9的第二极与第三电容C3的第一端电连接；第一电容C1的第一端与第三节点N3电连接，第一电容C1的第二端与级联输出信号端OUT1电连接；第二电容C2的第一端与第二节点N2电连接，第二电容C2的第二端与第一电源端VGH电连接。第三电容C3的第二端与第二时钟信号端CB电连接。
在示例性实施方式中，如图5和图6所示，级联输出子电路还可以包括：第四电容C4。其中，第四电容C4的第一端与第一电源端VGH电连接，第四电容C4的第二端与级联输出信号端OUT1电连接。
本公开中的第四电容C4的设置可以保证级联输出信号端的信号的稳定性，进而可以提升移位寄存器的可靠性。
在示例性实施方式中，图5和图6中的第六晶体管T6和第七晶体管T7可以称为输出晶体管。第六晶体管T6和第七晶体管T7中的至少一个晶体管的控制极和源电极之间的电容大于级联输出子电路中除了第六晶体管T6和第七晶体管T7之外的其他晶体管的控制极和源电极之间的电容。
图5和图6中示出了级联输出子电路的两种示例性结构，本公开中的级联输出子电路的实现方式不限于此。
在示例性实施方式中，如图5和图6所示，级联输出子电路中设置有第一节点N1、第二节点N2和第三节点N3。
在示例性实施方式中，第一控制输入信号端包括：第二时钟信号端CB和掩蔽信号端MS，第二控制输入信号端包括：第二时钟信号端CB时，其中，节点控制子电路可以分别与第一节点N1和第三节点N3中的其中一个节点、第二节点N2、掩蔽信号端MS、第二时钟信号端CB、第一电源端VGH、第二电源端VGL和第五节点N5电连接，被配置为在第一节点N1和第三节点N3中的其中一个节点、第二节点N2、掩蔽信号端MS、第二时钟信号端CB和第二电源端VGL的信号的控制下，向第五节点N5提供第一电源端VGH或者掩蔽信号端MS的信号，驱动输出子电路，分别与第二节点N2、第五节点N5、第二时钟信号端CB、第一电源端VGH和驱动输出信号端OUT2电连接，被配置为在第二节点N2和第五节点N5的信号的控制下，向驱动输出信号端OUT2提供第一电源端VGH或者第二时钟信号端CB的信号，或者，第一控制输入信号端包括：第二时钟信号端CB，所述第二控制输入信号端包括：掩蔽信号端MS时，节点控制子电路，分别与第一节点N1和第三节点N3中的其中一个节点、第二节点N2、第二时钟信号端CB、第一电源端VGH、第二电源端VGL和第五节点N5电连接，被配置为在第一节点N1和第三节点N3中的其中一个节点、第二节点N2、第二时钟信号端CB和第二电源端VGL的信号的控制下，向第五节点N5提供第一电源端VGH或者第二时钟信号端CB的信号，驱动输出子电路，分别与第二节点N2、第五节点N5、第一电源端VGH、掩蔽信号端MS和驱动输出信号端OUT2电连接，被配置为在被配置为在第二节点N2和第五节点N5的信号的控制下，向驱动输出信号端OUT 2提供第一电源端VGH或者掩蔽信号端MS的信号。图5和图6是以驱动输出子电路与第一节点N1为例进行说明的。
图7为驱动输出子电路和节点控制子电路的等效电路图一。如图7所示，在示例性实施方式中，驱动输出子电路包括：第十晶体管T10、第十一晶体管T11和第五电容C5，节点控制子电路包括：第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15和第六电容C6。其中，第十晶体管T10的控制极与第五节点N5电连接，第十晶体管T10的第一极与第二时钟信号端CB电连接，第十晶体管T10的第二极与驱动输出信号端OUT2电连接；第十一晶体管T11的控制极与第二节点N2电连接，第十一晶体管T11的第一极与第一电源端VGH电连接，第十一晶体管T11的第二极与驱动输出信号端OUT2电连接；第十二晶体管T12的控制极与第四节点N4电连接，第十二晶体管T12的第一极与掩蔽信号端MS电连接，第十二晶体管T12的第二极与第五节点N5电连接；第十三晶体管T13的控制极与第二时钟信号端CB电连接，第十三晶体管T13的第一极与第十四晶体管T14的第二极电连接，第十三晶体管T13的第二极与第五节点N5电连接；第十四晶体管T14的控制极与第二节点N2电连接，第十四晶体管T14的第一极与第一电源端VGH电连接；第十五晶体管T15的控制极与第二电源端VGL电连接，第十五晶体管T15的第一极与第一节点N1电连接，第十五晶体管T15的第二极与第四节点N4电连接；第五电容C5的第一端与第五节点N5电连接，第五电容C5的第二端与驱动输出信号端OUT2电连接；第六电容C6的第一端与第四节点N4电连接，第六电容C6的第二端与第五节点N5电连接。图7是以节点控制子电路，分别与第一节点N1、第二节点N2、掩蔽信号端MS、第二时钟信号端CB、第一电源端VGH、第二电源端VGL和第五节点N5电连接，驱动输出子电路分别与第二节点N2、第五节点N5、第二时钟信号端CB、第一电源端VGH和驱动输出信号端OUT2电连接为例进行说明的。
图8为驱动输出子电路和节点控制子电路的等效电路图二。在示例性实施方式中，如图8所示，驱动输出子电路可以包括：第十晶体管T10、第十一晶体管T11和第五电容C5，节点控制子电路可以包括：第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15和第六电容C6。其中，第十晶体管T10的控制极与第五节点N5电连接，第十晶体管T10的第一极与掩蔽信号端MS电连接，第十晶体管T10的第二极与驱动输出信号端OUT2电连接；第十一晶体管T11的控制极与第二节点N2电连接，第十一晶体管T11的第一极与第一电源端VGH电连接，第十一晶体管T11的第二极与驱动输出信号端OUT2电连接；第十二晶体管T12的控制极与第四节点N4电连接，第十二晶体管T12的第一极与第二时钟信号端CB电连接，第十二晶体管T12的第二极与第五节点N5电连接；第十三晶体管T13的控制极与第二时钟信号端CB电连接，第十三晶体管T13的第一极与第十四晶体管T14的第二极电连接，第十三晶体管T13的第二极与第五节点N5电连接；第十四晶体管T14的控制极与第二节点N2电连接，第十四晶体管T14的第一极与第一电源端VGH电连接；第十五晶体管T15的控制极与第二电源端VGL电连接，第十五晶体管T15的第一极与第一节点N1电连接，第十五晶体管T15的第二极与第四节点N4电连接；第五电容C5的第一端与第五节点N5电连接，第五电容C5的第二端与驱动输出信号端OUT2电连接；第六电容C6的第一端与第四节点N4电连接，第六电容C6的第二端与第五节点N5电连接。图8是以节点控制子电路，分别与第一节点N1、第二节点N2、第二时钟信号端CB、第一电源端VGH、第二电源端VGL和第五节点N5电连接，驱动输出子电路分别与第二节点N2、第五节点N5、掩蔽信号端MS、第一电源端VGH和驱动输出信号端OUT2电连接为例进行说明的。
图9为驱动输出子电路和节点控制子电路的等效电路图三。在示例性实施方式中，如图9所示，驱动输出子电路包括：第十晶体管T10、第十一晶体管T11和第五电容C5，节点控制子电路包括：第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15和第六电容C6。其中，第十晶体管T10的控制极与第五节点N5电连接，第十晶体管T10的第一极与第二时钟信号端CB电连接，第十晶体管T10的第二极与驱动输出信号端OUT2电连接；第十一晶体管T11的控制极与第二节点N2电连接，第十一晶体管T11的第一极与第一电源端VGH电连接，第十一晶体管T11的第二极与驱动输出信号端OUT2电连接；第十二晶体管T12的控制极与第四节点N4电连接，第十二晶体管T12的第一极与掩蔽信号端MS电连接，第十二晶体管T12的第二极与第五节点N5电连接；第十三晶体管T13的控制极与第二时钟信号端CB电连接，第十三晶体管T13的第一极与第十四晶体管T14的第二极电连接，第十三晶体管T13的第二极与第五节点N5电连接；第十四晶体管T14的控制极与第二节点N2电连接，第十四晶体管T14的第一极与第一电源端VGH电连接；第十五晶体管T15的控制极与第二电源端VGL电连接，第十五晶体管T15的第一极与第三节点N3电连接，第十五晶体管T15的第二极与第四节点N4电连接；第五电容C5的第一端与第五节点N5电连接，第五电容C5的第二端与驱动输出信号端OUT2电连接；第六电容C6的第一端与第四节点N4电连接，第六电容C6的第二端与第五节点N5电连接。图9是以节点控制子电路，分别与第三节点N3、第二节点N2、第二时钟信号端CB、掩蔽信号端MS、第一电源端VGH、第二电源端VGL和第五节点N5电连接，驱动输出子电路分别与第二节点N2、第五节点N5、第二时钟信号端CB、第一电源端VGH和驱动输出信号端OUT2电连接为例进行说明的。
图10为驱动输出子电路和节点控制子电路的等效电路图四。在示例性实施方式中，如图10所示，驱动输出子电路可以包括：第十晶体管T10、第十一晶体管T11、第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第五电容C5和第六电容C6。其中，第十晶体管T10的控制极与第五节点N5电连接，第十晶体管T10的第一极与掩蔽信号端MS电连接，第十晶体管T10的第二极与驱动输出信号端OUT2电连接；第十一晶体管T11的控制极与第二节点N2电连接，第十一晶体管T11的第一极与第一电源端VGH电连接，第十一晶体管T11的第二极与驱动输出信号端OUT2电连接；第十二晶体管T12的控制极与第四节点N4电连接，第十二晶体管T12的第一极与第二时钟信号端CB电连接，第十二晶体管T12的第二极与第五节点N5电连接；第十三晶体管T13的控制极与第二时钟信号端CB电连接，第十三晶体管T13的第一极与第十四晶体管T14的第二极电连接，第十三晶体管T13的第二极与第五节点N5电连接；第十四晶体管T14的控制极与第二节点N2电连接，第十四晶体管T14的第一极与第一电源端VGH电连接；第十五晶体管T15的控制极与第二电源端VGL电连接，第十五晶体管T15的第一极与第三节点N3电连接，第十五晶体管T15的第二极与第四节点N4电连接；第五电容C5的第一端与第五节点N5电连接，第五电容C5的第二端与驱动输出信号端OUT2电连接；第六电容C6的第一端与第四节点N4电连接，第六电容C6的第二端与第五节点N5电连接。图10是以节点控制子电路，分别与第三节点N3、第二节点N2、第二时钟信号端CB、第一电源端VGH、第二电源端VGL和第五节点N5电连接，驱动输出子电路分别与第二节点N2、第五节点N5、掩蔽信号端MS、第一电源端VGH和驱动输出信号端OUT2电连接为例进行说明的。
图7至图10提供的驱动输出子电路中第十晶体管T10和第十一晶体管T11为输出晶体管。第十晶体管T10和第十一晶体管T11中的至少一个晶体管的控制极和源电极之间的电容大于移位寄存器中除了第十晶体管T10和第十一晶体管T11中的其他晶体管的控制极和源电极之间电容。
图7和图9中驱动输出信号端OUT2的输出信号可以为第二时钟信号端CB的信号，图8和图10中驱动输出信号端OUT2的信号可以为掩蔽信号端MS的信号。由于掩蔽信号端MS的信号不会像第二时钟信号端CB的时钟信号时常发生跳变，所以图8和图10中由掩蔽信号端MS的信号向第五电容C5进行充电，可以降低移位寄存器的功耗。
图7至图10提供的驱动输出子电路中的第十二晶体管T12和第十五晶体管T15设置在第十晶体管T10的控制极和第一节点N1之间，或者设置在第十晶体管T10的控制极和第三节点N3之间，即将级联输出子电路中的第七晶体管T7的控制极与驱动输出子电路中的第十晶体管T10的控制极间隔开来，避免了直接由第一节点N1或者第三节点N3直接向驱动输出子电路中的第十晶体管T10的控制极提供控制信号，可以避免第一节点N1或者第三节点N3的信号的衰减对第十晶体管T10的控制极提供的控制信号的影响，可以保证第十晶体管T10的控制极的信号的稳定性，进而可以提升驱动输出子电路的抗干扰性。
图7至图10中示出了驱动输出子电路的两种示例性结构，本公开中的驱动输出子电路的实现方式不限于此。
图11为移位寄存器的等效电路图一，图12为移位寄存器的等效电路图二，图13为移位寄存器的等效电路图三，图14为移位寄存器的等效电路图四。在示例性实施方式中，如图11至图14所示，级联输出子电路可以包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第一电容C1和第二电容C2，或者包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第一电容C1、第二电容C2和第四电容C4。驱动输出子电路包括：第十晶体管T10、第十一晶体管T11和第五电容C5。节点控制子电路包括：第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15和第六电容C6。
如图11至图14所示，第一晶体管T1的控制极与第一时钟信号端CK电连接，第一晶体管T1的第一极与信号输入端IN电连接，第一晶体管T1的第二极与第一节点N1电连接；第二晶体管T2的控制极与第一节点N1电连接，第二晶体管T2的第一极与第一时钟信号端CK电连接，第二晶体管T2的第二极与第二节点N2电连接；第三晶体管T3的控制极与第一时钟信号端CK电连接，第三晶体管T3的第一极与第二电源端VGL电连接，第三晶体管T3的第二极与第二节点N2电连接；第四晶体管T4的控制极与第二节点N2电连接，第四晶体管T4的第一极与第一电源端VGH电连接，第四晶体管T4的第二极与第五晶体管T5的第一极电连接；第五晶体管T5的控制极与第二时钟信号端CB电连接，第五晶体管T5的第二极与第一节点N1电连接；第六晶体管T6的控制极与第二节点N2电连接，第六晶体管T6的第一极与第一电源端VGH电连接，第六晶体管T6的第二极与级联输出信号端OUT1电连接；第七晶体管T7的控制极与第三节点N3电连接，第七晶体管T7的第一极与第二时钟信号端CB电连接，第七晶体管T7的第二极与级联输出信号端OUT1电连接；第八晶体管T8的控制极与第二电源端VGL电连接，第八晶体管T8的第一极与第一节点N1电连接，第八晶体管T8的第二极与第三节点N3电连接；第十晶体管T10的控制极与第五节点N5电连接，第十晶体管T10的第一极与掩蔽信号端MS和第二时钟信号端CB的其中一个信号端电连接，第十晶体管T10的第二极与驱动输出信号端OUT2电连接；第十一晶体管T11的控制极与第二节点N2电连接，第十一晶体管T11的第一极与第一电源端VGH电连接，第十一晶体管T11的第二极与驱动输出信号端OUT2电连接；第十二晶体管T12的控制极与第四节点N4电连接，第十二晶体管T12的第一极与掩蔽信号端MS和第二时钟信号端CB中的另一个信号端电连接，第十二晶体管T12的第二极与第五节点N5电连接；第十三晶体管T13的控制极与第二时钟信号端CB电连接，第十三晶体管T13的第一极与第十四晶体管T14的第二极电连接，第十三晶体管T13的第二极与第五节点N5电连接；第十四晶体管T14的控制极与第二节点N2电连接，第十四晶体管T14的第一极与第一电源端VGH电连接；第十五晶体管T15的控制极与第二电源端VGL电连接，第十五晶体管T15的第一极与第一节点N1和第三节点N3中的其中一个节点电连接，第十五晶体管T15的第二极与第四节点N4电连接；第一电容C1的第一端与第三节点N3电连接，第一电容C1的第二端与级联输出信号端OUT1电连接；第二电容C2的第一端与第二节点N2电连接，第二电容C2的第二端与第一电源端VGH电连接；第四电容C4的第一端与第一电源端VGH电连接，第四电容C4的第二端与级联输出信号端OUT1电连接；第五电容C5的第一端与第五节点N5电连接，第五电容C5的第二端与驱动输出信号端OUT2电连接；第六电容C6的第一端与第四节点N4电连接，第六电容C6的第二端与第五节点N5电连接。图11是以第十晶体管T10与第二时钟信号端CB电连接，第十二晶体管T12的第一极与掩蔽信号端MS电连接，第十五晶体管T15的第一极与第一节点N1为例进行说明的。图12是以第十晶体管T10与第二时钟信号端CB电连接，第十二晶体管T12的第一极与掩蔽信号端MS电连接，第十五晶体管T15的第一极与第三节点N3为例进行说明的。图13是以第十晶体管T10与掩蔽信号端MS电连接，第十二晶体管T12的第一极与第二时钟信号端CB电连接，第十五晶体管T15的第一极与第一节点N1为例进行说明的。图14是以第十晶体管T10与掩蔽信号端MS电连接，第十二晶体管T12的第一极与第二时钟信号端CB电连接，第十五晶体管T15的第一极与第三节点N3为例进行说明的。
在示例性实施方式中，第一晶体管T1至第八晶体管T8以及第九晶体管T9至第十五晶体管T15中的至少一个晶体管可以为P型晶体管。
图15为移位寄存器的的等效电路图五，图16为移位寄存器的等效电路图六，图17为移位寄存器的等效电路图七，图18为移位寄存器的等效电路图八。在示例性实施方式中，如图15至图18所示，级联输出子电路包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第一电容C1、第二电容C2和第三电容C3，或者级联输出子电路包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第一电容C1、第二电容C2、第三电容C3和第四电容C4。驱动输出子电路包括：第十晶体管T10、第十一晶体管T11和第五电容C5。节点控制子电路包括：第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15和第六电容C6。
如图15至图18所示，第一晶体管T1的控制极与第一时钟信号端CK电连接，第一晶体管T1的第一极与信号输入端IN电连接，第一晶体管T1的第二极与第一节点N1电连接；第二晶体管T2的控制极与第一节点N1电连接，第二晶体管T2的第一极与第二电源端VGL电连接，第二晶体管T2的第二极与第二节点N2电连接；第三晶体管T3的控制极与第三电容C3的第一端电连接，第三晶体管T3的第一极与第二时钟信号端CB电连接，第三晶体管T3的第二极与第二节点N2电连接；第四晶体管T4的控制极与第二节点N2电连接，第四晶体管T4的第一极与第二电源端VGL电连接，第四晶体管T4的第二极与第五晶体管T5的第一极电连接；第五晶体管T5的控制极与第二时钟信号端CB电连接，第五晶体管T5的第二极与第一节点N1电连接；第六晶体管T6的控制极与第二节点N2电连接，第六晶体管T6的第一极与第一电源端VGH电连接，第六晶体管T6的第二极与级联输出信号端OUT1电连接；第七晶体管T7的控制极与第三节点N3电连接，第七晶体管T7的第一极与第二时钟信号端CB电连接，第七晶体管T7的第二极与级联输出信号端OUT1电连接；第八晶体管T8的控制极与第二电源端VGL电连接，第八晶体管T8的第一极与第一节点N1电连接，第八晶体管T8的第二极与第三节点N3电连接；第九晶体管T9的控制极与第一节点N1电连接，第九晶体管T9的第一极与第二电源端VGL电连接，第九晶体管T9的第二极与第三电容C3的第一端电连接；第十晶体管T10的控制极与第五节点N5电连接，第十晶体管T10的第一极与掩蔽信号端MS和第二时钟信号端CB的其中一个信号端电连接，第十晶体管T10的第二极与驱动输出信号端OUT2电连接；第十一晶体管T11的控制极与第二节点N2电连接，第十一晶体管T11的第一极与第一电源端VGH电连接，第十一晶体管T11的第二极与驱动输出信号端OUT2电连接；第十二晶体管T12的控制极与第四节点N4电连接，第十二晶体管T12的第一极与掩蔽信号端MS和第二时钟信号端CB中的另一个信号端电连接，第十二晶体管T12的第二极与第五节点N5电连接；第十三晶体管T13的控制极与第二时钟信号端CB电连接，第十三晶体管T13的第一极与第十四晶体管T14的第二极电连接，第十三晶体管T13的第二极与第五节点N5电连接；第十四晶体管T14的控制极与第二节点N2电连接，第十四晶体管T14的第一极与第一电源端VGH电连接；第十五晶体管T15的控制极与第二电源端VGL电连接，第十五晶体管T15的第一极与第一节点N1和第三节点N3中的其中一个节点电连接，第十五晶体管T15的第二极与第四节点N4电连接；第一电容C1的第一端与第三节点N3电连接，第一电容C1的第二端与级联输出信号端OUT1电连接；第二电容C2的第一端与第二节点N2电连接，第二电容C2的第二端与第一电源端VGH电连接；第三电容C3的第二端与第二时钟信号端CB电连接；第四电容C4的第一端与第一电源端VGH电连接，第四电容C4的第二端与级联输出信号端OUT1电连接；第五电容C5的第一端与第五节点N5电连接，第五电容C5的第二端与驱动输出信号端OUT2电连接；第六电容C6的第一端与第四节点N4电连接，第六电容C6的第二端与第五节点N5电连接。图15是以第十晶体管T10与第二时钟信号端CB电连接，第十二晶体管T12的第一极与掩蔽信号端MS电连接，第十五晶体管T15的第一极与第一节点N1为例进行说明的。图16是以第十晶体管T10与第二时钟信号端CB电连接，第十二晶体管T12的第一极与掩蔽信号端MS电连接，第十五晶体管T15的第一极与第三节点N3为例进行说明的。图17是以第十晶体管T10与掩蔽信号端MS电连接，第十二晶体管T12的第一极与第二时钟信号端CB电连接，第十五晶体管T15的第一极与第一节点N1为例进行说明的。图18是以第十晶体管T10与掩蔽信号端MS电连接，第十二晶体管T12的第一极与第二时钟信号端CB电连接，第十五晶体管T15的第一极与第三节点N3为例进行说明的。
在示例性实施方式中，第一晶体管T1至第十五晶体管T15中的至少一个晶体管可以为P型晶体管。
在示例性实施方式中，第一电容C1至第六电容C6中的任一电容可以是通过工艺制程制作的电容器件，例如，可以通过制作专门的电容电极来实现电容器件，电容的多个电容电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现。或者，第一电容C1至第六电容C6中的任一电容可以是多个器件之间的寄生电容，可以通过晶体管本身与其他器件、线路来实现。第一电容C1至第六电容C6中的任一电容的连接方式包括但不局限于上面描述的方式，可以为其它适用的连接方式，可以存储相应节点的电平即可。这里，本公开示例性实施方式对此不做限定。
图19为图11至图18提供的移位寄存器在第一显示模式下的工作时序图，图20为图11至图18提供的移位寄存器在第二显示模式下的工作时序图。图19和图20是以移位寄存器中的所有晶体管均为P型晶体管为例进行说明的。
在示例性实施方式中，如图19所示，在第一显示模式下，掩蔽信号端MS的信号为第一信号V1。
在示例性实施方式中，如图20所示，在第二显示模式下，掩蔽信号端MS的信号在至少部分时间段内为第一信号V1，且在至少部分时间段内为第二信号V2。掩蔽信号端MS的信号为第一信号V1的时间段与级联输出信号端OUT1输出信号的时间段不交叠，掩蔽信号端MS的信号为第二信号的时间段与级联输出信号端OUT1输出信号的时间段至少部分交叠。第一信号V1与第二信号V2中的至少一个信号的电压值恒定，且第一信号V1的电压值小于第二信号V2的电压值。
在示例性实施方式中，如图20所示，在第二显示模式下，级联输出信号端OUT1输出信号的时间段位于掩蔽信号端MS的信号为第二信号的时间段内。
在示例性实施方式中，如图20所示，掩蔽信号端MS的信号由第一信号变为第二信号的时刻t发生在输出时间段之前，其中，输出时间段为级联输出信号端输出信号的时间段。
在示例性实施方式中，掩蔽信号端MS的信号由第一信号变为第二信号的时刻t可以位于第一时间段t1或者第二时间段t2内，其中，在第一时间段t1内，第一时钟信号端CK的信号为低电平信号，第一时间段t1发生在输出时间段之前，第二时间段t2发生在第一时间段t 1和输出时间段之间，第二时间段t2的持续时间小于第一时间段t1或者输出时间段的至少一个时间段的持续时间。图20是以掩蔽信号端MS的信号由第一信号变为第二信号的时刻t位于第一时间段t1为例进行说明的。
图11至图18提供的移位寄存器中，由于第二电源端VGL的信号为低电平信号，因此，第八晶体管T8和第十五晶体管T15持续导通。
图11提供的移位寄存器与图12提供的移位寄存器提供的移位寄存器不同之处在于第十五晶体管T15的第一极连接的节点不同，图11提供的移位寄存器中第一节点N1的信号写入第四节点N4，而图12提供的移位寄存器中第三节点N3的信号写入第四节点N4。由于第十五晶体管T15持续导通，因此，第一节点N1和第三节点N3的信号相同，因此，图11提供的移位寄存器与图12提供的移位寄存器的工作过程相同。
如图19所示，图11和图12提供的移位寄存器在第一显示模式下的工作过程如下：
第一阶段S11，第一时钟信号端CK、信号输入端IN和掩蔽信号端MS为低电平信号，第二时钟信号端CB的信号为高电平信号，第一晶体管T1和第三晶体管T3导通，第五晶体管T5和第十三晶体管T13断开。
第一晶体管T1导通，信号输入端IN的低电平信号写入第一节点N1，第一节点N1的低电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7导通，第二时钟信号端CB的高电平信号写入级联输出信号端OUT1，第一节点N1或者第三节点N3的低电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12导通，掩蔽信号端MS的低电平信号写入第五节点N5，第十晶体管T10导通，第二时钟信号端CB的高电平信号写入驱动输出信号端OUT2。第一节点N1的信号为低电平信号，第二晶体管T2导通，第一时钟信号端CK的低电平信号写入第二节点N2，第三晶体管T3导通，第二电源端VGL的低电平信号写入第二节点N2，第二节点N2的信号为低电平信号，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14导通，第一电源端VGH的高电平信号写入第四晶体管T4和第五晶体管T5连接的节点、第十三晶体管T13和第十四晶体管T14的连接的节点、级联输出信号端OUT1和驱动输出信号端OUT2。
本阶段，第一节点N1、第二节点N2、第三节点N3、第四节点N4和第五节点N5的信号均为低电平信号。级联输出信号端OUT1和驱动输出信号端OUT2的信号为高电平信号。
第二阶段S12，第二时钟信号端CB和掩蔽信号端MS的信号为低电平信号，第一时钟信号端CK和信号输入端IN的信号为高电平信号，第一晶体管T1和第三晶体管T3断开，第五晶体管T5和第十三晶体管T13导通。
第一晶体管T1断开，信号输入端IN的高电平信号无法写入第一节点N1，第一节点N1的信号保持上一阶段的低电平信号，第一节点N1的低电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7导通，第二时钟信号端CB的低电平信号写入级联输出信号端OUT1，级联输出信号端OUT1的信号为低电平信号，在第一电容C1的作用下，第三节点N3的信号持续被拉低，第三节点N3的低电平信号通过导通的第八晶体管T8写入第一节点N1，第一节点N1持续被拉低，第一节点N1或者第三节点N3的低电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12导通，掩蔽信号端MS的低电平信号写入第五节点N5，第十晶体管T10导通，第二时钟信号端CB的低电平信号写入驱动输出信号端OUT2。第一节点N1的信号为低电平信号，第二晶体管T2导通，第一时钟信号端CK的高电平信号写入第二节点N2，第三晶体管T3断开，第二电源端VGL的低电平信号无法写入第二节点N2，第二节点N2的信号为高电平信号，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14断开，第一电源端VGH的高电平信号无法写入第四晶体管T4和第五晶体管T5连接的节点、第十三晶体管T13和第十四晶体管T14的连接的节点、级联输出信号端OUT1和驱动输出信号端OUT2。
本阶段，第一节点N1、第三节点N3、第四节点N4和第五节点N5的信号均为低电平信号，第二节点N2的信号为高电平信号。级联输出信号端OUT1和驱动输出信号端OUT2的信号为低电平信号。
第三阶段S13，第一时钟信号端CK和掩蔽信号端MS的信号为低电平信号，信号输入端IN和第二时钟信号端CB的信号为高电平信号，第一晶体管T1和第三晶体管T3导通，第五晶体管T5和第十三晶体管T13断开。
第一晶体管T1导通，信号输入端IN的高电平信号写入第一节点N1，第一节点N1的高电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7断开，第一节点N1或者第三节点N3的高电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12断开，掩蔽信号端MS的低电平信号无法写入第五节点N5。由于本阶段第四节点N4的信号被拉高，在第六电容C6的作用下，第五节点N5的信号同样被拉高，第五节点N5的信号为高电平信号，第十晶体管T10断开。第一节点N1的信号为高电平信号，第二晶体管T2断开，第一时钟信号端CK的低电平信号无法写入第二节点N2，第三晶体管T3导通，第二电源端VGL的低电平信号写入第二节点N2，第二节点N2的信号为低电平信号，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14导通，第一电源端VGH的高电平信号写入第四晶体管T4和第五晶体管T5连接的节点、第十三晶体管T13和第十四晶体管T14的连接的节点、级联输出信号端OUT1和驱动输出信号端OUT2。
本阶段，第一节点N1、第三节点N3、第四节点N4和第五节点N5的信号均为高电平信号，第二节点N2的信号为低电平信号，级联输出信号端OUT1和驱动输出信号端OUT2的信号为高电平信号。
第四阶段S14，第二时钟信号端CB和掩蔽信号端MS的信号为低电平信号，第一时钟信号端CK和信号输入端IN的信号为高电平信号，第一晶体管T1和第三晶体管T3断开，第五晶体管T5和第十三晶体管T13导通。
第一晶体管T1断开，第一节点N1的信号保持上一阶段的高电平信号，第一节点N1的高电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7断开，第一节点N1(第三节点N3)的高电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12断开，掩蔽信号端MS的低电平信号无法写入第五节点N5。第一节点N1的信号为高电平信号，第二晶体管T2断开，第一时钟信号端CK的高电平信号无法写入第二节点N2，在第二电容C2的作用下，第二节点N2的信号保持为上一阶段的低电平信号，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14导通，第一电源端VGH的高电平信号写入第四晶体管T4和第五晶体管T5连接的节点、第十三晶体管T13和第十四晶体管T14的连接的节点、级联输出信号端OUT1和驱动输出信号端OUT2。第一电源端VGH的高电平信号通过导通的第十三晶体管T13写入第五节点N5，第十晶体管T10断开。
本阶段，第一节点N1、第三节点N3、第四节点N4和第五节点N5的信号均为高电平信号，第二节点N2的信号为低电平信号。级联输出信号端OUT1和驱动输出信号端OUT2的信号为高电平信号。
在信号输入端IN的信号为低电平信号之前，移位寄存器持续执行第三阶段S13和第四阶段S14。
如图20所示，图11和图12提供的移位寄存器在第二显示模式下的工作过程如下：
第一阶段S21，第一时钟信号端CK、信号输入端IN和掩蔽信号端MS为低电平信号，第二时钟信号端CB的信号为高电平信号，第一晶体管T1和第三晶体管T3导通，第五晶体管T5和第十三晶体管T13断开。
第一晶体管T1导通，信号输入端IN的低电平信号写入第一节点N1，第一节点N1的低电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7导通，第二时钟信号端CB的高电平信号写入级联输出信号端OUT1，第一节点N1或者第三节点N3的低电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12导通，掩蔽信号端MS的低电平信号写入第五节点N5，第十晶体管T10导通，第二时钟信号端CB的高电平信号写入驱动输出信号端OUT2。第一节点N1的信号为低电平信号，第二晶体管T2导通，第一时钟信号端CK的低电平信号写入第二节点N2，第三晶体管T3导通，第二电源端VGL的低电平信号写入第二节点N2，第二节点N2的信号为低电平信号，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14导通，第一电源端VGH的高电平信号写入第四晶体管T4和第五晶体管T5连接的节点、第十三晶体管T13和第十四晶体管T14的连接的节点、级联输出信号端OUT1和驱动输出信号端OUT2。
本阶段，第一节点N1、第二节点N2、第三节点N3、第四节点N4和第五节点N5的信号均为低电平信号。级联输出信号端OUT1和驱动输出信号端OUT2的信号为高电平信号。
第二阶段S22，第二时钟信号端CB的信号为低电平信号，第一时钟信号端CK、信号输入端IN和掩蔽信号端MS的信号为高电平信号，第一晶体管T1和第三晶体管T3断开，第五晶体管T5和第十三晶体管T13导通。
第一晶体管T1断开，信号输入端IN的高电平信号无法写入第一节点N1，第一节点N1的信号保持上一阶段的低电平信号，第一节点N1的低电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7导通，第二时钟信号端CB的低电平信号写入级联输出信号端OUT1，级联输出信号端OUT1的信号为低电平信号，在第一电容C1的作用下，第三节点N3的信号持续被拉低，第三节点N3的低电平信号通过导通的第八晶体管T8写入第一节点N1，第一节点N1持续被拉低，第一节点N1或者第三节点N3的低电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12导通，掩蔽信号端MS的高电平信号写入第五节点N5，第十晶体管T10断开，第二时钟信号端CB的低电平信号无法写入驱动输出信号端OUT2。在第五电容C5的作用下，驱动输出信号端OUT2保持为上一阶段的高电平信号。第一节点N1的信号为低电平信号，第二晶体管T2导通，第一时钟信号端CK的高电平信号写入第二节点N2，第三晶体管T3断开，第二电源端VGL的低电平信号无法写入第二节点N2，第二节点N2的信号为高电平信号，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14断开，第一电源端VGH的高电平信号无法写入第四晶体管T4和第五晶体管T5连接的节点、第十三晶体管T13和第十四晶体管T14的连接的节点、级联输出信号端OUT1和驱动输出信号端OUT2。
本阶段，第一节点N1、第三节点N3、第四节点N4和第五节点N5的信号均为低电平信号，第二节点N2的信号为高电平信号。级联输出信号端OUT1的信号为低电平信号，驱动输出信号端OUT2浮接，保持上一阶段的低电平信号。
第三阶段S23，第一时钟信号端CK的信号为低电平信号，掩蔽信号端MS、信号输入端IN和第二时钟信号端CB的信号为高电平信号，第一晶体管T1和第三晶体管T3导通，第五晶体管T5和第十三晶体管T13断开。
第一晶体管T1导通，信号输入端IN的高电平信号写入第一节点N1，第一节点N1的高电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7断开，第一节点N1(或者第三节点N3的高电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12断开，掩蔽信号端MS的高电平信号无法写入第五节点N5。由于本阶段第四节点N4的信号被拉高，在第六电容C6的作用下，第五节点N5的信号同样被拉高，第五节点N5的信号为高电平信号，第十晶体管T10断开。第一节点N1的信号为高电平信号，第二晶体管T2断开，第一时钟信号端CK的低电平信号无法写入第二节点N2，第三晶体管T3导通，第二电源端VGL的低电平信号写入第二节点N2，第二节点N2的信号为低电平信号，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14导通，第一电源端VGH的高电平信号写入第四晶体管T4和第五晶体管T5连接的节点、第十三晶体管T13和第十四晶体管T14的连接的节点、级联输出信号端OUT1和驱动输出信号端OUT2。
本阶段，第一节点N1、第三节点N3、第四节点N4和第五节点N5的信号均为高电平信号，第二节点N2的信号为低电平信号，级联输出信号端OUT1和驱动输出信号端OUT2的信号为高电平信号。
第四阶段S24，第二时钟信号端CB的信号为低电平信号，第一时钟信号端CK、信号输入端IN和掩蔽信号端MS的信号为高电平信号，第一晶体管T1和第三晶体管T3断开，第五晶体管T5和第十三晶体管T13导通。
第一晶体管T1断开，第一节点N1的信号保持上一阶段的高电平信号，第一节点N1的高电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7断开，第一节点N1或者第三节点N3的高电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12断开，掩蔽信号端MS的高电平信号无法写入第五节点N5。第一节点N1的信号为高电平信号，第二晶体管T2断开，第一时钟信号端CK的高电平信号无法写入第二节点N2，在第二电容C2的作用下，第二节点N2的信号保持为上一阶段的低电平信号，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14导通，第一电源端VGH的高电平信号写入第四晶体管T4和第五晶体管T5连接的节点、第十三晶体管T13和第十四晶体管T14的连接的节点、级联输出信号端OUT1和驱动输出信号端OUT2，第一电源端VGH的高电平信号通过导通的第十三晶体管T13写入第五节点N5，第十晶体管T10断开。
本阶段，第一节点N1、第三节点N3、第四节点N4和第五节点N5的信号均为高电平信号，第二节点N2的信号为低电平信号。级联输出信号端OUT1和驱动输出信号端OUT2的信号为高电平信号。
在信号输入端IN的信号为低电平信号之前，移位寄存器持续执行第三阶段S23和第四阶段S24。
图13提供的移位寄存器与图14提供的移位寄存器提供的移位寄存器不同之处在于第十五晶体管T15的第一极连接的节点不同，图13提供的移位寄存器中第一节点N1的信号写入第四节点N4，而图14提供的移位寄存器中第三节点N3的信号写入第四节点N4。由于第十五晶体管T15持续导通，因此，第一节点N1和第三节点N3的信号相同，因此，图13提供的移位寄存器与图14提供的移位寄存器的工作过程相同。
如图19所示，图13和图14提供的移位寄存器在第一显示模式下的工作过程如下：
第一阶段S11，第一时钟信号端CK、信号输入端IN和掩蔽信号端MS为低电平信号，第二时钟信号端CB的信号为高电平信号，第一晶体管T1和第三晶体管T3导通，第五晶体管T5和第十三晶体管T13断开。
第一晶体管T1导通，信号输入端IN的低电平信号写入第一节点N1，第一节点N1的低电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7导通，第二时钟信号端CB的高电平信号写入级联输出信号端OUT1，第一节点N1或者第三节点N3的低电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12导通，第二时钟信号端CB的高电平信号写入第五节点N5，第十晶体管T10断开，掩蔽信号端MS的低电平信号无法写入驱动输出信号端OUT2。第一节点N1的信号为低电平信号，第二晶体管T2导通，第一时钟信号端CK的低电平信号写入第二节点N2，第三晶体管T3导通，第二电源端VGL的低电平信号写入第二节点N2，第二节点N2的信号为低电平信号，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14导通，第一电源端VGH的高电平信号写入第四晶体管T4和第五晶体管T5连接的节点、第十三晶体管T13和第十四晶体管T14的连接的节点、级联输出信号端OUT1和驱动输出信号端OUT2。
本阶段，第一节点N1、第二节点N2、第三节点N3、第四节点N4和第五节点N5的信号均为低电平信号。级联输出信号端OUT1和驱动输出信号端OUT2的信号为高电平信号。
第二阶段S12，第二时钟信号端CB和掩蔽信号端MS的信号为低电平信号，第一时钟信号端CK和信号输入端IN的信号为高电平信号，第一晶体管T1和第三晶体管T3断开，第五晶体管T5和第十三晶体管T13导通。
第一晶体管T1断开，信号输入端IN的高电平信号无法写入第一节点N1，第一节点N1的信号保持上一阶段的低电平信号，第一节点N1的低电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7导通，第二时钟信号端CB的低电平信号写入级联输出信号端OUT1，级联输出信号端OUT1的信号为低电平信号，在第一电容C1的作用下，第三节点N3的信号持续被拉低，第三节点N3的低电平信号通过导通的第八晶体管T8写入第一节点N1，第一节点N1持续被拉低，第一节点N1或者第三节点N3的低电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12导通，第二时钟信号端CB的低电平信号写入第五节点N5，第十晶体管T10导通，掩蔽信号端MS的低电平信号写入驱动输出信号端OUT2。第一节点N1的信号为低电平信号，第二晶体管T2导通，第一时钟信号端CK的高电平信号写入第二节点N2，第三晶体管T3断开，第二电源端VGL的低电平信号无法写入第二节点N2，第二节点N2的信号为高电平信号，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14断开，第一电源端VGH的高电平信号无法写入第四晶体管T4和第五晶体管T5连接的节点、第十三晶体管T13和第十四晶体管T14的连接的节点、级联输出信号端OUT1和驱动输出信号端OUT2。
本阶段，第一节点N1、第三节点N3、第四节点N4和第五节点N5的信号均为低电平信号，第二节点N2的信号为高电平信号。级联输出信号端OUT1和驱动输出信号端OUT2的信号为低电平信号。
第三阶段S13，第一时钟信号端CK和掩蔽信号端MS的信号为低电平信号，信号输入端IN和第二时钟信号端CB的信号为高电平信号，第一晶体管T1和第三晶体管T3导通，第五晶体管T5和第十三晶体管T13断开。
第一晶体管T1导通，信号输入端IN的高电平信号写入第一节点N1，第一节点N1的高电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7断开，第一节点N1或者第三节点N3的高电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12断开，第二时钟信号端CB的高电平信号无法写入第五节点N5。由于本阶段第四节点N4的信号被拉高，在第六电容C6的作用下，第五节点N5的信号同样被拉高，第五节点N5的信号为高电平信号，第十晶体管T10断开。第一节点N1的信号为高电平信号，第二晶体管T2断开，第一时钟信号端CK的低电平信号无法写入第二节点N2，第三晶体管T3导通，第二电源端VGL的低电平信号写入第二节点N2，第二节点N2的信号为低电平信号，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14导通，第一电源端VGH的高电平信号写入第四晶体管T4和第五晶体管T5连接的节点、第十三晶体管T13和第十四晶体管T14的连接的节点、级联输出信号端OUT1和驱动输出信号端OUT2。
本阶段，第一节点N1、第三节点N3、第四节点N4和第五节点N5的信号均为高电平信号，第二节点N2的信号为低电平信号，级联输出信号端OUT1和驱动输出信号端OUT2的信号为高电平信号。
第四阶段S14，第二时钟信号端CB和掩蔽信号端MS的信号为低电平信号，第一时钟信号端CK和信号输入端IN的信号为高电平信号，第一晶体管T1和第三晶体管T3断开，第五晶体管T5和第十三晶体管T13导通。
第一晶体管T1断开，第一节点N1的信号保持上一阶段的高电平信号，第一节点N1的高电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7断开，第一节点N1或者第三节点N3的高电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12断开，第二时钟信号端CB的低电平信号无法写入第五节点N5。第一节点N1的信号为高电平信号，第二晶体管T2断开，第一时钟信号端CK的高电平信号无法写入第二节点N2，在第二电容C2的作用下，第二节点N2的信号保持为上一阶段的低电平信号，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14导通，第一电源端VGH的高电平信号写入第四晶体管T4和第五晶体管T5连接的节点、第十三晶体管T13和第十四晶体管T14的连接的节点、级联输出信号端OUT1和驱动输出信号端OUT2。第一电源端VGH的高电平信号通过导通的第十三晶体管T13写入第五节点N5，第十晶体管T10断开。
本阶段，第一节点N1、第三节点N3、第四节点N4和第五节点N5的信号均为高电平信号，第二节点N2的信号为低电平信号。级联输出信号端OUT1和驱动输出信号端OUT2的信号为高电平信号。
在信号输入端IN的信号为低电平信号之前，移位寄存器持续执行第三阶段S13和第四阶段S14。
如图20所示，图13和图14提供的移位寄存器在第二显示模式下的工作过程如下：
第一阶段S21，第一时钟信号端CK、信号输入端IN和掩蔽信号端MS为低电平信号，第二时钟信号端CB的信号为高电平信号，第一晶体管T1和第三晶体管T3导通，第五晶体管T5和第十三晶体管T13断开。
第一晶体管T1导通，信号输入端IN的低电平信号写入第一节点N1，第一节点N1的低电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7导通，第二时钟信号端CB的高电平信号写入级联输出信号端OUT1，第一节点N1或者第三节点N3的低电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12导通，第二时钟信号端CB的高电平信号写入第五节点N5，第十晶体管T10断开，掩蔽信号端MS的低电平信号无法写入驱动输出信号端OUT2。第一节点N1的信号为低电平信号，第二晶体管T2导通，第一时钟信号端CK的低电平信号写入第二节点N2，第三晶体管T3导通，第二电源端VGL的低电平信号写入第二节点N2，第二节点N2的信号为低电平信号，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14导通，第一电源端VGH的高电平信号写入第四晶体管T4和第五晶体管T5连接的节点、第十三晶体管T13和第十四晶体管T14的连接的节点、级联输出信号端OUT1和驱动输出信号端OUT2。
本阶段，第一节点N1、第二节点N2、第三节点N3、第四节点N4和第五节点N5的信号均为低电平信号。级联输出信号端OUT1和驱动输出信号端OUT2的信号为高电平信号。
第二阶段S22，第二时钟信号端CB的信号为低电平信号，第一时钟信号端CK、信号输入端IN和掩蔽信号端MS的信号为高电平信号，第一晶体管T1和第三晶体管T3断开，第五晶体管T5和第十三晶体管T13导通。
第一晶体管T1断开，信号输入端IN的高电平信号无法写入第一节点N1，第一节点N1的信号保持上一阶段的低电平信号，第一节点N1的低电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7导通，第二时钟信号端CB的低电平信号写入级联输出信号端OUT1，级联输出信号端OUT1的信号为低电平信号，在第一电容C1的作用下，第三节点N3的信号持续被拉低，第三节点N3的低电平信号通过导通的第八晶体管T8写入第一节点N1，第一节点N1持续被拉低，第一节点N1或者第三节点N3的低电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12导通，第二时钟信号端CB的低电平信号写入第五节点N5，第十晶体管T10导通，掩蔽信号端MS的高电平信号写入驱动输出信号端OUT2。第一节点N1的信号为低电平信号，第二晶体管T2导通，第一时钟信号端CK的高电平信号写入第二节点N2，第三晶体管T3断开，第二电源端VGL的低电平信号无法写入第二节点N2，第二节点N2的信号为高电平信号，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14断开，第一电源端VGH的高电平信号无法写入第四晶体管T4和第五晶体管T5连接的节点、第十三晶体管T13和第十四晶体管T14的连接的节点、级联输出信号端OUT1和驱动输出信号端OUT2。
本阶段，第一节点N1、第三节点N3、第四节点N4和第五节点N5的信号均为低电平信号，第二节点N2的信号为高电平信号。级联输出信号端OUT1的信号为低电平信号，驱动输出信号端OUT2的信号为高电平信号。
第三阶段S23，第一时钟信号端CK的信号为低电平信号，掩蔽信号端MS、信号输入端IN和第二时钟信号端CB的信号为高电平信号，第一晶体管T1和第三晶体管T3导通，第五晶体管T5和第十三晶体管T13断开。
第一晶体管T1导通，信号输入端IN的高电平信号写入第一节点N1，第一节点N1的高电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7断开，第一节点N1(或者第三节点N3的高电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12断开，第二时钟信号端CB的高电平信号无法写入第五节点N5。由于本阶段第四节点N4的信号被拉高，在第六电容C6的作用下，第五节点N5的信号同样被拉高，第五节点N5的信号为高电平信号，第十晶体管T10断开。第一节点N1的信号为高电平信号，第二晶体管T2断开，第一时钟信号端CK的低电平信号无法写入第二节点N2，第三晶体管T3导通，第二电源端VGL的低电平信号写入第二节点N2，第二节点N2的信号为低电平信号，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14导通，第一电源端VGH的高电平信号写入第四晶体管T4和第五晶体管T5连接的节点、第十三晶体管T13和第十四晶体管T14的连接的节点、级联输出信号端OUT1和驱动输出信号端OUT2。
本阶段，第一节点N1、第三节点N3、第四节点N4和第五节点N5的信号均为高电平信号，第二节点N2的信号为低电平信号，级联输出信号端OUT1和驱动输出信号端OUT2的信号为高电平信号。
第四阶段S24，第二时钟信号端CB的信号为低电平信号，第一时钟信号端CK、信号输入端IN和掩蔽信号端MS的信号为高电平信号，第一晶体管T1和第三晶体管T3断开，第五晶体管T5和第十三晶体管T13导通。
第一晶体管T1断开，第一节点N1的信号保持上一阶段的高电平信号，第一节点N1的高电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7断开，第一节点N1或者第三节点N3的高电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12断开，第二时钟信号端CB的低电平信号无法写入第五节点N5。第一节点N1的信号为高电平信号，第二晶体管T2断开，第一时钟信号端CK的高电平信号无法写入第二节点N2，在第二电容C2的作用下，第二节点N2的信号保持为上一阶段的低电平信号，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14导通，第一电源端VGH的高电平信号写入第四晶体管T4和第五晶体管T5连接的节点、第十三晶体管T13和第十四晶体管T14的连接的节点、级联输出信号端OUT1和驱动输出信号端OUT2，第一电源端VGH的高电平信号通过导通的第十三晶体管T13写入第五节点N5，第十晶体管T10断开。
本阶段，第一节点N1、第三节点N3、第四节点N4和第五节点N5的信号均为高电平信号，第二节点N2的信号为低电平信号。级联输出信号端OUT1和驱动输出信号端OUT2的信号为高电平信号。
在信号输入端IN的信号为低电平信号之前，移位寄存器持续执行第三阶段S23和第四阶段S24。
图15提供的移位寄存器与图16提供的移位寄存器提供的移位寄存器不同之处在于第十五晶体管T15的第一极连接的节点不同，图15提供的移位寄存器中第一节点N1的信号写入第四节点N4，而图16提供的移位寄存器中第三节点N3的信号写入第四节点N4。由于第十五晶体管T15持续导通，因此，第一节点N1和第三节点N3的信号相同，因此，图15提供的移位寄存器与图16提供的移位寄存器的工作过程相同。
如图19所示，图15和图16提供的移位寄存器在第一显示模式下的工作过程如下：
第一阶段S11，第一时钟信号端CK、信号输入端IN和掩蔽信号端MS为低电平信号，第二时钟信号端CB的信号为高电平信号，第一晶体管T1导通，第五晶体管T5和第十三晶体管T13断开。
第一晶体管T1导通，信号输入端IN的低电平信号写入第一节点N1，第一节点N1的低电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7导通，第二时钟信号端CB的高电平信号写入级联输出信号端OUT1，第一节点N1或者第三节点N3的低电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12导通，掩蔽信号端MS的低电平信号写入第五节点N5，第十晶体管T10导通，第二时钟信号端CB的高电平信号写入驱动输出信号端OUT2。第一节点N1的信号为低电平信号，第二晶体管T2和第九晶体管T9导通，第一电源端VGH的高电平信号通过导通的第九晶体管T9写入第三电容C3的第一端，对第三电容C3进行充电，第三晶体管T3断开，第一电源端VGH的高电平信号通过导通的第二晶体管T2写入第二节点N2，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14断开。
本阶段，第一节点N1、第三节点N3、第四节点N4和第五节点N5的信号均为低电平信号，第二节点N2的信号为高电平信号。级联输出信号端OUT1和驱动输出信号端OUT2的信号为高电平信号。
第二阶段S12，第二时钟信号端CB和掩蔽信号端MS的信号为低电平信号，信号输入端IN和第一时钟信号端CK的信号为高电平信号，第一晶体管T1断开，第五晶体管T5和第十三晶体管T13导通。
第一晶体管T1断开，使得信号输入端IN的高电平信号无法写入第一节点N1，第一节点N1的信号保持上一阶段的低电平信号，在第一电容C1的作用下，第三节点N3的信号为低电平信号，第七晶体管T7导通，第二时钟信号端CB的低电平信号写入级联输出信号端OUT1，第一节点N1或者第三节点N3的低电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12导通，掩蔽信号端MS的低电平信号写入第五节点N5，第十晶体管T10导通，第二时钟信号端CB的低电平信号写入驱动输出信号端OUT2。第一节点N1的信号为低电平信号，第二晶体管T2和第九晶体管T9导通，第一电源端VGH的高电平信号仍通过导通的第九晶体管T9写入第三电容C3的第一端，对第三电容C3进行充电，第三晶体管T3断开，第一电源端VGH的高电平信号通过导通的第二晶体管T2写入第二节点N2，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14断开。
本阶段，第一节点N1、第三节点N3、第四节点N4和第五节点N5的信号均为低电平信号，第二节点N2的信号为高电平信号。级联输出信号端OUT1和驱动输出信号端OUT2的信号为低电平信号。
第三阶段S13，第一时钟信号端CK和掩蔽信号端MS的信号为低电平信号，信号输入端IN和第二时钟信号端CB的信号为高电平信号，第一晶体管T1导通，第五晶体管T5和第十三晶体管T13断开。
第一晶体管T1导通，信号输入端IN的高电平信号写入第一节点N1，第一节点N1的高电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7断开，在第一电容C1的耦合作用下，级联输出信号端OUT的信号变为高电平信号，第一节点N1或者第三节点N3的高电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12断开，掩蔽信号端MS的低电平信号无法写入第五节点N5，在第六电容C6的耦合作用下，第五节点N5的信号变为高电平信号，第十晶体管T10断开，在第五电容C5的耦合作用下，驱动输出信号端OUT2的信号变为高电平信号。第一节点N1的信号为高电平信号，第二晶体管T2和第九晶体管T9断开，第三电容C3的第二端浮接，由于第二时钟信号端CB信号的高电平信号，在第三电容C3的耦合作用下，第三电容C3的第二端的信号为高电平信号，第三晶体管T3断开，第二电容C2进行放电，使得第二节点N2的信号保持上一阶段的高电平信号，第一电源端VGH的高电平信号无法通过导通的第二晶体管T2写入第二节点N2，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14断开。
本阶段，第一节点N1、第二节点N2、第三节点N3、第四节点N4和第五节点N5的信号均为高电平信号，级联输出信号端OUT1和驱动输出信号端OUT2的信号为高电平信号。
第四阶段S14，第二时钟信号端CB和掩蔽信号端MS的信号为低电平信号，信号输入端IN和第一时钟信号端CK的信号为高电平信号，第一晶体管T1断开，第五晶体管T5和第十三晶体管T13导通。
第一晶体管T1断开，使得信号输入端IN的高电平信号无法写入第一节点N1，第一节点N1的信号保持上一阶段的高电平信号，第一节点N1的高电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7断开，第一节点N1或者第三节点N3的高电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12断开，掩蔽信号端MS的低电平信号无法写入第五节点N5，第五节点N5保持上一阶段的高电平信号，第十晶体管T10断开。第一节点N1的信号为高电平信号，第二晶体管T2和第九晶体管T9断开，第三电容C3的第二端浮接，由于第二时钟信号端CB的信号的低电平信号，在第三电容C3的耦合作用下，第三电容C3的第二端的信号为低电平信号，第三晶体管T3导通，第二时钟信号端CB的低电平信号写入第二节点N2，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14导通，第一电源端VGH的高电平信号写入级联输出信号端OUT1、驱动输出信号端OUT2、第四晶体管T4和第五晶体管T5连接的节点和第十三晶体管T13和第十四晶体管T14连接的节点。由于第四晶体管T4和第五晶体管T5导通，第一电源端VGH的高电平信号写入第一节点N1，使得第一节点N1的信号保持为高电平信号，由于第十三晶体管T13和第十四晶体管T14导通，第一电源端VGH的高电平信号写入第五节点N5，使得第五节点N5的信号保持为高电平信号。
本阶段，第一节点N1、第三节点N3、第四节点N4和第五节点N5的信号均为高电平信号，第二节点N2的信号为低电平信号。级联输出信号端OUT1和驱动输出信号端OUT2的信号均为高电平信号。
如图20所示，图15和图16提供的移位寄存器在第二显示模式下的工作过程如下：
第一阶段S21，第一时钟信号端CK和信号输入端IN的信号为低电平信号，掩蔽信号端MS的信号在至少部分时间段为低电平信号，在至少部分时间段为高电平信号，且掩蔽信号端MS的信号为低电平信号的时间段发生在掩蔽信号端MS的信号为高电平信号的时间段之前，第二时钟信号端CB的信号为高电平信号，第一晶体管T1导通，第五晶体管T5和第十三晶体管T13断开。
第一晶体管T1导通，信号输入端IN的低电平信号写入第一节点N1，第一节点N1的低电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7导通，第二时钟信号端CB的高电平信号写入级联输出信号端OUT1，第一节点N1或者第三节点N3的低电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12导通，在掩蔽信号端MS的信号为低电平信号的时间段掩蔽信号端MS的低电平信号写入第五节点N5，第十晶体管T10导通，第二时钟信号端CB的高电平信号写入驱动输出信号端OUT2。在掩蔽信号端MS的信号为高电平信号的时间段掩蔽信号端MS的高电平信号写入第五节点N5，第十晶体管T10断开。第一节点N1的信号为低电平信号，第二晶体管T2和第九晶体管T9导通，第一电源端VGH的高电平信号通过导通的第九晶体管T9写入第三电容C3的第一端，对第三电容C3进行充电，第三晶体管T3断开，第一电源端VGH的高电平信号通过导通的第二晶体管T2写入第二节点N2，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14断开。
本阶段，第一节点N1、第三节点N3、第四节点N4和第五节点N5的信号均为低电平信号，第二节点N2的信号为高电平信号。级联输出信号端OUT1和驱动输出信号端OUT2的信号为高电平信号。
第二阶段S22，第二时钟信号端CB的信号为低电平信号，信号输入端IN、第一时钟信号端CK和掩蔽信号端MS的信号为高电平信号，第一晶体管T1断开，第五晶体管T5和第十三晶体管T13导通。
第一晶体管T1断开，使得信号输入端IN的高电平信号无法写入第一节点N1，第一节点N1的信号保持上一阶段的低电平信号，在第一电容C1的作用下，第三节点N3的信号为低电平信号，第七晶体管T7导通，第二时钟信号端CB的低电平信号写入级联输出信号端OUT1，第一节点N1或者第三节点N3的低电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12导通，掩蔽信号端MS的高电平信号写入第五节点N5，第十晶体管T10断开，第二时钟信号端CB的低电平信号无法写入驱动输出信号端OUT2，在第五电容C5的耦合作用下，驱动输出信号端OUT2的信号保持上一阶段的高电平信号。第一节点N1的信号为低电平信号，第二晶体管T2和第九晶体管T9导通，第一电源端VGH的高电平信号仍通过导通的第九晶体管T9写入第三电容C3的第一端，对第三电容C3进行充电，第三晶体管T3断开，第一电源端VGH的高电平信号通过导通的第二晶体管T2写入第二节点N2，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14断开。
本阶段，第一节点N1、第三节点N3、第四节点N4和第五节点N5的信号均为低电平信号，第二节点N2的信号为高电平信号。级联输出信号端OUT1的信号为低电平信号，驱动输出信号端OUT2浮接，且保持上一阶段的高电平信号。
第三阶段S23，第一时钟信号端CK的信号为低电平信号，信号输入端IN、第二时钟信号端CB和掩蔽信号端MS的信号为高电平信号，第一晶体管T1导通，第五晶体管T5和第十三晶体管T13断开。
第一晶体管T1导通，信号输入端IN的高电平信号写入第一节点N1，第一节点N1的高电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7断开，在第一电容C1的耦合作用下，级联输出信号端OUT的信号变为高电平信号，第一节点N1或者第三节点N3的高电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12断开，掩蔽信号端MS的高电平信号无法写入第五节点N5，在第六电容C6的耦合作用下，第五节点N5的信号变为高电平信号，第十晶体管T10断开，在第五电容C5的耦合作用下，驱动输出信号端OUT2的信号变为高电平信号。第一节点N1的信号为高电平信号，第二晶体管T2和第九晶体管T9断开，第三电容C3的第二端浮接，由于第二时钟信号端CB信号的高电平信号，在第三电容C3的耦合作用下，第三电容C3的第二端的信号为高电平信号，第三晶体管T3断开，第二电容C2进行放电，使得第二节点N2的信号保持上一阶段的高电平信号，第一电源端VGH的高电平信号无法通过导通的第二晶体管T2写入第二节点N2，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14断开。
本阶段，第一节点N1、第二节点N2、第三节点N3、第四节点N4和第五节点N5的信号均为高电平信号，级联输出信号端OUT1的信号为高电平信号，驱动输出信号端OUT2浮接，且保持上一阶段的高电平信号。
第四阶段S24，第二时钟信号端CB的信号为低电平信号，信号输入端IN、第一时钟信号端CK和掩蔽信号端MS的信号为高电平信号，第一晶体管T1断开，第五晶体管T5和第十三晶体管T13导通。
第一晶体管T1断开，使得信号输入端IN的高电平信号无法写入第一节点N1，第一节点N1的信号保持上一阶段的高电平信号，第一节点N1的高电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7断开，第一节点N1或者第三节点N3的高电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12断开，掩蔽信号端MS的高电平信号无法写入第五节点N5，第十晶体管T10断开。第一节点N1的信号为高电平信号，第二晶体管T2和第九晶体管T9断开，第三电容C3的第二端浮接，由于第二时钟信号端CB的信号的低电平信号，在第三电容C3的耦合作用下，第三电容C3的第二端的信号为低电平信号，第三晶体管T3导通，第二时钟信号端CB的低电平信号写入第二节点N2，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14导通，第一电源端VGH的高电平信号写入级联输出信号端OUT1、驱动输出信号端OUT2、第四晶体管T4和第五晶体管T5连接的节点和第十三晶体管T13和第十四晶体管T14连接的节点。由于第四晶体管T4和第五晶体管T5导通，第一电源端VGH的高电平信号写入第一节点N1，使得第一节点N1的信号保持为高电平信号，由于第十三晶体管T13和第十四晶体管T14导通，第一电源端VGH的高电平信号写入第五节点N5，使得第五节点N5的信号保持为高电平信号。
本阶段，第一节点N1、第三节点N3、第四节点N4和第五节点N5的信号均为高电平信号，第二节点N2的信号为低电平信号。级联输出信号端OUT1和驱动输出信号端OUT2的信号均为高电平信号。
图17提供的移位寄存器与图18提供的移位寄存器提供的移位寄存器不同之处在于第十五晶体管T15的第一极连接的节点不同，图17提供的移位寄存器中第一节点N1的信号写入第四节点N4，而图18提供的移位寄存器中第三节点N3的信号写入第四节点N4。由于第十五晶体管T15持续导通，因此，第一节点N1和第三节点N3的信号相同，因此，图17提供的移位寄存器与图18提供的移位寄存器的工作过程相同。
如图20所示，图17和图18提供的移位寄存器在第一显示模式下的工作过程如下：
第一阶段S11，第一时钟信号端CK、信号输入端IN和掩蔽信号端MS为低电平信号，第二时钟信号端CB的信号为高电平信号，第一晶体管T1导通，第五晶体管T5和第十三晶体管T13断开。
第一晶体管T1导通，信号输入端IN的低电平信号写入第一节点N1，第一节点N1的低电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7导通，第二时钟信号端CB的高电平信号写入级联输出信号端OUT1，第一节点N1或者第三节点N3的低电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12导通，第二时钟信号端CB的高电平信号写入第五节点N5，第十晶体管T10断开，掩蔽信号端MS的低电平信号无法写入驱动输出信号端OUT2。第一节点N1的信号为低电平信号，第二晶体管T2和第九晶体管T9导通，第一电源端VGH的高电平信号通过导通的第九晶体管T9写入第三电容C3的第一端，对第三电容C3进行充电，第三晶体管T3断开，第一电源端VGH的高电平信号通过导通的第二晶体管T2写入第二节点N2，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14断开。
本阶段，第一节点N1、第三节点N3和第四节点N4的信号均为低电平信号，第二节点N2和第五节点N5的信号为高电平信号。级联输出信号端OUT1的信号为高电平信号，驱动输出信号端OUT2浮接，且维持上一阶段的高电平信号。
第二阶段S12，第二时钟信号端CB和掩蔽信号端MS的信号为低电平信号，信号输入端IN和第一时钟信号端CK的信号为高电平信号，第一晶体管T1断开，第五晶体管T5和第十三晶体管T13导通。
第一晶体管T1断开，使得信号输入端IN的高电平信号无法写入第一节点N1，第一节点N1的信号保持上一阶段的低电平信号，在第一电容C1的作用下，第三节点N3的信号为低电平信号，第三节点N3的信号为低电平信号，第七晶体管T7导通，第二时钟信号端CB的低电平信号写入级联输出信号端OUT1，级联输出信号端OUT1的信号为低电平信号，第一节点N1或者第三节点N3的低电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12导通，第二时钟信号端CB的低电平信号写入第五节点N5，第十晶体管T10导通，掩蔽信号端MS的低电平信号写入驱动输出信号端OUT2。第一节点N1的信号为低电平信号，第二晶体管T2和第九晶体管T9持续导通，第一电源端VGH的高电平信号通过导通的第九晶体管T9写入第三电容C3的第一端，对第三电容C3进行充电，第三晶体管T3断开，第一电源端VGH的高电平信号通过导通的第二晶体管T2写入第二节点N2，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14断开。
本阶段，第一节点N1、第三节点N3、第四节点N4和第五节点N5的信号均为低电平信号，第二节点N2的信号为高电平信号。级联输出信号端OUT1和驱动输出信号端OUT2的信号为低电平信号。
第三阶段S13，第一时钟信号端CK和掩蔽信号端MS的信号为低电平信号，信号输入端IN和第二时钟信号端CB的信号为高电平信号，第一晶体管T1导通，第五晶体管T5和第十三晶体管T13断开。
第一晶体管T1导通，信号输入端IN的高电平信号写入第一节点N1，第一节点N1的高电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7断开，在第一电容C1的耦合作用下，级联输出信号端OUT的信号变为高电平信号，第一节点N1或者第三节点N3的高电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12断开，第二时钟信号端CB的高电平信号无法写入第五节点N5，在第六电容C6的耦合作用下，第五节点N5的信号变为高电平信号，第十晶体管T10断开，在第五电容C5的耦合作用下，驱动输出信号端OUT2的信号变为高电平信号。第一节点N1的信号为高电平信号，第二晶体管T2和第九晶体管T9断开，第三电容C3的第二端浮接，由于第二时钟信号端CB信号的高电平信号，在第三电容C3的耦合作用下，第三电容C3的第二端的信号为高电平信号，第三晶体管T3断开，第二电容C2进行放电，使得第二节点N2的信号保持上一阶段的高电平信号，第一电源端VGH的高电平信号无法通过导通的第二晶体管T2写入第二节点N2，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14断开。
本阶段，第一节点N1、第二节点N2、第三节点N3、第四节点N4和第五节点N5的信号均为高电平信号，级联输出信号端OUT1浮接，且保持上一阶段的高电平信号，驱动输出信号端OUT2浮接，且保持上一阶段的高电平信号。
第四阶段S14，第二时钟信号端CB和掩蔽信号端MS的信号为低电平信号，信号输入端IN和第一时钟信号端CK的信号为高电平信号，第一晶体管T1断开，第五晶体管T5和第十三晶体管T13导通。
第一晶体管T1断开，使得信号输入端IN的高电平信号无法写入第一节点N1，第一节点N1的信号保持上一阶段的高电平信号，第一节点N1的高电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7断开，第一电容C1放电，级联输出信号端OUT1的信号为高电平信号，第一节点N1或者第三节点N3的高电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12断开，第二时钟信号端CB的低电平信号无法写入第五节点N5，第五节点N5保持上一阶段的高电平信号，第十晶体管T10断开。第一节点N1的信号为高电平信号，第二晶体管T2和第九晶体管T9断开，第三电容C3的第二端浮接，由于第二时钟信号端CB的信号的低电平信号，在第三电容C3的耦合作用下，第三电容C3的第二端的信号为低电平信号，第三晶体管T3导通，第二时钟信号端CB的低电平信号写入第二节点N2，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14导通，第一电源端VGH的高电平信号写入级联输出信号端OUT1、驱动输出信号端OUT2、第四晶体管T4和第五晶体管T5连接的节点和第十三晶体管T13和第十四晶体管T14连接的节点。由于第四晶体管T4和第五晶体管T5导通，第一电源端VGH的高电平信号写入第一节点N1，使得第一节点N1的信号保持为高电平信号，由于第十三晶体管T13和第十四晶体管T14导通，第一电源端VGH的高电平信号写入第五节点N5，使得第五节点N5的信号保持为高电平信号。
本阶段，第一节点N1、第三节点N3、第四节点N4和第五节点N5的信号均为高电平信号，第二节点N2的信号为低电平信号。级联输出信号端OUT1浮接，且保持上一阶段的高电平信号，驱动输出信号端OUT2浮接，且保持上一阶段的高电平信号。
如图20所示，图17和图18提供的移位寄存器在第二显示模式下的工作过程如下：
第一阶段S21，第一时钟信号端CK和信号输入端IN为低电平信号，掩蔽信号端MS的信号在至少部分时间段为低电平信号，在至少部分时间段为高电平信号，且掩蔽信号端MS的信号为低电平信号的时间段发生在掩蔽信号端MS的信号为高电平信号的时间段之前，第二时钟信号端CB的信号为高电平信号，第一晶体管T1导通，第五晶体管T5和第十三晶体管T13断开。
第一晶体管T1导通，信号输入端IN的低电平信号写入第一节点N1，第一节点N1的低电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7导通，第二时钟信号端CB的高电平信号写入级联输出信号端OUT1，第一节点N1或者第三节点N3的低电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12导通，第二时钟信号端CB的高电平信号写入第五节点N5，第十晶体管T10断开，掩蔽信号端MS的低电平信号无法写入驱动输出信号端OUT2。第一节点N1的信号为低电平信号，第二晶体管T2和第九晶体管T9导通，第一电源端VGH的高电平信号通过导通的第九晶体管T9写入第三电容C3的第一端，对第三电容C3进行充电，第三晶体管T3断开，第一电源端VGH的高电平信号通过导通的第二晶体管T2写入第二节点N2，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14断开。
本阶段，第一节点N1、第三节点N3、第四节点N4的信号均为低电平信号，第二节点N2和第五节点N5的信号为高电平信号。级联输出信号端OUT1的信号为高电平信号，驱动输出信号端OUT2浮接，且保持上一阶段的高电平信号。
第二阶段S22，第二时钟信号端CB的信号为低电平信号，信号输入端IN、第一时钟信号端CK和掩蔽信号端MS的信号为高电平信号，第一晶体管T1断开，第五晶体管T5和第十三晶体管T13导通。
第一晶体管T1断开，使得信号输入端IN的高电平信号无法写入第一节点N1，第一节点N1的信号保持上一阶段的低电平信号，在第一电容C1的作用下，第三节点N3的信号为低电平信号，第七晶体管T7导通，第二时钟信号端CB的低电平信号写入级联输出信号端OUT1，级联输出信号端OUT1的信号为低电平信号，第三节点N3的低电平信号通过导通的第八晶体管T8写入第一节点N1，第一节点N1或者第三节点N3的低电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12导通，第二时钟信号端CB的低电平信号写入第五节点N5，第十晶体管T10导通，掩蔽信号端MS的高电平信号写入驱动输出信号端OUT2。第一节点N1的信号为低电平信号，第二晶体管T2和第九晶体管T9导通，第一电源端VGH的高电平信号通过导通的第九晶体管T9写入第三电容C3的第一端，对第三电容C3进行充电，第三晶体管T3断开，第一电源端VGH的高电平信号通过导通的第二晶体管T2写入第二节点N2，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14断开。
本阶段，第一节点N1、第三节点N3、第四节点N4和第五节点N5的信号均为低电平信号，第二节点N2的信号为高电平信号。级联输出信号端OUT1的信号为低电平信号，驱动输出信号端OUT2的信号为高电平信号。
第三阶段S23，第一时钟信号端CK的信号为低电平信号，信号输入端IN、第二时钟信号端CB和掩蔽信号端MS的信号为高电平信号，第一晶体管T1导通，第五晶体管T5和第十三晶体管T13断开。
第一晶体管T1导通，信号输入端IN的高电平信号写入第一节点N1，第一节点N1的高电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7断开，在第一电容C1的耦合作用下，级联输出信号端OUT的信号变为高电平信号，第一节点N1或者第三节点N3的高电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12断开，第二时钟信号端CB的高电平信号无法写入第五节点N5，在第六电容C6的耦合作用下，第五节点N5的信号变为高电平信号，第十晶体管T10断开，掩蔽信号端MS的高电平信号无法写入驱动输出信号端OUT2，在第五电容C5的耦合作用下，驱动输出信号端OUT2的信号变为高电平信号。第一节点N1的信号为高电平信号，第二晶体管T2和第九晶体管T9断开，第三电容C3的第二端浮接，由于第二时钟信号端CB信号的高电平信号，在第三电容C3的耦合作用下，第三电容C3的第二端的信号为高电平信号，第三晶体管T3断开，第二电容C2进行放电，使得第二节点N2的信号保持上一阶段的高电平信号，第一电源端VGH的高电平信号无法通过导通的第二晶体管T2写入第二节点N2，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14断开。
本阶段，第一节点N1、第二节点N2、第三节点N3、第四节点N4和第五节点N5的信号均为高电平信号，级联输出信号端OUT1的信号为高电平信号，驱动输出信号端OUT2浮接，且保持上一阶段的高电平信号。
第四阶段S24，第二时钟信号端CB的信号为低电平信号，信号输入端IN、第一时钟信号端CK和掩蔽信号端MS的信号为高电平信号，第一晶体管T1断开，第五晶体管T5和第十三晶体管T13导通。
第一晶体管T1断开，使得信号输入端IN的高电平信号无法写入第一节点N1，第一节点N1的信号保持上一阶段的高电平信号，第一节点N1的高电平信号通过导通的第八晶体管T8写入第三节点N3，第七晶体管T7断开，第二时钟信号端CB的低电平信号无法写入级联输出信号端OUT1，第一节点N1或者第三节点N3的高电平信号通过导通的第十五晶体管T15写入第四节点N4，第十二晶体管T12断开，第二时钟信号端CB的低电平信号无法写入第五节点N5，第十晶体管T10断开。第一节点N1的信号为高电平信号，第二晶体管T2和第九晶体管T9断开，第三电容C3的第二端浮接，由于第二时钟信号端CB的信号的低电平信号，在第三电容C3的耦合作用下，第三电容C3的第二端的信号为低电平信号，第三晶体管T3导通，第二时钟信号端CB的低电平信号写入第二节点N2，第四晶体管T4、第六晶体管T6、第十一晶体管T11和第十四晶体管T14导通，第一电源端VGH的高电平信号写入级联输出信号端OUT1、驱动输出信号端OUT2、第四晶体管T4和第五晶体管T5连接的节点和第十三晶体管T13和第十四晶体管T14连接的节点。由于第四晶体管T4和第五晶体管T5导通，第一电源端VGH的高电平信号写入第一节点N1，使得第一节点N1的信号保持为高电平信号，由于第十三晶体管T13和第十四晶体管T14导通，第一电源端VGH的高电平信号写入第五节点N5，使得第五节点N5的信号保持为高电平信号。
本阶段，第一节点N1、第三节点N3、第四节点N4和第五节点N5的信号均为高电平信号，第二节点N2的信号为低电平信号。级联输出信号端OUT1和驱动输出信号端OUT2的信号为高电平信号。
本公开实施例还提供了一种移位寄存器的驱动方法，被配置为驱动前述任一个实施例提供的移位寄存器，方法包括：
级联输出子电路在信号输入端、第一时钟信号端、第二时钟信号端和第二电源端的信号的控制下，向级联输出信号端提供第一电源端或者第二时钟信号端的信号。
节点控制子电路在级联输出子电路、第一电源端、第二电源端和第一控制输入信号端的信号的控制下，向驱动输出子电路提供信号。
驱动输出子电路在级联输出子电路和节点控制子电路的信号的控制下，向驱动输出信号端提供第一电源端或者第二控制输入信号端的信号。
本公开实施例还提供了一种栅极驱动电路，包括：多个前述任一个实施例提供的移位寄存器。
在示例性实施方式中，至少一级移位寄存器的级联输出信号端与至少一级移位寄存器的信号输入端电连接。
本公开实施例还提供了一种显示装置，包括：前述任一个实施例提供的栅极驱动电路。
在示例性实施方式中，显示装置还可以包括：阵列排布的子像素、多条第一扫描信号线和多条数据信号线。至少一个子像素包括：图2A和图2B提供的像素驱动电路，至少一个子像素的像素驱动电路包括：写入晶体管，写入晶体管分别与第一扫描信号线和数据信号线电连接。
在示例性实施方式中，至少一级移位寄存器的驱动输出信号端与至少一个像素驱动电路所连接的第一扫描信号线电连接。即本公开中的移位寄存器的驱动输出信号端输出的信号被配置为控制写入晶体管是否导通，以控制数据信号线的数据电压写入像素驱动电路中。
在示例性实施方式中，显示装置还可以包括：还包括：多条第二复位信号线和多条第二初始信号线，至少一个子像素还分别与第二复位信号线和第二初始信号线电连接。至少一个子像素的像素驱动电路还包括：阳极复位晶体管，阳极复位晶体管分别与所在子像素连接的所述第二复位信号线和所述第二初始信号线电连接。
至少一级移位寄存器的驱动输出信号端与至少一行像素驱动电路所连接的第二复位信号线电连接。
在示例性实施方式中，至少一行像素驱动电路所连接的第一扫描信号线和第二复位信号线独立设置，或者至少一行像素驱动电路所连接的第二复位信号线与下一行像素驱动电路所连接的第一扫描信号线为同一信号线。图2A是以至少一行像素驱动电路所连接的第一扫描信号线和第二复位信号线独立设置为例进行说明的，图2B是至少一行像素驱动电路所连接的第二复位信号线与下一行像素驱动电路所连接的第一扫描信号线为同一信号线为例进行说明的。
至少一级移位寄存器的驱动输出信号端与至少一行像素驱动电路所连接的第一扫描信号线电连接。
在示例性实施方式中，本公开提供的显示基板可以为应用于具有像素驱动电路的显示装置中，如OLED、量子点显示(QLED)、发光二极管显示(Micro LED或Mini LED)或量子点发光二极管显示(QDLED)等，本公开在此不做限定。
本公开实施例附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (25)

  1. 一种移位寄存器，包括：级联输出子电路、驱动输出子电路和节点控制子电路；
    所述级联输出子电路，分别与信号输入端、第一时钟信号端、第二时钟信号端、第一电源端、第二电源端和级联输出信号端电连接，被配置为在信号输入端、第一时钟信号端、第二时钟信号端和第二电源端的信号的控制下，向级联输出信号端提供第一电源端或者第二时钟信号端的信号；
    所述节点控制子电路，分别与所述级联输出子电路、所述驱动输出子电路、第一电源端、第二电源端和第一控制输入信号端电连接，被配置为在所述级联输出子电路、第一电源端、第二电源端和第一控制输入信号端的信号的控制下，向驱动输出子电路提供信号；
    所述驱动输出子电路，分别与所述级联输出子电路、所述节点控制子电路、第一电源端、第二控制输入信号端和驱动输出信号端电连接，被配置为在级联输出子电路和节点控制子电路的信号的控制下，向驱动输出信号端提供第一电源端或者第二控制输入信号端的信号；
    所述第一控制输入信号端包括：第二时钟信号端，所述第二控制输入信号端包括：掩蔽信号端，或者，所述第一控制输入信号端包括：第二时钟信号端和掩蔽信号端，所述第二控制输入信号端包括：第二时钟信号端。
  2. 根据权利要求1所述的移位寄存器，其中，所述移位寄存器设置在显示装置中，所述显示装置所显示内容包括多个显示帧，所述显示装置的显示模式包括：第一显示模式和第二显示模式，所述第一显示模式的刷新率大于所述第二显示模式的刷新率；
    在所述第一显示模式下，移位寄存器的级联输出信号端的信号和驱动输出信号端的信号相同；
    在所述第二显示模式下，移位寄存器的级联输出信号端的信号和驱动输出信号端的信号在至少部分时间互为反相信号。
  3. 根据权利要求1所述的移位寄存器，其中，所述级联输出子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第一电容和第二电容；
    第一晶体管的控制极与第一时钟信号端电连接，第一晶体管的第一极与信号输入端电连接，第一晶体管的第二极与第一节点电连接；
    第二晶体管的控制极与第一节点电连接，第二晶体管的第一极与第一时钟信号端电连接，第二晶体管的第二极与第二节点电连接；
    第三晶体管的控制极与第一时钟信号端电连接，第三晶体管的第一极与第二电源端电连接，第三晶体管的第二极与第二节点电连接；
    第四晶体管的控制极与第二节点电连接，第四晶体管的第一极与第一电源端电连接，第四晶体管的第二极与第五晶体管的第一极电连接；
    第五晶体管的控制极与第二时钟信号端电连接，第五晶体管的第二极与第一节点电连接；
    第六晶体管的控制极与第二节点电连接，第六晶体管的第一极与第一电源端电连接，第六晶体管的第二极与级联输出信号端电连接；
    第七晶体管的控制极与第三节点电连接，第七晶体管的第一极与第二时钟信号端电连接，第七晶体管的第二极与级联输出信号端电连接；
    第八晶体管的控制极与第二电源端电连接，第八晶体管的第一极与第一节点电连接，第八晶体管的第二极与第三节点电连接；
    第一电容的第一端与第三节点电连接，第一电容的第二端与级联输出信号端电连接；
    第二电容的第一端与第二节点电连接，第二电容的第二端与第一电源端电连接。
  4. 根据权利要求1所述的移位寄存器，其中，所述级联输出子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第一电容、第二电容和第三电容；
    第一晶体管的控制极与第一时钟信号端电连接，第一晶体管的第一极与信号输入端电连接，第一晶体管的第二极与第一节点电连接；
    第二晶体管的控制极与第一节点电连接，第二晶体管的第一极与第二电源端电连接，第二晶体管的第二极与第二节点电连接；
    第三晶体管的控制极与第三电容的第一端电连接，第三晶体管的第一极与第二时钟信号端电连接，第三晶体管的第二极与第二节点电连接；
    第四晶体管的控制极与第二节点电连接，第四晶体管的第一极与第二电源端电连接，第四晶体管的第二极与第五晶体管的第一极电连接；
    第五晶体管的控制极与第二时钟信号端电连接，第五晶体管的第二极与第一节点电连接；
    第六晶体管的控制极与第二节点电连接，第六晶体管的第一极与第一电源端电连接，第六晶体管的第二极与级联输出信号端电连接；
    第七晶体管的控制极与第三节点电连接，第七晶体管的第一极与第二时钟信号端电连接，第七晶体管的第二极与级联输出信号端电连接；
    第八晶体管的控制极与第二电源端电连接，第八晶体管的第一极与第一节点电连接，第八晶体管的第二极与第三节点电连接；
    第九晶体管的控制极与第一节点电连接，第九晶体管的第一极与第二电源端电连接，第九晶体管的第二极与第三电容的第一端电连接；
    第一电容的第一端与第三节点电连接，第一电容的第二端与级联输出信号端电连接；
    第二电容的第一端与第二节点电连接，第二电容的第二端与第一电源端电连接；
    第三电容的第二端与第二时钟信号端电连接。
  5. 根据权利要求3或4所述的移位寄存器，其中，所述级联输出子电路还包括：第四电容；
    第四电容的第一端与第一电源端电连接，第四电容的第二端与级联输出信号端电连接。
  6. 根据权利要求1所述的移位寄存器，其中，所述第一控制输入信号端包括：第二时钟信号端和掩蔽信号端，所述第二控制输入信号端包括：第二时钟信号端；
    所述级联输出子电路中设置有第一节点、第二节点和第三节点；
    所述节点控制子电路，分别与所述第一节点、所述第二节点、掩蔽信号端、第二时钟信号端、第一电源端、第二电源端和第五节点电连接，被配置为在第一节点、第二节点、掩蔽信号端、第二时钟信号端和第二电源端的信号的控制下，向第五节点提供第一电源端或者掩蔽信号端的信号；
    所述驱动输出子电路，分别与所述第二节点、所述第五节点、第二时钟信号端、第一电源端和驱动输出信号端电连接，被配置为在第二节点和第五节点的信号的控制下，向驱动输出信号端提供第一电源端或者第二时钟信号端的信号。
  7. 根据权利要求6所述的移位寄存器，其中，所述驱动输出子电路包括：第十晶体管、第十一晶体管和第五电容，所述节点控制子电路包括：第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管和第六电容；
    第十晶体管的控制极与第五节点电连接，第十晶体管的第一极与第二时钟信号端电连接，第十晶体管的第二极与驱动输出信号端电连接；
    第十一晶体管的控制极与第二节点电连接，第十一晶体管的第一极与第一电源端电连接，第十一晶体管的第二极与驱动输出信号端电连接；
    第十二晶体管的控制极与第四节点电连接，第十二晶体管的第一极与掩蔽信号端电连接，第十二晶体管的第二极与第五节点电连接；
    第十三晶体管的控制极与第二时钟信号端电连接，第十三晶体管的第一极与第十四晶体管的第二极电连接，第十三晶体管的第二极与第五节点电连接；
    第十四晶体管的控制极与第二节点电连接，第十四晶体管的第一极与第一电源端电连接；
    第十五晶体管的控制极与第二电源端电连接，第十五晶体管的第一极与第一节点电连接，第十五晶体管的第二极与第四节点电连接；
    第五电容的第一端与第五节点电连接，第五电容的第二端与驱动输出信号端电连接；
    第六电容的第一端与第四节点电连接，第六电容的第二端与第五节点电连接。
  8. 根据权利要求1所述的移位寄存器，其中，所述第一控制输入信号端包括：第二时钟信号端，所述第二控制输入信号端包括：掩蔽信号端；
    所述级联输出子电路中设置有第一节点、第二节点和第三节点；
    所述节点控制子电路，分别与所述第一节点、所述第二节点、第二时钟信号端、第一电源端、第二电源端和第五节点电连接，被配置为在第一节点、第二节点、第二时钟信号端和第二电源端的信号的控制下，向第五节点提供第一电源端或者第二时钟信号端的信号；
    所述驱动输出子电路，分别与所述第二节点、所述第五节点、第一电源端、掩蔽信号端和驱动输出信号端电连接，被配置为在被配置为在第二节点和第五节点的信号的控制下，向驱动输出信号端提供第一电源端或者掩蔽信号端的信号。
  9. 根据权利要求8所述的移位寄存器，其中，所述驱动输出子电路包括：第十晶体管、第十一晶体管和第五电容，所述节点控制子电路包括：第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管和第六电容；
    第十晶体管的控制极与第五节点电连接，第十晶体管的第一极与掩蔽信号端电连接，第十晶体管的第二极与驱动输出信号端电连接；
    第十一晶体管的控制极与第二节点电连接，第十一晶体管的第一极与第一电源端电连接，第十一晶体管的第二极与驱动输出信号端电连接；
    第十二晶体管的控制极与第四节点电连接，第十二晶体管的第一极与第二时钟信号端电连接，第十二晶体管的第二极与第五节点电连接；
    第十三晶体管的控制极与第二时钟信号端电连接，第十三晶体管的第一极与第十四晶体管的第二极电连接，第十三晶体管的第二极与第五节点电连接；
    第十四晶体管的控制极与第二节点电连接，第十四晶体管的第一极与第一电源端电连接；
    第十五晶体管的控制极与第二电源端电连接，第十五晶体管的第一极与第一节点电连接，第十五晶体管的第二极与第四节点电连接；
    第五电容的第一端与第五节点电连接，第五电容的第二端与驱动输出信号端电连接；
    第六电容的第一端与第四节点电连接，第六电容的第二端与第五节点电连接。
  10. 根据权利要求1所述的移位寄存器，其中，所述第一控制输入信号端包括：第二时钟信号端和掩蔽信号端，所述第二控制输入信号端包括：第二时钟信号端；
    所述级联输出子电路中设置有第一节点、第二节点和第三节点；
    所述节点控制子电路，分别与所述第二节点、所述第三节点、掩蔽信号端、第二时钟信号端、第一电源端、第二电源端和第五节点电连接，被配置为在第二节点、第三节点、掩蔽信号端、第二时钟信号端和第二电源端的信号的控制下，向第五节点提供第一电源端或者掩蔽信号端的信号；
    所述驱动输出子电路，分别与所述第二节点、所述第五节点、第二时钟信号端、第一电源端和驱动输出信号端电连接，被配置为在第二节点和第五节点的信号的控制下，向驱动输出信号端提供第一电源端或者第二时钟信号端的信号。
  11. 根据权利要求10所述的移位寄存器，其中，所述驱动输出子电路包括：第十晶体管、第十一晶体管和第五电容，所述节点控制子电路包括：第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管和第六电容；
    第十晶体管的控制极与第五节点电连接，第十晶体管的第一极与第二时钟信号端电连接，第十晶体管的第二极与驱动输出信号端电连接；
    第十一晶体管的控制极与第二节点电连接，第十一晶体管的第一极与第一电源端电连接，第十一晶体管的第二极与驱动输出信号端电连接；
    第十二晶体管的控制极与第四节点电连接，第十二晶体管的第一极与掩蔽信号端电连接，第十二晶体管的第二极与第五节点电连接；
    第十三晶体管的控制极与第二时钟信号端电连接，第十三晶体管的第一极与第十四晶体管的第二极电连接，第十三晶体管的第二极与第五节点电连接；
    第十四晶体管的控制极与第二节点电连接，第十四晶体管的第一极与第一电源端电连接；
    第十五晶体管的控制极与第二电源端电连接，第十五晶体管的第一极与第三节点电连接，第十五晶体管的第二极与第四节点电连接；
    第五电容的第一端与第五节点电连接，第五电容的第二端与驱动输出信号端电连接；
    第六电容的第一端与第四节点电连接，第六电容的第二端与第五节点电连接。
  12. 根据权利要求1所述的移位寄存器，其中，所述第一控制输入信号端包括：第二时钟信号端，所述第二控制输入信号端包括：掩蔽信号端；
    所述级联输出子电路中设置有第一节点、第二节点和第三节点；
    所述节点控制子电路，分别与所述第二节点、所述第三节点、第二时钟信号端、第一电源端、第二电源端和第五节点电连接，被配置为在第二节点、第三节点、第二时钟信号端和第二电源端的信号的控制下，向第五节点提供第一电源端或者第二时钟信号端的信号；
    所述驱动输出子电路，分别与所述第二节点、所述第五节点、第一电源端、掩蔽信号端和驱动输出信号端电连接，被配置为在被配置为在第二节点和第五节点的信号的控制下，向驱动输出信号端提供第一电源端或者掩蔽信号端的信号。
  13. 根据权利要求12所述的移位寄存器，其中，所述驱动输出子电路包括：第十晶体管、第十一晶体管和第五电容，所述节点控制子电路包括：第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管和第六电容；
    第十晶体管的控制极与第五节点电连接，第十晶体管的第一极与掩蔽信号端电连接，第十晶体管的第二极与驱动输出信号端电连接；
    第十一晶体管的控制极与第二节点电连接，第十一晶体管的第一极与第一电源端电连接，第十一晶体管的第二极与驱动输出信号端电连接；
    第十二晶体管的控制极与第四节点电连接，第十二晶体管的第一极与第二时钟信号端电连接，第十二晶体管的第二极与第五节点电连接；
    第十三晶体管的控制极与第二时钟信号端电连接，第十三晶体管的第一极与第十四晶体管的第二极电连接，第十三晶体管的第二极与第五节点电连接；
    第十四晶体管的控制极与第二节点电连接，第十四晶体管的第一极与第一电源端电连接；
    第十五晶体管的控制极与第二电源端电连接，第十五晶体管的第一极与第三节点电连接，第十五晶体管的第二极与第四节点电连接；
    第五电容的第一端与第五节点电连接，第五电容的第二端与驱动输出信号端电连接；
    第六电容的第一端与第四节点电连接，第六电容的第二端与第五节点电连接。
  14. 根据权利要求1所述的移位寄存器，其中，所述级联输出子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第一电容和第二电容，所述驱动输出子电路包括：第十晶体管、第十一晶体管和第五电容；所述节点控制子电路包括：第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管和第六电容；
    第一晶体管的控制极与第一时钟信号端电连接，第一晶体管的第一极与信号输入端电连接，第一晶体管的第二极与第一节点电连接；
    第二晶体管的控制极与第一节点电连接，第二晶体管的第一极与第一时钟信号端电连接，第二晶体管的第二极与第二节点电连接；
    第三晶体管的控制极与第一时钟信号端电连接，第三晶体管的第一极与第二电源端电连接，第三晶体管的第二极与第二节点电连接；
    第四晶体管的控制极与第二节点电连接，第四晶体管的第一极与第一电源端电连接，第四晶体管的第二极与第五晶体管的第一极电连接；
    第五晶体管的控制极与第二时钟信号端电连接，第五晶体管的第二极与第一节点电连接；
    第六晶体管的控制极与第二节点电连接，第六晶体管的第一极与第一电源端电连接，第六晶体管的第二极与级联输出信号端电连接；
    第七晶体管的控制极与第三节点电连接，第七晶体管的第一极与第二时钟信号端电连接，第七晶体管的第二极与级联输出信号端电连接；
    第八晶体管的控制极与第二电源端电连接，第八晶体管的第一极与第一节点电连接，第八晶体管的第二极与第三节点电连接；
    第十晶体管的控制极与第五节点电连接，第十晶体管的第一极与掩蔽信号端和第二时钟信号端的其中一个信号端电连接，第十晶体管的第二极与驱动输出信号端电连接；
    第十一晶体管的控制极与第二节点电连接，第十一晶体管的第一极与第一电源端电连接，第十一晶体管的第二极与驱动输出信号端电连接；
    第十二晶体管的控制极与第四节点电连接，第十二晶体管的第一极与掩蔽信号端和第二时钟信号端中的另一个信号端电连接，第十二晶体管的第二极与第五节点电连接；
    第十三晶体管的控制极与第二时钟信号端电连接，第十三晶体管的第一极与第十四晶体管的第二极电连接，第十三晶体管的第二极与第五节点电连接；
    第十四晶体管的控制极与第二节点电连接，第十四晶体管的第一极与第一电源端电连接；
    第十五晶体管的控制极与第二电源端电连接，第十五晶体管的第一极与第一节点和第三节点中的其中一个节点电连接，第十五晶体管的第二极与第四节点电连接；
    第一电容的第一端与第三节点电连接，第一电容的第二端与级联输出信号端电连接；
    第二电容的第一端与第二节点电连接，第二电容的第二端与第一电源端电连接；
    第五电容的第一端与第五节点电连接，第五电容的第二端与驱动输出信号端电连接；
    第六电容的第一端与第四节点电连接，第六电容的第二端与第五节点电连接。
  15. 根据权利要求1所述的移位寄存器，其中，所述级联输出子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第一电容、第二电容和第四电容，所述驱动输出子电路包括：第十晶体管、第十一晶体管和第五电容，所述节点控制子电路包括：第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管和第六电容；
    第一晶体管的控制极与第一时钟信号端电连接，第一晶体管的第一极与信号输入端电连接，第一晶体管的第二极与第一节点电连接；
    第二晶体管的控制极与第一节点电连接，第二晶体管的第一极与第一时钟信号端电连接，第二晶体管的第二极与第二节点电连接；
    第三晶体管的控制极与第一时钟信号端电连接，第三晶体管的第一极与第二电源端电连接，第三晶体管的第二极与第二节点电连接；
    第四晶体管的控制极与第二节点电连接，第四晶体管的第一极与第一电源端电连接，第四晶体管的第二极与第五晶体管的第一极电连接；
    第五晶体管的控制极与第二时钟信号端电连接，第五晶体管的第二极与第一节点电连接；
    第六晶体管的控制极与第二节点电连接，第六晶体管的第一极与第一电源端电连接，第六晶体管的第二极与级联输出信号端电连接；
    第七晶体管的控制极与第三节点电连接，第七晶体管的第一极与第二时钟信号端电连接，第七晶体管的第二极与级联输出信号端电连接；
    第八晶体管的控制极与第二电源端电连接，第八晶体管的第一极与第一节点电连接，第八晶体管的第二极与第三节点电连接；
    第十晶体管的控制极与第五节点电连接，第十晶体管的第一极与掩蔽信号端和第二时钟信号端的其中一个信号端电连接，第十晶体管的第二极与驱动输出信号端电连接；
    第十一晶体管的控制极与第二节点电连接，第十一晶体管的第一极与第一电源端电连接，第十一晶体管的第二极与驱动输出信号端电连接；
    第十二晶体管的控制极与第四节点电连接，第十二晶体管的第一极与掩蔽信号端和第二时钟信号端中的另一个信号端电连接，第十二晶体管的第二极与第五节点电连接；
    第十三晶体管的控制极与第二时钟信号端电连接，第十三晶体管的第一极与第十四晶体管的第二极电连接，第十三晶体管的第二极与第五节点电连接；
    第十四晶体管的控制极与第二节点电连接，第十四晶体管的第一极与第一电源端电连接；
    第十五晶体管的控制极与第二电源端电连接，第十五晶体管的第一极与第一节点和第三节点中的其中一个节点电连接，第十五晶体管的第二极与第四节点电连接；
    第一电容的第一端与第三节点电连接，第一电容的第二端与级联输出信号端电连接；
    第二电容的第一端与第二节点电连接，第二电容的第二端与第一电源端电连接；
    第四电容的第一端与第一电源端电连接，第四电容的第二端与级联输出信号端电连接；
    第五电容的第一端与第五节点电连接，第五电容的第二端与驱动输出信号端电连接；
    第六电容的第一端与第四节点电连接，第六电容的第二端与第五节点电连接。
  16. 根据权利要求1所述的移位寄存器，其中，所述级联输出子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第一电容、第二电容和第三电容，所述驱动输出子电路包括：第十晶体管、第十一晶体管和第五电容，所述节点控制子电路包括：第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管和第六电容；
    第一晶体管的控制极与第一时钟信号端电连接，第一晶体管的第一极与信号输入端电连接，第一晶体管的第二极与第一节点电连接；
    第二晶体管的控制极与第一节点电连接，第二晶体管的第一极与第二电源端电连接，第二晶体管的第二极与第二节点电连接；
    第三晶体管的控制极与第三电容的第一端电连接，第三晶体管的第一极与第二时钟信号端电连接，第三晶体管的第二极与第二节点电连接；
    第四晶体管的控制极与第二节点电连接，第四晶体管的第一极与第二电源端电连接，第四晶体管的第二极与第五晶体管的第一极电连接；
    第五晶体管的控制极与第二时钟信号端电连接，第五晶体管的第二极与第一节点电连接；
    第六晶体管的控制极与第二节点电连接，第六晶体管的第一极与第一电源端电连接，第六晶体管的第二极与级联输出信号端电连接；
    第七晶体管的控制极与第三节点电连接，第七晶体管的第一极与第二时钟信号端电连接，第七晶体管的第二极与级联输出信号端电连接；
    第八晶体管的控制极与第二电源端电连接，第八晶体管的第一极与第一节点电连接，第八晶体管的第二极与第三节点电连接；
    第九晶体管的控制极与第一节点电连接，第九晶体管的第一极与第二电源端电连接，第九晶体管的第二极与第三电容的第一端电连接；
    第十晶体管的控制极与第五节点电连接，第十晶体管的第一极与掩蔽信号端和第二时钟信号端的其中一个信号端电连接，第十晶体管的第二极与驱动输出信号端电连接；
    第十一晶体管的控制极与第二节点电连接，第十一晶体管的第一极与第一电源端电连接，第十一晶体管的第二极与驱动输出信号端电连接；
    第十二晶体管的控制极与第四节点电连接，第十二晶体管的第一极与掩蔽信号端和第二时钟信号端中的另一个信号端电连接，第十二晶体管的第二极与第五节点电连接；
    第十三晶体管的控制极与第二时钟信号端电连接，第十三晶体管的第一极与第十四晶体管的第二极电连接，第十三晶体管的第二极与第五节点电连接；
    第十四晶体管的控制极与第二节点电连接，第十四晶体管的第一极与第一电源端电连接；
    第十五晶体管的控制极与第二电源端电连接，第十五晶体管的第一极与第一节点和第三节点中的其中一个节点电连接，第十五晶体管的第二极与第四节点电连接；
    第一电容的第一端与第三节点电连接，第一电容的第二端与级联输出信号端电连接；
    第二电容的第一端与第二节点电连接，第二电容的第二端与第一电源端电连接；
    第三电容的第二端与第二时钟信号端电连接；
    第五电容的第一端与第五节点电连接，第五电容的第二端与驱动输出信号端电连接；
    第六电容的第一端与第四节点电连接，第六电容的第二端与第五节点电连接。
  17. 根据权利要求1所述的移位寄存器，其中，所述级联输出子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第九晶体管、第一电容、第二电容、第三电容和第四电容，所述驱动输出子电路包括：第十晶体管、第十一晶体管和第五电容，所述节点控制子电路包括：第十二晶体管、第十三晶体管、第十四晶体管、第十五晶体管和第六电容；
    第一晶体管的控制极与第一时钟信号端电连接，第一晶体管的第一极与信号输入端电连接，第一晶体管的第二极与第一节点电连接；
    第二晶体管的控制极与第一节点电连接，第二晶体管的第一极与第二电源端电连接，第二晶体管的第二极与第二节点电连接；
    第三晶体管的控制极与第三电容的第一端电连接，第三晶体管的第一极与第二时钟信号端电连接，第三晶体管的第二极与第二节点电连接；
    第四晶体管的控制极与第二节点电连接，第四晶体管的第一极与第二电源端电连接，第四晶体管的第二极与第五晶体管的第一极电连接；
    第五晶体管的控制极与第二时钟信号端电连接，第五晶体管的第二极与第一节点电连接；
    第六晶体管的控制极与第二节点电连接，第六晶体管的第一极与第一电源端电连接，第六晶体管的第二极与级联输出信号端电连接；
    第七晶体管的控制极与第三节点电连接，第七晶体管的第一极与第二时钟信号端电连接，第七晶体管的第二极与级联输出信号端电连接；
    第八晶体管的控制极与第二电源端电连接，第八晶体管的第一极与第一节点电连接，第八晶体管的第二极与第三节点电连接；
    第九晶体管的控制极与第一节点电连接，第九晶体管的第一极与第二电源端电连接，第九晶体管的第二极与第三电容的第一端电连接；
    第十晶体管的控制极与第五节点电连接，第十晶体管的第一极与掩蔽信号端和第二时钟信号端的其中一个信号端电连接，第十晶体管的第二极与驱动输出信号端电连接；
    第十一晶体管的控制极与第二节点电连接，第十一晶体管的第一极与第一电源端电连接，第十一晶体管的第二极与驱动输出信号端电连接；
    第十二晶体管的控制极与第四节点电连接，第十二晶体管的第一极与掩蔽信号端和第二时钟信号端中的另一个信号端电连接，第十二晶体管的第二极与第五节点电连接；
    第十三晶体管的控制极与第二时钟信号端电连接，第十三晶体管的第一极与第十四晶体管的第二极电连接，第十三晶体管的第二极与第五节点电连接；
    第十四晶体管的控制极与第二节点电连接，第十四晶体管的第一极与第一电源端电连接；
    第十五晶体管的控制极与第二电源端电连接，第十五晶体管的第一极与第一节点和第三节点中的其中一个节点电连接，第十五晶体管的第二极与第四节点电连接；
    第一电容的第一端与第三节点电连接，第一电容的第二端与级联输出信号端电连接；
    第二电容的第一端与第二节点电连接，第二电容的第二端与第一电源端电连接；
    第三电容的第二端与第二时钟信号端电连接；
    第四电容的第一端与第一电源端电连接，第四电容的第二端与级联输出信号端电连接；
    第五电容的第一端与第五节点电连接，第五电容的第二端与驱动输出信号端电连接；
    第六电容的第一端与第四节点电连接，第六电容的第二端与第五节点电连接。
  18. 根据权利要求2所述的移位寄存器，其中，在所述第一显示模式下，所述掩蔽信号端的信号为第一信号，在所述第二显示模式下，所述掩蔽信号端的信号在至少部分时间段内为第一信号，且在至少部分时间段内为第二信号；
    所述掩蔽信号端的信号为第一信号的时间段与级联输出信号端输出信号的时间段不交叠，所述掩蔽信号端的信号为第二信号的时间段与级联输出信号端输出信号的时间段至少部分交叠；
    所述第一信号与所述第二信号中的至少一个信号的电压值恒定，且所述第一信号的电压值小于所述第二信号的电压值。
  19. 根据权利要求18所述的移位寄存器，其中，在所述第二显示模式下，所述级联输出信号端输出信号的时间段位于所述掩蔽信号端的信号为第二信号的时间段内。
  20. 根据权利要求19所述的移位寄存器，其中，所述掩蔽信号端的信号由第一信号变为第二信号的时刻位于输出时间段之前，其中，所述输出时间段为所述级联输出信号端输出信号的时间段。
  21. 一种栅极驱动电路，包括：多个如权利要求1至20任一项所述的移位寄存器；
    至少一级移位寄存器的级联输出信号端与至少一级移位寄存器的信号输入端电连接。
  22. 一种显示装置，包括：如权利要求21所述的栅极驱动电路。
  23. 根据权利要求22所述的显示装置，还包括：阵列排布的子像素、多条第一扫描信号线和多条数据信号线，至少一个子像素分别与第一扫描信号线和数据信号线电连接；
    至少一个子像素包括：像素驱动电路，至少一个子像素的像素驱动电路包括：写入晶体管，所述写入晶体管分别与所在子像素所连接的所述第一扫描信号线和所述数据信号线电连接；
    至少一级移位寄存器的驱动输出信号端与至少一行像素驱动电路所连接的第一扫描信号线电连接。
  24. 根据权利要求23所述的显示装置，还包括：多条第二复位信号线和多条第二初始信号线，至少一个子像素还分别与第二复位信号线和第二初始信号线电连接；
    至少一个子像素的像素驱动电路还包括：阳极复位晶体管，所述阳极复位晶体管分别与所在子像素连接的所述第二复位信号线和所述第二初始信号线电连接；
    至少一级移位寄存器的驱动输出信号端与至少一行像素驱动电路所连接的第二复位信号线电连接；
    至少一行像素驱动电路所连接的第一扫描信号线和第二复位信号线独立设置，或者至少一行像素驱动电路所连接的第二复位信号线与下一行像素驱动电路所连接的第一扫描信号线为同一信号线。
  25. 一种移位寄存器的驱动方法，被配置为驱动如权利要求1至20任一项所述的移位寄存器，所述方法包括：
    级联输出子电路在信号输入端、第一时钟信号端、第二时钟信号端和第二电源端的信号的控制下，向级联输出信号端提供第一电源端或者第二时钟信号端的信号；
    节点控制子电路在级联输出子电路、第一电源端、第二电源端和第一控制输入信号端的信号的控制下，向驱动输出子电路提供信号；
    驱动输出子电路在级联输出子电路和节点控制子电路的信号的控制下，向驱动输出信号端提供第一电源端或者第二控制输入信号端的信号。
PCT/CN2025/077129 2024-03-26 2025-02-13 移位寄存器及其驱动方法、栅极驱动电路、显示装置 Pending WO2025200830A1 (zh)

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