WO2025190036A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置

Info

Publication number
WO2025190036A1
WO2025190036A1 PCT/CN2025/077371 CN2025077371W WO2025190036A1 WO 2025190036 A1 WO2025190036 A1 WO 2025190036A1 CN 2025077371 W CN2025077371 W CN 2025077371W WO 2025190036 A1 WO2025190036 A1 WO 2025190036A1
Authority
WO
WIPO (PCT)
Prior art keywords
lines
bending
data
group
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/077371
Other languages
English (en)
French (fr)
Inventor
何帆
李双
谢涛峰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Publication of WO2025190036A1 publication Critical patent/WO2025190036A1/zh
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations

Definitions

  • This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device.
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • this embodiment provides a display substrate comprising: a display area and a first frame area located on one side of the display area along a first direction; the first frame area comprising a bending area and a first sub-area located between the bending area and the display area; the display area having a first centerline extending along the first direction, and the first frame area having a second centerline extending along the first direction; and a distance between the first centerline and the second centerline being greater than zero.
  • the display substrate comprises: a substrate; a plurality of sub-pixels and a plurality of data lines disposed on one side of the substrate and located in the display area; a plurality of first data fan-out lines located in the first sub-area; and a plurality of data bending lines located in the bending area.
  • the plurality of data lines are electrically connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels.
  • a plurality of first data fan-out lines are connected to the plurality of data lines.
  • a plurality of data bending lines are connected to the plurality of first data fan-out lines, and the plurality of data bending lines are symmetrically arranged about a third centerline; the third centerline coincides with the first centerline, or coincides with the second centerline, or is located between the first centerline and the second centerline.
  • the display substrate further comprises: a plurality of first power fold lines located in the bending region and extending along the first direction, the plurality of first power fold lines being spaced apart from the plurality of data fold lines along a second direction, the second direction intersecting the first direction.
  • the first border region further comprises: a second subregion located on a side of the bending region away from the first subregion.
  • the display substrate further comprises: a first peripheral power line located in the first subregion and a first power lead located in the second subregion, the first peripheral power line and the first power lead being connected via the plurality of first power fold lines; the plurality of first power fold lines being symmetrically arranged about the third centerline.
  • the plurality of data bending lines include: a first group of data bending lines, a second group of data bending lines, a third group of data bending lines, and a fourth group of data bending lines.
  • the plurality of first power bending lines include at least: a first group of first power bending lines, a second group of first power bending lines, and a third group of first power bending lines.
  • the third group of data bending lines, the second group of first power bending lines, the first group of data bending lines, the first group of first power bending lines, the second group of data bending lines, the third group of first power bending lines, and the fourth group of data bending lines are arranged sequentially along the second direction.
  • the first group of data bending lines and the second group of data bending lines are symmetrically arranged about the third center line, and the third group of data bending lines and the fourth group of data bending lines are symmetrically arranged about the third center line; the second group of first power bending lines and the third group of first power bending lines are symmetrically arranged about the third center line, and the first group of first power bending lines are symmetrically arranged about the third center line.
  • the total length of the first group of first power bending lines along the second direction is greater than or equal to the total length of the second group of first power bending lines along the second direction, and greater than or equal to the total length of the third group of first power bending lines along the second direction.
  • the plurality of first power bending lines further include: a fourth group of first power bending lines and a fifth group of first power bending lines, the fourth group of first power bending lines being located on a side of the third group of data bending lines away from the second group of first power bending lines, the fifth group of first power bending lines being located on a side of the fourth group of data bending lines away from the third group of first power bending lines; the fourth group of first power bending lines and the fifth group of first power bending lines being symmetrically arranged about the third center line.
  • the display substrate further includes: a plurality of second power bending lines located in the bending region and extending along the first direction, the plurality of second power bending lines being located on both sides of the plurality of data bending lines along the second direction.
  • the display substrate further includes: a second peripheral power line located in the first sub-region and a second power lead line located in the second sub-region, the second peripheral power line and the second power lead line being connected via the plurality of second power bending lines, the second peripheral power line transmitting a second voltage signal that is different from the first voltage signal transmitted by the first peripheral power line; the plurality of second power bending lines being symmetrically arranged about the third center line.
  • the display substrate further includes: a plurality of control bending lines located in the bending area and extending along the first direction, the plurality of control bending lines being located on both sides of the plurality of second power bending lines along the second direction; and the plurality of control bending lines being symmetrically arranged about the third center line.
  • the third centerline coincides with the second centerline.
  • the first border region has a first border edge and a second border edge extending along the first direction, the first border edge and the second border edge being located on either side of the alignment of the bending region along the second direction, and the second direction intersecting the first direction.
  • the minimum distance between the alignment of the bending region and the first border edge is a first edge distance
  • the minimum distance between the alignment of the bending region and the second border edge is a second edge distance
  • the ratio of the first edge distance to the second edge distance is 0.9 to 1.1.
  • the third centerline is located between the first centerline and the second centerline, or the third centerline coincides with the first centerline.
  • the first border area has a first border edge and a second border edge extending along the first direction, the first border edge and the second border edge are located on either side of the alignment of the bending area along the second direction, and the second direction intersects the first direction.
  • the minimum distance between the alignment of the bending area and the first border edge is the first edge distance
  • the minimum distance between the alignment of the bending area and the second border edge is the second edge distance
  • the ratio of the first edge distance to the second edge distance is greater than 1
  • the ratio of the second edge distance to the first edge distance is greater than 1.
  • At least one of the plurality of first data fan-out lines includes a first data extension segment and a second data extension segment connected to each other, the second data extension segment being connected to at least one of the plurality of data bend lines, and the second data extension segment being a straight line segment extending along the first direction, with the extension direction of the first data extension segment intersecting the first direction.
  • a second centerline is located on a first side of the first centerline in a second direction, with the second direction intersecting the first direction; and the third centerline does not overlap with the first centerline.
  • the length of the first data extension segment of the at least one first data fan-out line located near the first centerline and on a first side of the first centerline is greater than the length of the first data extension segment of the at least one first data fan-out line located near the first centerline and on a second side of the first centerline.
  • the third center line coincides with the first center line, and the plurality of first data fan-out lines are symmetrically arranged about the third center line.
  • the first border region further includes a second sub-region located on a side of the bending region away from the first sub-region.
  • the display substrate further includes a plurality of data lead lines located in the second sub-region, the plurality of data lead lines being connected to the plurality of data bending lines; the plurality of data lead lines being symmetrically arranged about the third center line.
  • the display substrate further comprises: a plurality of power bending lines located in the bending region, the plurality of power bending lines being spaced apart from the plurality of data bending lines along a second direction, the second direction intersecting the first direction.
  • the plurality of power bending lines include: a first group of power bending lines and a second group of power bending lines located on either side of the third centerline. The total length of the first group of power bending lines along the second direction is different from the total length of the second group of power bending lines along the second direction.
  • the third centerline coincides with the first centerline.
  • the first border region has a first border edge and a second border edge extending along the first direction, the first border edge and the second border edge being located on either side of the alignment of the bending region along a second direction, and the second direction intersecting the first direction.
  • the minimum distance between the alignment of the bending region and the first border edge is a first edge distance
  • the minimum distance between the alignment of the bending region and the second border edge is a second edge distance
  • the ratio of the first edge distance to the second edge distance is 0.9 to 1.1.
  • the third center line coincides with the first center line, the second center line and the first group of power bending lines are located on the same side of the first center line; and the total length of the first group of power bending lines along the second direction is greater than the total length of the second group of power bending lines along the second direction.
  • this embodiment further provides a display device including the display substrate described above.
  • this embodiment provides a display substrate comprising: a display area and a first frame area located on one side of the display area along a first direction, the first frame area comprising a bending area and a first sub-area located between the bending area and the display area; the display area having a first centerline extending along the first direction, the first frame area having a second centerline extending along the first direction, and the distance between the first centerline and the second centerline being greater than zero.
  • the display substrate comprises: a substrate, a plurality of sub-pixels and a plurality of data lines disposed on one side of the substrate and located in the display area, a plurality of first data fan-out lines located in the first sub-area, and a plurality of signal bending lines located in the bending area.
  • the plurality of data lines are electrically connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels.
  • a plurality of first data fan-out lines are connected to the plurality of data lines.
  • a plurality of signal bending lines are located on the same conductive layer.
  • the plurality of signal bending lines include at least a plurality of data bending lines connected to the plurality of first data fan-out lines, and the plurality of data bending lines are symmetrically arranged about a third centerline.
  • the plurality of signal bending lines have a fourth center line extending along the first direction. The fourth center line coincides with the third center line, or is located on a side of the third center line close to the second center line.
  • the plurality of signal bend lines are symmetrically arranged about the fourth centerline; the third centerline and the fourth centerline coincide with the second centerline.
  • the first border region has a first border edge and a second border edge extending along the first direction, the first border edge and the second border edge being located on either side of the signal bend line of the bend region along a second direction, the second direction intersecting the first direction.
  • the minimum distance between the signal bend line of the bend region and the first border edge is a first edge distance
  • the minimum distance between the signal bend line of the bend region and the second border edge is a second edge distance, with the ratio of the first edge distance to the second edge distance being 0.9 to 1.1.
  • the plurality of signal bend lines are symmetrically arranged about the fourth center line.
  • the third center line coincides with the fourth center line and is located between the first center line and the second center line; or, the third center line and the fourth center line coincide with the first center line.
  • the first border area has a first border edge and a second border edge extending along the first direction, and the first border edge and the second border edge are located on both sides of the signal bend line of the bend area along the second direction, and the second direction intersects the first direction.
  • the minimum distance between the signal bend line of the bend area and the first border edge is the first edge distance
  • the minimum distance between the signal bend line of the bend area and the second border edge is the second edge distance
  • the ratio of the first edge distance to the second edge distance is greater than 1, or the ratio of the second edge distance to the first edge distance is greater than 1.
  • the plurality of signal bend lines are asymmetrically arranged about the fourth centerline, the fourth centerline coincides with the second centerline, and the third centerline coincides with the first centerline.
  • the first border region has a first border edge and a second border edge extending along the first direction, the first border edge and the second border edge being located on either side of the signal bend line of the bend region along a second direction; the second direction intersects the first direction.
  • the minimum distance between the signal bend line of the bend region and the first border edge is a first edge distance
  • the minimum distance between the signal bend line of the bend region and the second border edge is a second edge distance, with the ratio of the first edge distance to the second edge distance being 0.9 to 1.1.
  • FIG1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • FIG2A is a schematic partial cross-sectional view of a display region of a display substrate according to at least one embodiment of the present disclosure
  • FIG2B is another partial cross-sectional schematic diagram of the display region of the display substrate according to at least one embodiment of the present disclosure.
  • FIG3 is a schematic diagram of a partial structure of a first frame area according to at least one embodiment of the present disclosure
  • FIG4 is a partial enlarged schematic diagram of area S1 in FIG3 ;
  • FIG5 is another partial structural diagram of the first frame area according to at least one embodiment of the present disclosure.
  • FIG6 is a schematic diagram of local wiring in a first border area according to at least one embodiment of the present disclosure.
  • FIG7 is another partial schematic diagram of the first frame area according to at least one embodiment of the present disclosure.
  • FIG8 is another partial schematic diagram of the first frame area according to at least one embodiment of the present disclosure.
  • FIG9 is a partial enlarged schematic diagram of area S2 in FIG8 ;
  • FIG10 is another partial schematic diagram of the first frame area according to at least one embodiment of the present disclosure.
  • FIG11 is a partial enlarged schematic diagram of area S3 in FIG10 ;
  • FIG12 is another partial schematic diagram of the first border area according to at least one embodiment of the present disclosure.
  • FIG13 is a partial enlarged schematic diagram of area S4 in FIG12 ;
  • FIG14 is another partial schematic diagram of the first frame area according to at least one embodiment of the present disclosure.
  • FIG15 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • FIG. 16 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • orientation or positional relationships such as “middle,” “upper,” “lower,” “front,” “back,” “vertical,” “horizontal,” “top,” “bottom,” “inside,” and “outside,” are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings.
  • This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure.
  • the positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.
  • the terms “mounted,” “connected,” and “connected” should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the circumstances.
  • electrically connected includes components connected together via an element having some electrical function.
  • element having some electrical function There are no particular limitations on the “element having some electrical function” as long as it enables transmission of electrical signals between the connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.
  • a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source.
  • a transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source.
  • the channel region refers to the region through which current primarily flows.
  • the first electrode can be referred to as the drain and the second electrode as the source, or vice versa.
  • the functions of "source” and “drain” are sometimes interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms “source” and “drain” can be interchanged.
  • the gate electrode can also be referred to as the control electrode.
  • parallel refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.
  • circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.
  • a extends along direction B means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions.
  • a extends along direction B means “the main portion of A extends along direction B.”
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the orthographic projection of A contains the orthographic projection of B means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • the "shape of A” mentioned in the present disclosure refers to the shape of the orthographic projection of A on the substrate.
  • the distance between A and B refers to the vertical distance or the minimum distance between A and B.
  • the secondary screen of the large folding display needs to be designed with a cover.
  • the appearance is asymmetrical, so that the center line of the display area and the center line of the lower frame are not on the same straight line, which puts forward new requirements for the signal routing layout of the lower frame.
  • This embodiment provides a display substrate, comprising: a display area and a first frame area located on one side of the display area along a first direction.
  • the first frame area includes a bending area and a first sub-area located between the bending area and the display area.
  • the display area has a first centerline extending along the first direction, and the first frame area has a second centerline extending along the first direction. The distance between the first centerline and the second centerline is greater than zero.
  • the display substrate includes: a substrate, a plurality of sub-pixels and a plurality of data lines disposed on one side of the substrate and located in the display area, a plurality of first data fan-out lines located in the first sub-area, and a plurality of data bending lines located in the bending area.
  • the plurality of data lines are electrically connected to the plurality of sub-pixels, and the plurality of data lines are configured to provide data signals to the plurality of sub-pixels.
  • the plurality of first data fan-out lines are connected to the plurality of data lines.
  • the plurality of data bending lines are connected to the plurality of first data fan-out lines, and the plurality of data bending lines are symmetrically arranged about a third centerline.
  • the third centerline coincides with the first centerline, or coincides with the second centerline, or is located between the first and second centerlines.
  • the third centerline, the first centerline, and the second centerline may extend in the same direction.
  • multiple data bending lines in the bending area are symmetrically arranged about a third centerline. This ensures the density and film consistency of the data bending lines on both sides of the third centerline, thus ensuring a good bending effect. Furthermore, the third centerline coincides with the first or second centerline, or lies between the first and second centerlines, thereby alleviating the problem of signal routing differences caused by the asymmetric shape of the display substrate.
  • the display substrate may further include: a plurality of first power zigzag lines located in the bend region and extending along a first direction, the plurality of first power zigzag lines being spaced apart from the plurality of data zigzag lines along a second direction.
  • the second direction intersects the first direction; for example, the second direction may be perpendicular to the first direction.
  • the first border region may further include: a second subregion located on a side of the bend region away from the first subregion.
  • the display substrate may further include: a first peripheral power line located in the first subregion and a first power lead located in the second subregion. The first peripheral power line and the first power lead may be connected via the plurality of first power zigzag lines.
  • the plurality of first power zigzag lines may be symmetrically arranged about a third centerline.
  • the first peripheral power line, the first power lead, and the plurality of first power zigzag lines are electrically connected and configured to transmit a first voltage signal.
  • the display substrate may further include: a plurality of second power zigzag lines extending along the first direction; the plurality of second power zigzag lines may be located on either side of the plurality of data zigzag lines along the second direction.
  • the display substrate may further include: a second peripheral power line located in the first sub-region and a second power lead line located in the second sub-region; the second peripheral power line and the second power lead line may be connected via the plurality of second power zigzag lines; the second peripheral power line transmits a second voltage signal that is different from the first voltage signal transmitted by the first peripheral power line.
  • the plurality of second power zigzag lines may be symmetrically arranged about a third centerline.
  • the first voltage signal may be greater than the second voltage signal.
  • the first voltage signal may be configured to be supplied to the first power line connected to the sub-pixels in the display area
  • the second voltage signal may be configured to be supplied to the cathode of the light-emitting element of the sub-pixel in the display area or to the second power line connected to the sub-pixel.
  • the display substrate may further include: a plurality of control bend lines located in the bend region and extending along the first direction, the plurality of control bend lines being located on both sides of the plurality of second power bend lines along the second direction; the plurality of control bend lines may be symmetrically arranged about a third center line.
  • the plurality of control bend lines may include: a plurality of traces for providing control signals (e.g., including a start signal, a clock signal, a voltage signal, etc.) to the gate drive circuit, and traces for transmitting panel test signals.
  • the gate drive circuit may be configured to provide pixel control signals (e.g., including a scan signal, a reset signal, a light-emitting control signal, etc.) to the plurality of sub-pixels in the display region.
  • pixel control signals e.g., including a scan signal, a reset signal, a light-emitting control signal, etc.
  • the third center line may coincide with the second center line.
  • the first frame area may have a first frame edge and a second frame edge extending along the first direction, and the first frame edge and the second frame edge may be located on both sides of the routing of the bending area along the second direction.
  • the minimum distance between the routing of the bending area and the first frame edge is the first edge distance
  • the minimum distance between the routing of the bending area and the second frame edge is the second edge distance
  • the ratio of the first edge distance to the second edge distance is 0.9 to 1.1.
  • the first edge distance may be equal to the second edge distance. This example can ensure the consistency of the distance between the routing of the bending area and the two side edges of the display substrate, which is beneficial to the routing arrangement of the bending area and to ensure the bending effect.
  • the third center line may be located between the first center line and the second center line, or the third center line may coincide with the first center line.
  • the first border area may have a first border edge and a second border edge extending along the first direction, and the first border edge and the second border edge are located on both sides of the routing of the bending area along the second direction.
  • the minimum distance between the routing of the bending area and the first border edge is the first edge distance
  • the minimum distance between the routing of the bending area and the second border edge is the second edge distance
  • the ratio of the first edge distance to the second edge distance is greater than 1
  • the ratio of the second edge distance to the first edge distance is greater than 1.
  • the first edge distance is different from the second edge distance. This example helps to ensure the symmetrical arrangement of the routing of the bending area by adjusting the difference between the first edge distance and the second edge distance, thereby reducing the difference between the signals transmitted on both sides of the second center line in the first border area.
  • the display substrate may include: a plurality of power bend lines located in a bend region, wherein the plurality of power bend lines and the plurality of data bend lines may be spaced apart along a second direction.
  • the plurality of power bend lines may include: a first group of power bend lines and a second group of power bend lines located on either side of a third center line, wherein the total length of the first group of power bend lines along the second direction may be different from the total length of the second group of power bend lines along the second direction.
  • the total length of a group of power bend lines along the second direction may include: the sum of the line width of each power bend line within the group of power bend lines and the spacing between adjacent power bend lines.
  • no other wiring is provided between adjacent power bend lines.
  • the symmetrical arrangement of the plurality of data bend lines can be ensured by adjusting the total length of one or more groups of power bend lines along the second direction on either side of the third center line.
  • the third centerline can coincide with the first centerline, and the second centerline and the first group of power meander lines can be located on the same side of the first centerline.
  • the total length of the first group of power meander lines along the second direction can be greater than the total length of the second group of power meander lines along the second direction.
  • the wiring layout of the first border area can be optimized by adjusting the lengths of the first and second groups of power meander lines along the second direction.
  • FIG. 1 is a schematic diagram of a display substrate of at least one embodiment of the present disclosure.
  • the display substrate may be a closed polygon including linear edges.
  • the display substrate of this example may be applied to a sub-screen of a large stack display product.
  • the display substrate may include: a display area AA and a border area BB located around the display area AA.
  • the display area AA may include: a first display edge (lower display edge) and a second display edge (upper display edge) arranged opposite to each other in a first direction Y, and a third display edge (left display edge) and a fourth display edge (right display edge) arranged opposite to each other in a second direction X.
  • the first display edge and the second display edge may be linear edges parallel to each other, and the third display edge and the fourth display edge may be linear edges parallel to each other. Adjacent linear edges may be connected by curved edges (e.g., arcuate edges).
  • the border area BB may include: a first border area B1 and a fourth border area B4 located on both sides of the display area AA along the first direction Y, and a second border area B2 and a third border area B3 located on both sides of the display area AA along the second direction X.
  • the first border area B1 can be connected to the first display edge
  • the second border area B2 can be connected to the third display edge
  • the third border area B3 can be connected to the fourth display edge
  • the fourth border area B4 can be connected to the second display edge.
  • the first border area B1 can be connected to the second border area B2 and the third border area B3, and the third border area B4 can be connected to the second border area B2 and the third border area B3.
  • the first border area B1 can also be called the lower border area of the display substrate
  • the second border area B2 can also be called the left border area of the display substrate
  • the third border area B3 can also be called the right border area of the display substrate
  • the fourth border area B4 can also be called the upper border area of the display substrate.
  • this embodiment is not limited to this.
  • the display area AA of the display substrate may include at least: a plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines DL.
  • the plurality of gate lines GL may extend along the second direction X and be arranged along the first direction Y; the plurality of data lines DL may extend along the first direction Y and be arranged along the second direction X.
  • the plurality of data lines DL may be electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL may be configured to provide data signals to the plurality of sub-pixels PX.
  • the plurality of gate lines GL may be electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines GL may be configured to provide pixel control signals to the plurality of sub-pixels PX.
  • the pixel control signal may include a scan signal, or may include a scan signal and a light-emitting control signal, or may include a scan signal, a reset control signal, and a light-emitting control signal.
  • the second direction X may be the extending direction (e.g., the row direction) of the gate lines GL in the display area AA;
  • the first direction Y may be the extending direction (e.g., the column direction) of the data lines DL in the display area AA.
  • the first direction Y and the second direction X may intersect with each other, for example, may be perpendicular to each other.
  • a pixel unit of the display area AA may include three sub-pixels, and the three sub-pixels may be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., green light), and a third sub-pixel emitting a third color light (e.g., blue light).
  • a pixel unit may include four sub-pixels, and the four sub-pixels may be a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light.
  • a pixel unit may include four sub-pixels, and the four sub-pixels may include a sub-pixel emitting red light, a sub-pixel emitting blue light, and two sub-pixels emitting green light.
  • a sub-pixel may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit.
  • the pixel circuit may include multiple transistors and at least one capacitor.
  • the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • T refers to a thin film transistor
  • C refers to a capacitor
  • the number before T represents the number of thin film transistors in the circuit
  • the number before C represents the number of capacitors in the circuit.
  • the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors.
  • the multiple transistors in the pixel circuit may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the product yield.
  • the shape of the light-emitting elements of a sub-pixel can be rectangular, rhombus, pentagonal, or hexagonal.
  • the light-emitting elements of the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally, vertically, or in a square pattern.
  • this embodiment is not limited to this.
  • the light-emitting element can be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc.
  • the light-emitting element can be an OLED, and the light-emitting element can emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit.
  • the color of the light emitted by the light-emitting element can be determined according to needs.
  • the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode.
  • the anode of the light-emitting element can be electrically connected to the corresponding pixel circuit.
  • this embodiment is not limited to this.
  • Figure 2A is a schematic partial cross-sectional view of a display region of a display substrate according to at least one embodiment of the present disclosure.
  • Figure 2A illustrates the structure of a sub-pixel in the display region as an example.
  • the multiple pixel transistors in the pixel circuit can be of different transistor types, such as low-temperature polysilicon thin-film transistors and oxide thin-film transistors.
  • the display area of the display substrate may include: a substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, and an encapsulation structure layer 14 sequentially disposed on the substrate.
  • the circuit structure layer 12 may include at least: pixel circuits for multiple sub-pixels, each of which may include multiple transistors and at least one capacitor.
  • the light-emitting structure layer 13 may include at least: light-emitting elements for multiple sub-pixels.
  • the display substrate may further include: a touch structure layer located on a side of the encapsulation structure layer away from the substrate.
  • the touch structure layer may include at least one touch conductive layer.
  • FIG2A illustrates an example of each sub-pixel including a first transistor 21, a second transistor 22, and a capacitor 23.
  • the first transistor 21 and the second transistor 22 may be of different transistor types.
  • the first transistor 21 may be a low-temperature polysilicon thin-film transistor, and the second transistor 22 may be an oxide thin-film transistor.
  • the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, and a second source-drain metal layer disposed on the substrate 10 .
  • a first insulating layer 101 may be provided between the first semiconductor layer and the first gate metal layer, and a second insulating layer 102 may be provided between the first gate metal layer and the second gate metal layer; a third insulating layer 103 may be provided between the second gate metal layer and the second semiconductor layer; a fourth insulating layer 104 may be provided between the second semiconductor layer and the third gate metal layer; a fifth insulating layer 105 may be provided between the third gate metal layer and the first source-drain metal layer; a sixth insulating layer 106 (also referred to as a passivation (PVX) layer) and a seventh insulating layer 107 (also referred to as a first flattening (PLN) layer) may be provided between the first source-drain metal layer and the second source-drain metal layer, and the seventh insulating layer 107 may be located on the side of the sixth insulating layer 106 away from the substrate 10; an eighth insulating layer 108 (also referred to as a second flattening layer) may
  • the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, the fifth insulating layer 105 and the sixth insulating layer 106 can be inorganic insulating layers, and the seventh insulating layer 107 and the eighth insulating layer 108 can be organic insulating layers.
  • this embodiment is not limited to this.
  • a buffer layer can be further provided on the side of the first semiconductor layer close to the substrate. The buffer layer can prevent harmful substances in the substrate from invading the interior of the display substrate and can also increase the adhesion of the film layer in the display substrate to the substrate.
  • a bottom shielding metal layer can be further provided on the side of the buffer layer close to the substrate.
  • the bottom shielding metal layer can be configured to at least partially cover the active layer of the transistor of the pixel circuit to prevent external light from affecting the performance of the transistor.
  • the sixth insulating layer can be omitted between the first source and drain metal layer and the second source and drain metal layer, and only the seventh insulating layer can be provided between the first source and drain metal layer and the second source and drain metal layer.
  • the first semiconductor layer in the display area may include at least a first active layer 210 of the first transistor 21.
  • the first active layer 210 of the first transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102.
  • the first gate metal layer may include at least a first gate electrode 213 of the first transistor 21 and a first plate 231 of the capacitor 23.
  • the orthographic projection of the first gate electrode 213 of the first transistor 21 on the substrate 10 may overlap the orthographic projection of the channel region 2100 of the first active layer 210 on the substrate 10.
  • the second gate metal layer may include at least a second plate 232 of the capacitor 23.
  • the orthographic projections of the second plate 232 and the first plate 231 of the capacitor 23 on the substrate 10 may at least partially overlap, for example, they may coincide.
  • the second semiconductor layer may include at least a second active layer 220 of the second transistor 22.
  • the third gate metal layer may include at least a second gate electrode 223 of the second transistor 22.
  • An orthographic projection of the second gate 223 of the second transistor 22 on the substrate 10 may partially overlap with an orthographic projection of the second active layer 220 on the substrate 10 .
  • the first source-drain metal layer may include at least: a first source 211 and a first drain 212 of the first transistor 21, and a second source 221 and a second drain 222 of the second transistor 22.
  • the fifth insulating layer 105 may have a plurality of pixel vias (e.g., including a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area.
  • the fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the first pixel via may be removed to expose at least a portion of the surface of the first region 2101 of the first active layer 210; the fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the second pixel via may be removed to expose at least a portion of the surface of the second region 2102 of the first active layer 210.
  • the fifth insulating layer 105 and the fourth insulating layer 104 within the third and fourth pixel vias can be removed, exposing at least portions of the surfaces of both ends of the second active layer 220.
  • the first source electrode 211 of the first transistor 21 can be electrically connected to the first region 2101 of the first active layer 210 through the first pixel via, and the first drain electrode 212 can be electrically connected to the second region 2102 of the first active layer 210 through the second pixel via.
  • the second source electrode 221 of the second transistor 22 can be electrically connected to one end of the second active layer 220 through the third pixel via, and the second drain electrode 222 of the second transistor 22 can be electrically connected to the other end of the second active layer 220 through the fourth pixel via.
  • the second source-drain metal layer can include at least a first transition electrode 241.
  • the first transition electrode 241 can be electrically connected to the first drain electrode 212 of the first transistor 21 of the pixel circuit through a fifth pixel via defined between the sixth and seventh insulating layers 106 and 107.
  • the first transition electrode 241 can be used to achieve electrical connection between the pixel circuit and the light-emitting element.
  • the multiple gate lines of the display substrate may include: a first scan line, a second scan line, a first reset control line, a second reset control line, and a light emission control line.
  • the multiple gate lines may, for example, be located in a first gate metal layer and a third gate metal layer.
  • the first scan line, the first reset control line, the second reset control line, and the light emission control line may be located in the first gate metal layer
  • the second scan line may be located in the third gate metal layer.
  • the multiple data lines may, for example, be located in the second source/drain metal layer
  • the first power line of the display area may, for example, be located in the second source/drain metal layer.
  • this embodiment is not limited to this.
  • the light-emitting structure layer 13 may include a pixel definition layer 134 and multiple light-emitting elements.
  • each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133.
  • the first electrode 131 of the light-emitting element may be an anode.
  • the first electrode 131 may be disposed on the eighth insulating layer 108 and electrically connected to the first transfer electrode 241 through a sixth pixel via provided in the eighth insulating layer 108.
  • the pixel definition layer 134 is disposed on the first electrode 131 and the eighth insulating layer 108.
  • the pixel definition layer 134 may have multiple pixel openings, each of which may expose at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 may be disposed within a pixel opening and connected to the corresponding first electrode 131.
  • the second electrode 133 may be disposed on and connected to the organic light-emitting layer 132. Driven by the first electrode 131 and the second electrode 133, the organic light-emitting layer 132 may emit light of a corresponding color.
  • the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML), and one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL).
  • EML emitting layer
  • HIL hole injection layer
  • HTL hole transport layer
  • HBL hole blocking layer
  • EBL electron blocking layer
  • EIL electron injection layer
  • ETL electron transport layer
  • the light-emitting layers of light-emitting elements of different colors may be different.
  • a red light-emitting element includes a red light-emitting layer
  • a green light-emitting element includes a green light-emitting layer
  • a blue light-emitting element includes a blue light-emitting layer.
  • the hole injection layer and the hole transport layer on one side of the light-emitting layer may use a common layer
  • the electron injection layer and the electron transport layer on the other side of the light-emitting layer may use a common layer.
  • any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be produced by a single process (a single evaporation process or a single inkjet printing process), and isolation can be achieved by means of a surface step difference of the formed film layer or by surface treatment.
  • any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels can be isolated.
  • the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM) or an open mask (Open Mask), or by inkjet technology.
  • FMM fine metal mask
  • Open Mask open mask
  • the encapsulation structure layer 14 may include a stacked first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143.
  • the first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, and the like.
  • the second encapsulation layer 142 may be disposed between the first and third encapsulation layers 141, 143 to prevent external moisture from entering the light-emitting element.
  • the second encapsulation layer 142 may be made of an organic material, such as a polymer material containing a desiccant or a polymer material that can block moisture, or a polymer resin to planarize the surface of the display substrate and relieve stress on the first and third encapsulation layers 141, 143. It may also include a desiccant or other absorbent material to absorb intrusive water, oxygen, and other substances. However, this embodiment is not limited to this.
  • the encapsulation structure layer may have a five-layer stacked structure: inorganic/organic/inorganic/organic/inorganic/inorganic.
  • Figure 2B is another partial cross-sectional schematic diagram of the display area of the display substrate of at least one embodiment of the present disclosure.
  • the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer, disposed on the substrate 10.
  • An eighth insulating layer 108 may be disposed between the second source-drain metal layer and the third source-drain metal layer, and a ninth insulating layer 109 (also referred to as a third planar layer) may be disposed on the side of the third source-drain metal layer away from the substrate.
  • the ninth insulating layer 109 may be an organic insulating layer.
  • the third source-drain metal layer may include at least: a second transfer electrode 242, which may be connected to a first transfer electrode 241 located in the second source-drain metal layer.
  • the first transfer electrode 241 and the second transfer electrode 242 may be used to achieve electrical connection between the pixel circuit and the first electrode 131 of the light-emitting element.
  • the remaining structure of the display area of the display substrate of this example can be referred to the description of the embodiment shown in Figure 2A, so it will not be repeated here.
  • the first border area B1 may include: a first sub-area B11, a bending area B12, and a second sub-area B13 arranged in sequence along a direction away from the display area AA.
  • the bending area B12 can connect the first sub-area B11 and the second sub-area B12.
  • the first sub-area B11 can connect the second border area B2 and the third border area B3, and be connected to the display area AA.
  • the first sub-area B11 can also be referred to as a first fan-out area.
  • the bending area B12 can be configured to bend the second sub-area B13 to the back of the display area AA.
  • a plurality of signal bending lines can be provided in the bending area B12 to achieve electrical connection between the traces transmitting the same signal in the first sub-area B11 and the second sub-area B13.
  • the second sub-area B13 may include at least: a first signal access area B14.
  • the first signal access area B14 may be provided with a plurality of first contact pads, and the plurality of first contact pads may be configured to connect a driver integrated circuit (IC).
  • IC driver integrated circuit
  • the second sub-area B13 may include: a first signal access area B14, a circuit configuration area located between the bending area B12 and the first signal access area B14, a second fan-out area located between the bending area B12 and the circuit configuration area, a third fan-out area located between the circuit configuration area and the first signal access area B14, and a second signal access area located on a side of the first signal access area B14 away from the bending area B12.
  • the second fan-out area, the circuit configuration area, the third fan-out area, the first signal access area B14, and the second signal access area may be arranged sequentially in a direction away from the bending area B12.
  • the circuit configuration area may include at least a plurality of test circuits arranged along the second direction X; alternatively, the circuit configuration area may include a plurality of test circuits, a plurality of electrostatic discharge circuits located on a side of the plurality of test circuits near the bending area B12, and a plurality of data selection circuits located on a side of the plurality of test circuits away from the bending area B12.
  • the second signal access area may include a plurality of second contact pads, which may be configured to be bonded to an external flexible printed circuit (FPC). At least one first contact pad within the first signal access area B14 and at least one second contact pad within the second signal access area can be connected via a lead-out connection line. This embodiment is not limited to this.
  • the second sub-area B13 may include a second fan-out area, a first signal access area B14, and a second signal access area, arranged sequentially in a direction away from the bending area B12.
  • the display area AA may have a first centerline O1 extending along a first direction Y, with the first centerline O1 passing through a center point C1 of the display area AA.
  • the distance between the first display edge and the center point C1 may be the same as the distance between the second display edge and the center point C1; and the distance between the third display edge and the center point C1 may be the same as the distance between the fourth display edge and the center point C1.
  • the first centerline O1 may divide the display area AA into a first sub-display area and a second sub-display area arranged along a second direction X.
  • the multiple data lines DL within the display area AA may include: a first group of data lines located in the first sub-display area and a second group of data lines located in the second sub-display area.
  • the number of data lines in the first group of data lines may be the same as the number of data lines in the second group of data lines.
  • the first group of data lines and the second group of data lines may be symmetrically arranged about the first centerline O1.
  • this embodiment is not limited to this.
  • two groups of routing lines are arranged symmetrically about a centerline, meaning that the two groups have the same number of routing lines and are arranged symmetrically about the centerline.
  • the routing lines in the two groups arranged symmetrically about the centerline have the same line width and the same spacing length as adjacent routing lines.
  • a group of routing lines is arranged symmetrically about a centerline, meaning that the group of routing lines can be divided into two symmetrically arranged sections on either side of the centerline, with the two sections including the same number of routing lines; or, the group of routing lines can be divided into two symmetrically arranged sections on either side of the centerline and a routing line passing through the centerline, with the two sections including the same number of routing lines.
  • FIG3 is a schematic diagram of a partial structure of the first border area of at least one embodiment of the present disclosure.
  • the border area BB may include at least: a first border edge B101 and a second border edge B102 of the first border area B1 arranged opposite to each other in the second direction X, and a third border edge B201 and a fourth border edge B301 arranged opposite to each other in the second direction X.
  • the first border edge B101 and the second border edge B102 may extend substantially along the first direction Y.
  • the first border edge B101 and the second border edge B102 may be linear edges parallel to each other.
  • the first border edge B101 is, for example, the left edge of the first border area B1
  • the second border edge B102 is, for example, the right edge of the first border area B1.
  • the third border edge B201 may be the left edge of the second border area B2, and the right edge of the second border area B2 is connected to the third display edge of the display area AA.
  • the fourth border edge B202 may be the right edge of the third border area B3, and the left edge of the third border area B3 is connected to the fourth display edge of the display area AA.
  • the third frame edge B201 and the third display edge may be parallel linear edges
  • the fourth frame edge B301 and the fourth display edge may be parallel linear edges.
  • the first frame edge B101 and the third frame edge B201 may be connected by a curved frame edge
  • the third frame edge B201 and the fourth frame edge B202 may be connected by a curved frame edge
  • the first frame edge B101 and the second frame edge B102 may be connected by a fifth frame edge B103 extending along the second direction X
  • the third frame edge B201 and the fourth frame edge B301 may be connected by an edge of the fourth frame area B4 away from the display area AA.
  • the first border area B1 may have a second center line O2 extending along the first direction Y, and the second center line O2 passes through the center point C2 of the first border area B1.
  • the distance between the first border edge B101 and the center point C2 may be approximately the same as the distance between the second border edge B102 and the center point C2, and the distance between the first display edge and the center point C2 may be approximately the same as the distance between the fifth border edge B103 and the center point C2.
  • the second center line O2 can divide the first border area B1 into a lower left border area and a lower right border area arranged along the second direction X.
  • the second center line O2 may pass through the center point of the first signal access area B14.
  • the center line of the first signal access area B14 extending along the first direction Y may coincide with the second center line O2.
  • this embodiment is not limited to this.
  • the center line of the first signal access area B14 extending along the first direction Y may coincide with the first center line O1.
  • the first frame edge B101 and the third frame edge B201 have a first distance L1 in the second direction X
  • the second frame edge B102 and the fourth frame edge B301 have a second distance L2 in the second direction X.
  • the first distance L1 is not equal to the second distance L2.
  • the first distance L1 may be smaller than the second distance L2.
  • the display substrate of this example has an asymmetric structure as a whole, and the second center line O2 of the first frame area B1 and the first center line O1 of the display area AA do not overlap.
  • the second center line O2 may be located on one side of the first center line O1 in the opposite direction of the second direction X.
  • the second center line O2 may be located on one side of the first center line O1 in the second direction X.
  • the bending region B12 may be provided with a set of signal bending lines, including multiple signal bending lines (e.g., multiple data bending lines, multiple first power bending lines, multiple second power bending lines, and multiple control bending lines).
  • the multiple signal bending lines may extend along a first direction Y and be arranged along a second direction X.
  • the orthographic projection of the set of signal bending lines on the substrate may have a fourth centerline O4 extending along the first direction Y.
  • the set of signal bending lines may be symmetrically arranged about the fourth centerline O4.
  • the fourth centerline O4 may coincide with the third centerline O3.
  • the third centerline O3 passes through the center point of the region corresponding to the orthographic projection of the set of signal bending lines on the substrate.
  • the region corresponding to the orthographic projection of the set of signal bending lines on the substrate may be substantially rectangular.
  • the orthographic projection of the group of signal meander lines on the substrate may include a first routing edge B121 and a second routing edge B122.
  • the first routing edge B121 may be an edge routing of the group of signal meander lines (e.g., the leftmost routing, such as the control bending line of the edge) close to the edge of the first frame edge B101
  • the second routing edge B122 may be an edge routing of the group of signal meander lines (e.g., the rightmost routing, such as the control bending line of the edge) close to the edge of the second frame left edge B102.
  • the first routing edge B121 and the second routing edge B122 may both extend approximately along the first direction Y.
  • the distance between the first routing edge B121 and the third center line O3 and the distance between the second routing edge B122 and the third center line O3 may be approximately the same.
  • the distance between the first routing edge B121 and the third center line O3 can be the sum of the line widths and spacings of multiple signal bending lines located on the side of the third center line O3 in the opposite direction of the second direction X; the distance between the second edge routing B122 and the third center line O3 can be the sum of the line widths and spacings of multiple signal bending lines located on the side of the third center line O3 in the second direction X.
  • the bending region B12 may be provided with: four groups of data bending lines (e.g., including a first group of data bending lines 311, a second group of data bending lines 312, a third group of data bending lines 313, and a fourth group of data bending lines 314), five groups of first power bending lines (e.g., including a first group of first power bending lines 321, a second group of first power bending lines 322, a third group of first power bending lines 323, a third group of first power bending lines 324, and a fifth group of first power bending lines 325), two groups of second power bending lines (e.g., including a first group of second power bending lines 331 and a second group of second power bending lines 332), and two groups of control bending lines (e.g., including a first group of control bending lines 341 and a second group of control bending lines 342).
  • FIG3 illustrates an overall view of each group of data bending lines
  • each group of data meander lines may include multiple data meander lines arranged along the second direction X.
  • the multiple data meander lines may have the same line width, and the spacing between adjacent data meander lines may be the same.
  • Each group of first power meander lines may include multiple first power meander lines arranged along the second direction X.
  • the multiple first power meander lines may have the same line width, and the spacing between adjacent first power meander lines may be the same.
  • Multiple first power meander lines within the same group of first power meander lines may be interconnected.
  • Each group of second power meander lines may include multiple second power meander lines arranged along the second direction X. The multiple second power meander lines may have the same line width, and the spacing between adjacent second power meander lines may be the same.
  • Each group of control meander lines may include multiple control meander lines arranged along the second direction X. Control meander lines transmitting the same signal may have the same line width, and the spacing between adjacent control meander lines may be the same.
  • the multiple signal meander lines within the bend region B12 may be located in the same conductive film layer, such as the second source/drain metal layer. However, this embodiment is not limited to this. For example, the multiple signal meander lines may be located in the first source/drain metal layer, or in the third source/drain metal layer.
  • the first group of control bending lines 341, the first group of second power bending lines 331, the fourth group of first power bending lines 324, the third group of data bending lines 313, the second group of first power bending lines 322, the first group of data bending lines 311, the first group of first power bending lines 321, the second group of data bending lines 312, the third group of first power bending lines 323, the fourth group of data bending lines 314, the fifth group of first power bending lines 325, the second group of second power bending lines 332, and the second group of control bending lines 342 can be arranged in sequence along the second direction X.
  • the plurality of data bending lines may be arranged symmetrically about the third centerline O3.
  • the number of data bending lines in the first group of data bending lines 311 and the number of data bending lines in the second group of data bending lines 312 may be the same, and the first group of data bending lines 311 and the second group of data bending lines 312 may be arranged symmetrically about the third centerline O3.
  • the number of data bending lines in the third group of data bending lines 313 and the number of data bending lines in the fourth group of data bending lines 314 may be the same, and the third group of data bending lines 313 and the fourth group of data bending lines 314 may be arranged symmetrically about the third centerline O3.
  • multiple first power fold lines can be symmetrically arranged about the third centerline O3.
  • the first group of first power fold lines 321 can be arranged symmetrically about the third centerline O3.
  • the number of first power fold lines in the second group of first power fold lines 322 can be the same as the number of first power fold lines in the third group of first power fold lines 323, and the second group of first power fold lines 322 and the third group of first power fold lines 323 can be arranged symmetrically about the third centerline O3.
  • the number of first power fold lines in the fourth group of first power fold lines 324 and the number of first power fold lines in the fifth group of first power fold lines 325 can be the same, and the fourth group of first power fold lines 324 and the fifth group of first power fold lines 325 can be arranged symmetrically about the third centerline O3.
  • the total length of the first group of first power zigzag lines 321 along the second direction X can be greater than the total length of the second group of first power zigzag lines 322 along the second direction X, and greater than the total length of the fourth group of first power zigzag lines 324 along the second direction X.
  • the total lengths of the second group of first power zigzag lines 322, the third group of first power zigzag lines 323, the fourth group of first power zigzag lines 324, and the fifth group of first power zigzag lines 325 along the second direction X can be substantially the same. However, this embodiment is not limited to this.
  • the total lengths of the second group of first power zigzag lines 322 and the third group of first power zigzag lines 323 along the second direction X can be substantially the same
  • the total lengths of the fourth group of first power zigzag lines 324 and the fifth group of first power zigzag lines 325 along the second direction X can be substantially the same
  • the total lengths of the second group of first power zigzag lines 322 and the fourth group of first power zigzag lines 324 along the second direction X can be different.
  • the total length of the group of first power bending lines along the second direction may include: the line widths of the N first power bending lines in the group of first power bending lines and the sum of the lengths of N-1 adjacent intervals.
  • the plurality of second power meander lines may be symmetrically arranged about the third center line O3.
  • the number of second power meander lines in the first group of second power meander lines 331 and the number of second power meander lines in the second group of second power meander lines 332 may be the same, and the first group of second power meander lines 331 and the second group of second power meander lines 332 may be symmetrically arranged about the third center line O3.
  • multiple control bending lines can be arranged symmetrically about the third centerline O3.
  • the number of control bending lines in the first group of control bending lines 341 and the number of control bending lines in the second group of control bending lines 342 can be the same, and the first group of control bending lines 341 and the second group of control bending lines 342 can be arranged symmetrically about the third centerline O3.
  • the control bending lines in the first group of control bending lines 341 or the second group of control bending lines 342 can include: active control bending lines and inactive control bending lines.
  • inactive control bending lines can be provided to ensure that the number of control bending lines in the first group of control bending lines 341 and the second group of control bending lines 342 are the same and that they are arranged symmetrically about the third centerline O3.
  • the third center line O3 may coincide with the second center line O2.
  • the plurality of signal bending lines of the bending area B12 may be symmetrically arranged about the second center line O2.
  • the minimum distance between the first trace edge B121 and the first frame edge B101 is a first edge distance a
  • the minimum distance between the second trace edge B122 and the second frame edge B102 is a second edge distance b.
  • the ratio of the first edge distance a to the second edge distance b can be 0.9 to 1.1.
  • the first edge distance a can be equal to the second edge distance b.
  • the first edge distance a can be greater than or equal to 0.4 mm
  • the second edge distance b can be greater than or equal to 0.4 mm.
  • the signal bending line of the bending area B12 is set symmetrically about the second center line O2, and the first edge distance a and the second edge distance b are roughly the same, which can reduce the wiring differences within the lower left frame and the lower right frame, and is conducive to reducing the transmission load differences of the same signal in the lower left frame and the lower right frame.
  • Figure 4 is a partially enlarged schematic diagram of area S1 in Figure 3 .
  • Figure 4 provides an overall schematic diagram of the first group of data meander lines 311, the second group of data meander lines 312, and the first group of first power meander lines 321.
  • the multiple data lines in display area AA can be divided into a first group of data lines DL1a and a second group of data lines DL1b based on a first center line O1.
  • the number of data lines in the first group of data lines DL1a and the number of data lines in the second group of data lines DL1b can be the same.
  • the first group of data lines DL1a and the second group of data lines DL1b can be arranged symmetrically about the first center line O1.
  • the multiple data lines can be located in the second source/drain metal layer or the third source/drain metal layer.
  • the first sub-area B11 may be provided with a plurality of first data fan-out lines.
  • the plurality of first data fan-out lines may include a first group of first data fan-out lines 211 and a second group of first data fan-out lines 212.
  • the first group of first data fan-out lines 211 may be connected to the first group of data lines DLa
  • the second group of first data fan-out lines 212 may be connected to the second group of data lines DLb.
  • the first group of first data fan-out lines 211 may include a plurality of first data fan-out lines 21a, and the plurality of first data fan-out lines 21a may be electrically connected to the plurality of data lines in the first group of data lines DLa in a one-to-one correspondence.
  • the second group of first data fan-out lines 212 may include a plurality of first data fan-out lines 21b, and the plurality of second data fan-out lines 21b may be electrically connected to the plurality of data lines in the second group of data lines DLb in a one-to-one correspondence.
  • the plurality of first data fan-out lines may be alternately arranged in the first gate metal layer and the second gate metal layer, and the orthographic projections of adjacent first data fan-out lines on the substrate may not overlap.
  • the first data fan-out line 21a may include a first data extension segment 21-1a and a second data extension segment 21-2a that are interconnected.
  • the second data extension segment 21-2a may be connected to at least one data bend line within a set of data bend lines (e.g., the first set of data bend lines 311).
  • the first data extension segment 21-1a may be located on a side of the second data extension segment 21-2a that is closer to the display area AA.
  • the second data extension segment 21-2a may be a straight line segment extending along the first direction Y.
  • the extension direction of the first data extension segment 21-1a may intersect the first direction Y.
  • the first data extension segment 21-1a may be an oblique line segment whose extension direction intersects both the first direction Y and the second direction X.
  • the first data fan-out line 21b may include a first data extension segment 21-1b and a second data extension segment 21-2b that are interconnected.
  • the second data extension segment 21-2b may be connected to at least one data bend line within a set of data bend lines (e.g., the second set of data bend lines 312).
  • the first data extension segment 21-1b may be located on a side of the second data extension segment 21-2b that is closer to the display area AA.
  • the second data extension segment 21-2b may be a straight line segment extending along the first direction Y.
  • the extension direction of the first data extension segment 21-1b may intersect the first direction Y.
  • the first data extension segment 21-1b may be an oblique line segment whose extension direction intersects both the first direction Y and the second direction X.
  • the length of the first data extension segment 21-1a of at least one first data fan-out line (e.g., first data fan-out line 21a) near the first center line O1 and located on a first side (e.g., the left side) of the first center line O1 can be greater than the length of the first data extension line 21-1b of at least one first data fan-out line (e.g., first data fan-out line 21b) near the first center line O1 and located on a second side (e.g., the right side) of the first center line O1.
  • the length of the second data extension segment 21-2a of the at least one first data fan-out line 21a near the first center line O1 can be less than the length of the second data extension line 21-2b of the at least one first data fan-out line 21b near the first center line O1.
  • the symmetric center lines of the data bending lines in the bending area B12 can be moved toward the side opposite to the first center line O1 along the second direction X.
  • the symmetric center lines of multiple data bending lines in the bending area B12 i.e., the third center line O3 can be made to coincide with the second center line O2.
  • the second sub-area B13 may be provided with multiple data lead lines.
  • the multiple data lead lines may include at least: a first group of data lead lines 411 and a second group of data lead lines 412.
  • the first group of data lead lines 411 may be connected to the first group of data meander lines 311, and the second group of data lead lines 412 may be connected to the second group of data meander lines 312.
  • the number of data lead lines located on both sides of the second center line O2 may be the same, and the data lead lines located on both sides of the second center line O2 may not be arranged symmetrically about the second center line O2.
  • the multiple data lead lines may be arranged alternately in the first gate metal layer and the second gate metal layer, and the orthographic projections of adjacent data lead lines on the substrate may not overlap.
  • this embodiment is not limited to this.
  • the data lead lines located on both sides of the second center line O2 may be arranged symmetrically about the second center line O2.
  • the multiple signal bending lines in bending region B12 can be arranged symmetrically about the third centerline O3, and the third centerline O3 can coincide with the second centerline O2. This ensures consistency of the signal bending lines in the regions on both sides of the second centerline O2, thereby ensuring a good bending effect. For example, this arrangement can ensure that the routing loads of the same signal within the bending regions on both sides of the second centerline O2 are consistent, thereby avoiding display issues caused by inconsistent signal loads.
  • the multiple first data fan-out lines within the first sub-area B11 are not symmetrically arranged about the second center line O2 and the multiple data lead lines within the second sub-area B13 are not symmetrically arranged about the second center line O2.
  • the multiple data contact pads provided in the first signal access area B14 can be symmetrically arranged about the second center line O2, and the multiple data lead lines can be connected to the multiple data contact pads.
  • a data load compensation structure can be provided in the second sub-area B13 to achieve load uniformity for data signals transmitted in the first border area.
  • the second sub-area B13 may include a second fan-out area and a third fan-out area.
  • the plurality of data lead lines may include: a plurality of second data fan-out lines located in the second fan-out area and a plurality of third data fan-out lines located in the third fan-out area.
  • the data load compensation structure may be located in at least one of the second and third fan-out areas of the second sub-area.
  • the data load compensation structure may be connected in series with the data lead lines in the second sub-area.
  • the data load compensation structure may be located in the second fan-out area and connected in series with the second data fan-out line, or located in the third fan-out area and connected in series with the third data fan-out line.
  • the data load compensation structure may be a serpentine trace, which increases resistance by increasing the length of the data lead line.
  • a serpentine trace is a meandering curve. For example, one end of the trace extends a certain distance in one direction, then bends and twists and extends a certain distance in the opposite direction, then bends and twists again to extend in the same direction, and repeats this process several times to form a serpentine trace.
  • the resistance of the data lead lines in the second sub-region can be increased by thinning them to achieve load compensation.
  • the resistance of the data lead lines in the second sub-region can be increased by increasing the number of jumpers between multiple segments to achieve load compensation.
  • the resistance of the data lead lines in the second sub-region can be increased by placing them in a conductive layer with a higher resistivity.
  • the resistance can be reduced by increasing the line width of the data lead lines in the second sub-region to perform load compensation.
  • the resistance can be reduced by configuring the data lead lines in the second sub-region as double-layer or multi-layer routing.
  • the resistance can be reduced by configuring the data lead lines in the second sub-region as a conductive layer with a lower resistivity. This embodiment does not limit the load compensation method for the data signal in the first border region.
  • Figure 5 is another partial structural diagram of the first border region of at least one embodiment of the present disclosure.
  • Figure 6 is a partial wiring diagram of the first border region of at least one embodiment of the present disclosure.
  • Figures 5 and 6 collectively illustrate each set of data bending lines, each set of first power bending lines, each set of second power bending lines, each set of control bending lines, and each set of touch bending lines in the bending region B12.
  • the bending area B12 can be provided with: four groups of data bending lines (for example, including a first group of data bending lines 311, a second group of data bending lines 312, a third group of data bending lines 313 and a fourth group of data bending lines 314), three groups of first power bending lines (for example, including a first group of first power bending lines 321, a second group of first power bending lines 322 and a third group of first power bending lines 323), four groups of second power bending lines (for example, including a first group of second power bending lines 331, a second group of second power bending lines 332, a third group of second power bending lines 333 and a fourth group of second power bending lines 334), two groups of control bending lines (for example, including a first group of control bending lines 341 and a second group of control bending lines 342), and two groups of touch bending lines (for example, including a first group of touch bending lines 351
  • the multiple signal bending lines within the bending area B12 can have a fourth center line O4 extending along the first direction Y, the fourth center line O4 can coincide with the third center line O3, the multiple signal bending lines within the bending area B12 can be symmetrically arranged about the third center line O3, and the third center line O3 can coincide with the second center line O2.
  • the first group of control bending lines 341, the third group of second power bending lines 333, the first group of touch bending lines 351, the first group of second power bending lines 331, the third group of data bending lines 313, the second group of first power bending lines 322, the first group of data bending lines 311, the first group of first power bending lines 321, the second group of data bending lines 312, the third group of first power bending lines 323, the fourth group of data bending lines 314, the second group of second power bending lines 332, the second group of touch bending lines 351, the fourth group of second power bending lines 334, and the second group of control bending lines 342 can be arranged in sequence along the second direction X.
  • the first sub-region B11 may be provided with a plurality of first data fan-out lines, a first peripheral power line 22, second peripheral power lines 231 and 232, and a plurality of peripheral control lines (e.g., including a first group of peripheral control lines 241 and a second group of peripheral control lines 242).
  • the plurality of first data fan-out lines may include a first group of first data fan-out lines, a second group of first data fan-out lines, a third group of first data fan-out lines 213, and a fourth group of first data fan-out lines 214.
  • the third group of first data fan-out lines 213, the first group of first data fan-out lines, the second group of first data fan-out lines, and the fourth group of first data fan-out lines 214 may be arranged sequentially along the second direction X.
  • the first group of first data fan-out lines may be connected to the first group of data bending lines 311, the second group of first data fan-out lines may be connected to the second group of data bending lines 312, the third group of first data fan-out lines 213 may be connected to the third group of data bending lines 313, and the fourth group of first data fan-out lines 214 may be connected to the fourth group of data bending lines 314.
  • the plurality of first data fan-out lines may be alternately arranged in the first gate metal layer and the second gate metal layer, or may all be located in the first gate metal layer, or may all be located in the second gate metal layer.
  • the first peripheral power line 22 can be a single-layer trace located in the first source-drain metal layer, or can be a single-layer trace located in the second source-drain metal layer, or can be a double-layer trace located in the first source-drain metal layer and the second source-drain metal layer.
  • the first peripheral power line 22 may include a first power main body extending along the second direction X and a plurality of first power connection portions (for example, three first connection portions) extending along the first direction Y.
  • the three first power connection portions can be electrically connected to three groups of first power bending lines (for example, including a first group of first power bending lines 321, a second group of first power bending lines 322, and a third group of first power bending lines 323) in a one-to-one correspondence.
  • a first power connection portion and a corresponding group of first power bending lines can be an integrated structure connected to each other.
  • the first peripheral power line 22 can be roughly symmetrical about the third center line O3.
  • the second peripheral power lines 231 and 232 may be located on a side of the first power main portion of the first peripheral power line 22 that is away from the display area AA.
  • the second peripheral power line 231 may extend toward the second border area B2, and the second peripheral power line 232 may extend toward the third border area B3.
  • the second peripheral power line 231 may be located on one side of the third centerline O3, and the second peripheral power line 232 may be located on the other side of the third centerline O3.
  • the second peripheral power lines 231 and 232 may be substantially symmetrical about the third centerline O3.
  • the second peripheral power line 231 may be connected to the first group of second power meander lines 331 and the third group of second power meander lines 333.
  • the second peripheral power line 232 may be connected to the second group of second power meander lines 332 and the fourth group of second power meander lines 334.
  • the second peripheral power lines 231 and 232 may be single-layer traces located in the first source/drain metal layer, single-layer traces located in the second source/drain metal layer, or double-layer traces located in both the first source/drain metal layer and the second source/drain metal layer.
  • the first group of peripheral control lines 241 can be located on one side of the third center line O3, and the second group of peripheral control lines 242 can be located on the other side of the third center line O3.
  • the first group of peripheral control lines 241 can extend toward the second border area B2, and the second group of peripheral control lines 242 can extend toward the third border area B3.
  • the first group of peripheral control lines 241 can be connected to the first group of control bending lines 341, and the second group of peripheral control lines 242 can be connected to the second group of control bending lines 342.
  • the multiple peripheral control lines can be located on a side of the second peripheral power lines 231 and 232 that is close to the substrate, for example, in the first gate metal layer or the second gate metal layer.
  • the second sub-area B13 may be provided with a first power lead 42, second power lead 431 and 432, a plurality of control lead 441 and a second control lead 442, and a plurality of data lead 413 and a fourth data lead 414.
  • the third data lead 413, the first data lead, the second data lead, and the fourth data lead 414 may be arranged along the second direction X.
  • the first data lead may be connected to the first data meandering line 311
  • the second data lead may be connected to the second data meandering line 312
  • the third data lead 413 may be connected to the third data meandering line 313, and the fourth data lead 414 may be connected to the fourth data meandering line 314.
  • the first group of data bending lines 311 can electrically connect the first group of first data fan-out lines to the first group of data lead-out lines
  • the second group of data bending lines 312 can electrically connect the second group of first data fan-out lines to the second group of data lead-out lines
  • the third group of data bending lines 313 can electrically connect the third group of first data fan-out lines to the third group of data lead-out lines
  • the fourth group of data bending lines 314 can electrically connect the fourth group of first data fan-out lines to the fourth group of data lead-out lines.
  • the multiple data lead-out lines can be alternately arranged in the first gate metal layer and the second gate metal layer, or can all be arranged in the first gate metal layer, or can all be arranged in the second gate metal layer.
  • the first power lead 42 may include: a second power main body 420 extending along the second direction X; a first power extension 421 and a second power extension 422 extending along the first direction Y and located on the side of the second power main body 420 away from the bending region B12; and multiple second power connection portions (e.g., including three second power connection portions) extending along the second direction Y and located on the side of the second power main body 420 closer to the bending region B12.
  • the second power main body 420, the first power extension 421, the second power extension 422, and the multiple second power connection portions may be interconnected and integrally formed.
  • the first power lead 42 may be substantially symmetrical about the third centerline O3.
  • the first power extension 421 is connected to one end of the second power main body 420 in the second direction X, and the second power extension 422 is connected to the other end of the second power main body 420 in the second direction X.
  • the first power extension portion 421 can extend from the first signal access area B14 on one side (e.g., the left side) opposite to the second direction X, bypassing the first signal access area B14, and extending to the second signal access area B15, thereby connecting to the second contact pad within the second signal access area B15.
  • the second power extension portion 422 can extend from the first signal access area B14 on the other side (e.g., the right side) of the first signal access area B14, bypassing the first signal access area B14, and extending to the second signal access area B15, thereby connecting to the second contact pad within the second signal access area B15.
  • the three second power connectors can be electrically connected to the first group of first power meander lines 321, the second group of first power meander lines 322, and the third group of first power meander lines 323 in a one-to-one correspondence, thereby achieving electrical connection with the first peripheral power lines 22 within the first sub-area B11.
  • the first power lead 42 can be a single-layer trace located in the first source/drain metal layer, a single-layer trace located in the second source/drain metal layer, or a double-layer trace located in both the first source/drain metal layer and the second source/drain metal layer.
  • the second power lead 431 can be located on one side of the first power lead 42 in the opposite direction of the second direction X, and the second power lead 432 can be located on one side of the first power lead 42 in the second direction X.
  • the second power lead 431 can be connected to the first group of second power meandering lines 331 and the third group of second power meandering lines 333 to achieve electrical connection with the second peripheral power lines 231 in the first sub-region B11; the second power lead 432 can be connected to the second group of second power lead 332 and the fourth group of second power lead 334 to achieve electrical connection with the second peripheral power lines 232 in the first sub-region B11.
  • the second power lead 431 and the second power lead 432 can be substantially symmetrical about the third centerline O3.
  • the second power lead lines 431 and 432 can be single-layer lines located in the first source-drain metal layer, or can be single-layer lines located in the second source-drain metal layer, or can be double-layer lines located in the first source-drain metal layer and the second source-drain metal layer.
  • the first power lead 42 is configured to transmit a first voltage signal
  • the second power lead 431 and 432 are configured to transmit a second voltage signal.
  • the first voltage signal is different from the second voltage signal.
  • the first voltage signal can be greater than the second voltage signal.
  • the first voltage signal can be configured to be provided to the pixel circuit of the sub-pixel in the display area
  • the second voltage signal can be configured to be provided to the cathode of the light-emitting element of the sub-pixel in the display area. This embodiment is not limited to this.
  • the first group of control lead lines 441 can be connected to the first group of control meandering lines 341 to achieve electrical connection with the first group of peripheral control lines 241 within the first sub-region B11; the second group of control lead lines 442 can be connected to the second group of control meandering lines 342 to achieve electrical connection with the second group of peripheral control lines 242 within the first sub-region B11.
  • the multiple control lead lines can include: lines that provide signals (such as start signals, clock signals, voltage signals, etc.) to the gate drive circuit, lines that transmit panel test signals, etc.
  • the signal bending lines of the bending area B12 of this example can be symmetrically arranged about the third center line O3, and the third center line O3 can coincide with the second center line O2.
  • the first edge distance a and the second edge distance b are roughly the same, which can ensure the density of the routing and the consistency of the film layer of the bending area B12 in the area on both sides of the second center line O2, so as to ensure the bending performance.
  • This example can ensure the load consistency of the signals transmitted by the first group of control bending lines 341 and the second group of control bending lines 342, avoiding display problems caused by inconsistent signal loads on both sides.
  • This example can also ensure the transmission load consistency of the first voltage signal and the second voltage signal on both sides of the second center line.
  • This example can also ensure that the space of the first border area is maximized.
  • FIG7 is another partial schematic diagram of the first border region of at least one embodiment of the present disclosure.
  • the bending region B12 may be provided with: four groups of data bending lines (e.g., a first group of data bending lines 311, a second group of data bending lines 312, a third group of data bending lines 313, and a fourth group of data bending lines 314), three groups of first power bending lines (e.g., a first group of first power bending lines 321, a second group of first power bending lines 322, and a third group of first power bending lines 323), two groups of second power bending lines (e.g., a first group of second power bending lines 331 and a second group of second power bending lines 332), and two groups of control bending lines (e.g., a first group of control bending lines 341 and a second group of control bending lines 342).
  • four groups of data bending lines e.g., a first group of data bending lines 311, a second group of
  • the first group of control bending lines 341, the first group of second power bending lines 331, the third group of data bending lines 313, the second group of first power bending lines 322, the first group of data bending lines 311, the first group of first power bending lines 321, the second group of data bending lines 312, the third group of first power bending lines 323, the fourth group of data bending lines 314, the second group of second power bending lines 332 and the second group of control bending lines 342 can be arranged in sequence along the second direction X.
  • the first group of data bending lines 311 and the second group of data bending lines 312 can be symmetrically arranged about the third center line O3
  • the second group of data bending lines 313 and the fourth group of data bending lines 314 can be symmetrically arranged about the third center line O3
  • the first group of first power bending lines 321 can be symmetrically arranged about the third center line O3
  • the second group of first power bending lines 322 and the third group of first power bending lines 323 can be symmetrically arranged about the third center line O3
  • the first group of second power bending lines 331 and the second group of second power bending lines 332 can be symmetrically arranged about the third center line O3
  • the first group of control bending lines 341 and the second group of control bending lines 342 can be symmetrically arranged about the third center line O3.
  • the fourth centerline O4 coincides with the third centerline O3.
  • the third centerline O3 may coincide with the second centerline O2.
  • the first edge distance a and the second edge distance b may be substantially the same.
  • wiring differences within the lower left and right borders can be reduced, thereby facilitating reduced transmission load differences for the same signal within the lower left and right borders.
  • FIG8 is another partial schematic diagram of the first border region of at least one embodiment of the present disclosure.
  • FIG9 is a partial enlarged schematic diagram of region S2 in FIG8 .
  • the multiple signal bending lines in bending region B12 may include: four groups of data bending lines (e.g., a first group of data bending lines 311, a second group of data bending lines 312, a third group of data bending lines 313, and a fourth group of data bending lines 314), five groups of first power bending lines (e.g., a first group of first power bending lines 321, a second group of first power bending lines 322, a third group of first power bending lines 323, a fourth group of first power bending lines 324, and a fifth group of first power bending lines 325), two groups of second power bending lines (e.g., a first group of second power bending lines 331, a second group of second power bending lines 332), and two groups of control bending lines (e.g., a first group of
  • the first group of control bending lines 342, the first group of second power bending lines 331, the fourth group of first power bending lines 324, the third group of data bending lines 313, the second group of first power bending lines 322, the first group of data bending lines 311, the first group of first power bending lines 321, the second group of data bending lines 313, the third group of first power bending lines 323, the fourth group of data bending lines 314, the fifth group of first power bending lines 325, the second group of second power bending lines 332 and the second group of control bending lines 342 can be arranged in sequence along the second direction X.
  • the multiple signal meander lines in the bend region B12 may have a fourth centerline O4 extending along the first direction Y, and the fourth centerline O4 may coincide with the third centerline O3.
  • the multiple signal meander lines may be symmetrically arranged about the third centerline O3.
  • the orthographic projection of the lines in the bend region B12 onto the substrate may have a first line edge B121 and a second line edge B122 extending along the first direction Y.
  • the first line edge B121 may be the left edge of the line
  • the second line edge B122 may be the right edge of the line.
  • the distance between the third centerline O3 and the first line edge B121 and the distance between the third centerline O3 and the second line edge B122 may be the same.
  • the distance between the third centerline O3 and the second centerline O2 in the second direction X may be greater than zero.
  • the third centerline O3 and the second centerline O2 may not overlap.
  • the third centerline O3 may be located between the second centerline O2 and the first centerline O1.
  • the distance between the third centerline O3 and the first centerline O1 may be the same as or different from the distance between the third centerline O3 and the second centerline O2.
  • the first centerline O1 may be located on one side of the second centerline O2 in the second direction X.
  • this embodiment is not limited to this.
  • the third centerline O3 may overlap with the first centerline O1.
  • the minimum distance between the first trace edge B121 and the first frame edge B101 is a first edge distance a
  • the minimum distance between the second trace edge and the second frame edge B102 is a second edge distance b.
  • the first edge distance a can be different from the second edge distance b.
  • the ratio of the first edge distance a to the second edge distance b can be greater than 1.
  • the first edge distance a can be greater than the second edge distance b.
  • the first edge distance a can be greater than or equal to 0.4 mm
  • the second edge distance b can be greater than or equal to 0.4 mm.
  • the first sub-area B11 may be provided with a plurality of first data fan-out lines.
  • the plurality of first data fan-out lines may include a first group of first data fan-out lines 211 and a second group of first data fan-out lines 212.
  • the first group of first data fan-out lines 211 may be connected to the first group of data lines DLa
  • the second group of first data fan-out lines 212 may be connected to the second group of data lines DLb.
  • the first group of first data fan-out lines 211 may include a plurality of first data fan-out lines 21a, and the plurality of first data fan-out lines 21a may be electrically connected to the plurality of data lines in the first group of data lines DLa in a one-to-one correspondence.
  • the second group of first data fan-out lines 212 may include a plurality of first data fan-out lines 21b, and the plurality of second data fan-out lines 21b may be electrically connected to the plurality of data lines in the second group of data lines DLb in a one-to-one correspondence.
  • the first data fan-out line 21a may include a first data extension segment 21-1a and a second data extension segment 21-2a connected to each other.
  • the second data extension segment 21-2a may be connected to at least one data bend line within a set of data bend lines (e.g., the first set of data bend lines 311).
  • the first data extension segment 21-1a may be located on a side of the second data extension segment 21-2a closer to the display area AA.
  • the second data extension segment 21-2a may be a straight line segment extending along the first direction Y.
  • the extension direction of the first data extension segment 21-1a may intersect the first direction Y.
  • the first data extension segment 21-1a may be an oblique line segment whose extension direction intersects both the first direction Y and the second direction X.
  • the first data fan-out line 21b may include a first data extension segment 21-1b and a second data extension segment 21-2b connected to each other.
  • the second data extension segment 21-2b may be connected to at least one data bend line within a set of data bend lines (e.g., the second set of data bend lines 312).
  • the first data extension segment 21-1b may be located on a side of the second data extension segment 21-2b closer to the display area AA.
  • the second data extension segment 21-2b may be a straight line segment extending along the first direction Y.
  • the extension direction of the first data extension segment 21-1b may intersect the first direction Y.
  • the first data extension segment 21-1b may be an oblique line segment whose extension direction intersects both the first direction Y and the second direction X.
  • the length of the first data extension segment 21-1a of at least one first data fan-out line 21a near the first center line O1 can be greater than the length of the first data extension segment 21-1b of at least one first data fan-out line 21b near the first center line O1.
  • the length ratio of the first data extension segment 21-1a of the first data fan-out line 21a to the first data extension segment 21-b of the first data fan-out line 21b can be smaller than the length ratio of the first data extension segment 21-1a of the first data fan-out line 21a to the first data extension segment 21-b of the first data fan-out line 21b in the embodiment shown in FIG. 4 , thereby reducing the load difference between the first data fan-out lines on both sides of the first center line O1.
  • the routing of the bending area B12 can be arranged roughly symmetrically about the third center line O3.
  • the third center line O3 can be located between the second center line O2 and the first center line O1, reducing the load difference between the first data fan-out lines in the first sub-area B11, thereby facilitating the compensation of the data signal and helping to achieve load consistency of the data signal.
  • This example can reduce the wiring differences within the lower left and lower right borders, which is beneficial to reducing the transmission load differences of the same signal within the lower left and lower right borders. The remaining description of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.
  • Figure 10 is another partial schematic diagram of the first border area of at least one embodiment of the present disclosure.
  • Figure 11 is a partial enlarged schematic diagram of area S3 in Figure 10.
  • the first distance L1 can be greater than the second distance L2
  • the first centerline O2 can be located on one side of the first centerline O1 in the second direction X.
  • the left and right alignments of the third centerline O3 in the bending area B12 can be arranged roughly symmetrically.
  • the third centerline O3 can be located between the first centerline O1 and the second centerline O2.
  • the fourth centerline O4 can coincide with the third centerline O3.
  • a ratio of the second edge distance b to the first edge distance a may be greater than 1. In other words, the second edge distance b may be greater than the first edge distance a.
  • the length of the first data extension segment 21-1a of the at least one first data fan-out line 21a near the first center line O1 may be shorter than the length of the first data extension line 21-1b of the at least one first data fan-out line 21b near the first center line O1.
  • the length of the second data extension segment 21-2a of the at least one first data fan-out line 21a near the first center line O1 may be longer than the length of the second data extension line 21-2b of the at least one first data fan-out line 21b near the first center line O1.
  • the routing of the bending area B12 can be arranged roughly symmetrically about the third center line O3.
  • the third center line O3 can be located between the second center line O2 and the first center line O1 (or coincide with the first center line O1), reducing the load difference between the first data fan-out lines in the first sub-area B11, thereby facilitating the compensation of the data signal, and can be beneficial to achieving load consistency of the data signal.
  • This example can reduce the wiring differences within the lower left frame and the lower right frame, which is beneficial to reducing the transmission load difference of the same signal within the lower left frame and the lower right frame.
  • the remaining description of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.
  • Figure 12 is another partial schematic diagram of the first border region of at least one embodiment of the present disclosure.
  • Figure 13 is a partial enlarged schematic diagram of region S4 in Figure 12.
  • the first centerline O1 can be located on one side of the second centerline O2 in the second direction X.
  • the multiple signal bending lines in the bending area B12 may include: four groups of data bending lines (for example, including a first group of data bending lines 311, a second group of data bending lines 312, a third group of data bending lines 313 and a fourth group of data bending lines 314), five groups of first power bending lines (for example, including a first group of first power bending lines 321, a second group of first power bending lines 322, a third group of first power bending lines 323, a fourth group of first power bending lines 324 and a fifth group of first power bending lines 325), two groups of second power bending lines (for example, including a first group of second power bending lines 331, a second group of second power bending lines 332), and two groups of control bending lines (for example, including a first group of control bending lines 341 and a second group of control bending lines 342).
  • four groups of data bending lines for example, including a first group of data bending lines 311, a second group of data
  • the first group of control bending lines 342, the first group of second power bending lines 331, the fourth group of first power bending lines 324, the third group of data bending lines 313, the second group of first power bending lines 322, the first group of data bending lines 311, the first group of first power bending lines 321, the second group of data bending lines 313, the third group of first power bending lines 323, the fourth group of data bending lines 314, the fifth group of first power bending lines 325, the second group of second power bending lines 332 and the second group of control bending lines 342 can be arranged in sequence along the second direction X.
  • the total length of the first group of first power meander lines 321 along the second direction X may be less than the total length of the first group of first power meander lines along the second direction X in the embodiment shown in FIG8 .
  • the total length along the second direction X may be reduced by reducing the number of first power meander lines in the first group of first power meander lines, or by reducing the spacing between adjacent first power meander lines in the first group of first power meander lines, or by reducing the line width and spacing of the first power meander lines in the first group of first power meander lines. This embodiment is not limited to this.
  • the multiple signal bending lines in the bending region may have a fourth centerline O4 extending along the first direction Y.
  • the multiple signal bending lines may be symmetrically arranged about the fourth centerline O4.
  • the fourth centerline O4 may coincide with the third centerline O3, and the third centerline O3 may coincide with the first centerline O1.
  • the multiple first data fan-out lines within the first sub-region B11 may be symmetrically arranged about the first centerline O1.
  • the multiple first data fan-out lines 21a and the multiple first data fan-out lines 21b may be symmetrically arranged about the first centerline O1.
  • the first group of data lead lines 411 and the second group of data lead lines 412 may be symmetrically arranged about the first centerline O1.
  • the third centerline O3 can be made to coincide with the first centerline O1.
  • This example allows the multiple first data fan-out lines within the first sub-region B11 to be roughly symmetrical about the first centerline O1, thereby ensuring data signal load consistency within the first sub-region.
  • the symmetrical arrangement of the group of signal bending lines in this example about the first centerline O1 can help reduce wiring differences within the lower left and right borders, and thus help reduce differences in transmission load for the same signal within the lower left and right borders.
  • FIG14 is another partial schematic diagram of the first border region according to at least one embodiment of the present disclosure.
  • the first centerline O1 can be located on one side of the second centerline O2 in the second direction X.
  • the multiple signal bending lines in the bending region B12 can include: four groups of data bending lines (e.g., a first group of data bending lines 311, a second group of data bending lines 312, a third group of data bending lines 313, and a fourth group of data bending lines 314); five groups of first power bending lines (e.g., a first group of first power bending lines 321, a second group of first power bending lines 322, a third group of first power bending lines 323, a fourth group of first power bending lines 324, and a fifth group of first power bending lines 325); two groups of second power bending lines (e.g., a first group of second power bending lines 331 and a second group of second power bending lines 332); and two groups of data bending lines (
  • the first group of control bending lines 342, the first group of second power bending lines 331, the fourth group of first power bending lines 324, the third group of data bending lines 313, the second group of first power bending lines 322, the first group of data bending lines 311, the first group of first power bending lines 321, the second group of data bending lines 313, the third group of first power bending lines 323, the fourth group of data bending lines 314, the fifth group of first power bending lines 325, the second group of second power bending lines 332 and the second group of control bending lines 342 can be arranged in sequence along the second direction X.
  • the length of the orthographic projection of the fourth group of first power bending lines 324 on the substrate along the second direction X may be greater than the length of the orthographic projection of the first group of first power bending lines 321 on the substrate along the second direction X; the length of the orthographic projection of the first group of first power bending lines 321 on the substrate along the second direction X may be greater than the length of the orthographic projection of the second group of first power bending lines 322, the third group of first power bending lines 323, and the fifth group of first power bending lines 325 on the substrate along the second direction X.
  • the total length of the fourth group of first power supply bending lines 324 along the second direction X can be increased by at least one of the following methods: increasing the number of first power supply bending lines in the fourth group of first power supply bending lines 324, increasing the spacing between adjacent first power supply bending lines in the fourth group of first power supply bending lines 324, or increasing the width of the first power supply bending lines in the fourth group of first inner power supply bending lines 324.
  • this embodiment is not limited to this.
  • the multiple power bending lines in the bending region may include: multiple first power bending lines and multiple second power bending lines.
  • the first group of power bending lines located on one side of the third centerline O3 may include: a second group of first power bending lines 322, a fourth group of first power bending lines 324, half of the first group of first power bending lines 321, and a first group of second power bending lines 331.
  • the second group of power bending lines located on the other side of the third centerline O3 may include: a third group of first power bending lines 323, a fifth group of first power bending lines 325, half of the first group of first power bending lines 321, and a second group of second power bending lines 332.
  • the length of the first group of power bending lines along the second direction X is increased to be greater than the length of the second group of power bending lines along the second direction X.
  • this embodiment is not limited to this.
  • the length of the first group of second power bending lines 331 along the second direction X may be increased so that the length of the first group of second power bending lines along the second direction X is greater than the length of the second group of power bending lines along the second direction X.
  • multiple data bending lines among the multiple signal bending lines may be symmetrically arranged about the third centerline O3.
  • the multiple signal bending lines may have a fourth centerline O4 extending along the first direction Y.
  • the fourth centerline O4 may be located on a side of the third centerline O3 closer to the second centerline O2.
  • the fourth centerline O4 may coincide with the second centerline O2.
  • the multiple signal bending lines may be asymmetrically arranged about the fourth centerline O4.
  • the third centerline O3 is a line of symmetry for multiple sets of data bending lines.
  • the third centerline O3 may coincide with the first centerline O1.
  • the first set of data bending lines 311 and the second set of data bending lines 312 may be substantially symmetrical about the first centerline O1
  • the third set of data bending lines 313 and the fourth set of data bending lines 314 may be substantially symmetrical about the first centerline O1.
  • the multiple data fan-out lines within the first sub-area B11 can be symmetrically arranged about the first centerline O1, thereby reducing load differences between the first data fan-out lines on both sides of the first centerline O1 within the first sub-area B11, thereby facilitating load consistency for data signals.
  • the first group of control bending lines 341 and the second group of control bending lines 342 are not symmetrically arranged about the third centerline O3, and the first group of second power bending lines 331 and the second group of second power bending lines 332 are not symmetrically arranged about the third centerline O3.
  • the first group of control bending lines 341 and the second group of control bending lines 342 can be symmetrically arranged about the second centerline O2, and the first group of second power bending lines 331 and the second group of second power bending lines 332 can be symmetrically arranged about the second centerline O2.
  • the ratio of the first edge distance a to the second edge distance b can be 0.9 to 1.1.
  • the first edge distance a and the second edge distance b can be substantially the same. This can help improve the routing uniformity within the bending area and ensure the bending effect.
  • first edge distance and the second edge distance can be made substantially equal, thereby reducing wiring differences within the lower left and right frames, and facilitating reducing transmission load differences for the same signal within the lower left and right frames.
  • the lengths of the fourth group of first power bending lines and the first group of second power bending lines along the second direction can be increased so that the multiple groups of data bending lines are symmetrically arranged about the first center line and the first edge distance and the second edge distance are approximately the same.
  • the multiple groups of data bending lines can be symmetrically arranged about the first center line and the first edge distance and the second edge distance can be approximately the same by reducing the length of at least one of the fifth group of first power bending lines and the second group of second power bending lines along the second direction.
  • multiple groups of data bend lines can be symmetrically arranged about the first center line, and the first edge distance and the second edge distance can be approximately the same.
  • Figure 15 is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • the display area AA may be provided with multiple data lines DL and multiple data transfer lines 25.
  • At least one data line DL may be connected to the first data fan-out line of the first sub-area B11 via the data transfer line 25.
  • the data transfer line 25 may include a first transfer segment 251 extending along the second direction X and a second transfer segment 252 extending along the first direction Y.
  • the first transfer segment 251 may be connected to the data line DL and a second transfer segment 252, and the second transfer segment 252 may be connected to the first data fan-out line.
  • the second transfer segment 252 may be located on a side of the connected data line DL away from the edge of the display substrate.
  • the first transfer segment 251 and the second transfer segment 252 may be located in the third source-drain metal layer, and the data line DL may be located in the second source-drain metal layer.
  • this embodiment is not limited to this.
  • the structural description of the first border area of the display substrate in this example can be referred to the description of the previous embodiment, and therefore will not be repeated here.
  • This embodiment also provides a display substrate, comprising: a display area and a first frame area located on one side of the display area along a first direction.
  • the first frame area comprises a bending area and a first sub-area located between the bending area and the display area.
  • the display area has a first centerline extending along the first direction, and the first frame area has a second centerline extending along the first direction, with a distance between the first centerline and the second centerline being greater than zero.
  • the display substrate comprises: a substrate, a plurality of sub-pixels and a plurality of data lines disposed on one side of the substrate and located in the display area, a plurality of first data fan-out lines located in the first sub-area, and a plurality of signal bending lines located in the bending area.
  • the plurality of data lines are electrically connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels.
  • the plurality of first data fan-out lines are connected to the plurality of data lines.
  • the plurality of signal bending lines are located on the same conductive layer.
  • the plurality of signal bending lines include at least a plurality of data bending lines connected to the plurality of first data fan-out lines, and the plurality of data bending lines are symmetrically arranged about a third centerline.
  • the plurality of signal meander lines have a fourth centerline extending along the first direction, the fourth centerline coinciding with the third centerline or being located on a side of the third centerline closer to the second centerline.
  • the first centerline, the second centerline, the third centerline, and the fourth centerline may extend in the same direction.
  • the multiple data bending lines in the bending area are symmetrically arranged according to the third center line, and the fourth center line of the multiple signal bending lines in the bending area coincides with the third center line, or is located on the side of the third center line close to the second center line.
  • the plurality of signal bending lines may be symmetrically arranged about a fourth center line; the third center line and the fourth center line coincide with the second center line.
  • the first frame area has a first frame edge and a second frame edge extending along a first direction, the first frame edge and the second frame edge being located on either side of the signal bending line of the bending area along a second direction, and the second direction intersects the first direction.
  • the second direction may be perpendicular to the first direction.
  • the minimum distance between the signal bending line of the bending area and the first frame edge is the first edge distance
  • the minimum distance between the signal bending line of the bending area and the second frame edge is the second edge distance
  • the ratio of the first edge distance to the second edge distance is 0.9 to 1.1.
  • the first edge distance may be equal to the second edge distance.
  • the multiple signal bend lines can be symmetrically arranged about the fourth center line.
  • the third center line coincides with the fourth center line and is located between the first center line and the second center line; or, the third center line and the fourth center line coincide with the first center line.
  • the first border area has a first border edge and a second border edge extending along the first direction, and the first border edge and the second border edge are located on both sides of the signal bend line of the bend area along the second direction.
  • the minimum distance between the signal bend line of the bend area and the first border edge is the first edge distance
  • the minimum distance between the signal bend line of the bend area and the second border edge is the second edge distance.
  • the ratio of the first edge distance to the second edge distance is greater than 1, or the ratio of the second edge distance to the first edge distance is greater than 1.
  • the first edge distance is different from the second edge distance. This example helps to ensure the symmetrical arrangement of the routing of the bend area by adjusting the difference between the first edge distance and the second edge distance, thereby reducing the difference between the signals in the first border area.
  • multiple signal bending lines can be asymmetrically arranged about a fourth center line, the fourth center line can coincide with the second center line, and the third center line can coincide with the first center line.
  • the first frame area can have a first frame edge and a second frame edge extending along the first direction, and the first frame edge and the second frame edge are located on both sides of the signal bending line of the bending area along the second direction.
  • the minimum distance between the signal bending line of the bending area and the first frame edge is the first edge distance
  • the minimum distance between the signal bending line of the bending area and the second frame edge is the second edge distance
  • the ratio of the first edge distance to the second edge distance is 0.9 to 1.1.
  • the first edge distance can be equal to the second edge distance. This example can ensure the consistency of the distance between the wiring of the bending area and the two side edges of the display substrate, which is beneficial to the wiring arrangement of the bending area and to ensure the bending effect.
  • FIG 16 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • display device 91 may include a display substrate 910.
  • Display substrate 910 may be an OLED display substrate.
  • Display device 91 may be any product or component with a display function, such as an OLED display device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a foldable display screen, an in-vehicle display device, or a navigation system.
  • this embodiment is not limited to this.
  • the reference terms "one embodiment”, “some embodiments”, “example” or “some examples” and the like mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application.
  • the schematic representations of the above terms do not necessarily refer to the same embodiment or example.
  • the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
  • those skilled in the art may combine and combine different embodiments or examples described in this specification and features of different embodiments or examples, unless they are mutually inconsistent.

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Abstract

一种显示基板，包括：显示区域和沿第一方向位于显示区域一侧的第一边框区域。第一边框区域包括弯折区域以及位于弯折区域和显示区域之间的第一子区域。显示区域具有沿第一方向延伸的第一中心线，第一边框区域具有沿第一方向延伸的第二中心线。第一中心线和第二中心线之间的距离大于0。显示基板包括：衬底、设置在衬底的一侧且位于显示区域的多个子像素和多条数据线、位于第一子区域的多条第一数据扇出线和位于弯折区域的多条数据弯折线。所述多条数据弯折线关于第三中心线对称设置；第三中心线与第一中心线重合，或者与第二中心线重合，或者位于第一中心线和第二中心线之间。

Description

显示基板及显示装置
本申请要求于2024年3月15日提交的、申请号为202410303553.8、发明名称为“显示基板及显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及显示装置。
背景技术
随着移动设备和消费电子产品的快速发展，对更大屏幕显示面积和更便携式设计的需求不断增加。传统平板电脑和智能手机的显示屏尺寸有限，用户在日常使用中希望获得更大的视觉体验。近年来，大折叠显示屏技术逐渐引起了人们的兴趣。这种技术结合了柔性显示屏和可折叠屏幕的特点，使得用户可以通过展开或折叠的方式实现屏幕尺寸的变化，从而在保持便携性的同时获得更大的显示区域。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种显示基板及显示装置。
一方面，本实施例提供一种显示基板，包括：显示区域和沿第一方向位于所述显示区域一侧的第一边框区域；所述第一边框区域包括：弯折区域、位于弯折区域和显示区域之间的第一子区域；所述显示区域具有沿所述第一方向延伸的第一中心线，所述第一边框区域具有沿所述第一方向延伸的第二中心线；所述第一中心线和所述第二中心线之间的距离大于0。所述显示基板包括：衬底、设置在所述衬底的一侧且位于显示区域的多个子像素和多条数据线、位于第一子区域的多条第一数据扇出线、以及弯折区域的多条数据弯折线。多条数据线与多个子像素电连接，多条数据线被配置为给多个子像素提供数据信号。多条第一数据扇出线与多条数据线连接。多条数据弯折线与所述多条第一数据扇出线连接，所述多条数据弯折线关于第三中心线对称设置；所述第三中心线与所述第一中心线重合，或者与所述第二中心线重合，或者位于所述第一中心线和所述第二中心线之间。
在一些示例性实施方式中，所述显示基板还包括：位于所述弯折区域且沿所述第一方向延伸的多条第一电源弯折线，所述多条第一电源弯折线与所述多条数据弯折线沿第二方向间隔设置，所述第二方向与所述第一方向交叉。所述第一边框区域还包括：位于所述弯折区域远离所述第一子区域一侧的第二子区域。所述显示基板还包括：位于所述第一子区域的第一周边电源线和位于所述第二子区域的第一电源引出线，所述第一周边电源线和所述第一电源引出线通过所述多条第一电源弯折线连接；所述多条第一电源弯折线关于所述第三中心线对称设置。
在一些示例性实施方式中，所述多条数据弯折线包括：第一组数据弯折线、第二组数据弯折线、第三组数据弯折线和第四组数据弯折线。所述多条第一电源弯折线至少包括：第一组第一电源弯折线、第二组第一电源弯折线和第三组第一电源弯折线。所述第三组数据弯折线、所述第二组第一电源弯折线、所述第一组数据弯折线、所述第一组第一电源弯折线、所述第二组数据弯折线、所述第三组第一电源弯折线、以及所述第四组数据弯折线沿所述第二方向依次设置。所述第一组数据弯折线和所述第二组数据弯折线关于所述第三中心线对称设置，所述第三组数据弯折线和所述第四组数据弯折线关于所述第三中心线对称设置；所述第二组第一电源弯折线与所述第三组第一电源弯折线关于所述第三中心线对称设置，所述第一组第一电源弯折线关于所述第三中心线对称设置。
在一些示例性实施方式中，所述第一组第一电源弯折线沿所述第二方向的总长度，大于或等于所述第二组第一电源弯折线沿所述第二方向的总长度，且大于或等于所述第三组第一电源弯折线沿所述第二方向的总长度。
在一些示例性实施方式中，所述多条第一电源弯折线还包括：第四组第一电源弯折线和第五组第一电源弯折线，所述第四组第一电源弯折线位于所述第三组数据弯折线远离所述第二组第一电源弯折线的一侧，所述第五组第一电源弯折线位于所述第四组数据弯折线远离所述第三组第一电源弯折线的一侧；所述第四组第一电源弯折线与所述第五组第一电源弯折线关于所述第三中心线对称设置。
在一些示例性实施方式中，所述显示基板还包括：位于所述弯折区域且沿所述第一方向延伸的多条第二电源弯折线，所述多条第二电源弯折线位于所述多条数据弯折线沿所述第二方向的两侧。所述显示基板还包括：位于所述第一子区域的第二周边电源线和位于所述第二子区域的第二电源引出线，所述第二周边电源线和所述第二电源引出线通过所述多条第二电源弯折线连接，所述第二周边电源线传输的第二电压信号不同于所述第一周边电源线传输的第一电压信号；所述多条第二电源弯折线关于所述第三中心线对称设置。
在一些示例性实施方式中，所述显示基板还包括：位于所述弯折区域且沿所述第一方向延伸的多条控制弯折线，所述多条控制弯折线位于所述多条第二电源弯折线沿所述第二方向的两侧；所述多条控制弯折线关于所述第三中心线对称设置。
在一些示例性实施方式中，所述第三中心线与所述第二中心线重合。所述第一边框区域具有沿所述第一方向延伸的第一边框边缘和第二边框边缘，所述第一边框边缘和所述第二边框边缘沿第二方向位于所述弯折区域的走线两侧，所述第二方向与所述第一方向交叉。所述弯折区域的走线与所述第一边框边缘的最小距离为第一边缘距离，所述弯折区域的走线与所述第二边框边缘的最小距离为第二边缘距离，所述第一边缘距离与所述第二边缘距离的比值为0.9至1.1。
在一些示例性实施方式中，所述第三中心线位于所述第一中心线和所述第二中心线之间，或者，所述第三中心线与所述第一中心线重合。所述第一边框区域具有沿所述第一方向延伸的第一边框边缘和第二边框边缘，所述第一边框边缘和所述第二边框边缘沿第二方向位于所述弯折区域的走线的两侧，所述第二方向与所述第一方向交叉。所述弯折区域的走线与所述第一边框边缘的最小距离为第一边缘距离，所述弯折区域的走线与所述第二边框边缘的最小距离为第二边缘距离，所述第一边缘距离与所述第二边缘距离的比值大于1，或者，所述第二边缘距离与所述第一边缘距离的比值大于1。
在一些示例性实施方式中，所述多条第一数据扇出线中的至少一条第一数据扇出线包括：相互连接的第一数据延伸段和第二数据延伸段，所述第二数据延伸段与所述多条数据弯折线中的至少一条数据弯折线连接，且所述第二数据延伸段为沿所述第一方向延伸的直线段，所述第一数据延伸段的延伸方向与所述第一方向交叉。所述第二中心线在第二方向上位于所述第一中心线的第一侧，所述第二方向与所述第一方向交叉；所述第三中心线与所述第一中心线没有重合。靠近所述第一中心线且位于所述第一中心线的第一侧的至少一条第一数据扇出线的第一数据延伸段的长度，大于靠近所述第一中心线且位于所述第一中心线的第二侧的至少一条第一数据扇出线的第一数据延伸段的长度。
在一些示例性实施方式中，所述第三中心线与所述第一中心线重合，所述多条第一数据扇出线关于所述第三中心线对称设置。
在一些示例性实施方式中，所述第一边框区域还包括：位于所述弯折区域远离所述第一子区域一侧的第二子区域。所述显示基板还包括：位于所述第二子区域的多条数据引出线，所述多条数据引出线与所述多条数据弯折线连接；所述多条数据引出线关于所述第三中心线对称设置。
在一些示例性实施方式中，所述显示基板还包括：位于所述弯折区域的多条电源弯折线，所述多条电源弯折线与所述多条数据弯折线沿第二方向间隔设置，所述第二方向与所述第一方向交叉。所述多条电源弯折线包括：位于所述第三中心线两侧的第一组电源弯折线和第二组电源弯折线。所述第一组电源弯折线沿所述第二方向的总长度不同于所述第二组电源弯折线沿所述第二方向的总长度。
在一些示例性实施方式中，所述第三中心线与所述第一中心线重合。所述第一边框区域具有沿所述第一方向延伸的第一边框边缘和第二边框边缘，所述第一边框边缘和所述第二边框边缘沿第二方向位于所述弯折区域的走线两侧，所述第二方向与所述第一方向交叉。所述弯折区域的走线与所述第一边框边缘的最小距离为第一边缘距离，所述弯折区域的走线与所述第二边框边缘的最小距离为第二边缘距离，所述第一边缘距离与所述第二边缘距离的比值为0.9至1.1。
在一些示例性实施方式中，所述第三中心线与所述第一中心线重合，所述第二中心线和所述第一组电源弯折线位于所述第一中心线的同一侧；所述第一组电源弯折线沿所述第二方向的总长度大于所述第二组电源弯折线沿所述第二方向的总长度。
另一方面，本实施例还提供一种显示装置，包括如上所述的显示基板。
另一方面，本实施例提供一种显示基板，包括：显示区域和沿第一方向位于所述显示区域一侧的第一边框区域，所述第一边框区域包括：弯折区域、位于所述弯折区域和所述显示区域之间的第一子区域；所述显示区域具有沿所述第一方向延伸的第一中心线，所述第一边框区域具有沿所述第一方向延伸的第二中心线，所述第一中心线与所述第二中心线之间的距离大于0。所述显示基板包括：衬底、设置在所述衬底的一侧且位于所述显示区域的多个子像素和多条数据线、位于第一子区域的多条第一数据扇出线、以及位于弯折区域的多条信号弯折线。所述多条数据线与所述多个子像素电连接，所述多条数据线配置为给所述多个子像素提供数据信号。多条第一数据扇出线与所述多条数据线连接。多条信号弯折线位于同一导电层。所述多条信号弯折线至少包括：多条数据弯折线，所述多条数据弯折线与所述多条第一数据扇出线连接，所述多条数据弯折线关于第三中心线对称设置。所述多条信号弯折线具有沿第一方向延伸的第四中心线，所述第四中心线与所述第三中心线重合，或者，位于所述第三中心线靠近所述第二中心线的一侧。
在一些示例性实施方式中，所述多条信号弯折线关于所述第四中心线对称设置；所述第三中心线和所述第四中心线与所述第二中心线重合。所述第一边框区域具有沿所述第一方向延伸的第一边框边缘和第二边框边缘，所述第一边框边缘和所述第二边框边缘沿第二方向位于所述弯折区域的信号弯折线的两侧，所述第二方向与所述第一方向交叉。所述弯折区域的信号弯折线与所述第一边框边缘的最小距离为第一边缘距离，所述弯折区域的信号弯折线与所述第二边框边缘的最小距离为第二边缘距离，所述第一边缘距离与所述第二边缘距离的比值为0.9至1.1。
在一些示例性实施方式中，所述多条信号弯折线关于所述第四中心线对称设置。所述第三中心线与所述第四中心线重合，且位于所述第一中心线和所述第二中心线之间；或者，所述第三中心线和所述第四中心线与所述第一中心线重合。所述第一边框区域具有沿所述第一方向延伸的第一边框边缘和第二边框边缘，所述第一边框边缘和所述第二边框边缘沿第二方向位于所述弯折区域的信号弯折线的两侧，所述第二方向与所述第一方向交叉。所述弯折区域的信号弯折线与所述第一边框边缘的最小距离为第一边缘距离，所述弯折区域的信号弯折线与所述第二边框边缘的最小距离为第二边缘距离，所述第一边缘距离与所述第二边缘距离的比值大于1，或者，所述第二边缘距离与所述第一边缘距离的比值大于1。
在一些示例性实施方式中，所述多条信号弯折线关于所述第四中心线非对称设置，所述第四中心线与所述第二中心线重合，所述第三中心线与所述第一中心线重合。所述第一边框区域具有沿所述第一方向延伸的第一边框边缘和第二边框边缘，所述第一边框边缘和所述第二边框边缘沿第二方向位于所述弯折区域的信号弯折线的两侧；所述第二方向与所述第一方向交叉。所述弯折区域的信号弯折线与所述第一边框边缘的最小距离为第一边缘距离，所述弯折区域的信号弯折线与所述第二边框边缘的最小距离为第二边缘距离，所述第一边缘距离与所述第二边缘距离的比值为0.9至1.1。
本申请的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本申请而了解。本申请的其他优点可通过在说明书以及附图中所描述的方案来实现和获得。
附图概述
附图用来提供对本申请技术方案的理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1为本公开至少一实施例的显示基板的示意图；
图2A为本公开至少一实施例的显示基板的显示区域的局部剖面示意图；
图2B为本公开至少一实施例的显示基板的显示区域的另一局部剖面示意图；
图3为本公开至少一实施例的第一边框区域的局部结构示意图；
图4为图3中区域S1的局部放大示意图；
图5为本公开至少一实施例的第一边框区域的另一局部结构示意图；
图6为本公开至少一实施例的第一边框区域的局部走线示意图；
图7为本公开至少一实施例的第一边框区域的另一局部示意图；
图8为本公开至少一实施例的第一边框区域的另一局部示意图；
图9为图8中区域S2的局部放大示意图；
图10为本公开至少一实施例的第一边框区域的另一局部示意图；
图11为图10中区域S3的局部放大示意图；
图12为本公开至少一实施例的第一边框区域的另一局部示意图；
图13为图12中区域S4的局部放大示意图；
图14为本公开至少一实施例的第一边框区域的另一局部示意图；
图15为本公开至少一实施例的显示基板的另一示意图；
图16为本公开至少一实施例的显示装置的示意图。
详述
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏极、沟道区域以及源极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。另外，栅极还可以称为控制极。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，圆形、椭圆形、三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似圆形、近似椭圆形、近似三角形、近似矩形、近似梯形、近似五边形或近似六边形等，可以存在公差导致的一些小变形，例如可以存在导角、弧边以及变形等。
本公开中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。在本公开中，“大致相同”是指数值相差10％以内的情况。本公开中的“对称”是指允许工艺和测量误差范围内的对称情况。
在本公开中，A沿着B方向延伸是指，A可以包括主体部分和与主体部分连接的次要部分，主体部分是线、线段或条形状体，主体部分沿着B方向伸展，且主体部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展的长度。本公开中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。
本公开中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。本公开所说的“A的形状”是指A在衬底的正投影的形状。
本公开中，A与B之间的距离是指A与B之间的垂直距离或最小距离。
在一些实现方式中，大折叠显示屏的副屏需要配合盖板设计，通常情况下外形为不对称设计，使得显示区域的中心线和下边框的中心线不在同一条直线上，从而对下边框的信号走线排布提出了新要求。
本实施例提供一种显示基板，包括：显示区域和沿第一方向位于显示区域一侧的第一边框区域，第一边框区域包括：弯折区域、位于弯折区域和显示区域之间的第一子区域。显示区域具有沿第一方向延伸的第一中心线，第一边框区域具有沿第一方向延伸的第二中心线。第一中心线与第二中心线之间的距离大于0。显示基板包括：衬底、设置在衬底的一侧且位于显示区域的多个子像素和多条数据线、位于第一子区域的多条第一数据扇出线、以及位于弯折区域的多条数据弯折线。多条数据线与多个子像素电连接，所述多条数据线配置为给所述多个子像素提供数据信号。多条第一数据扇出线与多条数据线连接。多条数据弯折线与多条第一数据扇出线连接，所述多条数据弯折线关于第三中心线对称设置。第三中心线与第一中心线重合，或者与第二中心线重合，或者位于第一中心线和第二中心线之间。其中，第三中心线、第一中心线和第二中心线的延伸方向可以相同。
本实施例针对显示区域的第一中心线和第一边框区域的第二中心线不在同一条直线的情况，将弯折区域的多条数据弯折线按照第三中心线对称设置，可以保证第三中心线两侧的数据弯折线的密度和膜层一致性，便于保证弯折效果。而且，第三中心线与第一中心线或者第二中心线重合，或者，位于第一中心线和第二中心线之间，可以改善显示基板的不对称外形带来的信号走线差异化所带来的问题。
在一些示例性实施方式中，显示基板还可以包括：位于弯折区域且沿第一方向延伸的多条第一电源弯折线，所述多条第一电源弯折线与多条数据弯折线沿第二方向间隔设置。第二方向与第一方向交叉，例如，第二方向可以垂直于第一方向。第一边框区域还可以包括：位于弯折区域远离第一子区域一侧的第二子区域。显示基板还可以包括：位于第一子区域的第一周边电源线和位于第二子区域的第一电源引出线，第一周边电源线和第一电源引出线可以通过所述多条第一电源弯折线连接。所述多条第一电源弯折线可以关于第三中心线对称设置。在一些示例中，第一周边电源线、第一电源引出线和多条第一电源弯折线电连接，配置为传输第一电压信号。本示例通过将弯折区域的多条第一电源弯折线关于第三中心线对称设置，可以保证第三中心线两侧的第一电源弯折线的密度和膜层一致性，而且可以有利于保证第三中心线两侧的第一电压信号的传输负载一致性。
在一些示例性实施方式中，显示基板还可以包括：沿第一方向延伸的多条第二电源弯折线，所述多条第二电源弯折线可以位于多条数据弯折线沿第二方向的两侧。显示基板还可以包括：位于第一子区域的第二周边电源线和位于第二子区域的第二电源引出线，第二周边电源线和第二电源引出线可以通过所述多条第二电源弯折线连接，第二周边电源线传输的第二电压信号不同于第一周边电源线传输的第一电压信号。多条第二电源弯折线可以关于第三中心线对称设置。在一些示例中，第一电压信号可以大于第二电压信号。第一电压信号可以被配置为提供给显示区域的子像素所连接的第一电源线，第二电压信号可以被配置为提供给显示区域的子像素的发光元件的阴极或者子像素所连接的第二电源线。本示例通过将弯折区域的多条第二电源弯折线关于第三中心线对称设置，可以保证第三中心线两侧的第二电源弯折线的密度和膜层一致性，而且可以有利于保证第三中心线两侧的第二电压信号的传输负载一致性。
在一些示例性实施方式中，显示基板还可以包括：位于弯折区域且沿第一方向延伸的多条控制弯折线，所述多条控制弯折线位于多条第二电源弯折线沿第二方向的两侧；所述多条控制弯折线可以关于第三中心线对称设置。在一些示例中，多条控制弯折线可以包括：给栅极驱动电路提供控制信号(例如包括起始信号、时钟信号、电压信号等)的多条走线、传输面板测试信号的走线。栅极驱动电路可以配置为给显示区域的多个子像素提供像素控制信号(例如包括扫描信号、复位信号、发光控制信号等)。本示例通过将弯折区域的多条控制弯折线关于第三中心线对称设置，可以保证第三中心线两侧的控制弯折线的密度和膜层一致性，而且可以有利于保证第三中心线两侧的相同的控制信号的传输负载一致性。
在一些示例性实施方式中，第三中心线可以与第二中心线重合。第一边框区域可以具有沿第一方向延伸的第一边框边缘和第二边框边缘，第一边框边缘和第二边框边缘沿第二方向可以位于弯折区域的走线两侧。弯折区域的走线与第一边框边缘的最小距离为第一边缘距离，弯折区域的走线与第二边框边缘的最小距离为第二边缘距离，第一边缘距离与第二边缘距离的比值为0.9至1.1。例如，第一边缘距离可以等于第二边缘距离。本示例可以保证弯折区域的走线与显示基板的两侧边缘的距离一致性，有利于弯折区域的走线排布，有利于保证弯折效果。
在一些示例性实施方式中，第三中心线可以位于第一中心线和第二中心线之间，或者，第三中心线可以与第一中心线重合。第一边框区域可以具有沿第一方向延伸的第一边框边缘和第二边框边缘，第一边框边缘和第二边框边缘沿第二方向位于所述弯折区域的走线的两侧。弯折区域的走线与第一边框边缘的最小距离为第一边缘距离，弯折区域的走线与第二边框边缘的最小距离为第二边缘距离，第一边缘距离与第二边缘距离的比值大于1，或者，第二边缘距离与第一边缘距离的比值大于1。换言之，第一边缘距离不同于第二边缘距离。本示例通过调整第一边缘距离和第二边缘距离存在差异性，有利于保证弯折区域的走线的对称排布，从而减小第一边框区域内在第二中心线两侧传输的信号之间的差异性。
在一些示例性实施方式中，显示基板可以包括：位于弯折区域的多条电源弯折线，多条电源弯折线与多条数据弯折线可以沿第二方向间隔设置。多条电源弯折线可以包括：位于第三中心线两侧的第一组电源弯折线和第二组电源弯折线，第一组电源弯折线沿第二方向的总长度可以不同于第二组电源弯折线沿第二方向的总长度。在一些示例中，一组电源弯折线沿第二方向的总长度可以包括：该组电源弯折线内每条电源弯折线的线宽、以及相邻电源弯折线之间的间隔的总和。本示例中，相邻电源弯折线之间没有设置其他走线。本示例可以通过调节第三中心线两侧的一组或多组电源弯折线沿第二方向的总长度来保证多条数据弯折线的对称排布。
在一些示例中，第三中心线与第一中心线可以重合，第二中心线和第一组电源弯折线可以位于第一中心线的同一侧。第一组电源弯折线沿第二方向的总长度可以大于第二组电源弯折线沿第二方向的总长度。本示例可以通过调整第一组电源弯折线和第二组电源弯折线沿第二方向的长度，来优化第一边框区域的走线排布。
下面通过一些示例对本实施例的方案进行举例说明。
图1为本公开至少一实施例的显示基板的示意图。在一些示例中，如图1所示，显示基板可以为包括线性边的闭合多边形。例如，本示例的显示基板可以应用于大叠显示产品的副屏。显示基板可以包括：显示区域AA和位于显示区域AA周围的边框区域BB。例如，显示区域AA可以包括：在第一方向Y上相对设置的第一显示边缘(下显示边缘)和第二显示边缘(上显示边缘)，以及在第二方向X上相对设置的第三显示边缘(左显示边缘)和第四显示边缘(右显示边缘)。第一显示边缘和第二显示边缘可以为相互平行的线性边，第三显示边缘和第四显示边缘可以为相互平行的线性边。相邻线性边之间可以通过弯曲边缘(例如弧形边缘)连接。
在一些示例中，边框区域BB可以包括：沿第一方向Y位于显示区域AA两侧的第一边框区域B1和第四边框区域B4、沿第二方向X位于显示区域AA两侧的第二边框区域B2和第三边框区域B3。第一边框区域B1可以连接第一显示边缘，第二边框区域B2可以连接第三显示边缘，第三边框区域B3可以连接第四显示边缘，第四边框区域B4可以连接第二显示边缘。第一边框区域B1可以与第二边框区域B2和第三边框区域B3连通，第三边框区域B4可以与第二边框区域B2和第三边框区域B3连通，第一边框区域B1、第二边框区域B2、第三边框区域B3和第四边框区域B4连通后可以围绕显示区域AA。例如，第一边框区域B1还可以称为显示基板的下边框区域，第二边框区域B2还可以称为显示基板的左边框区域，第三边框区域B3还可以称为显示基板的右边框区域，第四边框区域B4还可以称为显示基板的上边框区域。然而，本实施例对此并不限定。
在一些示例中，显示基板的显示区域AA可以至少包括：多个子像素PX、多条栅线GL和多条数据线DL。多条栅线GL可以沿第二方向X延伸，并沿第一方向Y排布；多条数据线DL可以沿第一方向Y延伸，并沿第二方向X排布。多条数据线DL可以与多个子像素PX电连接，多条数据线DL可以被配置为向多个子像素PX提供数据信号。多条栅线GL可以与多个子像素PX电连接，多条栅线GL可以被配置为向多个子像素PX提供像素控制信号。例如，像素控制信号可以包括扫描信号，或者可以包括扫描信号和发光控制信号，或者可以包括扫描信号、复位控制信号和发光控制信号。
在一些示例中，第二方向X可以是显示区域AA内栅线GL的延伸方向(例如，行方向)；第一方向Y可以是显示区域AA内数据线DL的延伸方向(例如，列方向)。第一方向Y与第二方向X可以相互交叉，例如可以相互垂直。
在一些示例中，显示区域AA的一个像素单元可以包括三个子像素，三个子像素可以分别为出射第一颜色光(例如，红光)的第一子像素、出射第二颜色光(例如，绿光)的第二子像素和出射第三颜色光(例如，蓝光)的第三子像素。然而，本实施例对此并不限定。在一些示例中，一个像素单元可以包括四个子像素，四个子像素可以分别为出射红光的子像素、出射绿光的子像素、出射蓝光的子像素和出射白光的子像素。又如，一个像素单元可以包括四个子像素，四个子像素可以包括一个出射红光的子像素、一个出射蓝光的子像素、以及两个出射绿光的子像素。
在一些示例中，一个子像素可以包括：像素电路以及与像素电路电连接的发光元件。像素电路可以包括多个晶体管和至少一个电容。例如，像素电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。其中，上述电路结构中的T指的是薄膜晶体管，C指的是电容，T前面的数字代表电路中薄膜晶体管的数量，C前面的数字代表电路中电容的数量。在一些示例中，像素电路中的多个晶体管可以包括P型晶体管和N型晶体管。在另一些示例中，像素电路中的多个晶体管可以为P型晶体管或者可以为N型晶体管，像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板的工艺难度，提高产品的良率。
在一些示例中，子像素的发光元件的形状可以是矩形、菱形、五边形或六边形。一个像素单元包括三个子像素时，三个子像素的发光元件可以采用水平并列、竖直并列或品字方式排列；一个像素单元包括四个子像素时，四个子像素的发光元件可以采用水平并列、竖直并列或正方形方式排列。然而，本实施例对此并不限定。
在一些示例中，发光元件可以是发光二极管(LED，Light Emitting Diode)、有机发光二极管(OLED，Organic Light Emitting Diode)、量子点发光二极管(QLED，Quantum Dot Light Emitting Diode)、微LED(包括：mini-LED或micro-LED)等中的任一者。例如，发光元件可以为OLED，发光元件在其对应的像素电路的驱动下可以发出红光、绿光、蓝光、或者白光等。发光元件发光的颜色可根据需要而定。在一些示例中，发光元件可以包括：阳极、阴极以及位于阳极和阴极之间的有机发光层。发光元件的阳极可以与对应的像素电路电连接。然而，本实施例对此并不限定。
图2A为本公开至少一实施例的显示基板的显示区域的局部剖面示意图。图2A中以显示区域的一个子像素的结构为例进行示意。本示例中，像素电路中的多个像素晶体管的晶体管类型可以不同，例如可以包括低温多晶硅薄膜晶体管和氧化物薄膜晶体管。
在一些示例中，如图2A所示，在垂直于显示基板的方向上，显示基板的显示区域可以包括：衬底10、以及依次设置在衬底上的电路结构层12、发光结构层13、以及封装结构层14。电路结构层12可以至少包括：多个子像素的像素电路，每个子像素的像素电路可以包括多个晶体管和至少一个电容。发光结构层13可以至少包括：多个子像素的发光元件。在另一些示例中，显示基板还可以包括：位于封装结构层远离衬底一侧的触控结构层。例如，触控结构层可以包括至少一个触控导电层。
在一些示例中，图2A中以每个子像素包括的一个第一晶体管21、一个第二晶体管22以及一个电容23为例进行示意。第一晶体管21和第二晶体管22的晶体管类型可以不同。其中，第一晶体管21可以为低温多晶硅薄膜晶体管，第二晶体管22可以为氧化物薄膜晶体管。
在一些示例中，显示区域的电路结构层12可以包括：设置在衬底10上的第一半导体层、第一栅金属层、第二栅金属层、第二半导体层、第三栅金属层、第一源漏金属层以及第二源漏金属层。第一半导体层和第一栅金属层之间可以设置有第一绝缘层101，第一栅金属层和第二栅金属层之间可以设置有第二绝缘层102；第二栅金属层和第二半导体层之间可以设置有第三绝缘层103；第二半导体层和第三栅金属层之间可以设置有第四绝缘层104；第三栅金属层和第一源漏金属层之间可以设置有第五绝缘层105；第一源漏金属层和第二源漏金属层之间可以设置有第六绝缘层106(还可以称为钝化(PVX)层)和第七绝缘层107(还可以称为第一平坦(PLN)层)，第七绝缘层107可以位于第六绝缘层106远离衬底10的一侧；第二源漏金属层远离衬底10的一侧可以设置有第八绝缘层108(还可以称为第二平坦层)。其中，第一绝缘层101、第二绝缘层102、第三绝缘层103、第四绝缘层104、第五绝缘层105以及第六绝缘层106可以为无机绝缘层，第七绝缘层107和第八绝缘层108可以为有机绝缘层。然而，本实施例对此并不限定。在另一些示例中，第一半导体层靠近衬底一侧还可以设置缓冲层，缓冲层可以防止衬底中的有害物质侵入显示基板的内部，还可以增加显示基板中的膜层在衬底上的附着力。在另一些示例中，在缓冲层靠近衬底一侧还可以设置底部遮光金属层(BSM，Bottom Shielding Metal)，底部遮光金属层可以被配置为至少部分覆盖像素电路的晶体管的有源层，以避免外部光线对晶体管的性能产生影响。另一些示例中，第一源漏金属层和第二源漏金属层之间可以省略第六绝缘层，第一源漏金属层和第二源漏金属层之间可以仅设置第七绝缘层。
在一些示例中，如图2A所示，显示区域的第一半导体层可以至少包括：第一晶体管21的第一有源层210。第一晶体管21的第一有源层210可以包括：第一区2101、第二区2102以及位于第一区2101和第二区2102之间的沟道区2100。第一栅金属层可以至少包括：第一晶体管21的第一栅极213、以及电容23的第一极板231。第一晶体管21的第一栅极213在衬底10的正投影可以覆盖第一有源层210的沟道区2100在衬底10的正投影。第二栅金属层可以至少包括：电容23的第二极板232。电容23的第二极板232和第一极板231在衬底10的正投影可以至少部分交叠，例如，两者可以重合。第二半导体层可以至少包括：第二晶体管22的第二有源层220。第三栅金属层可以至少包括：第二晶体管22的第二栅极223。第二晶体管22的第二栅极223在衬底10的正投影与第二有源层220在衬底10的正投影可以部分交叠。
在一些示例中，如图2A所示，第一源漏金属层可以至少包括：第一晶体管21的第一源极211和第一漏极212、第二晶体管22的第二源极221和第二漏极222。第五绝缘层105在显示区域可以开设有多个像素过孔(例如，包括第一像素过孔、第二像素过孔、第三像素过孔和第四像素过孔)，第一像素过孔内的第五绝缘层105、第四绝缘层104、第三绝缘层103、第二绝缘层102和第一绝缘层101可以被去掉，暴露出第一有源层210的第一区2101的至少部分表面；第二像素过孔内的第五绝缘层105、第四绝缘层104、第三绝缘层103、第二绝缘层102和第一绝缘层101可以被去掉，暴露出第一有源层210的第二区2102的至少部分表面。第三像素过孔和第四像素过孔内的第五绝缘层105和第四绝缘层104可以被去掉，暴露出第二有源层220的两端的至少部分表面。第一晶体管21的第一源极211可以通过第一像素过孔与第一有源层210的第一区2101电连接，第一漏极212可以通过第二像素过孔与第一有源层210的第二区2102电连接。第二晶体管22的第二源极221可以通过第三像素过孔与第二有源层220的一端电连接，第二晶体管22的第二漏极222可以通过第四像素过孔与第二有源层220的另一端电连接。第二源漏金属层可以至少包括：第一转接电极241。第一转接电极241可以通过第六绝缘层106和第七绝缘层107开设的第五像素过孔与像素电路的第一晶体管21的第一漏极212电连接。本示例可以通过第一转接电极241实现像素电路与发光元件之间的电连接。
在一些示例中，显示基板的多条栅线可以包括：第一扫描线、第二扫描线、第一复位控制线、第二复位控制线和发光控制线。多条栅线例如可以位于第一栅金属层和第三栅金属层。例如，第一扫描线、第一复位控制线、第二复位控制线和发光控制线可以位于第一栅金属层，第二扫描线可以位于第三栅金属层。多条数据线例如可以位于第二源漏金属层，显示区域的第一电源线例如可以位于第二源漏金属层。然而，本实施例对此并不限定。
在一些示例中，如图2A所示，发光结构层13可以包括：像素定义层134和多个发光元件。例如，每个发光元件可以包括：叠设的第一电极131、有机发光层132和第二电极133。发光元件的第一电极131可以为阳极，第一电极131可以设置在第八绝缘层108上，并通过第八绝缘层108开设的第六像素过孔，与第一转接电极241电连接。像素定义层134设置在第一电极131和第八绝缘层108上，像素定义层134可以开设有多个像素开口，一个像素开口可以暴露出对应的一个第一电极131的至少部分表面。有机发光层132的至少部分可以设置在一个像素开口内，并与对应的第一电极131连接。第二电极133可以设置在有机发光层132上，并与有机发光层132连接。有机发光层132在第一电极131和第二电极133的驱动下可以出射相应颜色的光线。
在一些示例中，发光元件的有机发光层132可以包括发光层(EML，Emitting Layer)，以及包括空穴注入层(HIL，Hole Injection Layer)、空穴传输层(HTL，Hole Transport Layer)、空穴阻挡层(HBL，Hole Block Layer)、电子阻挡层(EBL，Electron Block Layer)、电子注入层(EIL，Electron Injection Layer)、电子传输层(ETL，Electron Transport Layer)中的一个或多个膜层。在第一电极131和第二电极133的电压驱动下，可以利用有机材料的发光特性根据需要的灰度发光。
在一些示例中，不同颜色的发光元件的发光层可以不同。例如，红色发光元件包括红色发光层，绿色发光元件包括绿色发光层，蓝色发光元件包括蓝色发光层。为了降低工艺难度和提升良率，位于发光层一侧的空穴注入层和空穴传输层可以采用共通层，位于发光层另一侧的电子注入层和电子传输层可以采用共通层。在一些示例中，空穴注入层、空穴传输层、电子注入层和电子传输层中的任意一层或多层可以通过一次工艺(一次蒸镀工艺或一次喷墨打印工艺)制作，并通过形成的膜层表面段差或者通过表面处理等手段实现隔离。例如，相邻子像素对应的空穴注入层、空穴传输层、电子注入层和电子传输层中的任意一层或多层可以是隔离的。在一些示例中，有机发光层可以通过采用精细金属掩模版(FMM，Fine Metal Mask)或者开放式掩膜版(Open Mask)蒸镀制备形成，或者采用喷墨工艺制备形成。
在一些示例中，如图2A所示，封装结构层14可以包括叠设的第一封装层141、第二封装层142和第三封装层143。其中，第一封装层141和第三封装层143可以采用无机材料，例如氮化硅、氧化硅、氮氧化硅等，无机材料的致密性高，可以防止水、氧等的侵入。第二封装层142可以设置在第一封装层141和第三封装层143之间，以保证外界水汽无法进入发光元件。第二封装层142可以采用有机材料，例如，可以为含有干燥剂的高分子材料或可阻挡水汽的高分子材料等，或者可以为高分子树脂等以对显示基板的表面进行平坦化处理，并且可以缓解第一封装层141和第三封装层143的应力，还可以包括干燥剂等吸水性材料以吸收侵入内部的水、氧等物质。然而，本实施例对此并不限定。例如，封装结构层可以采用无机/有机/无机/有机/无机的五层叠设结构。
图2B为本公开至少一实施例的显示基板的显示区域的另一局部剖面示意图。在一些示例中，如图2B所示，显示区域的电路结构层12可以包括：设置在衬底10上的第一半导体层、第一栅金属层、第二栅金属层、第二半导体层、第三栅金属层、第一源漏金属层、第二源漏金属层以及第三源漏金属层。第二源漏金属层和第三源漏金属层之间可以设置有第八绝缘层108，第三源漏金属层远离衬底一侧可以设置第九绝缘层109(还可以称为第三平坦层)。第九绝缘层109可以为有机绝缘层。第三源漏金属层可以至少包括：第二转接电极242，第二转接电极242可以与位于第二源漏金属层的第一转接电极241连接。本示例可以通过第一转接电极241和第二转接电极242实现像素电路与发光元件的第一电极131之间的电连接。关于本示例的显示基板的显示区域的其余结构可以参照图2A所示实施例的描述，故于此不再赘述。
在一些示例中，如图1所示，第一边框区域B1可以包括：沿着远离显示区域AA的方向依次设置的第一子区域B11、弯折区域B12和第二子区域B13。弯折区域B12可以连通第一子区域B11和第二子区域B12。第一子区域B11可以连通第二边框区域B2和第三边框区域B3，并与显示区域AA连接。第一子区域B11还可以称为第一扇出区域。弯折区域B12可以配置为使第二子区域B13弯折到显示区域AA的背面。弯折区域B12内可以设置有多条信号弯折线，以实现第一子区域B11和第二子区域B13内传输相同信号的走线之间的电连接。第二子区域B13可以至少包括：第一信号接入区域B14。第一信号接入区域B14可以设置有多个第一接触垫，多个第一接触垫可以配置为连接驱动集成电路(IC)。
在一些示例中，第二子区域B13可以包括：第一信号接入区域B14、位于弯折区域B12和第一信号接入区域B14之间的电路设置区域、位于弯折区域B12和电路设置区域之间的第二扇出区域、位于电路设置区域和第一信号接入区域B14之间的第三扇出区域、以及位于第一信号接入区域B14远离弯折区域B12一侧的第二信号接入区域。其中，第二扇出区域、电路设置区域、第三扇出区域、第一信号接入区域B14和第二信号接入区域可以沿着远离弯折区域B12的方向依次设置。电路设置区域可以至少设置沿第二方向X排布的多个测试电路；或者，设置有多个测试电路、位于多个测试电路靠近弯折区域B12一侧的多个静电释放电路、以及位于多个测试电路远离弯折区域B12一侧的多个数据选择电路。第二信号接入区域可以设置有多个第二接触垫，多个第二接触垫可以配置为与外部的柔性电路板(FPC)绑定连接。第一信号接入区域B14内的至少一个第一接触垫和第二信号接入区域内的至少一个第二接触垫可以通过引出连接线连接。本实施例对此并不限定。在另一些示例中，第二子区域B13可以包括沿远离弯折区域B12的方向依次设置的第二扇出区域、第一信号接入区域B14和第二信号接入区域。
在一些示例中，如图1所示，显示区域AA可以具有沿第一方向Y延伸的第一中心线O1，第一中心线O1经过显示区域AA的中心点C1。例如，第一显示边缘与中心点C1之间的距离和第二显示边缘与中心点C1之间的距离可以相同；第三显示边缘与中心点C1之间的距离和第四显示边缘与中心点C1之间的距离可以相同。第一中心线O1可以将显示区域AA划分为沿第二方向X排布的第一子显示区和第二子显示区。显示区域AA内的多条数据线DL可以包括：位于第一子显示区的第一组数据线和位于第二子显示区的第二组数据线。其中，第一组数据线内的数据线数目和第二组数据线内的数据线数目可以相同。例如，第一组数据线和第二组数据线可以关于第一中心线O1对称设置。然而，本实施例对此并不限定。
本示例中，两组走线关于一条中心线对称设置是指：两组走线内的走线数目相同，且两组走线内的走线关于该条中心线对称排布，其中，两组走线内关于该条中心线对称排布的走线的线宽相同，与相邻走线之间的间距长度相同。一组走线关于一条中心线对称设置是指：该组走线可以划分为位于该条中心线两侧且对称排布的两部分，且所述两部分包括相同数目的走线；或者，该组走线可以划分为位于该条中心线两侧且对称排布的两部分以及经过该条中心线的一条走线，且所述两部分包括相同数目的走线。
图3为本公开至少一实施例的第一边框区域的局部结构示意图。在一些示例中，如图1和图3所示，边框区域BB可以至少包括：第一边框区域B1在第二方向X上相对设置的第一边框边缘B101和第二边框边缘B102、在第二方向X上相对设置的第三边框边缘B201和第四边框边缘B301。第一边框边缘B101和第二边框边缘B102可以大致沿第一方向Y延伸。例如，第一边框边缘B101和第二边缘边框B102可以为相互平行的线性边。第一边框边缘B101例如为第一边框区域B1的左侧边缘，第二边框边缘B102例如为第一边框区域B1的右侧边缘。第三边框边缘B201可以为第二边框区域B2的左侧边缘，第二边框区域B2的右侧边缘与显示区域AA的第三显示边缘连接。第四边框边缘B202可以为第三边框区域B3的右侧边缘，第三边框区域B3的左侧边缘与显示区域AA的第四显示边缘连接。第三边框边缘B201和第三显示边缘可以为相互平行的线形边，第四边框边缘B301和第四显示边缘可以为相互平行的线性边。第一边框边缘B101和第三边框边缘B201可以通过弯曲边框边缘连接，第三边框边缘B201和第四边框边缘B202可以通过弯曲边框边缘连接。第一边框边缘B101和第二边框边缘B102可以通过沿第二方向X延伸的第五边框边缘B103连接，第三边框边缘B201和第四边框边缘B301可以通过第四边框区域B4远离显示区域AA的边缘连接。
在一些示例中，如图1和图3所示，第一边框区域B1可以具有沿第一方向Y延伸的第二中心线O2，第二中心线O2经过第一边框区域B1的中心点C2。第一边框边缘B101与中心点C2之间的距离与第二边框边缘B102与中心点C2之间的距离可以大致相同，第一显示边缘与中心点C2之间的距离与第五边框边缘B103与中心点C2之间的距离可以大致相同。第二中心线O2可以将第一边框区域B1划分为沿第二方向X排布的左下边框区和右下边框区。第二中心线O2可以经过第一信号接入区域B14的中心点。换言之，第一信号接入区域B14沿第一方向Y延伸的中心线可以与第二中心线O2重合。然而，本实施例对此并不限定。在另一些示例中，第一信号接入区域B14沿第一方向Y延伸的中心线可以与第一中心线O1重合。
在一些示例中，第一边框边缘B101和第三边框边缘B201在第二方向X上具有第一距离L1，第二边框边缘B102和第四边框边缘B301在第二方向X上具有第二距离L2。第一距离L1不等于第二距离L2。例如，第一距离L1可以小于第二距离L2。本示例的显示基板整体为不对称结构，第一边框区域B1的第二中心线O2和显示区域AA的第一中心线O1没有重合。例如，第二中心线O2可以位于第一中心线O1在第二方向X的反方向的一侧。在另一些示例中，当第一距离L1大于第二距离L2，第二中心线O2可以位于第一中心线O1在第二方向X的一侧。
在一些示例中，如图3所示，弯折区域B12可以设置有一组信号弯折线，该组信号弯折线包括多条信号弯折线(例如包括多条数据弯折线、多条第一电源弯折线、多条第二电源弯折线以及多条控制弯折线)，多条信号弯折线可以沿第一方向Y延伸，并沿第二方向X排布。该组信号弯折线在衬底的正投影可以具有沿第一方向Y延伸的第四中心线O4。该组信号弯折线可以关于第四中心线O4对称设置。例如，第四中心线O4可以与第三中心线O3重合。第三中心线O3经过该组信号弯折线在衬底的正投影所对应区域的中心点。例如，该组信号弯折线在衬底的正投影所对应的区域可以大致为矩形。该组信号弯折线在衬底的正投影可以具有第一走线边缘B121和第二走线边缘B122，第一走线边缘B121可以为该组信号弯折线的边缘走线(例如，最左侧走线，比如边缘的控制弯折线)靠近第一边框边缘B101的边缘，第二走线边缘B122可以为该组信号弯折线的边缘走线(例如，最右侧走线，比如边缘的控制弯折线)靠近第二边框左边缘B102的边缘。第一走线边缘B121和第二走线边缘B122可以均大致沿第一方向Y延伸。第一走线边缘B121与第三中心线O3之间的距离，和第二走线边缘B122与第三中心线O3之间的距离可以大致相同。第一走线边缘B121与第三中心线O3之间的距离可以为位于第三中心线O3在第二方向X的反方向一侧的多条信号弯折线的线宽与间距的总和；第二边缘走线B122与第三中心线O3之间的距离可以为位于第三中心线O3在第二方向X一侧的多条信号弯折线的线宽与间距的总和。
在一些示例中，如图3所示，弯折区域B12可以设置有：四组数据弯折线(例如包括第一组数据弯折线311、第二组数据弯折线312、第三组数据弯折线313、第四组数据弯折线314)、五组第一电源弯折线(例如包括第一组第一电源弯折线321、第二组第一电源弯折线322、第三组第一电源弯折线323、第三组第一电源弯折线324和第五组第一电源弯折线325)、两组第二电源弯折线(例如包括第一组第二电源弯折线331和第二组第二电源弯折线332)、两组控制弯折线(例如包括第一组控制弯折线341和第二组控制弯折线342)。图3中对弯折区域B12的每组数据弯折线、每组第一电源弯折线、每组第二电源弯折线、每组控制弯折线以及每组触控弯折线进行了整体示意。
在一些示例中，每组数据弯折线可以包括沿第二方向X排布的多条数据弯折线，多条数据弯折线的线宽可以相同，相邻数据弯折线之间的间距可以相同。每组第一电源弯折线可以包括沿第二方向X排布的多条第一电源弯折线。多条第一电源弯折线的线宽可以相同，相邻第一电源弯折线之间的间距可以相同。同一组第一电源弯折线内的多条第一电源弯折线可以相互连接。每组第二电源弯折线可以包括沿第二方向X排布的多条第二电源弯折线，多条第二电源弯折线的线宽可以相同，相邻第二电源弯折线之间的间距可以相同。同一组第二电源弯折线内的多条第二电源弯折线可以相互连接。每组控制弯折线可以包括沿第二方向X排布的多条控制弯折线。传输相同信号的控制弯折线的线宽可以相同，相邻控制弯折线之间的间距可以相同。
在一些示例中，弯折区域B12内的多条信号弯折线可以位于同一导电膜层，例如可以位于第二源漏金属层。然而，本实施例对此并不限定。例如，多条信号弯折线可以位于第一源漏金属层，或者可以位于第三源漏金属层。
在一些示例中，第一组控制弯折线341、第一组第二电源弯折线331、第四组第一电源弯折线324、第三组数据弯折线313、第二组第一电源弯折线322、第一组数据弯折线311、第一组第一电源弯折线321、第二组数据弯折线312、第三组第一电源弯折线323、第四组数据弯折线314、第五组第一电源弯折线325、第二组第二电源弯折线332、第二组控制弯折线342可以沿第二方向X依次排布。
在一些示例中，多条数据弯折线可以关于第三中心线O3对称设置。其中，第一组数据弯折线311内的数据弯折线的数目和第二组数据弯折线312内的数据弯折线的数目可以相同，且第一组数据弯折线311和第二组数据弯折线312可以关于第三中心线O3对称排布；第三组数据弯折线313内的数据弯折线的数目与第四组数据弯折线314内的数据弯折线的数目可以相同，且第三组数据弯折线313和第四组数据弯折线314可以关于第三中心线O3对称排布。
在一些示例中，多条第一电源弯折线可以关于第三中心线O3对称设置。其中，第一组第一电源弯折线321可以关于第三中心线O3对称排布。第二组第一电源弯折线322内的第一电源弯折线的数目与第三组第一电源弯折线323内的第一电源弯折线的数目可以相同，且第二组第一电源弯折线322和第三组第一电源弯折线323可以关于第三中心线O3对称排布。第四组第一电源弯折线324内的第一电源弯折线的数目与第五组第一电源弯折线325内的第一电源弯折线的数目可以相同，且第四组第一电源弯折线324和第五组第一电源弯折线325可以关于第三中心线O3对称排布。
在一些示例中，第一组第一电源弯折线321沿第二方向X的总长度可以大于第二组第一电源弯折线322沿第二方向X的总长度，且大于第四组第一电源弯折线324沿第二方向X的总长度；第二组第一电源弯折线322、第三组第一电源弯折线323、第四组第一电源弯折线324和第五组第一电源弯折线325沿第二方向X的总长度可以大致相同。然而，本实施例对此并不限定。例如，第二组第一电源弯折线322和第三组第一电源弯折线323沿第二方向X的总长度可以大致相同，第四组第一电源弯折线324和第五组第一电源弯折线325沿第二方向X的总长度可以大致相同，第二组第一电源弯折线322和第四组第一电源弯折线324沿第二方向X的总长度可以不同。其中，以一组第一电源弯折线包括N条第一电源弯折线为例，该组第一电源弯折线沿第二方向的总长度可以包括：该组第一电源弯折线内N条第一电源弯折线的线宽、N-1个相邻间隔长度的总和。
在一些示例中，多条第二电源弯折线可以关于第三中心线O3对称设置。第一组第二电源弯折线331内的第二电源弯折线的数目和第二组第二电源弯折线332内的第二电源弯折线的数目可以相同，且第一组第二电源弯折线331和第二组第二电源弯折线332可以关于第三中心线O3对称排布。
在一些示例中，多条控制弯折线可以关于第三中心线O3对称设置。第一组控制弯折线341内的控制弯折线的数目和第二组控制弯折线342内的控制弯折线的数目可以相同，且第一组控制弯折线341和第二组控制弯折线342可以关于第三中心线O3对称排布。在一些示例中，第一组控制弯折线341或第二组控制弯折线342内的控制弯折线可以包括：有效控制弯折线和无效控制弯折线；在第一组控制弯折线341的有效控制弯折线和第二组控制弯折线342的有效控制弯折线的数目不同时，可以通过设置无效控制弯折线来保证第一组控制弯折线341和第二组控制弯折线342内的控制弯折线的数目一致且关于第三中心线O3对称排布。
在一些示例中，第三中心线O3可以与第二中心线O2重合。换言之，弯折区域B12的多条信号弯折线可以关于第二中心线O2对称设置。
在一些示例中，第一走线边缘B121与第一边框边缘B101的最小距离为第一边缘距离a，第二走线边缘B122与第二边框边缘B102的最小距离为第二边缘距离b。第一边缘距离a与第二边缘距离b的比值可以为0.9至1.1，例如，第一边缘距离a可以等于第二边缘距离b。例如，第一边缘距离a可以大于或等于0.4毫米，第二边缘距离b可以大于或等于0.4毫米。
本示例通过设置弯折区域B12的信号弯折线关于第二中心线O2对称设置，且第一边缘距离a和第二边缘距离b大致相同，可以减小左下边框和右下边框内的布线差异性，有利于减小左下边框和右下边框内相同信号的传输负载差异。
图4为图3中区域S1的局部放大示意图。图4中对第一组数据弯折线311、第二组数据弯折线312和第一组第一电源弯折线321进行了整体示意。在一些示例中，如图4所示，显示区域AA的多条数据线可以根据第一中心线O1划分为第一组数据线DL1a和第二组数据线DL1b，第一组数据线DL1a内的数据线的数目和第二组数据线DL1b内的数据线的数目可以相同。例如，第一组数据线DL1a和第二组数据线DL1b可以关于第一中心线O1对称排布。例如，多条数据线可以位于第二源漏金属层或第三源漏金属层。
在一些示例中，如图4所示，第一子区域B11可以设置有多条第一数据扇出线。多条第一数据扇出线可以包括第一组第一数据扇出线211和第二组第一数据扇出线212。第一组第一数据扇出线211可以与第一组数据线DLa连接，第二组第一数据扇出线212可以与第二组数据线DLb连接。第一组第一数据扇出线211可以包括多条第一数据扇出线21a，多条第一数据扇出线21a可以与第一组数据线DLa内的多条数据线一一对应电连接。第二组第一数据扇出线212可以包括多条第一数据扇出线21b，多条第二数据扇出线21b可以与第二组数据线DLb内的多条数据线一一对应电连接。例如，多条第一数据扇出线可以交替排布在第一栅金属层和第二栅金属层，且相邻第一数据扇出线在衬底的正投影可以没有交叠。
在一些示例中，第一数据扇出线21a可以包括：相互连接的第一数据延伸段21-1a和第二数据延伸段21-2a。第二数据延伸段21-2a可以与一组数据弯折线(例如第一组数据弯折线311)内的至少一条数据弯折线连接。第一数据延伸段21-1a可以位于第二数据延伸段21-2a靠近显示区域AA的一侧。第二数据延伸段21-2a可以为沿第一方向Y延伸的直线段，第一数据延伸段21-1a的延伸方向可以与第一方向Y交叉，例如第一数据延伸段21-1a可以为延伸方向与第一方向Y和第二方向X均交叉的斜线段。
在一些示例中，第一数据扇出线21b可以包括：相互连接的第一数据延伸段21-1b和第二数据延伸段21-2b。第二数据延伸段21-2b可以与一组数据弯折线(例如第二组数据弯折线312)内的至少一条数据弯折线连接。第一数据延伸段21-1b可以位于第二数据延伸段21-2b靠近显示区域AA的一侧。第二数据延伸段21-2b可以为沿第一方向Y延伸的直线段，第一数据延伸段21-1b的延伸方向可以与第一方向Y交叉，例如第一数据延伸段21-1b可以为延伸方向与第一方向Y和第二方向X均交叉的斜线段。
在一些示例中，靠近第一中心线O1且位于第一中心线O1的第一侧(例如左侧)的至少一条第一数据扇出线(例如，第一数据扇出线21a)的第一数据延伸段21-1a的长度，可以大于靠近第一中心线O1且位于第一中心线O1的第二侧(例如右侧)的至少一条第一数据扇出线(例如，第一数据扇出线21b)的第一数据延伸线21-1b的长度。靠近第一中心线O1的至少一条第一数据扇出线21a的第二数据延伸段21-2a的长度，可以小于靠近第一中心线O1的至少一条第一数据扇出线21b的第二数据延伸线21-2b的长度。本示例通过设置第一数据延伸段21-1a的长度大于第一数据延伸段21-1b的长度，可以使得弯折区域B12的数据弯折线的对称中心线向第一中心线O1沿第二方向X的反方向一侧移动，例如，可以使得弯折区域B12的多条数据弯折线的对称中心线(即第三中心线O3)与第二中心线O2重合。
在一些示例中，第二子区域B13可以设置有多条数据引出线。多条数据引出线可以至少包括：第一组数据引出线411和第二组数据引出线412。第一组数据引出线411可以与第一组数据弯折线311连接，第二组数据引出线412可以与第二组数据弯折线312连接。位于第二中心线O2两侧的数据引出线的数目可以相同，且位于第二中心线O2两侧的数据引出线可以没有关于第二中心线O2对称排布。例如，多条数据引出线可以交替排布在第一栅金属层和第二栅金属层，且相邻数据引出线在衬底的正投影可以没有交叠。然而，本实施例对此并不限定。在另一些示例中，位于第二中心线O2两侧的数据引出线可以关于第二中心线O2对称排布。
本示例中，弯折区域B12的多条信号弯折线可以关于第三中心线O3对称设置，且第三中心线O3可以与第二中心线O2重合，从而保证第二中心线O2两侧区域内的信号弯折线的一致性，可以保证弯折效果。例如，本示例的设置方式可以保证第二中心线O2两侧的弯折区域内的传输相同信号的走线负载一致，从而避免由于信号负载不一致带来的显示问题。
在一些示例中，第一子区域B11内的多条第一数据扇出线没有关于第二中心线O2对称设置，第二子区域B13内的多条数据引出线没有关于第二中心线O2对称设置。第一信号接入区域B14设置的多个数据接触垫可以关于第二中心线O2对称设置，多条数据引出线可以与多个数据接触垫连接。例如，第二子区域B13可以设置数据负载补偿结构，以实现第一边框区域传输的数据信号的负载均一性。
在一些示例中，第二子区域B13可以包括第二扇出区域和第三扇出区域。多条数据引出线可以包括：位于第二扇出区域的多条第二数据扇出线和位于第三扇出区域的多条第三数据扇出线。数据负载补偿结构可以位于第二子区域的第二扇出区域和第三扇出区域中的至少之一区域，数据负载补偿结构可以与第二子区域内的数据引出线串联连接；比如，数据负载补偿结构可以位于第二扇出区域并与第二数据扇出线串联连接，或者，可以位于第三扇出区域并与第三数据扇出线串联连接。在一些示例中，数据负载补偿结构可以为蛇形走线，通过增加数据引出线的长度来增加电阻。蛇形走线是一种弯折曲线。例如，走线一端沿一个方向延伸一段距离后，弯折迂回并向与该方向的相反方向延伸一段距离，再次弯折迂回而向该方向延伸，如此反复弯折迂回若干次，形成蛇形走线。
在另一些示例中，可以通过将第二子区域内的数据引出线变细来增加电阻，以进行负载补偿。或者，可以通过增加第二子区域内的数据引出线的多个线段之间的跳线次数，来增加电阻，以进行负载补偿。或者，可以将第二子区域内的数据引出线设置在电阻率较高的导电层，来增加电阻。
在另一些示例中，可以通过增大第二子区域内的数据引出线的线宽来降低电阻，以进行负载补偿。或者，可以通过将第二子区域内的数据引出线设置为双层或多层走线来降低电阻。或者，可以将第二子区域内的数据引出线设置在电阻率较低的导电层来降低电阻。本实施例对于第一边框区域的数据信号的负载补偿方式并不限定。
图5为本公开至少一实施例的第一边框区域的另一局部结构示意图。图6为本公开至少一实施例的第一边框区域的局部走线示意图。图5和图6中整体示意了弯折区域B12的每组数据弯折线、每组第一电源弯折线、每组第二电源弯折线、每组控制弯折线以及每组触控弯折线。
在一些示例中，如图5和图6所示，弯折区域B12可以设置有：四组数据弯折线(例如包括第一组数据弯折线311、第二组数据弯折线312、第三组数据弯折线313和第四组数据弯折线314)、三组第一电源弯折线(例如包括第一组第一电源弯折线321、第二组第一电源弯折线322和第三组第一电源弯折线323)、四组第二电源弯折线(例如包括第一组第二电源弯折线331、第二组第二电源弯折线332、第三组第二电源弯折线333和第四组第二电源弯折线334)、两组控制弯折线(例如包括第一组控制弯折线341和第二组控制弯折线342)、两组触控弯折线(例如包括第一组触控弯折线351和第二组触控弯折线352)。弯折区域B12内的多条信号弯折线可以具有沿第一方向Y延伸的第四中心线O4，第四中心线O4可以与第三中心线O3重合，弯折区域B12内的多条信号弯折线可以关于第三中心线O3对称设置，且第三中心线O3可以与第二中心线O2重合。
在一些示例中，第一组控制弯折线341、第三组第二电源弯折线333、第一组触控弯折线351、第一组第二电源弯折线331、第三组数据弯折线313、第二组第一电源弯折线322、第一组数据弯折线311、第一组第一电源弯折线321、第二组数据弯折线312、第三组第一电源弯折线323、第四组数据弯折线314、第二组第二电源弯折线332、第二组触控弯折线351、第四组第二电源弯折线334、以及第二组控制弯折线342可以沿第二方向X依次排布。
在一些示例中，如图6所示，第一子区域B11可以设置有多条第一数据扇出线、第一周边电源线22、第二周边电源线231和232、以及多条周边控制线(例如包括第一组周边控制线241和第二组周边控制线242)。多条第一数据扇出线可以包括第一组第一数据扇出线、第二组第一数据扇出线、第三组第一数据扇出线213和第四组第一数据扇出线214。第三组第一数据扇出线213、第一组第一数据扇出线、第二组第一数据扇出线和第四组第一数据扇出线214可以沿第二方向X依次排布。第一组第一数据扇出线可以与第一组数据弯折线311连接，第二组第一数据扇出线可以与第二组数据弯折线312连接，第三组第一数据扇出线213可以与第三组数据弯折线313连接，第四组第一数据扇出线214可以与第四组数据弯折线314连接。例如，多条第一数据扇出线可以交替排布在第一栅金属层和第二栅金属层，或者可以均位于第一栅金属层，或者可以均位于第二栅金属层。
在一些示例中，第一周边电源线22可以为位于第一源漏金属层的单层走线，或者可以为位于第二源漏金属层的单层走线，或者可以为位于第一源漏金属层和第二源漏金属层的双层走线。第一周边电源线22可以包括沿第二方向X延伸的第一电源主体部和沿第一方向Y延伸的多个第一电源连接部(例如三个第一连接部)。三个第一电源连接部可以与三组第一电源弯折线(例如包括第一组第一电源弯折线321、第二组第一电源弯折线322和第三组第一电源弯折线323)一一对应电连接。例如，一个第一电源连接部与对应连接的一组第一电源弯折线可以为相互连接的一体结构。在一些示例中，第一周边电源线22可以关于第三中心线O3大致对称。
在一些示例中，第二周边电源线231和232可以位于第一周边电源线22的第一电源主体部远离显示区域AA的一侧。第二周边电源线231可以向第二边框区域B2延伸，第二周边电源线232可以向第三边框区域B3延伸。第二周边电源线231可以位于第三中心线O3的一侧，第二周边电源线232可以位于第三中心线O3的另一侧。例如，第二周边电源线231和232可以关于第三中心线O3大致对称。第二周边电源线231可以与第一组第二电源弯折线331和第三组第二电源弯折线333连接。第二周边电源线232可以与第二组第二电源弯折线332和第四组第二电源弯折线334连接。在一些示例中，第二周边电源线231和232可以为位于第一源漏金属层的单层走线，或者可以为位于第二源漏金属层的单层走线，或者可以为位于第一源漏金属层和第二源漏金属层的双层走线。
在一些示例中，第一组周边控制线241可以位于第三中心线O3的一侧，第二组周边控制线242可以位于第三中心线O3的另一侧。第一组周边控制线241可以向第二边框区域B2延伸，第二组周边控制线242可以向第三边框区域B3延伸。第一组周边控制线241可以与第一组控制弯折线341连接，第二组周边控制线242可以与第二组控制弯折线342连接。多条周边控制线可以位于第二周边电源线231和232靠近衬底的一侧，例如可以位于第一栅金属层或第二栅金属层。
在一些示例中，第二子区域B13可以设置有第一电源引出线42、第二电源引出线431和432、多条控制引出线(例如包括第一组控制引出线441和第二组控制引出线442)、多条数据引出线(例如包括第一组数据引出线、第二组数据引出线、第三组数据引出线413和第四组数据引出线414)。第三组数据引出线413、第一组数据引出线、第二组数据引出线和第四组数据引出线414可以沿第二方向X排布。第一组数据引出线可以与第一组数据弯折线311连接，第二组数据引出线可以与第二组数据弯折线312连接，第三组数据引出线413可以与第三组数据弯折线313连接，第四组数据引出线414可以与第四组数据弯折线314连接。第一组数据弯折线311可以实现第一组第一数据扇出线和第一组数据引出线之间的电连接，第二组数据弯折线312可以实现第二组第一数据扇出线和第二组数据引出线之间的电连接，第三组数据弯折线313可以实现第三组第一数据扇出线和第三组数据引出线之间的电连接，第四组数据弯折线314可以实现第四组第一数据扇出线和第四组数据引出线之间的电连接。在一些示例中，多条数据引出线可以交替排布在第一栅金属层和第二栅金属层，或者可以均设置在第一栅金属层，或者可以均设置在第二栅金属层。
在一些示例中，如图5和图6所示，第一电源引出线42可以包括：沿第二方向X延伸的第二电源主体部420、沿第一方向Y延伸且位于第二电源主体420远离弯折区域B12一侧的第一电源延伸部421和第二电源延伸部422、沿第二方向Y延伸且位于第二电源主体部420靠近弯折区域B12一侧的多个第二电源连接部(例如包括三个第二电源连接部)。第二电源主体部420、第一电源延伸部421、第二电源延伸部422和多个第二电源连接部可以为相互连接的一体结构。例如，第一电源引出线42可以关于第三中心线O3大致对称。第一电源延伸部421连接在第二电源主体部420在第二方向X的一端，第二电源延伸部422连接在第二电源主体部420在第二方向X的另一端。第一电源延伸部421可以从第一信号接入区域B14在第二方向X的反方向的一侧(例如左侧)绕过第一信号接入区域B14，并延伸至第二信号接入区域B15，与第二信号接入区域B15内的第二接触垫连接。第二电源延伸部422可以从第一信号接入区域B14在第二方向X的另一侧(例如右侧)绕过第一信号接入区域B14，并延伸至第二信号接入区域B15，与第二信号接入区域B15内的第二接触垫连接。三个第二电源连接部可以与第一组第一电源弯折线321、第二组第一电源弯折线322和第三组第一电源弯折线323一一对应电连接，以实现与第一子区域B11内的第一周边电源线22电连接。在一些示例中，第一电源引出线42可以为位于第一源漏金属层的单层走线，或者，可以为位于第二源漏金属层的单层走线，或者，可以为位于第一源漏金属层和第二源漏金属层的双层走线。
在一些示例中，第二电源引出线431可以位于第一电源引出线42在第二方向X的反方向的一侧，第二电源引出线432可以位于第一电源引出线42在第二方向X的一侧。第二电源引出线431可以与第一组第二电源弯折线331和第三组第二电源弯折线333连接，以实现与第一子区域B11内的第二周边电源线231的电连接；第二电源引出线432可以与第二组第二电源引出线332和第四组第二电源引出线334连接，以实现与第一子区域B11内的第二周边电源线232的电连接。例如，第二电源引出线431和第二电源引出线432可以关于第三中心线O3大致对称。在一些示例中，第二电源引出线431和432可以为位于第一源漏金属层的单层走线，或者，可以为位于第二源漏金属层的单层走线，或者，可以为位于第一源漏金属层和第二源漏金属层的双层走线。
在一些示例中，第一电源引出线42配置为传输第一电压信号，第二电源引出线431和432配置为传输第二电压信号。第一电压信号不同于第二电压信号。例如，第一电压信号可以大于第二电压信号。第一电压信号可以被配置为提供给显示区域的子像素的像素电路，第二电压信号可以被配置为提供给显示区域的子像素的发光元件的阴极。本实施例对此并不限定。
在一些示例中，第一组控制引出线441可以与第一组控制弯折线341连接，以实现与第一子区域B11内的第一组周边控制线241的电连接；第二组控制引出线442可以与第二组控制弯折线342连接，以实现与第一子区域B11内的第二组周边控制线242的电连接。多条控制引出线可以包括：给栅极驱动电路提供信号(例如起始信号、时钟信号、电压信号等)的走线、传输面板测试信号的走线等。
本示例的弯折区域B12的信号弯折线可以关于第三中心线O3对称设置，且第三中心线O3可以与第二中心线O2重合，第一边缘距离a和第二边缘距离b大致相同，可以保证弯折区域B12在第二中心线O2两侧区域内的走线的密度和膜层一致性，便于保证弯折性能。本示例可以保证第一组控制弯折线341和第二组控制弯折线342所传输信号的负载一致性，避免由于两侧信号负载不一致带来的显示问题。本示例还可以保证第二中心线两侧的第一电压信号和第二电压信号的传输负载一致性。本示例还可以保证第一边框区域的空间被最大化利用。关于本示例的第一边框区域的其余结构可以参照前述实施例的描述，故于此不再赘述。
图7为本公开至少一实施例的第一边框区域的另一局部示意图。在一些示例中，如图7所示，弯折区域B12可以设置有：四组数据弯折线(例如第一组数据弯折线311、第二组数据弯折线312、第三组数据弯折线313和第四组数据弯折线314)、三组第一电源弯折线(例如第一组第一电源弯折线321、第二组第一电源弯折线322、第三组第一电源弯折线323)、两组第二电源弯折线(例如第一组第二电源弯折线331和第二组第二电源弯折线332)以及两组控制弯折线(例如第一组控制弯折线341和第二组控制弯折线342)。
在一些示例中，第一组控制弯折线341、第一组第二电源弯折线331、第三组数据弯折线313、第二组第一电源弯折线322、第一组数据弯折线311、第一组第一电源弯折线321、第二组数据弯折线312、第三组第一电源弯折线323、第四组数据弯折线314、第二组第二电源弯折线332和第二组控制弯折线342可以沿第二方向X依次设置。
在一些示例中，第一组数据弯折线311和第二组数据弯折线312可以关于第三中心线O3对称设置，第二组数据弯折线313和第四组数据弯折线314可以关于第三中心线O3对称设置，第一组第一电源弯折线321可以关于第三中心线O3对称设置，第二组第一电源弯折线322和第三组第一电源弯折线323可以关于第三中心线O3对称设置，第一组第二电源弯折线331和第二组第二电源弯折线332可以关于第三中心线O3对称设置，第一组控制弯折线341和第二组控制弯折线342可以关于第三中心线O3对称设置。
在一些示例中，第四中心线O4与第三中心线O3重合。第三中心线O3可以与第二中心线O2重合。第一边缘距离a和第二边缘距离b可以大致相同。本示例通过设置弯折区域B12的一组信号弯折线关于第二中心线O2对称设置，且第一边缘距离a和第二边缘距离b大致相同，可以减小左下边框和右下边框内的布线差异性，有利于减小左下边框和右下边框内相同信号的传输负载差异。
关于本示例的第一边框区域的其余说明可以参照前述实施例的描述，故于此不再赘述。
图8为本公开至少一实施例的第一边框区域的另一局部示意图。图9为图8中区域S2的局部放大示意图。在一些示例中，如图8和图9所示，弯折区域B12的多条信号弯折线可以包括：四组数据弯折线(例如包括第一组数据弯折线311、第二组数据弯折线312、第三组数据弯折线313和第四组数据弯折线314)、五组第一电源弯折线(例如包括第一组第一电源弯折线321、第二组第一电源弯折线322、第三组第一电源弯折线323、第四组第一电源弯折线324和第五组第一电源弯折线325)、两组第二电源弯折线(例如包括第一组第二电源弯折线331、第二组第二电源弯折线332)、两组控制弯折线(例如包括第一组控制弯折线341和第二组控制弯折线342)。
在一些示例中，如图8所示，第一组控制弯折线342、第一组第二电源弯折线331、第四组第一电源弯折线324、第三组数据弯折线313、第二组第一电源弯折线322、第一组数据弯折线311、第一组第一电源弯折线321、第二组数据弯折线313、第三组第一电源弯折线323、第四组数据弯折线314、第五组第一电源弯折线325、第二组第二电源弯折线332和第二组控制弯折线342可以沿第二方向X依次排布。
在一些示例中，弯折区域B12的多条信号弯折线可以具有沿第一方向Y延伸的第四中心线O4，第四中心线O4可以与第三中心线O3重合。例如，多条信号弯折线可以关于第三中心线O3对称设置。弯折区域B12的走线在衬底的正投影可以具有沿第一方向Y延伸的第一走线边缘B121和第二走线边缘B122，第一走线边缘B121可以为走线左侧边缘，第二走线边缘B122可以为走线右侧边缘。第三中心线O3与第一走线边缘B121之间的距离和第三中心线O3与第二走线边缘B122之间的距离可以相同。
在一些示例中，第三中心线O3与第二中心线O2在第二方向X上的距离可以大于0。第三中心线O3与第二中心线O2可以没有重合。例如，第三中心线O3可以位于第二中心线O2和第一中心线O1的中间。第三中心线O3与第一中心线O1之间的距离与第三中心线O3与第二中心线O2之间的距离可以相同，或者，可以不同。第一中心线O1可以位于第二中心线O2在第二方向X的一侧。然而，本实施例对此并不限定。在另一些示例中，第三中心线O3可以与第一中心线O1重合。
在一些示例中，第一走线边缘B121与第一边框边缘B101的最小距离为第一边缘距离a，第二走线边缘与第二边框边缘B102的最小距离为第二边缘距离b。第一边缘距离a可以不同于第二边缘距离b。例如，第一边缘距离a和第二边缘距离b的比值可以大于1。换言之，第一边缘距离a可以大于第二边缘距离b。其中，第一边缘距离a可以大于或等于0.4毫米，第二边缘距离b可以大于或等于0.4毫米。
在一些示例中，如图9所示，第一子区域B11可以设置有多条第一数据扇出线。多条第一数据扇出线可以包括第一组第一数据扇出线211和第二组第一数据扇出线212。第一组第一数据扇出线211可以与第一组数据线DLa连接，第二组第一数据扇出线212可以与第二组数据线DLb连接。第一组第一数据扇出线211可以包括多条第一数据扇出线21a，多条第一数据扇出线21a可以与第一组数据线DLa内的多条数据线一一对应电连接。第二组第一数据扇出线212可以包括多条第一数据扇出线21b，多条第二数据扇出线21b可以与第二组数据线DLb内的多条数据线一一对应电连接。
在一些示例中，第一数据扇出线21a可以包括相互连接的第一数据延伸段21-1a和第二数据延伸段21-2a。第二数据延伸段21-2a可以与一组数据弯折线(例如第一组数据弯折线311)内的至少一条数据弯折线连接。第一数据延伸段21-1a可以位于第二数据延伸段21-2a靠近显示区域AA的一侧。第二数据延伸段21-2a可以为沿第一方向Y延伸的直线段，第一数据延伸段21-1a的延伸方向可以与第一方向Y交叉，例如第一数据延伸段21-1a可以为延伸方向与第一方向Y和第二方向X均交叉的斜线段。
在一些示例中，第一数据扇出线21b可以包括相互连接的第一数据延伸段21-1b和第二数据延伸段21-2b。第二数据延伸段21-2b可以与一组数据弯折线(例如第二组数据弯折线312)内的至少一条数据弯折线连接。第一数据延伸段21-1b可以位于第二数据延伸段21-2b靠近显示区域AA的一侧。第二数据延伸段21-2b可以为沿第一方向Y延伸的直线段，第一数据延伸段21-1b的延伸方向可以与第一方向Y交叉，例如第一数据延伸段21-1b可以为延伸方向与第一方向Y和第二方向X均交叉的斜线段。
在一些示例中，靠近第一中心线O1的至少一条第一数据扇出线21a的第一数据延伸段21-1a的长度，可以大于靠近第一中心线O1的至少一条第一数据扇出线21b的第一数据延伸线21-1b的长度。本示例中，第一数据扇出线21a的第一数据延伸段21-1a与第一数据扇出线21b的第一数据延伸段21-b的长度比值，可以小于图4所示实施例中的第一数据扇出线21a的第一数据延伸段21-1a与第一数据扇出线21b的第一数据延伸段21-b的长度比值，可以减小第一中心线O1两侧的第一数据扇出线之间的负载差异。
在本示例中，弯折区域B12的走线可以关于第三中心线O3大致对称设置，通过调整第一边缘距离a和第二边缘距离b(例如第一边缘距离a大于第二边缘距离b)，可以使得第三中心线O3位于第二中心线O2和第一中心线O1之间，减少第一子区域B11内的第一数据扇出线之间的负载差异，从而便于数据信号的补偿，可以有利于实现数据信号的负载一致性。本示例可以减小左下边框和右下边框内的布线差异性，有利于减小左下边框和右下边框内相同信号的传输负载差异。关于本示例的其余说明可以参照前述实施例的描述，故于此不再赘述。
图10为本公开至少一实施例的第一边框区域的另一局部示意图。图11为图10中区域S3的局部放大示意图。在一些示例中，如图10和图11所示，第一距离L1可以大于第二距离L2，第一中心线O2可以位于第一中心线O1在第二方向X的一侧。弯折区域B12内第三中心线O3的左侧走线与右侧走线可以大致对称排布。第三中心线O3可以位于第一中心线O1和第二中心线O2的中间。第四中心线O4可以与第三中心线O3重合。
在一些示例中，第二边缘距离b与第一边缘距离a的比值可以大于1。换言之，第二边缘距离b可以大于第一边缘距离a。
在一些示例中，靠近第一中心线O1的至少一条第一数据扇出线21a的第一数据延伸段21-1a的长度，可以小于靠近第一中心线O1的至少一条第一数据扇出线21b的第一数据延伸线21-1b的长度。靠近第一中心线O1的至少一条第一数据扇出线21a的第二数据延伸段21-2a的长度，可以大于靠近第一中心线O1的至少一条第一数据扇出线21b的第二数据延伸线21-2b的长度。
在本示例中，弯折区域B12的走线可以关于第三中心线O3大致对称设置，通过调整第一边缘距离a和第二边缘距离b(例如第二边缘距离b大于第一边缘距离a)，可以使得第三中心线O3位于第二中心线O2和第一中心线O1之间(或者与第一中心线O1重合)，减少第一子区域B11内的第一数据扇出线之间的负载差异，从而便于数据信号的补偿，可以有利于实现数据信号的负载一致性。本示例可以减小左下边框和右下边框内的布线差异性，有利于减小左下边框和右下边框内相同信号的传输负载差异。关于本示例的其余说明可以参照前述实施例的描述，故于此不再赘述。
图12为本公开至少一实施例的第一边框区域的另一局部示意图。图13为图12中区域S4的局部放大示意图。在一些示例中，如图12和图13所示，第一中心线O1可以位于第二中心线O2在第二方向X的一侧。弯折区域B12的多条信号弯折线可以包括：四组数据弯折线(例如包括第一组数据弯折线311、第二组数据弯折线312、第三组数据弯折线313和第四组数据弯折线314)、五组第一电源弯折线(例如包括第一组第一电源弯折线321、第二组第一电源弯折线322、第三组第一电源弯折线323、第四组第一电源弯折线324和第五组第一电源弯折线325)、两组第二电源弯折线(例如包括第一组第二电源弯折线331、第二组第二电源弯折线332)、两组控制弯折线(例如包括第一组控制弯折线341和第二组控制弯折线342)。第一组控制弯折线342、第一组第二电源弯折线331、第四组第一电源弯折线324、第三组数据弯折线313、第二组第一电源弯折线322、第一组数据弯折线311、第一组第一电源弯折线321、第二组数据弯折线313、第三组第一电源弯折线323、第四组数据弯折线314、第五组第一电源弯折线325、第二组第二电源弯折线332和第二组控制弯折线342可以沿第二方向X依次排布。
在一些示例中，第一组第一电源弯折线321沿第二方向X的总长度，可以小于图8所示实施例中第一组第一电源弯折线沿第二方向X的总长度。例如，可以通过减小第一组第一电源弯折线中的第一电源弯折线的数目来减少沿第二方向X的总长度，或者，可以通过减小第一组第一电源弯折线中相邻第一电源弯折线之间的间距来减少沿第二方向X的总长度，或者，可以通过减小第一组第一电源弯折线中的第一电源弯折线的线宽和间距来减少沿第二方向X的长度。本实施例对此并不限定。
在一些示例中，弯折区域的多条信号弯折线可以具有沿第一方向Y延伸的第四中心线O4，多条信号弯折线可以关于第四中心线O4对称设置。第四中心线O4可以与第三中心线O3重合，第三中心线O3可以与第一中心线O1重合。第一子区域B11内的多条第一数据扇出线可以关于第一中心线O1对称设置，例如，多条第一数据扇出线21a和多条第一数据扇出线21b可以关于第一中心线O1对称设置。第一组数据引出线411和第二组数据引出线412可以关于第一中心线O1对称设置。
本示例通过沿第二方向X整体移动弯折区域B12内的走线并减少第一组第一电源弯折线沿第二方向的长度，并结合对第一边缘距离a和第二边缘距离b的调整，可以使得第三中心线O3与第一中心线O1重合。本示例可以使得第一子区域B11内的多条第一数据扇出线关于第一中心线O1大致对称，可以保证第一子区域内的数据信号负载一致性。本示例的一组信号弯折线关于第一中心线O1对称设置，可以有利于减小左下边框和右下边框内的布线差异性，有利于减小左下边框和右下边框内相同信号的传输负载差异。关于本示例的其余说明可以参照前述实施例的描述，故于此不再赘述。
图14为本公开至少一实施例的第一边框区域的另一局部示意图。在一些示例中，如图14所示，第一中心线O1可以位于第二中心线O2在第二方向X的一侧。弯折区域B12的多条信号弯折线可以包括：四组数据弯折线(例如包括第一组数据弯折线311、第二组数据弯折线312、第三组数据弯折线313和第四组数据弯折线314)、五组第一电源弯折线(例如包括第一组第一电源弯折线321、第二组第一电源弯折线322、第三组第一电源弯折线323、第四组第一电源弯折线324和第五组第一电源弯折线325)、两组第二电源弯折线(例如包括第一组第二电源弯折线331、第二组第二电源弯折线332)、两组控制弯折线(例如包括第一组控制弯折线341和第二组控制弯折线342)。第一组控制弯折线342、第一组第二电源弯折线331、第四组第一电源弯折线324、第三组数据弯折线313、第二组第一电源弯折线322、第一组数据弯折线311、第一组第一电源弯折线321、第二组数据弯折线313、第三组第一电源弯折线323、第四组数据弯折线314、第五组第一电源弯折线325、第二组第二电源弯折线332和第二组控制弯折线342可以沿第二方向X依次排布。
在一些示例中，第四组第一电源弯折线324在衬底的正投影沿第二方向X的长度，可以大于第一组第一电源弯折线321在衬底的正投影沿第二方向X的长度；第一组第一电源弯折线321在衬底的正投影沿第二方向X的长度，可以大于第二组第一电源弯折线322、第三组第一电源弯折线323、第五组第一电源弯折线325各自在衬底的正投影沿第二方向X的长度。
在一些示例中，可以通过以下至少之一方式来增加第四组第一电源弯折线324沿第二方向X的总长度：增加第四组第一电源弯折线324中的第一电源弯折线的数目、增加第四组第一电源弯折线324中相邻第一电源弯折线之间的间距长度、增加第四组第一电源内弯折线324中的第一电源弯折线的线宽。然而，本实施例对此并不限定。
本示例中，弯折区域的多条电源弯折线可以包括：多条第一电源弯折线和多条第二电源弯折线。位于第三中心线O3一侧的第一组电源弯折线可以包括：第二组第一电源弯折线322、第四组第一电源弯折线324、第一组第一电源弯折线321的一半走线、第一组第二电源弯折线331；位于第三中心线O3另一侧的第二组电源弯折线可以包括：第三组第一电源弯折线323、第五组第一电源弯折线325、第一组第一电源弯折线321的一半走线、第二组第二电源弯折线332。通过增加第四组第一电源弯折线324沿第二方向X的长度，来使得第一组电源弯折线沿第二方向X的长度大于第二组电源弯折线沿第二方向X的长度。然而，本实施例对此并不限定。在另一些示例中，可以通过增加第一组第二电源弯折线331沿第二方向X的长度，来使得第一组电源弯折线沿第二方向X的长度大于第二组电源弯折线沿第二方向X的长度。
在一些示例中，多条信号弯折线中的多条数据弯折线可以关于第三中心线O3对称设置，多条信号弯折线可以具有沿第一方向Y延伸的第四中心线O4，第四中心线O4可以位于第三中心线O3靠近第二中心线O2的一侧，例如，第四中心线O4可以与第二中心线O2重合。多条信号弯折线可以关于第四中心线O4非对称设置。
在一些示例中，第三中心线O3是多组数据弯折线的对称线。第三中心线O3可以与第一中心线O1重合。例如，第一组数据弯折线311和第二组数据弯折线312可以第一中心线O1大致对称，第三组数据弯折线313和第四组数据弯折线314可以关于第一中心线O1大致对称。如此一来，第一子区域B11内的多条数据扇出线可以关于第一中心线O1对称设置，从而可以减少第一子区域B11内第一中心线O1两侧的第一数据扇出线之间的负载差异，有利于实现数据信号的负载一致性。
在一些示例中，第一组控制弯折线341和第二组控制弯折线342没有关于第三中心线O3对称设置，第一组第二电源弯折线331和第二组第二电源弯折线332没有关于第三中心线O3对称设置。例如，第一组控制弯折线341和第二组控制弯折线342可以关于第二中心线O2对称设置，第一组第二电源弯折线331和第二组第二电源弯折线332可以关于第二中心线O2对称设置。第一边缘距离a与第二边缘距离b的比值可以为0.9至1.1，例如，第一边缘距离a和第二边缘距离b可以大致相同。如此一来，可以有利于改善弯折区域内的走线均一性，保证弯折效果。
本示例通过增加第四组第一电源弯折线324沿第二方向X的长度，可以使得多组数据弯折线关于第一中心线O1对称设置，可以有利于实现数据信号的负载一致性，而且可以使得第一边缘距离和第二边缘距离大致相同，可以减小左下边框和右下边框内的布线差异性，有利于减小左下边框和右下边框内相同信号的传输负载差异。关于本示例的其余说明可以参照前述实施例的描述，故于此不再赘述。
在另一些示例中，可以通过增加第四组第一电源弯折线和第一组第二电源弯折线沿第二方向的长度，来使得多组数据弯折线关于第一中心线对称设置，且使得第一边缘距离和第二边缘距离大致相同。
在另一些示例中，可以通过减少第五组第一电源弯折线和第二组第二电源弯折线中至少之一沿第二方向的长度，来使得多组数据弯折线关于第一中心线对称设置，且使得第一边缘距离和第二边缘距离大致相同。
在另一些示例中，可以通过增加第四组第一电源弯折线和第一组第二电源弯折线中至少之一沿第二方向的长度，且通过减少第五组第一电源弯折线和第二组第二电源弯折线中至少之一沿第二方向的长度，使得多组数据弯折线关于第一中心线对称设置，且使得第一边缘距离和第二边缘距离大致相同。
图15为本公开至少一实施例的显示基板的另一示意图。在一些示例中，如图15所示，显示区域AA可以设置有多条数据线DL和多条数据转接线25。至少一条数据线DL可以通过数据转接线25与第一子区域B11的第一数据扇出线连接。数据转接线25可以包括沿第二方向X延伸的第一转接段251和沿第一方向Y延伸的第二转接段252。第一转接段251可以与数据线DL和第二转接段252连接，第二转接段252可以与第一数据扇出线连接。第二转接段252可以位于所连接的数据线DL远离显示基板的边缘的一侧。在一些示例中，第一转接段251和第二转接段252可以位于第三源漏金属层，数据线DL可以位于第二源漏金属层。然而，本实施例对此并不限定。关于本示例的显示基板的第一边框区域的结构说明可以参照前述实施例的描述，故于此不再赘述。
本实施例还提供一种显示基板，包括：显示区域和沿第一方向位于显示区域一侧的第一边框区域。第一边框区域包括：弯折区域、位于弯折区域和显示区域之间的第一子区域；显示区域具有沿第一方向延伸的第一中心线，第一边框区域具有沿第一方向延伸的第二中心线，第一中心线与第二中心线之间的距离大于0。显示基板包括：衬底、设置在衬底的一侧且位于显示区域的多个子像素和多条数据线、位于第一子区域的多条第一数据扇出线、以及位于弯折区域的多条信号弯折线。所述多条数据线与多个子像素电连接，所述多条数据线配置为给所述多个子像素提供数据信号。多条第一数据扇出线与多条数据线连接。多条信号弯折线位于同一导电层。多条信号弯折线至少包括：多条数据弯折线，多条数据弯折线与多条第一数据扇出线连接，所述多条数据弯折线关于第三中心线对称设置。所述多条信号弯折线具有沿第一方向延伸的第四中心线，第四中心线与第三中心线重合，或者，位于第三中心线靠近第二中心线的一侧。其中，第一中心线、第二中心线、第三中心线和第四中心线的延伸方向可以相同。
本实施例针对显示区域的第一中心线和第一边框区域的第二中心线不在同一条直线的情况，将弯折区域的多条数据弯折线按照第三中心线对称设置，且弯折区域的多条信号弯折线的第四中心线与第三中心线重合，或者位于第三中心线靠近第二中心线的一侧，可以保证弯折区域的数据弯折线的密度和膜层一致性，便于保证弯折效果，并可以改善显示基板的不对称外形带来的信号走线差异化所带来的问题。
在一些示例性实施方式中，所述多条信号弯折线可以关于第四中心线对称设置；第三中心线和第四中心线与第二中心线重合。第一边框区域具有沿第一方向延伸的第一边框边缘和第二边框边缘，第一边框边缘和第二边框边缘沿第二方向位于弯折区域的信号弯折线的两侧，第二方向与第一方向交叉。例如，第二方向可以垂直于第一方向。弯折区域的信号弯折线与第一边框边缘的最小距离为第一边缘距离，弯折区域的信号弯折线与第二边框边缘的最小距离为第二边缘距离，第一边缘距离与第二边缘距离的比值为0.9至1.1。例如，第一边缘距离可以等于第二边缘距离。本示例可以保证弯折区域的走线与显示基板的两侧边缘的距离一致性，有利于弯折区域的走线排布，有利于保证弯折效果。
在一些示例性实施方式中，所述多条信号弯折线可以关于第四中心线对称设置。第三中心线与第四中心线重合，且位于第一中心线和第二中心线之间；或者，第三中心线和第四中心线与第一中心线重合。第一边框区域具有沿第一方向延伸的第一边框边缘和第二边框边缘，第一边框边缘和第二边框边缘沿第二方向位于弯折区域的信号弯折线的两侧。弯折区域的信号弯折线与第一边框边缘的最小距离为第一边缘距离，弯折区域的信号弯折线与第二边框边缘的最小距离为第二边缘距离，第一边缘距离与第二边缘距离的比值大于1，或者，第二边缘距离与第一边缘距离的比值大于1。换言之，第一边缘距离不同于第二边缘距离。本示例通过调整第一边缘距离和第二边缘距离存在差异性，有利于保证弯折区域的走线的对称排布，从而减小第一边框区域内信号之间的差异性。
在一些示例性实施方式中，多条信号弯折线可以关于第四中心线非对称设置，第四中心线可以与第二中心线重合，第三中心线可以与第一中心线重合。第一边框区域可以具有沿第一方向延伸的第一边框边缘和第二边框边缘，第一边框边缘和第二边框边缘沿第二方向位于弯折区域的信号弯折线的两侧。弯折区域的信号弯折线与第一边框边缘的最小距离为第一边缘距离，弯折区域的信号弯折线与第二边框边缘的最小距离为第二边缘距离，第一边缘距离与第二边缘距离的比值为0.9至1.1。例如，第一边缘距离可以等于第二边缘距离。本示例可以保证弯折区域的走线与显示基板的两侧边缘的距离一致性，有利于弯折区域的走线排布，有利于保证弯折效果。
关于本实施例的显示基板的其余说明可以参照前述实施例的描述，故于此不再赘述。
图16为本公开至少一实施例的显示装置的示意图。在一些示例中，如图16所示，显示装置91可以包括显示基板910。显示基板910可以为OLED显示基板。显示装置91可以为：OLED显示装置、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、折叠显示屏、车载显示装置或导航仪等任何具有显示功能的产品或部件。然而，本实施例对此并不限定。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本申请的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本申请的限制，本领域的普通技术人员在本申请的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (20)

  1. 一种显示基板，包括：显示区域和沿第一方向位于所述显示区域一侧的第一边框区域；所述第一边框区域包括：弯折区域、位于所述弯折区域和所述显示区域之间的第一子区域；所述显示区域具有沿所述第一方向延伸的第一中心线，所述第一边框区域具有沿所述第一方向延伸的第二中心线；所述第一中心线与所述第二中心线之间的距离大于0；
    所述显示基板包括：
    衬底；
    多个子像素，设置在所述衬底的一侧且位于所述显示区域；
    多条数据线，位于所述显示区域，所述多条数据线与所述多个子像素电连接，所述多条数据线配置为给所述多个子像素提供数据信号；
    多条第一数据扇出线，位于所述第一子区域，并与所述多条数据线连接；
    多条数据弯折线，位于所述弯折区域，并与所述多条第一数据扇出线连接，所述多条数据弯折线关于第三中心线对称设置；所述第三中心线与所述第一中心线重合，或者与所述第二中心线重合，或者位于所述第一中心线和所述第二中心线之间。
  2. 根据权利要求1所述的显示基板，还包括：位于所述弯折区域且沿所述第一方向延伸的多条第一电源弯折线，所述多条第一电源弯折线与所述多条数据弯折线沿第二方向间隔设置，所述第二方向与所述第一方向交叉；
    所述第一边框区域还包括：位于所述弯折区域远离所述第一子区域一侧的第二子区域；
    所述显示基板还包括：位于所述第一子区域的第一周边电源线和位于所述第二子区域的第一电源引出线，所述第一周边电源线和所述第一电源引出线通过所述多条第一电源弯折线连接；所述多条第一电源弯折线关于所述第三中心线对称设置。
  3. 根据权利要求2所述的显示基板，其中，所述多条数据弯折线包括：第一组数据弯折线、第二组数据弯折线、第三组数据弯折线和第四组数据弯折线；
    所述多条第一电源弯折线至少包括：第一组第一电源弯折线、第二组第一电源弯折线和第三组第一电源弯折线；
    所述第三组数据弯折线、所述第二组第一电源弯折线、所述第一组数据弯折线、所述第一组第一电源弯折线、所述第二组数据弯折线、所述第三组第一电源弯折线、以及所述第四组数据弯折线沿所述第二方向依次设置；
    所述第一组数据弯折线和所述第二组数据弯折线关于所述第三中心线对称设置，所述第三组数据弯折线和所述第四组数据弯折线关于所述第三中心线对称设置；所述第二组第一电源弯折线与所述第三组第一电源弯折线关于所述第三中心线对称设置，所述第一组第一电源弯折线关于所述第三中心线对称设置。
  4. 根据权利要求3所述的显示基板，其中，所述第一组第一电源弯折线沿所述第二方向的总长度，大于或等于所述第二组第一电源弯折线沿所述第二方向的总长度，且大于或等于所述第三组第一电源弯折线沿所述第二方向的总长度。
  5. 根据权利要求3所述的显示基板，其中，所述多条第一电源弯折线还包括：第四组第一电源弯折线和第五组第一电源弯折线，所述第四组第一电源弯折线位于所述第三组数据弯折线远离所述第二组第一电源弯折线的一侧，所述第五组第一电源弯折线位于所述第四组数据弯折线远离所述第三组第一电源弯折线的一侧；所述第四组第一电源弯折线与所述第五组第一电源弯折线关于所述第三中心线对称设置。
  6. 根据权利要求2所述的显示基板，还包括：位于所述弯折区域且沿所述第一方向延伸的多条第二电源弯折线，所述多条第二电源弯折线位于所述多条数据弯折线沿所述第二方向的两侧；
    所述显示基板还包括：位于所述第一子区域的第二周边电源线和位于所述第二子区域的第二电源引出线，所述第二周边电源线和所述第二电源引出线通过所述多条第二电源弯折线连接，所述第二周边电源线传输的第二电压信号不同于所述第一周边电源线传输的第一电压信号；所述多条第二电源弯折线关于所述第三中心线对称设置。
  7. 根据权利要求6所述的显示基板，还包括：位于所述弯折区域且沿所述第一方向延伸的多条控制弯折线，所述多条控制弯折线位于所述多条第二电源弯折线沿所述第二方向的两侧；所述多条控制弯折线关于所述第三中心线对称设置。
  8. 根据权利要求1至7中任一项所述的显示基板，其中，所述第三中心线与所述第二中心线重合；
    所述第一边框区域具有沿所述第一方向延伸的第一边框边缘和第二边框边缘，所述第一边框边缘和所述第二边框边缘沿第二方向位于所述弯折区域的走线两侧，所述第二方向与所述第一方向交叉；
    所述弯折区域的走线与所述第一边框边缘的最小距离为第一边缘距离，所述弯折区域的走线与所述第二边框边缘的最小距离为第二边缘距离，所述第一边缘距离与所述第二边缘距离的比值为0.9至1.1。
  9. 根据权利要求1至7中任一项所述的显示基板，其中，所述第三中心线位于所述第一中心线和所述第二中心线之间，或者，所述第三中心线与所述第一中心线重合；
    所述第一边框区域具有沿所述第一方向延伸的第一边框边缘和第二边框边缘，所述第一边框边缘和所述第二边框边缘沿第二方向位于所述弯折区域的走线的两侧，所述第二方向与所述第一方向交叉；
    所述弯折区域的走线与所述第一边框边缘的最小距离为第一边缘距离，所述弯折区域的走线与所述第二边框边缘的最小距离为第二边缘距离，所述第一边缘距离与所述第二边缘距离的比值大于1，或者，所述第二边缘距离与所述第一边缘距离的比值大于1。
  10. 根据权利要求1所述的显示基板，其中，所述多条第一数据扇出线中的至少一条第一数据扇出线包括：相互连接的第一数据延伸段和第二数据延伸段，所述第二数据延伸段与所述多条数据弯折线中的至少一条数据弯折线连接，且所述第二数据延伸段为沿所述第一方向延伸的直线段，所述第一数据延伸段的延伸方向与所述第一方向交叉；
    所述第二中心线在第二方向上位于所述第一中心线的第一侧，所述第二方向与所述第一方向交叉；所述第三中心线与所述第一中心线没有重合；
    靠近所述第一中心线且位于所述第一中心线的第一侧的至少一条第一数据扇出线的第一数据延伸段的长度，大于靠近所述第一中心线且位于所述第一中心线的第二侧的至少一条第一数据扇出线的第一数据延伸段的长度。
  11. 根据权利要求1所述的显示基板，其中，所述第三中心线与所述第一中心线重合，所述多条第一数据扇出线关于所述第三中心线对称设置。
  12. 根据权利要求11所述的显示基板，其中，所述第一边框区域还包括：位于所述弯折区域远离所述第一子区域一侧的第二子区域；
    所述显示基板还包括：位于所述第二子区域的多条数据引出线，所述多条数据引出线与所述多条数据弯折线连接；所述多条数据引出线关于所述第三中心线对称设置。
  13. 根据权利要求1所述的显示基板，还包括：位于所述弯折区域的多条电源弯折线，所述多条电源弯折线与所述多条数据弯折线沿第二方向间隔设置，所述第二方向与所述第一方向交叉；
    所述多条电源弯折线包括：位于所述第三中心线两侧的第一组电源弯折线和第二组电源弯折线；
    所述第一组电源弯折线沿所述第二方向的总长度不同于所述第二组电源弯折线沿所述第二方向的总长度。
  14. 根据权利要求13所述的显示基板，其中，所述第三中心线与所述第一中心线重合；
    所述第一边框区域具有沿所述第一方向延伸的第一边框边缘和第二边框边缘，所述第一边框边缘和所述第二边框边缘沿所述第二方向位于所述弯折区域的走线两侧；
    所述弯折区域的走线与所述第一边框边缘的最小距离为第一边缘距离，所述弯折区域的走线与所述第二边框边缘的最小距离为第二边缘距离，所述第一边缘距离与所述第二边缘距离的比值为0.9至1.1。
  15. 根据权利要求13或14所述的显示基板，其中，所述第三中心线与所述第一中心线重合，所述第二中心线和所述第一组电源弯折线位于所述第一中心线的同一侧；所述第一组电源弯折线沿所述第二方向的总长度大于所述第二组电源弯折线沿所述第二方向的总长度。
  16. 一种显示装置，包括如权利要求1至15中任一项所述的显示基板。
  17. 一种显示基板，包括：显示区域和沿第一方向位于所述显示区域一侧的第一边框区域，所述第一边框区域包括：弯折区域、位于所述弯折区域和所述显示区域之间的第一子区域；所述显示区域具有沿所述第一方向延伸的第一中心线，所述第一边框区域具有沿所述第一方向延伸的第二中心线，所述第一中心线与所述第二中心线之间的距离大于0；
    所述显示基板包括：
    衬底；
    多个子像素，设置在所述衬底的一侧且位于所述显示区域；
    多条数据线，位于所述显示区域，所述多条数据线与所述多个子像素电连接，所述多条数据线配置为给所述多个子像素提供数据信号；
    多条第一数据扇出线，位于所述第一子区域，并与所述多条数据线连接；
    多条信号弯折线，位于所述弯折区域且位于同一导电层；所述多条信号弯折线至少包括：多条数据弯折线，所述多条数据弯折线与所述多条第一数据扇出线连接，所述多条数据弯折线关于第三中心线对称设置；
    所述多条信号弯折线具有沿第一方向延伸的第四中心线，所述第四中心线与所述第三中心线重合，或者，位于所述第三中心线靠近所述第二中心线的一侧。
  18. 根据权利要求17所述的显示基板，其中，所述多条信号弯折线关于所述第四中心线对称设置；所述第三中心线和所述第四中心线与所述第二中心线重合；
    所述第一边框区域具有沿所述第一方向延伸的第一边框边缘和第二边框边缘，所述第一边框边缘和所述第二边框边缘沿第二方向位于所述弯折区域的信号弯折线的两侧，所述第二方向与所述第一方向交叉；
    所述弯折区域的信号弯折线与所述第一边框边缘的最小距离为第一边缘距离，所述弯折区域的信号弯折线与所述第二边框边缘的最小距离为第二边缘距离，所述第一边缘距离与所述第二边缘距离的比值为0.9至1.1。
  19. 根据权利要求17所述的显示基板，其中，所述多条信号弯折线关于所述第四中心线对称设置；所述第三中心线与所述第四中心线重合，且位于所述第一中心线和所述第二中心线之间，或者，所述第三中心线和所述第四中心线与所述第一中心线重合；
    所述第一边框区域具有沿所述第一方向延伸的第一边框边缘和第二边框边缘，所述第一边框边缘和所述第二边框边缘沿第二方向位于所述弯折区域的信号弯折线的两侧，所述第二方向与所述第一方向交叉；
    所述弯折区域的信号弯折线与所述第一边框边缘的最小距离为第一边缘距离，所述弯折区域的信号弯折线与所述第二边框边缘的最小距离为第二边缘距离，所述第一边缘距离与所述第二边缘距离的比值大于1，或者，所述第二边缘距离与所述第一边缘距离的比值大于1。
  20. 根据权利要求17所述的显示基板，其中，所述多条信号弯折线关于所述第四中心线非对称设置，所述第四中心线与所述第二中心线重合，所述第三中心线与所述第一中心线重合；
    所述第一边框区域具有沿所述第一方向延伸的第一边框边缘和第二边框边缘，所述第一边框边缘和所述第二边框边缘沿第二方向位于所述弯折区域的信号弯折线的两侧；所述第二方向与所述第一方向交叉；
    所述弯折区域的信号弯折线与所述第一边框边缘的最小距离为第一边缘距离，所述弯折区域的信号弯折线与所述第二边框边缘的最小距离为第二边缘距离，所述第一边缘距离与所述第二边缘距离的比值为0.9至1.1。
PCT/CN2025/077371 2024-03-15 2025-02-14 显示基板及显示装置 Pending WO2025190036A1 (zh)

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CN110445907A (zh) * 2018-05-04 2019-11-12 Oppo广东移动通信有限公司 电子装置及其折叠式显示装置
CN114023771A (zh) * 2021-11-02 2022-02-08 京东方科技集团股份有限公司 显示基板及显示装置
CN115101575A (zh) * 2022-04-25 2022-09-23 京东方科技集团股份有限公司 显示基板和显示装置

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Publication number Priority date Publication date Assignee Title
US20120113364A1 (en) * 2010-11-05 2012-05-10 Chimei Innolux Corporation Display panel
CN110445907A (zh) * 2018-05-04 2019-11-12 Oppo广东移动通信有限公司 电子装置及其折叠式显示装置
CN114023771A (zh) * 2021-11-02 2022-02-08 京东方科技集团股份有限公司 显示基板及显示装置
CN115101575A (zh) * 2022-04-25 2022-09-23 京东方科技集团股份有限公司 显示基板和显示装置

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