Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/66—Vertical DMOS [VDMOS] FETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs

Definitions

• the present invention relates to a semiconductor device.
• Patent Document 1 JP 2016-136620 A
• a first conductivity type emitter region provided on the front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a second conductivity type contact region provided above the drift region and having a doping concentration higher than that of the base region; a first conductivity type cathode region provided on a back surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; and a second conductivity type collector region provided on the back surface of the semiconductor substrate and having a doping concentration higher than that of the base region, and the semiconductor device further includes a mixed region in which transistor regions below the collector regions and diode regions below the cathode regions are alternately arranged in the trench extension direction.
• the mixing section may be provided between the transistor section and the diode section.
• the width of the mixed portion may be smaller than the width of the transistor portion.
• the width of the mixing portion may be smaller than the width of the diode portion.
• the length of the transistor region of the mixed portion may be 5 ⁇ m or more and 250 ⁇ m or less.
• the mixed portion may have a diode portion-side mixed region adjacent to the diode portion and a transistor portion-side mixed region adjacent to the transistor portion, and the width of the mixed portion in the trench arrangement direction may be 4.6 ⁇ m or more and less than the width of the virtual diode portion, which is the sum of the diode portion-side mixed regions at both ends of the diode portion.
• the ratio of the length of the transistor region of the mixed portion to the length of the diode region is 1:1 in the trench extension direction
• the ratio of the width of the transistor portion side mixed region to the width of the diode portion side mixed region in the trench arrangement direction may be 1:1.
• the width of the mixed region on the transistor portion side may be greater than the width of the mixed region on the diode portion side in the trench arrangement direction.
• the width of the transistor portion side mixed region in the trench arrangement direction may be smaller than the width of the diode portion side mixed region.
• the semiconductor device may include an active region having the transistor portion and the diode portion, and an edge termination structure portion provided on the outer periphery of the active region in a top view, and the mixed portion may be provided between an end of the diode portion and the edge termination structure portion in the trench extension direction.
• the diode section may have a dummy trench section and a gate trench section, and the gate trench section of the diode section may extend from the diode section to the mixing section.
• the semiconductor device may include an accumulation region of the first conductivity type located above the drift region and having a higher doping concentration than the drift region.
• the accumulation region may be provided in each of the transistor section, the mixing section, and the diode section.
• the semiconductor device may include a backside lifetime control region provided on the backside of the semiconductor substrate.
• the semiconductor device may include a front surface side lifetime control region provided on the front surface side of the semiconductor substrate, and the front surface side lifetime control region may extend from the end of the mixed portion on the diode portion side toward the transistor portion by 0 ⁇ m or more and 360 ⁇ m or less.
• the semiconductor device may include a contact trench portion extending from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate.
• the semiconductor device may include a plug region of a second conductivity type provided below the contact trench portion and having a doping concentration higher than that of the base region.
• FIG. 1 shows an example of a top view of a semiconductor device 100 according to an embodiment.
• FIG. 2 is an enlarged view showing an example of an area A in FIG. 1 .
• FIG. 3 is a diagram showing an example of a cross section taken along the line aa' in FIG. 2.
• FIG. 3 is a diagram showing an example of a cross section taken along the line bb′ in FIG. 2.
• FIG. 3 is a diagram showing another example of the aa' cross section in FIG. 2.
• FIG. 3 is a diagram showing another example of the aa' cross section in FIG. 2.
• FIG. 3 is a diagram showing another example of the aa' cross section in FIG. 2.
• FIG. 3 is a diagram showing another example of the aa' cross section in FIG. 2.
• FIG. 3 is a diagram showing another example of the aa' cross section in FIG. 2.
• FIG. 2 is an enlarged view showing an example of an area A in FIG. 1 .
• FIG. 3 is a
• FIG. 2 is an enlarged view showing an example of region B in FIG. 1 .
• FIG. 4B is a diagram showing an example of a cross section taken along the line cc' in FIG. 4A. An example of the arrangement of the collector region 22 and the cathode region 82 is shown.
• FIG. 2 is an enlarged view showing another example of region B in FIG. 1 .
• FIG. 2 is an enlarged view showing yet another example of region B in FIG. 1 .
• FIG. 2 is an enlarged view showing another example of region A in FIG. 1 .
• FIG. 2 is an enlarged view showing yet another example of region A in FIG. 1 .
• top and bottom are not limited to the direction of gravity or the directions when the semiconductor device is mounted.
• Cartesian coordinate axes of the X, Y, and Z axes merely identify the relative positions of components and do not limit specific directions.
• the Z axis does not limit the height direction relative to the ground.
• the +Z axis direction and the -Z axis direction are opposite directions.
• the Z axis direction is referred to without specifying positive or negative, it means the direction parallel to the +Z axis and the -Z axis.
• the orthogonal axes parallel to the front and back surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, the axis perpendicular to the front and back surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. Furthermore, in this specification, the direction parallel to the front and back surfaces of the semiconductor substrate, including the X-axis and Y-axis, is sometimes referred to as the horizontal direction.
• the region from the center of the semiconductor substrate in the depth direction to the front surface of the semiconductor substrate may be referred to as the front surface side.
• the region from the center of the semiconductor substrate in the depth direction to the back surface of the semiconductor substrate may be referred to as the back surface side.
• the conductivity type of a doped region doped with impurities is described as P-type or N-type.
• impurities can particularly refer to either N-type donors or P-type acceptors, and may be referred to as dopants.
• doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor that exhibits N-type conductivity or P-type conductivity.
• FIG. 1 shows an example of a top view of a semiconductor device 100 according to an embodiment.
• the positions of each component projected onto the front surface of the semiconductor substrate 10 are shown.
• FIG. 1 only some of the components of the semiconductor device 100 are shown, and some components are omitted.
• the semiconductor device 100 includes a semiconductor substrate 10.
• the semiconductor substrate 10 has edges 102 when viewed from above.
• the term "top view” simply refers to a view from the front surface of the semiconductor substrate 10.
• the semiconductor substrate 10 has two pairs of edges 102 that face each other when viewed from above.
• the X-axis and Y-axis are parallel to one of the edges 102.
• the Z-axis is perpendicular to the front surface of the semiconductor substrate 10.
• the semiconductor substrate 10 has an active region 160.
• the active region 160 is a region through which a main current flows in the depth direction between the front and back surfaces of the semiconductor substrate 10 when the semiconductor device 100 is operating.
• An emitter electrode is provided above the active region 160, but is omitted from Figure 1.
• the active region 160 includes a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as a free wheel diode (FWD).
• the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT). Note that the semiconductor device 100 may be either an IGBT or a MOS transistor.
• the transistor sections 70 and diode sections 80 are arranged alternately along a predetermined arrangement direction (the X-axis direction in this example) on the front surface of the semiconductor substrate 10.
• a mixing section 90 is provided between the transistor sections 70 and the diode sections 80 in the X-axis direction. The mixing section 90 will be described later.
• the region where the transistor section 70 is arranged is marked with the symbol "I"
• the region where the diode section 80 is arranged is marked with the symbol "F”.
• the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (the Y-axis direction in Figure 1).
• the transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction.
• the length of the transistor section 70 in the Y-axis direction is greater than the width in the X-axis direction.
• the length of the diode section 80 in the Y-axis direction is greater than the width in the X-axis direction.
• the extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section, which will be described later.
• the Y-axis direction end of the transistor section 70 is located closer to the edge 102 than the Y-axis direction end of the diode section 80. Furthermore, the X-axis direction width of the transistor section 70 is wider than the X-axis direction width of the diode section 80.
• the diode section 80 has an N+ type cathode region in a region that contacts the back surface of the semiconductor substrate 10.
• the region in which the cathode region is provided and that extends in the Y-axis direction is referred to as the diode section 80.
• the extension region in which the diode section 80 extends in the Y-axis direction to the edge termination structure section 162, which will be described later, may also be included in the diode section 80.
• a collector region is provided on the back surface of the extension region.
• the transistor section 70 has a P+ type collector region in a region that contacts the back surface of the semiconductor substrate 10.
• the region in which the collector region is provided and that extends in the Y-axis direction is referred to as the transistor section 70.
• the transistor section 70 has an N-type emitter region, a P-type base region, a gate conductive portion, and a gate trench portion having a gate insulating film periodically arranged on the front surface side of the semiconductor substrate 10.
• the semiconductor device 100 may have one or more pads above the semiconductor substrate 10.
• the semiconductor device 100 may have pads such as a gate pad, an anode pad, a cathode pad, and a current detection pad (current sense unit).
• Each pad is located near the edge 102.
• the vicinity of the edge 102 refers to the area between the edge 102 and the emitter electrode when viewed from above.
• each pad may be connected to an external circuit via wiring such as a wire.
• the gate metal layer 50 is disposed between the active region 160 and the edge 102 of the semiconductor substrate 10 in a top view.
• the gate metal layer 50 connects the gate trench portion and the gate pad.
• the gate metal layer 50 surrounds the active region 160 in a top view.
• the area surrounded by the gate metal layer 50 in a top view may also be referred to as the active region 160.
• a temperature detection diode may be provided in the center of the active region 160, and the temperature detection diode may be connected to the anode pad and cathode pad.
• the semiconductor device 100 of this example includes an edge termination structure 162 between the active region 160 and the edge 102.
• the edge termination structure 162 of this example is disposed between the gate metal layer 50 and the edge 102.
• the edge termination structure 162 alleviates electric field concentration on the front surface side of the semiconductor substrate 10.
• the edge termination structure 162 may include multiple guard rings.
• the guard rings are P-type regions that contact the front surface of the semiconductor substrate 10. By providing multiple guard rings, the depletion layer on the upper surface side of the active region 160 can be extended outward, improving the breakdown voltage of the semiconductor device 100.
• the edge termination structure 162 may further include at least one of a field plate and a resurf arranged in a ring shape surrounding the active region 160.
• FIG. 2 is an enlarged view showing an example of region A in FIG. 1.
• Region A is a region that straddles the transistor section 70, the mixing section 90, and the diode section 80 at the edge side on the negative side in the Y-axis direction of the semiconductor device 100 when viewed from above. Note that within the range shown in FIG. 2, the front surface structure of the mixing section 90 is almost the same as the front surface structure of the transistor section 70, so a description will be omitted except for the differences.
• the transistor section 70 is a region in which a collector region 22 is provided on the back side of the semiconductor substrate 10.
• the collector region 22 is, for example, a P+ type.
• the transistor section 70 includes a transistor such as an IGBT.
• the diode section 80 is a region in which a cathode region 82 is provided on the back side of the semiconductor substrate 10.
• the cathode region 82 is, for example, an N+ type.
• the diode section 80 includes a diode such as a free wheel diode (FWD) provided adjacent to the transistor section 70 on the front surface of the semiconductor substrate 10.
• FWD free wheel diode
• the semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride.
• the semiconductor substrate 10 is a silicon substrate.
• the semiconductor device 100 of this example includes, on the front surface of the semiconductor substrate 10, a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17.
• the semiconductor device 100 of this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface of the semiconductor substrate 10.
• the emitter electrode 52 is provided above the gate trench portion 40, dummy trench portion 30, emitter region 12, base region 14, contact region 15, and well region 17.
• the gate metal layer 50 is provided above the gate trench portion 40 and well region 17.
• the emitter electrode 52 and the gate metal layer 50 are formed from a material containing metal. At least a portion of the emitter electrode 52 may be formed from aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. At least a portion of the gate metal layer 50 may be formed from aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy.
• the emitter electrode 52 and the gate metal layer 50 may have a barrier metal formed from titanium, a titanium compound, or the like below the region formed from aluminum, etc.
• the emitter electrode 52 and the gate metal layer 50 are provided separately from each other.
• the emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10, with an interlayer insulating film 38 sandwiched between them.
• the interlayer insulating film 38 is omitted in Figure 2.
• Contact holes 54, 55, and 56 are provided through the interlayer insulating film 38.
• the contact hole 55 connects the gate conductive portion in the gate trench portion 40 of the transistor portion 70 to the gate metal layer 50.
• a plug made of tungsten or the like may be formed inside the contact hole 55 via a barrier metal.
• the contact hole 56 connects the emitter electrode 52 to the dummy conductive portion in the dummy trench portion 30 provided in the transistor portion 70 and the diode portion 80.
• a plug made of tungsten or the like may be formed inside the contact hole 56 via a barrier metal.
• connection portion 25 electrically connects a front surface electrode, such as the emitter electrode 52 or the gate metal layer 50, to the semiconductor substrate 10.
• the connection portion 25 is provided in a region between the gate metal layer 50 and the gate conductive portion, including inside the contact hole 55.
• the connection portion 25 is also provided in a region between the emitter electrode 52 and the dummy conductive portion, including inside the contact hole 56.
• the connection portion 25 is made of a conductive material, such as a metal such as tungsten or polysilicon doped with impurities.
• the connection portion 25 may also have a barrier metal such as titanium nitride.
• the connection portion 25 is polysilicon (N+) doped with N-type impurities.
• the connection portion 25 is provided above the front surface of the semiconductor substrate 10 via an insulating film such as an oxide film.
• the gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction).
• the gate trench portion 40 may have two extension portions 41 that extend parallel to the front surface of the semiconductor substrate 10 and along an extension direction perpendicular to the arrangement direction (in this example, the Y-axis direction), and a connection portion 43 that connects the two extension portions 41.
• connection portion 43 be formed in a curved shape.
• the gate metal layer 50 may be connected to the gate conductive portion.
• the dummy trench portion 30 is a trench portion in which a dummy conductive portion provided therein is electrically connected to the emitter electrode 52.
• the dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction).
• the dummy trench portion 30 in this example may have a U-shape on the front surface of the semiconductor substrate 10. That is, the dummy trench portion 30 may have two extension portions 31 extending along the extension direction and a connection portion 33 connecting the two extension portions 31.
• the transistor section 70 in this example has a structure in which two gate trench sections 40 and three dummy trench sections 30 are arranged repeatedly. That is, the transistor section 70 in this example has gate trench sections 40 and dummy trench sections 30 in a ratio of 2:3. For example, the transistor section 70 has one extension section 31 between two extension sections 41. The transistor section 70 also has two extension sections 31 adjacent to the gate trench section 40.
• the ratio of gate trench portions 40 to dummy trench portions 30 is not limited to this example.
• the ratio of gate trench portions 40 to dummy trench portions 30 may be 1:1 or 2:4.
• the transistor portion 70 may not have dummy trench portions 30, and may be entirely made up of gate trench portions 40.
• the well region 17 is provided closer to the front surface of the semiconductor substrate 10 than the drift region 18, which will be described later.
• the well region 17 is an example of a well region provided on the edge side of the semiconductor device 100.
• the well region 17 is, for example, P+ type.
• the well region 17 is provided within a predetermined range from the end of the active region 160 on the side where the gate metal layer 50 is provided.
• the diffusion depth of the well region 17 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30.
• Part of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side are provided in the well region 17.
• the bottoms of the ends of the gate trench portion 40 and the dummy trench portion 30 in the extension direction may be covered by the well region 17.
• contact holes 54 are provided above the emitter region 12 and contact region 15.
• contact holes 54 are provided above the base region 14. None of the contact holes 54 are provided above the well regions 17 provided at both ends in the Y-axis direction. In this way, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 may be provided extending in the extension direction.
• a contact trench portion 60 is provided, extending from the front surface of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10 (in this example, the Z-axis direction).
• the contact trench portion 60 electrically connects the emitter electrode 52 and the semiconductor substrate 10.
• the contact trench portion 60 is provided extending in the Y-axis direction when viewed from above. In other words, the contact trench portion 60 is arranged in a stripe pattern along the gate trench portion 40 and the dummy trench portion 30.
• Mesa portion 71, mesa portion 81, and mesa portion 91 are mesa portions provided adjacent to trench portions in a plane parallel to the front surface of semiconductor substrate 10.
• a mesa portion is a portion of semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be the portion from the front surface of semiconductor substrate 10 to the deepest bottom of each trench portion.
• the extended portion of each trench portion may be considered a single trench portion. In other words, the area sandwiched between two extended portions may be considered a mesa portion.
• the mesa portion 71 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40.
• the mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface of the semiconductor substrate 10.
• the emitter regions 12 and the contact regions 15 are provided alternately in the extension direction.
• mesa portion 91 is provided in the mixed portion 90. Similar to mesa portion 71, mesa portion 91, as shown in FIG. 2, has well regions 17, base regions 14, emitter regions 12, and contact regions 15 arranged alternately in the extension direction on the front surface of semiconductor substrate 10.
• the mesa portion 81 is provided in the region of the diode portion 80 that is sandwiched between adjacent dummy trench portions 30.
• the mesa portion 81 has a base region 14 on the front surface of the semiconductor substrate 10, and a well region 17 on the negative side in the Y-axis direction.
• the mesa portion 81 may also have a contact region 15, similar to the mixed portion 90, provided on the front surface of the base region 14.
• the base region 14 is a region provided on the front surface side of the semiconductor substrate 10 in the transistor section 70 and the diode section 80.
• the base region 14 is, for example, P-type.
• the base region 14 may be provided on the front surface of the semiconductor substrate 10 at both ends of the mesa section 71 and the mesa section 91 in the Y-axis direction. Note that Figure 2 only shows the negative end of the base region 14 in the Y-axis direction.
• the emitter region 12 is a region of the same conductivity type as the drift region 18, but with a higher doping concentration than the drift region 18.
• the emitter region 12 is, for example, N+ type.
• One example of a dopant for the emitter region 12 is arsenic (As).
• the emitter region 12 is provided on the front surface of the mesa portion 71, in contact with the gate trench portion 40.
• the emitter region 12 may be provided extending in the X-axis direction from one to the other of the two trench portions that sandwich the mesa portion 71.
• the emitter region 12 is also provided below the contact hole 54.
• the contact region 15 has the same conductivity type as the base region 14 and a higher doping concentration than the base region 14.
• the contact region 15 is P+ type, for example.
• the contact region 15 is provided on the front surfaces of the mesa portion 71 and the mesa portion 91.
• the contact region 15 may be provided in the X-axis direction from one of the two trench portions that sandwich the mesa portion 71 or the mesa portion 91 to the other.
• the contact region 15 may or may not be in contact with the gate trench portion 40.
• the contact region 15 may or may not be in contact with the dummy trench portion 30.
• the contact region 15 is in contact with the dummy trench portion 30 and the gate trench portion 40.
• the contact region 15 is also provided below the contact hole 54.
• Figure 3A is a diagram showing an example of the a-a' cross section in Figure 2.
• the a-a' cross section is an XZ plane that passes through the emitter region 12 in the mixing section 90.
• the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.
• the emitter electrode 52 is provided above the semiconductor substrate 10 and the interlayer insulating film 38.
• the transistor section 70 has approximately the same structure as the mixing section 90 on the same XZ plane, so it is not shown in the figure.
• the drift region 18 is a region provided in the semiconductor substrate 10.
• the drift region 18 is, for example, N-type.
• the drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein.
• the doping concentration of the drift region 18 may be the same as the doping concentration of the semiconductor substrate 10.
• the buffer region 20 is a region provided below the drift region 18.
• the buffer region 20 has the same conductivity type as the drift region 18, for example, N-type.
• the doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18.
• the buffer region 20 may function as a field stop layer that prevents the depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22 and the cathode region 82.
• the collector region 22 is a region of a different conductivity type from the drift region 18, located below the buffer region 20 in the transistor section 70.
• the cathode region 82 is a region of the same conductivity type as the drift region 18, located below the buffer region 20 in the diode section 80.
• the base region 14 is a region of a different conductivity type from the drift region 18, located above the drift region 18 in the mesa portion 71, mesa portion 81, and mesa portion 91.
• the base region 14 is P-type, for example.
• the base region 14 is provided in contact with the gate trench portion 40.
• the base region 14 may also be provided in contact with the dummy trench portion 30.
• the contact trench portion 60 has a conductive material filled in the contact hole 54.
• the contact trench portion 60 is provided between two adjacent trench portions among the multiple trench portions.
• the contact trench portion 60 is provided from the front surface 21 through the emitter region 12, and is in contact with the plug region 19 at the bottom surface.
• the contact trench portion 60 may have the same material as the emitter electrode 52.
• the contact trench portion 60 may also have a plug via a barrier metal.
• the lower end of the contact trench portion 60 may be deeper or shallower than the lower end of the emitter region 12.
• the resistance of the base region 14 is reduced, making it easier to extract minority carriers (e.g., holes). This improves the breakdown resistance, such as latch-up resistance, caused by minority carriers.
• the plug region 19 is provided below the contact trench portion 60.
• the plug region 19 has the same conductivity type as the base region 14, but has a higher doping concentration than the base region 14.
• the plug region 19 is, for example, a P+ type.
• the plug region 19 is formed by ion implantation of boron (B) or boron fluoride (BF 2 ).
• the plug region 19 may have the same doping concentration as the contact region 15.
• the plug region 19 suppresses latch-up by extracting minority carriers.
• the plug region 19 may be provided on the sidewall and bottom surface of the contact trench portion 60.
• the plug region 19 may be provided in each of the mesa portion 71, the mesa portion 81, and the mesa portion 91.
• the plug region 19 may be provided extending in the Y-axis direction.
• the accumulation region 16 is a region provided above the drift region 18.
• the accumulation region 16 has the same conductivity type as the drift region 18, but has a higher doping concentration than the drift region 18.
• the accumulation region 16 is N+ type, for example.
• the accumulation region 16 is provided in each of the transistor section 70, the mixing section 90, and the diode section 80.
• the accumulation region 16 may be provided only in the transistor section 70, and not in the mixing section 90 or the diode section 80.
• the accumulation region 16 may be provided in the transistor section 70 and the mixing section 90, and not in the diode section 80.
• the accumulation region 16 is provided in contact with the gate trench portion 40.
• the accumulation region 16 may or may not be in contact with the dummy trench portion 30.
• the carrier injection enhancement effect IE effect
• the accumulation region 16 can be enhanced, reducing the on-voltage of the transistor portion 70.
• the gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side, across the gate insulating film 42, in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.
• the interlayer insulating film 38 is provided on the front surface 21 of the semiconductor substrate 10.
• An emitter electrode 52 is provided above the interlayer insulating film 38.
• One or more contact holes 54 are provided in the interlayer insulating film 38 to electrically connect the emitter electrode 52 to the semiconductor substrate 10.
• Contact holes 55 and 56 may also be provided penetrating the interlayer insulating film 38.
• the semiconductor device 100 of this example has a backside lifetime control region 151 and a frontside lifetime control region 152. However, the semiconductor device 100 does not necessarily have to have either the backside lifetime control region 151 or the frontside lifetime control region 152.
• the backside lifetime control region 151 and the frontside lifetime control region 152 are regions in which lifetime killers are intentionally formed by, for example, implanting impurities into the semiconductor substrate 10.
• Lifetime killers are carrier recombination centers.
• the lifetime killers may be lattice defects.
• the lifetime killers may be vacancies, divacancies, complex defects formed by these with elements constituting the semiconductor substrate 10, or dislocations.
• the lifetime killers may also be rare gas elements such as helium or neon, or metal elements such as platinum. Electron beams or protons may be used to form the lattice defects.
• the backside lifetime control region 151 is provided on the backside 23 side of the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. In this example, the backside lifetime control region 151 is provided in the buffer region 20. In this example, the backside lifetime control region 151 is provided over the entire surface of the semiconductor substrate 10 in the XY plane, and can be formed without using a mask.
• the backside lifetime control region 151 may be formed by implantation from the backside 23 side of the semiconductor substrate 10. This can suppress any effects on the front surface 21 side of the semiconductor device 100.
• the backside lifetime control region 151 is formed by irradiating helium or protons from the backside 23 side of the semiconductor device 100. Whether the backside lifetime control region 151 was formed by implantation from the front surface 21 or backside 23 side of the semiconductor device 100 can be determined by obtaining the state of the front surface 21 side of the semiconductor device 100 using the SR method or leakage current measurement.
• the front surface side lifetime control region 152 is provided on the front surface 21 side of the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. In this example, the front surface side lifetime control region 152 is provided in the drift region 18. In this example, the front surface side lifetime control region 152 is provided extending a distance W in the X-axis direction from the end of the mixing section 90 on the diode section 80 side toward the transistor section 70.
• the extension distance W may be 0 ⁇ m or more and 360 ⁇ m or less, or may be 2.0 ⁇ m or more and 360 ⁇ m or less.
• the lower limit of the extension distance W may be the width of one mesa section 91.
• the front surface side lifetime control region 152 extending from the diode section 80 may extend through the mixed section 90 to a part of the transistor section 70, or may terminate within the mixed section 90 without reaching the transistor section 70.
• the front surface side lifetime control region 152 may be formed by irradiation from the front surface 21 of the semiconductor substrate 10.
• the front surface side lifetime control region 152 may be formed by irradiation from the back surface 23 of the semiconductor substrate 10.
• the elements and dose amounts used to form the back surface side lifetime control region 151 and the front surface side lifetime control region 152 may be the same or different.
• the front surface side lifetime control region 152 may be provided below the gate trench portion 40.
• defects may occur at the interface between the gate oxide film and the semiconductor substrate, causing the threshold voltage to fluctuate.
• the extension distance W from the diode portion 80 within the above-mentioned range, it is possible to suppress fluctuations in the threshold voltage.
• FIG. 3B is a diagram showing an example of the b-b' cross section in FIG. 2.
• the b-b' cross section is an XZ plane that passes through the contact region 15 in the transistor section 70. Note that, like the a-a' cross section, the b-b' cross section does not pass through the transistor section 70, but since the transistor section 70 has almost the same structure as the mixing section 90 on the same XZ plane, it is not shown in the figure.
• mesa portion 71 and mesa portion 91 have a base region 14, a contact region 15, an accumulation region 16, and a plug region 19.
• mesa portion 91 has a contact region 15, an accumulation region 16, and a plug region 19.
• mesa portion 71 has the same structure as mesa portion 91.
• mesa portion 81 has a base region 14, an accumulation region 16, and a plug region 19.
• FIG. 3C is a diagram showing another example of the a-a' cross section in Figure 2.
• the a-a' cross section is an XZ plane that passes through the emitter region 12 in the mixing section 90.
• the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.
• the emitter electrode 52 is provided above the semiconductor substrate 10 and the interlayer insulating film 38.
• the transistor section 70 has approximately the same structure as the mixing section 90 on the same XZ plane, so it is not shown in the figure.
• Figure 3C differs from Figure 3A in that the backside lifetime control region 151 is not provided.
• the backside lifetime control region 151 may not be provided depending on the doping concentration of the buffer region 20 and the application of the semiconductor device 100.
• Figure 3D is a diagram showing another example of the a-a' cross section in Figure 2.
• the a-a' cross section is an XZ plane that passes through the emitter region 12 in the mixed section 90.
• the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.
• the emitter electrode 52 is provided above the semiconductor substrate 10 and the interlayer insulating film 38.
• Figure 3D differs from Figure 3A in that the front surface side lifetime control region 152 is provided over the entire surface. Furthermore, the semiconductor device 100 of this example does not have an extension distance W.
• the front surface side lifetime control region 152 may be formed by implantation from the back surface 23 side of the semiconductor substrate 10, similar to the back surface side lifetime control region 151. This makes it possible to suppress the impact on the front surface 21 side of the semiconductor device 100.
• the front surface side lifetime control region 152 is formed by irradiating helium or protons from the back surface 23 side of the semiconductor device 100.
• the front surface side lifetime control region 152 of this example is provided over the entire surface of the semiconductor substrate 10 in the XY plane, and can be formed without using a mask.
• Figure 3E is a diagram showing another example of the a-a' cross section in Figure 2.
• the a-a' cross section is an XZ plane that passes through the emitter region 12 in the mixing section 90.
• the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.
• the emitter electrode 52 is provided above the semiconductor substrate 10 and the interlayer insulating film 38.
• the transistor section 70 has approximately the same structure as the mixing section 90 on the same XZ plane, so it is not shown in the figure.
• Figure 3E differs from Figure 3A in that it does not include the backside lifetime control region 151 and the frontside lifetime control region 152.
• the backside lifetime control region 151 and the frontside lifetime control region 152 may not be provided depending on the doping concentration of the buffer region 20 and the application of the semiconductor device 100.
• Figure 3F is a diagram showing another example of the a-a' cross section in Figure 2.
• the a-a' cross section is an XZ plane that passes through the emitter region 12 in the mixing section 90.
• the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.
• the emitter electrode 52 is provided above the semiconductor substrate 10 and the interlayer insulating film 38.
• the transistor section 70 has approximately the same structure as the mixing section 90 on the same XZ plane, so it is not shown in the figure.
• Figure 3F differs from Figure 3A in that the front surface side lifetime control region 152 is not provided.
• the front surface side lifetime control region 152 may not be provided depending on the doping concentration of the buffer region 20 and the application of the semiconductor device 100.
• FIG. 4A is an enlarged view showing an example of region B in FIG. 1.
• Region B is a region on the edge side of the semiconductor device 100 on the negative side in the Y-axis direction, centered on the diode section 80, spanning the mixed section 90 and part of the transistor section 70, when viewed from above.
• FIG. 4A also shows an enlarged view of region C of the mesa section 91 of the mixed section 90.
• the mixed section 90 is a region in which, in the Y-axis direction, transistor regions 970, each having a collector region 22 provided therebelow, and diode regions 980, each having a cathode region 82 provided therebelow, are alternately arranged.
• the mixed section 90 is provided between the transistor section 70 and the diode section 80.
• the mixed section 90 has a gate trench section 40 and a dummy trench section 30.
• the ratio of the gate trench sections 40 to the dummy trench sections 30 in the mixed section 90 may be the same as in the transistor section 70.
• a contact hole 54 is provided above the mesa section 91 of the mixed section 90.
• the transistor region 970 has emitter regions 12 and contact regions 15 arranged alternately in the Y-axis direction on the front surface of the mesa portion 91.
• the front surface structure of the transistor region 970 is common to the front surface structure of the transistor portion 70.
• the transistor regions 970 of the transistor portion 70 and the mixing portion 90 i.e., the regions that operate as transistors, are hatched.
• the diode region 980 is adjacent to the transistor region 970 in the Y-axis direction.
• the diode region 980 has a base region 14 provided on the front surface 21 of the semiconductor substrate 10.
• the front surface structure of the diode region 980 is common to the front surface structure of the diode section 80.
• the region that operates as a transistor (hatched region) and the region that operates as a diode form a sawtooth-shaped boundary in the mixed region 90.
• RC-IGBTs suppress temperature changes by having both the transistor and diode bear the heat generated during continuous operation or a short circuit.
• temperature changes are suppressed by diffusing heat to the diode when the transistor is operating, and to the transistor when the diode is operating. During this process, heat is exchanged through the boundary between the transistor and diode. By dissipating heat suddenly generated in the transistor during a short circuit to the diode, short-circuit resistance can be improved.
• the region operating as a transistor and the region operating as a diode form a sawtooth-shaped boundary in the mixing section 90, so the extension distance of the boundary is greater than when the boundary between the transistor and diode is linear. This promotes thermal diffusion and improves short-circuit resistance. Improved short-circuit resistance makes it possible to increase saturation current, which in turn reduces turn-on loss.
• the width Xm of the mixed portion 90 may be 50 ⁇ m or more and 200 ⁇ m or less.
• the width Xm of the mixed portion 90 may be smaller than the width of the transistor portion 70 and may be smaller than the width Xf of the diode portion.
• the length Yi of the transistor region 970 of the mixed section 90 may be 5 ⁇ m or more and 250 ⁇ m or less.
• the ratio of the length Yi of the transistor region 970 of the mixed section 90 to the length Yf of the diode region 980 is 1:1.
• the region of the mixing section 90 adjacent to the diode section 80 is the diode section side mixing region, and the region adjacent to the transistor section 70 is the transistor section side mixing region.
• the range obtained by adding the diode section side mixing region to both ends of the diode section 80 in the X-axis direction is the virtual diode section 1080, and the range obtained by adding the transistor section side mixing region to both ends of the transistor section 70 is the virtual transistor section 1070.
• the virtual diode section 1080 and the virtual transistor section 1070 correspond to the diode section and the transistor section, respectively, when the mixing section 90 is not provided.
• the width Xm of the mixed portion 90 may be 4.6 ⁇ m or more and may be less than the width Xfv of the virtual diode portion 1080.
• the ratio of the total area of the transistor region 970 to the total area of the diode region 980 in the mixing section 90 is determined according to the ratio of the width Xmi of the transistor section side mixing region to the width Xmf of the diode section side mixing region in the X-axis direction, and the ratio of the length Yi of the transistor region 970 to the length Yf of the diode region 980 in the Y-axis direction.
• the total area of the transistor region 970 is equal to the area of the mixed region on the transistor portion side
• the total area of the diode region 980 is equal to the area of the mixed region on the diode portion side.
• the area of the region that operates as a transistor i.e., the sum of the area of transistor section 70 and the total area of transistor region 970
• the area of the region that operates as a diode i.e., the sum of the area of diode section 80 and the total area of diode region 980
• the characteristics of transistor section 70 and diode section 80 are maintained when mixing section 90 is not provided, while providing mixing section 90 promotes heat diffusion and improves short-circuit resistance. Improving short-circuit resistance makes it possible to increase saturation current, which in turn reduces turn-on loss.
• the ratio of the length Yi of the transistor region 970 to the length Yf of the diode region 980 is 1:1 in the Y-axis direction
• the ratio of the width Xmi of the transistor portion side mixed region to the width Xmf of the diode portion side mixed region may be 1:1 in the X-axis direction.
• FIG. 4B is a diagram showing an example of the c-c' cross section in FIG. 4A.
• the c-c' cross section is a YZ plane passing through the mesa portion 91.
• a collector region 22 is provided on the rear surface 23 of the semiconductor substrate 10
• a cathode region 82 is provided on the rear surface 23 of the semiconductor substrate 10.
• Figure 4C shows an example of the arrangement of the collector region 22 and the cathode region 82.
• Figure 4C is a top view of the semiconductor device 100, but for convenience, the components above the collector region 22 and the cathode region 82 are omitted.
• a collector region 22 is provided on the back surface 23 of the semiconductor substrate 10, and in the diode section 80, a cathode region 82 is provided on the back surface 23 of the semiconductor substrate 10. In the edge termination structure section 162, a collector region 22 may be provided on the back surface 23 of the semiconductor substrate 10.
• collector regions 22 corresponding to the transistor regions 970 and cathode regions 82 corresponding to the diode regions 980 are arranged alternately in the Y-axis direction.
• the collector regions 22 corresponding to the transistor regions 970 of the transistor section 70 and mixing section 90 and the cathode regions 82 corresponding to the diode regions 980 of the diode section 80 and mixing section 90 form a sawtooth boundary in the mixing section 90.
• FIG. 5 is an enlarged view showing another example of region B in FIG. 1.
• the length Yi of the transistor region 970 in the mixing section 90 is greater than the length Yf of the diode region 980
• the width Xmi of the transistor section side mixing region is greater than the width Xmf of the diode section side mixing region.
• FIG. 6 is an enlarged view showing yet another example of region B in FIG. 1.
• the length Yi of the transistor region 970 in the mixing section 90 is smaller than the length Yf of the diode region 980
• the width Xmi of the transistor section side mixing region is smaller than the width Xmf of the diode section side mixing region.
• Figure 7A is an enlarged view showing another example of region A in Figure 1.
• the mixing section 90 is also provided between the end of the diode section 80 and the edge termination structure section 162 in the Y-axis direction.
• the diode section 80 of this example differs from the examples shown in Figures 1 to 6 in that it has a gate trench section 40.
• the gate trench section 40 of the diode section 80 extends from the diode section 80 to the mixing section 90.
• the region between the end of the diode section 80 and the edge termination structure 162 is sometimes referred to as the extension region of the diode section 80.
• the electric field strength is strongest near the end of the diode section 80 during reverse recovery operation, and current is concentrated there. Therefore, in the extension region, a cathode region 82 is not provided on the back surface of the semiconductor substrate 10, and instead a collector region 22 is provided.
• the mixed region 90 is expanded into the extension region of the diode region 80, and a gate trench portion 40 is provided that extends from the diode region 80 to the mixed region 90.
• This allows the ineffective region that does not function as a diode to function as a transistor, and promotes thermal diffusion as shown in Figures 1 to 6, improving short-circuit resistance. Improving short-circuit resistance makes it possible to increase saturation current, which in turn reduces turn-on loss.
• Figure 7B is an enlarged view showing yet another example of region A in Figure 1.
• the semiconductor device 100 of this example has emitter regions 12 and contact regions 15 alternately arranged in the Y-axis direction between the end of the diode section 80 and the edge termination structure section 162.
• the diode section 80 of this example has a gate trench section 40.
• the gate trench section 40 of the diode section 80 is arranged to extend from the diode section 80 to the mixing section 90.
• a transistor region 970 is provided in the extension region of the diode section 80. This allows the inactive region that does not function as a diode to function as a transistor, thereby increasing the active area.

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  • 2025-01-10 JP JP2026503684A patent/JPWO2025182319A1/ja active Pending
  • 2025-01-10 WO PCT/JP2025/000734 patent/WO2025182319A1/ja active Pending

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