Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
  • H01G4/00—Fixed capacitors; Processes of their manufacture
  • H01G4/30—Stacked capacitors

Definitions

• the present invention relates to a multilayer ceramic capacitor.
• multilayer ceramic capacitors are manufactured by laminating multiple dielectric ceramic sheets via internal electrode layers, and then forming external electrodes and plating films of nickel, copper, solder, tin, etc. on both end surfaces of the resulting multilayer ceramic capacitor.
• the object of the present invention is to provide a highly reliable multilayer ceramic capacitor that can suppress cracks from occurring inside the multilayer ceramic capacitor.
• the inventors discovered a multilayer ceramic capacitor comprising a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers, the laminate having first and second main surfaces opposing each other in the lamination direction, first and second side surfaces opposing each other in a width direction perpendicular to the lamination direction, and first and second end surfaces opposing each other in a length direction perpendicular to the lamination direction and the width direction, and external electrodes provided on the first end surfaces and the second end surfaces and connected to the internal electrode layers, the external electrodes comprising a base electrode layer having a recess formed on its surface, an organic layer formed on the base electrode layer, and a plating layer formed on the organic layer, with a gap formed between the organic layer formed on the recess of the base electrode layer and the plating layer, and thus completed the present invention.
• the present invention makes it possible to provide a highly reliable multilayer ceramic capacitor that can suppress cracks from occurring inside the multilayer ceramic capacitor.
• FIG. 1 is a diagram showing a multilayer ceramic capacitor according to the present invention.
• FIG. 2 is a cross-sectional view taken along line 200-200 of FIG.
• FIG. 3 is a cross-sectional view taken along line 201-201 in FIG.
• FIG. 4A is a diagram showing an example of a floating internal electrode layer.
• FIG. 4B is a diagram showing an example of a floating internal electrode layer.
• FIG. 4C is a diagram showing an example of a floating internal electrode layer.
• FIG. 5 is an enlarged view of a portion of FIG.
• FIG. 6 is a table showing the results of Experimental Example 1.
• FIG. 7 is a table showing the results of Experimental Example 2.
• FIG. 8 is a table showing the results of Experimental Example 3.
• FIG. 1 is a diagram showing a multilayer ceramic capacitor 1 according to an embodiment of the present invention.
• FIG. 2 is a cross-sectional view taken along line 200-200 of FIG. 1.
• FIG. 3 is a cross-sectional view taken along line 201-201 of FIG. 1.
• the multilayer ceramic capacitor 1 includes a laminate 2 and external electrodes 50.
• the external electrodes 50 include a first external electrode 51 and a second external electrode 52.
• the laminate 2 includes a plurality of laminated dielectric layers 30 and a plurality of laminated internal electrode layers 40.
• the lamination direction T the direction in which the dielectric layers 30 and the internal electrode layers 40 are laminated.
• the surfaces of the laminate 2 facing the lamination direction T are called the first main surface 4 and the second main surface 5.
• the surfaces of the laminate 2 facing the width direction W perpendicular to the lamination direction T are called the first side surface 6 and the second side surface 7.
• the surfaces of the laminate 2 facing the length direction L perpendicular to the lamination direction T and the width direction W are called the first end face 8 and the second end face 9.
• the shape of the laminate 2 is approximately a rectangular parallelepiped. A portion where three surfaces of the laminate 2 intersect is called a corner. A portion where two surfaces of the laminate 2 intersect is called a ridge. The corners and ridges are preferably rounded. Some or all of the main surfaces, side surfaces, and end surfaces may have irregularities formed thereon.
• the material of the dielectric layer 30 is a ceramic material.
• the ceramic material include dielectric ceramics composed of main components such as barium titanate, calcium titanate, strontium titanate, and calcium zirconate.
• the dielectric ceramic may be one in which a secondary component is added to the above-mentioned main component.
• the secondary component include manganese compounds, iron compounds, chromium compounds, cobalt compounds, and nickel compounds.
• the multilayer ceramic capacitor functions as a ceramic piezoelectric element.
• a piezoelectric ceramic material is lead zirconate titanate (PZT)-based ceramic material.
• the multilayer ceramic capacitor functions as a thermistor element.
• a semiconducting ceramic material is a spinel-based ceramic material.
• the multilayer ceramic capacitor When magnetic ceramic is used as the laminate material, the multilayer ceramic capacitor functions as an inductor element. When a multilayer ceramic capacitor functions as an inductor element, the internal electrode layers become coiled conductors.
• An example of a magnetic ceramic material is ferrite ceramic material.
• the preferred thickness of the dielectric layer 30 is 0.5 ⁇ m or more and 10 ⁇ m or less.
• the laminate 2 can be divided into an effective layer portion 10 and an outer layer portion 12 in a stacking direction T, which is a direction connecting the first main surface 4 and the second main surface 5.
• the effective layer portion 10 is a portion where the internal electrode layers 40 face each other.
• the outer layer portion 12 includes a first outer layer portion 13 and a second outer layer portion 14.
• the first outer layer portion 13 is the portion between the internal electrode layer 40 closest to the first main surface 4 and the first main surface 4.
• the second outer layer portion 14 is the portion between the internal electrode layer 40 closest to the second main surface 5 and the second main surface 5.
• the first outer layer portion 13 is located on the first main surface 4 side of the laminate 2.
• the first outer layer portion 13 is an assembly of multiple dielectric layers 30 located between the first main surface 4 and the internal electrode layer 40 closest to the first main surface 4.
• the second outer layer portion 14 is located on the second main surface 5 side of the laminate 2.
• the second outer layer portion 14 is an assembly of multiple dielectric layers 30 located between the second main surface 5 and the internal electrode layer 40 closest to the second main surface 5.
• the effective layer portion 10 is the area sandwiched between the first outer layer portion 13 and the second outer layer portion 14.
• the dimensions of the laminate 2 are not particularly limited.
• the preferred length of the laminate 2 in the longitudinal direction L is 0.2 mm or more and 10 mm or less.
• the preferred length of the laminate 2 in the width direction W is 0.1 mm or more and 10 mm or less.
• the preferred length of the laminate 2 in the stacking direction T is 0.1 mm or more and 5 mm or less.
• the laminate 2 can be divided into a counter electrode portion 20 and an end portion 23 in the longitudinal direction L.
• the counter electrode portion 20 is a portion where the first internal electrode layer 41 and the second internal electrode layer 42 face each other.
• the end portion 23 includes a first end portion 24 and a second end portion 25.
• the end surfaces of the opposing electrode portion 20 in the longitudinal direction L are called opposing electrode portion end faces 21.
• the first end portion 24 is the portion between the opposing electrode portion end face 21 on the first end face 8 side and the first end face 8.
• the second end portion 25 is the portion between the opposing electrode portion end face 21 on the second end face 9 side and the second end face 9.
• the end portion 23 is also called the L gap.
• the laminate 2 can be divided into a counter electrode portion 20 and a side portion 26 in the width direction W.
• the counter electrode portion 20 is a portion where the first internal electrode layer 41 and the second internal electrode layer 42 face each other.
• the side portion 26 includes a first side portion 27 and a second side portion 28.
• the end surfaces of the opposing electrode portion 20 in the width direction W are called opposing electrode portion side surfaces 22.
• the first side portion 27 is the portion between the opposing electrode portion side surface 22 on the first side surface 6 side and the first side surface 6.
• the second side portion 28 is the portion between the opposing electrode portion side surface 22 on the second side surface 7 side and the second side surface 7.
• the side portion 26 is also called the W gap.
• the internal electrode layers 40 include a plurality of first internal electrode layers 41 and a plurality of second internal electrode layers 42. As shown in Fig. 2, the first internal electrode layers 41 are exposed at the first end face 8. The second internal electrode layers 42 are exposed at the second end face 9.
• the first internal electrode layer 41 has a first opposing electrode portion 43 and a first extraction electrode portion 44 in the longitudinal direction L.
• the first opposing electrode portion 43 is the portion of the first internal electrode layer 41 that faces the second internal electrode layer 42.
• the first extraction electrode portion 44 is the portion of the first internal electrode layer 41 that is extracted from the first opposing electrode portion 43 to the first end face 8.
• the second internal electrode layer 42 has a second opposing electrode portion 45 and a second extraction electrode portion 46 in the longitudinal direction L.
• the second opposing electrode portion 45 is the portion of the second internal electrode layer 42 that faces the first internal electrode layer 41.
• the second extraction electrode portion 46 is the portion of the second internal electrode layer 42 that is extracted from the second opposing electrode portion 45 to the second end face 9.
• the shapes of the first opposing electrode portion 43 of the first internal electrode layer 41, the second opposing electrode portion 45 of the second internal electrode layer 42, the first extraction electrode portion 44 of the first internal electrode layer 41, and the second extraction electrode portion 46 of the second internal electrode layer 42 are not particularly limited.
• the preferred shape of the first opposing electrode portion 43 of the first internal electrode layer 41, the second opposing electrode portion 45 of the second internal electrode layer 42, the first extraction electrode portion 44 of the first internal electrode layer 41, and the second extraction electrode portion 46 of the second internal electrode layer 42 is rectangular. However, the corners may be rounded or angled (tapered). The tapered shape may also be tapered in either direction.
• the width in the width direction W of the first opposing electrode portion 43 of the first internal electrode layer 41 and the width of the first extraction electrode portion 44 of the first internal electrode layer 41 may be the same width, or one of them may be formed with a narrower width.
• the width of the second opposing electrode portion 45 of the second internal electrode layer 42 and the width of the second extraction electrode portion 46 of the second internal electrode layer 42 may be the same width, or one of them may be formed with a narrower width.
• the floating internal electrode layer 47 will be described with reference to Figures 4A to 4C.
• the floating internal electrode layer 47 is an internal electrode layer 40 that is not drawn to either the first end face 8 or the second end face 9.
• Figures 4A to 4C are views corresponding to the cross-sectional view taken along line 200-200 in Figure 1. However, Figures 4A to 4C do not show the external electrode 50.
• the first internal electrode layer 41 and the second internal electrode layer 42 may be provided with floating internal electrode layers 47.
• the internal electrode layer 40 may have a structure in which the first opposing electrode portion 43 of the first internal electrode layer 41 or the second opposing electrode portion 45 of the second internal electrode layer 42 is divided into multiple portions.
• the first internal electrode layer 41 and the second internal electrode layer 42 are provided on the same layer.
• a floating internal electrode layer 47 is provided between the layer on which the first internal electrode layer 41 and the second internal electrode layer 42 are provided and another layer on which the first internal electrode layer 41 and the second internal electrode layer 42 are formed.
• a floating internal electrode layer 47 is provided on each of the layers on which the first internal electrode layer 41 is provided and the second internal electrode layer 42 is provided.
• the floating internal electrode layers 47 are not limited to being arranged in pairs in the same layer in the longitudinal direction L, as shown in Figure 4C. It goes without saying that structures with three, four, five or more layers are also acceptable.
• Examples of materials for the internal electrode layers 40 include metals such as nickel, copper, silver, palladium, and gold, or alloys containing at least one of these metals, such as a silver-palladium alloy, and other suitable conductive materials.
• capacitance is formed when opposing portions of the internal electrode layers 40 face each other with the dielectric layer 30 interposed between them. This capacitance is what gives rise to the characteristics of the capacitor.
• An example thickness of the internal electrode layer 40 is 0.2 ⁇ m or more and 2.0 ⁇ m or less.
• the external electrode 50 includes a first external electrode 51 and a second external electrode 52.
• the first external electrode 51 is connected to the first internal electrode layer 41.
• a major portion of the first external electrode 51 is disposed on the first end face 8.
• the first external electrode 51 may also be disposed on a portion of the first main surface 4, a portion of the second main surface 5, a portion of the first side surface 6, and a portion of the second side surface 7.
• the first external electrode 51 is formed to extend from the first end face 8 to a portion of the first main surface 4, a portion of the second main surface 5, a portion of the first side surface 6, and a portion of the second side surface 7.
• the second external electrode 52 is connected to the second internal electrode layer 42.
• the main portion of the second external electrode 52 is disposed on the second end face 9.
• the second external electrode 52 may also be disposed on part of the first main surface 4, part of the second main surface 5, part of the first side surface 6, and part of the second side surface 7.
• the second external electrode 52 is formed to extend from the second end face 9 to part of the first main surface 4, part of the second main surface 5, part of the first side surface 6, and part of the second side surface 7.
• the external electrode 50 includes a base electrode layer 53, an organic layer 54 formed on the base electrode layer 53, and a plating layer 55 formed on the organic layer 54.
• the plating layer includes a nickel plating layer 56 and a tin plating layer 57.
• FIG. 5 is an enlarged view of a portion of the box 210 in FIG. 2. As shown in FIG. 5, the recess 70 is formed on the surface 60 of the base electrode layer 53.
• FIG. 5 illustrates a recess 70 having a V-shaped cross section.
• FIG. 5 also shows two recesses 70 adjacent to each other in the longitudinal direction L.
• One of the recesses 70 is referred to as a first recess 71.
• the other recess 70 is referred to as a second recess 72.
• the area between the first recess 71 and the second recess 72 is omitted.
• the organic layer 54 will be described.
• the organic layer 54 is formed on the surface 60 of the base electrode layer 53.
• the organic layer 54 is also formed on the surface 60 of the base electrode layer 53 in the recess 71.
• the organic layer 54 is formed along the surface 60 of the base electrode layer 53. Therefore, the organic layer 54 forms a concave shape in the recess 71.
• Figure 5 illustrates an example where the cross-sectional shape of the organic layer 54 is U-shaped.
• a plating layer 55 is formed on the organic layer 54.
• Fig. 5 illustrates a nickel plating layer 56 as the plating layer 55. As shown in Fig. 5, the nickel plating layer 56 does not completely conform to the recesses of the organic layer 54. As a result, a gap 80 is formed between the organic layer 54 and the nickel plating layer 56.
• distance D1 The distance in the stacking direction T from the lower end 73 of the recess 70 to the upper end 74 of the recess 70 is referred to as distance D1.
• distance D1 is 0.5 ⁇ m or more and 5 ⁇ m or less.
• distance D2 The distance in the longitudinal direction L between the two upper ends 74 in the cross section of the recess 70 is referred to as distance D2.
• distance D2 is 2.1 ⁇ m or more and 8 ⁇ m or less.
• a plurality of recesses 70 may be formed as shown in FIG. 5 .
• Two recesses 70 adjacent to each other in the longitudinal direction L are designated as a first recess 71 and a second recess 72.
• Imaginary lines drawn perpendicularly from each of the two upper ends 74 of the first recess 71 are designated as imaginary lines L1 and L2.
• the distance D2 described above corresponds to the distance in the longitudinal direction L between the imaginary lines L1 and L2.
• imaginary lines drawn parallel to the stacking direction T from each of the two upper ends 74 are designated as imaginary lines L1 and L2.
• the imaginary line located midway between the imaginary lines L1 and L2 is designated as imaginary line L3.
• the distance D3 shown in FIG. 5 is half the distance D2.
• distance D4 is the spacing between adjacent recesses.
• An example of distance D4 is 0.25 ⁇ m or more and 2 ⁇ m or less.
• cross-sectional shape of the recesses 70 in the base electrode layer 53 is not limited to a V-shape.
• the cross-sectional shape of the recesses 70 may also be a U-shape, a rectangle, or the like.
• the void 80 shown in FIG. 5 is formed between the organic layer 54 formed on the recess 70 of the base electrode layer 53 and the nickel plating layer 56, which is the plating layer 55 formed on the organic layer 54.
• the plating layer 55 that defines the void 80 is not limited to the nickel plating layer 56.
• the plating layer 55 that defines the void 80 may be a plating layer 55 of another metal type.
• a gap 80 is formed between the organic layer 54 formed on the recess 70 of the base electrode layer 53 and the nickel plating layer 56. This allows for better dispersion of the bending stress caused by bending of the substrate. As a result, the occurrence of cracks inside the laminate 2 can be suppressed.
• the multilayer ceramic capacitor 1 of this embodiment can further reduce the incidence of short circuits in the multilayer ceramic capacitor 1. Furthermore, the multilayer ceramic capacitor 1 of this embodiment can further suppress a decrease in reliability caused by peeling of the external electrodes 50 due to cracks.
• the deflection stress caused by the deflection of the substrate may not be sufficiently dispersed. If the stress caused by the deflection of the substrate is not dispersed, the deflection stress may be directly transmitted to the organic layer 54 and the base electrode layer 53, and the propagation of cracks into the laminate 2 may not be suppressed.
• the following describes a method for measuring the dimensions of the organic layer 54 and the voids 80 of the multilayer ceramic capacitor 1.
• An example of the material for the organic layer 54 is polyfunctional alkoxysilane Si—(C n H 2n+1 ) 3. The material for the organic layer 54 will be described later.
• the cross section of the multilayer ceramic capacitor 1 is exposed. Specifically, the cross section is polished from the first side surface 6 or the second side surface 7 of the multilayer ceramic capacitor 1 to the center of the width direction W of the multilayer ceramic capacitor 1, exposing a cross section parallel to the length direction L and the stacking direction T.
• the cross section parallel to the length direction L and the stacking direction T is called the LT cross section.
• the exposed LT cross section is subjected to surface precision polishing using focused ion beam (FIB) processing.
• the polished first external electrode 51 and second external electrode 52 are then observed and imaged using an SEM (scanning electron microscope).
• the observation and image capturing conditions are a magnification of 2000x, an acceleration voltage of 5 kV, and a field of view of 10 ⁇ m x 10 ⁇ m.
• WDX analysis is then performed, and the portion in which silicon, carbon, hydrogen, or nitrogen is detected is considered to be an organic layer.
• the portion in which silicon, carbon, hydrogen, or nitrogen is not detected is considered to be a void 80. In this way, the void 80 portion is identified, and the dimensions of the void 80 are measured.
• the voids 80 can be formed even when no recesses 70 are formed on the surface 60 of the base electrode layer 53.
• the organic layer 54 may not be formed on the entire surface 60 of the base electrode layer 53.
• the coverage of the organic layer 54 with respect to the surface 60 of the base electrode layer 53 is, for example, 40% or more and 80% or less.
• the portions of the surface 60 of the base electrode layer 53 on which the organic layer 54 is not formed are recessed relative to the portions on which the organic layer 54 is formed. When these recessed portions are covered with the plating layer 55, the recessed portions can become voids 80.
• the dimensions of the void 80 will be described.
• the depth direction T1 is indicated by an arrow T1.
• the gap lower end 81 In the void 80, the deepest portion in the depth direction T1 is referred to as the gap lower end 81.
• the gap upper end 82 In the void 80, the shallowest portion in the depth direction T1 is referred to as the gap upper end 82.
• the gap lower end 81 is typically located at the interface between the void 80 and the organic layer 54.
• the gap upper end 82 is typically located at the interface between the void 80 and the plating layer 55.
• the distance between the gap lower end 81 and the gap upper end 82 in the stacking direction T is defined as a distance D5.
• the distance D5 indicates the dimension of the void 80 in the depth direction T1.
• An example of the distance D5 is 0.3 ⁇ m or more and 2 ⁇ m or less.
• the gap size is defined as the length of the longest imaginary line connecting the ends of one gap 80 formed between the organic layer 54 formed on the recess 70 of the base electrode layer 53 and the plating layer 55 in the stacking direction T, the length direction L, and the width direction W.
• An example of a preferred gap size is 0.3 ⁇ m or more and 2 ⁇ m or less.
• the gap size of the gap 80 formed between the organic layer 54 formed on the recess 70 of the base electrode layer 53 and the plating layer 55 is set to 0.3 ⁇ m or more and 2 ⁇ m or less.
• the bending stress of the substrate caused by external stress can be better dispersed. This further reduces the occurrence of cracks inside the laminate 2.
• the incidence of short circuits in the multilayer ceramic capacitor 1 can be reduced, and the deterioration of reliability caused by peeling of the external electrode 50 due to cracks can be further reduced.
• the gap size is 0.3 ⁇ m or larger, the bending stress of the substrate caused by external stress can be sufficiently dispersed.
• the gap size is less than 0.3 ⁇ m, the bending stress of the substrate caused by external stress cannot be sufficiently dispersed, which makes it easier for cracks to occur inside the laminate 2. If the cracks reach the internal electrode layers 40, moisture will flow in from the outside through the cracks, increasing the incidence of short circuits and reducing reliability.
• the gap size refers to the length of the longest imaginary line connecting the ends of one gap 80 formed between the organic layer 54 formed on the recess 70 of the base electrode layer 53 and the plating layer 55 in the stacking direction T, the length direction L, and the width direction W.
• the gap size of the gap 80 formed between the organic layer 54 formed on the recess 70 of the base electrode layer 53 and the plating layer 55 is measured by the following method.
• cross-section polishing is performed from the first side surface 6 or the second side surface 7 of the multilayer ceramic capacitor 1 to the center of the multilayer ceramic capacitor 1 in the width direction W, exposing the LT cross section.
• the cut surface (LT cross section) is subjected to precision surface polishing using focused ion beam (FIB) processing.
• the polished first external electrode 51 and second external electrode 52 are then observed and imaged using an SEM.
• the conditions for observation and imaging are a magnification of 2000x, an acceleration voltage of 5 kV, and a field of view of 30 ⁇ m x 30 ⁇ m.
• the portions in which silicon, carbon, hydrogen, or nitrogen elements are detected in the WDX analysis are considered to be the organic layer 54.
• Portions in which silicon, carbon, hydrogen, or nitrogen elements are not detected are considered to be voids. This allows the void size to be measured.
• Void size ( ⁇ m) (total void size within observation range/number of voids within observation range)
• the recesses 70 of the base electrode layer 53 are preferably spaced apart at intervals of 0.25 ⁇ m to 2 ⁇ m. By arranging the adjacent recesses 70 at intervals of 0.25 ⁇ m to 2 ⁇ m, the bending stress of the substrate caused by external stress can be more effectively dispersed. As a result, cracks occurring inside the laminate 2 can be suppressed.
• the recesses 70 are not spaced too far apart. This makes it possible to continuously peel the organic layer 54 and the plating layer 55, starting from peeling at adjacent recesses 70.
• the spacing between the recesses 70 is 0.25 ⁇ m or more, this is an appropriate spacing, making it less likely that minor external impacts will induce peeling between the organic layer 54 and the plating layer 55. This prevents excessive peeling of the plating layer due to external impacts that would not otherwise require peeling.
• the interval between the recesses 70 is less than 0.25 ⁇ m, the interval between the recesses 70 will be so narrow that even a slight external impact will induce peeling between the organic layer 54 and the plating layer 55. As a result, an external impact or the like that would not actually require peeling may cause excessive peeling of the plating layer 55, and the multilayer ceramic capacitor 1 may not be able to maintain its functionality.
• the distance between the recesses 70 of the base electrode layer 53 is the distance between a portion of the surface 60 of the base electrode layer 53 that extends further toward the effective layer 10 than the surface 60 of the base electrode layer 53 and a portion of the adjacent base electrode layer 53 that extends further toward the effective layer 10 than the surface 60 of the base electrode layer 53.
• the distance between the recesses 70 in the base electrode layer 53 of the multilayer ceramic capacitor 1 is measured as follows. First, the cross section of the multilayer ceramic capacitor 1 is exposed. Specifically, the cross section is polished from the first side surface 6 or the second side surface 7 of the multilayer ceramic capacitor 1 to the center of the multilayer ceramic capacitor 1 in the width direction W, exposing the LT cross section. Next, the exposed LT cross section is subjected to surface precision polishing using focused ion beam (FIB) processing. The polished first external electrode 51 and second external electrode 52 are then observed and imaged using an SEM. The observation conditions are a magnification of 2000x, an acceleration voltage of 5 kV, and a field of view of 30 ⁇ m x 30 ⁇ m.
• FIB focused ion beam
• the distance between the recesses 70 of the base electrode layer 53 is calculated based on the scale in the SEM image. Specifically, as described above, a virtual line (virtual line L3) is drawn in the center between the two ends (top ends 74) of the recesses 70 of the base electrode layer 53 within the observation range. Similarly, a virtual line (virtual line L3) is drawn in the center between the ends (top ends 74) of the recesses 70 of adjacent base electrode layers 53. The distance to each virtual line L3 is then measured. The distance D4 in FIG. 5 corresponds to the distance to each virtual line L3.
• the average value of the distances between the recesses 70 of the base electrode layer 53 within the observation range is then calculated, and this average value of the distances between the recesses 70 of the base electrode layer 53 is used as the distance between the recesses 70 of the base electrode layer 53 in this embodiment.
• Distance ( ⁇ m) between the recesses 70 of the base electrode layer 53 (total distance between the recesses 70 of the base electrode layer 53 / number of recesses 70 within the observation range)
• the organic layer 54 preferably has a structure of polyfunctional alkoxysilane Si—(C n H 2n+1 ) 3 and contains an organosilicon compound containing a nitrogen element.
• the height of the recess 70 in the base electrode layer 53 is 0.5 ⁇ m or more and 5 ⁇ m or less.
• the recess 70 is defined as a portion between a portion where the surface 60 of the base electrode layer 53 extends further toward the effective layer 10 than the surfaces 60 of the surrounding base electrode layers 53 and an adjacent portion where the surface 60 of the base electrode layer 53 extends further toward the effective layer 10 than the surfaces 60 of the surrounding base electrode layers 53.
• the height of the recess 70 is the length in the stacking direction T of the line segment having the longest distance connecting the portion where the surface 60 of the base electrode layer 53 extends further toward the effective layer 10 than the surfaces 60 of the surrounding base electrode layers 53 in the recess 70, and the end of the portion where the recessed portion extends furthest toward the effective layer 10.
• the portion of the surface 60 of the base electrode layer 53 that extends further toward the effective layer 10 than the surfaces 60 of the surrounding base electrode layers 53 corresponds to the upper end 74 of the recess 70.
• the end of the portion that extends furthest toward the effective layer 10 from this extended portion corresponds to the lower end 73 of the recess 70.
• the distance D1 in the stacking direction T from the lower end 73 of the recess 70 to the upper end 74 of the recess 70 was explained.
• Distance D1 corresponds to the height of the recess 70 in the base electrode layer 53.
• the height of the recess 70 in the multilayer ceramic capacitor 1 is measured by first exposing the cross section of the multilayer ceramic capacitor 1. Specifically, the cross section is polished from the first side surface 6 or the second side surface 7 of the multilayer ceramic capacitor 1 to the center of the width direction W of the multilayer ceramic capacitor 1 to expose the LT cross section. Next, the exposed LT cross section is subjected to precision surface polishing using focused ion beam (FIB) processing. The polished first external electrode 51 and second external electrode 52 are then observed and imaged using an SEM. The observation conditions are a magnification of 2000x, an acceleration voltage of 5 kV, and a field of view of 10 ⁇ m x 10 ⁇ m.
• FIB focused ion beam
• the height of the recesses 70 in the base electrode layer 53 is measured using the scale in the SEM image.
• the average value of the heights of the recesses 70 in the base electrode layer 53 within the observation range is calculated, and this average value of the heights of the recesses 70 in the base electrode layer 53 is set as the height of the recesses 70 in the base electrode layer 53.
• Height ( ⁇ m) of recesses 70 in base electrode layer 53 (total height of recesses 70 in base electrode layer 53/total number of recesses 70 in base electrode layer 53)
• the height of the recess 70 By setting the height of the recess 70 to be 0.5 ⁇ m or more and 5 ⁇ m or less, a sufficient gap 80 can be formed between the plating layer 55 and the organic layer 54. As a result, smooth peeling between the organic layer 54 and the plating layer 55 can be induced.
• the height of the recess 70 is outside the preferred range. If the height of the recess 70 is less than 0.5 ⁇ m, it is not possible to form a void 80 of sufficient size within the recess 70. As a result, the organic layer 54 and the plating layer 55 cannot be sufficiently peeled off, which may result in cracks occurring inside the laminate 2.
• the nickel plating layer 56 will flow excessively into the recess 70, preventing smooth peeling. Therefore, when the multilayer ceramic capacitor 1 receives an external impact, the bending stress caused by the bending of the substrate will make it difficult for the nickel plating layer 56 and the organic layer 54 to peel off. As a result, the bending stress caused by the bending of the substrate may not be sufficiently dispersed, which may result in cracks occurring inside the laminate 2.
• the external electrode 50 includes a base electrode layer 53, an organic layer 54, and a plating layer 55.
• the plating layer 55 includes a nickel plating layer 56 and a tin plating layer 57.
• the base electrode layer 53 is made of a baking layer.
• the baking layer contains a glass component and a metal.
• the glass component contains at least one selected from boron, silicon, barium, magnesium, aluminum, lithium, etc.
• the metal component contains at least one selected from copper, nickel, silver, palladium, a silver-palladium alloy, gold, etc.
• the baked layer may consist of multiple layers.
• the baked layer is formed by applying a conductive paste containing glass and metal to the laminate 2 and baking it.
• the baked layer may be co-fired with the internal electrode layer 40 and the dielectric layer 30, or may be baked after the internal electrode layer 40 and the dielectric layer 30 have been baked.
• the conductive paste is baked simultaneously with the internal electrode layer 40 and the dielectric layer 30, it is preferable to add a dielectric material instead of the glass component to form the baked electrode.
• the thickness of the baked layer serving as the base electrode layer 53 located on the first end face 8 and the second end face 9, at the center in the stacking direction T connecting the first main surface 4 and the second main surface 5, and at the center in the width direction W connecting the first side surface 6 and the second side surface 7, is preferably, for example, approximately 3 ⁇ m or more and 160 ⁇ m or less.
• the thickness of the baked layer as the base electrode layer 53 located on the first principal surface 4 and the second principal surface 5 at the center in the length direction L and the center in the width direction W is preferably, for example, about 3 ⁇ m or more and 40 ⁇ m or less.
• the thickness of the baked layer as the base electrode layer 53 located on the first side surface 6 and the second side surface 7 at the center in the length direction L and the center in the stacking direction T is preferably, for example, about 3 ⁇ m or more and 40 ⁇ m or less.
• An organic layer 54 is formed on the base electrode layer 53.
• the organic layer 54 is made of, for example, a monofunctional silane coupling material. Specific examples of the silane coupling material include decyltrimethoxysilane, n-propyltrimethoxysilane, and octyltriethoxysilane.
• plating layer 55 is formed on the organic layer 54.
• the material of the plating layer 55 includes at least one selected from the group consisting of copper, nickel, tin, silver, palladium, a silver-palladium alloy, and gold.
• the plating layer 55 may be formed from multiple layers. Preferably, the plating layer 55 has a two-layer structure of nickel plating and tin plating. In the multilayer ceramic capacitor 1 of this embodiment, the plating layer 55 includes a nickel plating layer 56 and a tin plating layer 57.
• the nickel plating layer 56 prevents the base electrode layer 53 from being eroded by solder when mounting ceramic electronic components.
• the tin plating layer 57 improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. As a result, mounting to a substrate via solder is easier.
• the preferred thickness of each plating layer is 1 ⁇ m or more and 15 ⁇ m or less.
• the dimension in the length direction L of the multilayer ceramic capacitor 1, including the laminate 2 and the external electrodes 50, is referred to as the L dimension.
• a preferred L dimension is 0.2 mm or more and 10 mm or less.
• the dimension in the stacking direction T of the multilayer ceramic capacitor 1, including the laminate 2 and the external electrodes 50, is referred to as the T dimension.
• a preferred T dimension is 0.1 mm or more and 10 mm or less.
• the dimension in the width direction W of the multilayer ceramic capacitor 1, including the laminate 2 and the external electrodes 50, is referred to as the W dimension.
• a preferred W dimension is 0.1 mm or more and 10 mm or less.
• a laminate 2 is prepared having the first internal electrode layer 41 and the second internal electrode layer 42.
• a ceramic paste containing ceramic powder is applied in a sheet form by, for example, a screen printing method, and dried to produce a mother ceramic green sheet.
• a conductive paste for forming internal electrode layers is printed in a predetermined pattern on the mother ceramic green sheet, for example, by screen printing, to form a conductive pattern for forming internal electrode layers of the first internal electrode layer 41.
• a conductive paste for forming internal electrode layers is printed in a predetermined pattern on another mother ceramic green sheet, for example, by screen printing, to form a conductive pattern for forming internal electrode layers of the second internal electrode layer.
• mother ceramic green sheets are prepared on which the conductive pattern for forming the first internal electrode layer 41 is formed, mother ceramic green sheets on which the conductive pattern for forming the second internal electrode layer 42 is formed, and mother ceramic green sheets on which no conductive pattern for forming the internal electrode layer is formed.
• the ceramic paste and the conductive paste for forming the internal electrode layers may contain, for example, well-known binders and solvents.
• the mother laminate is produced as follows. A predetermined number of mother ceramic green sheets for outer layers, which do not have a conductive pattern for forming internal electrode layers printed on them, are stacked on top of which mother ceramic green sheets, which have a conductive pattern for forming internal electrode layers of the first internal electrode layer 41 printed on them, and mother ceramic green sheets, which have a conductive pattern for forming internal electrode layers of the second internal electrode layer 42 printed on them, are stacked alternately in sequence. A predetermined number of mother ceramic green sheets for outer layers, which do not have a conductive pattern for forming internal electrode layers printed on them, are then stacked on top of which to produce the mother laminate.
• the mother laminate may be pressed in the lamination direction T using means such as an isostatic press.
• the mother laminate is cut at predetermined positions to cut out a plurality of raw laminates of predetermined dimensions.
• the corners and ridges of the raw laminates may be rounded by barrel polishing or the like.
• the green laminate 2 is fired to obtain a laminate 2 in which the first internal electrode layers 41 and the second internal electrode layers 42 are disposed therein, the first lead electrode portions 44 of the first internal electrode layers 41 are exposed at the first end face 8, and the second lead electrode portions 46 of the second internal electrode layers 42 are exposed at the second end face 9.
• the firing temperature is set appropriately depending on the types of ceramic material and conductive material. The firing temperature is set, for example, within a range of 900°C to 1300°C.
• base electrode layers 53 of the external electrodes 50 are formed on both ends of the fired laminate 2.
• a conductive paste for the external electrodes is applied to both ends of the fired laminate 2 and baked, thereby forming the base electrode layers 53.
• a preferred baking temperature is 700°C or higher and 900°C or lower.
• recesses 70 are formed in the base electrode layer 53 by polishing the surface of the laminate 2. Blasting is used for the polishing. To obtain the desired recesses 70, the particle size of the blasting material, the discharge pressure, and the blasting time are adjusted.
• the polishing method may be at least one of laser irradiation, barrel polishing, polishing with abrasive paper, abrasives, grinding stones, buffs, etc., and chemical polishing, in addition to blasting.
• the method of forming the spacing between the recesses 70 in the base electrode layer 53 can be the same as the method of forming the recesses 70, which is a method of polishing the surface of the laminate 2. Blasting is used for polishing. To obtain the desired spacing between the recesses 70, the particle size of the blasting material, the discharge pressure, the blasting time, and the like are adjusted. Note that the polishing method may be at least one of laser irradiation, barrel polishing, polishing with abrasive paper, abrasives, grinding stones, buffs, and the like, and chemical polishing, in addition to blasting.
• the organic layer 54 is formed as follows.
• the organic layer 54 is formed by applying or immersing an organic treatment liquid so as to cover predetermined surfaces of the base electrode layer 53 and the laminate 2.
• the organic treatment liquid is applied to the base electrode layer 53, etc.
• the laminates 2 to which the base electrode layers 53 of the external electrodes 50 have been baked are aligned in the longitudinal direction, and the surfaces of the external electrodes 50 (surfaces 60 of the base electrode layers 53) are immersed in the organic treatment liquid.
• the organic treatment liquid is made of a monofunctional silane coupling material. Specifically, the organic treatment liquid uses decyltrimethoxysilane, n-propyltrimethoxysilane, octyltriethoxysilane, etc. The organic treatment liquid is made by diluting these materials in an alcohol solvent to a concentration of 3% by weight or less.
• the void 80 between the organic layer 54 and the plating layer 55 is formed as follows. A resin is applied to the organic layer 54 formed in the recess 70 of the base electrode layer 53 to form the void.
• the resin applied to the organic layer 54 is mainly a binder. Therefore, the resin disappears during the firing process. As a result, the void 80 is formed.
• the amount of resin applied to the organic layer 54 the size of the void 80 formed between the base electrode layer 53 and the organic layer 54 can be controlled.
• the plating layer 55 of the external electrode 50 is formed on both ends of the laminate 2.
• the plating layer 55 of the external electrode 50 is formed so as to cover almost the entire surface 60 of the base electrode layer 53 of the external electrode 50.
• the above method makes it possible to prevent cracks and deformations from occurring in the ceramic portion and active layer portion of the laminate 2, making it easy to manufacture multilayer ceramic capacitors with improved performance and reliability.
• voids 80 can be formed without using a binder by forming a plating layer 55 on the organic layer 54.
• voids 80 can be formed without using a binder by forming a plating layer 55 on the organic layer 54.
• the coverage rate of the organic layer 54 relative to the surface 60 of the base electrode layer 53 is not 100%.
• the coverage rate can be changed by adjusting the concentration of the organic treatment liquid used when forming the organic layer 54.
• the portions of the surface 60 of the base electrode layer 53 where the organic layer 54 is not formed can become voids 80 by forming the plating layer 55 after forming the organic layer 54. Therefore, voids 80 can be formed without using a binder by, for example, adjusting the coverage rate of the organic layer 54 relative to the surface 60 of the base electrode layer 53 when forming the organic layer 54.
• Example 1 is a multilayer ceramic capacitor according to an embodiment of the present invention.
• the multilayer ceramic capacitor of Example 1 may be simply referred to as Example 1.
• FIG. 6 is a table showing the results of Experimental Example 1.
• Example 1 has voids. Comparative Examples 1 and 2 do not have voids. Comparative Example 2 is the same as Example 1 except that it does not have voids. Comparative Example 1 does not have voids, and in addition does not have an organic layer.
• the test method for Experimental Example 1 was as follows: LF solder was applied to a thickness of 150 ⁇ m on a JEITA land FR4 board measuring 40 mm wide, 100 mm long, and 1.6 mm thick, and then the multilayer ceramic capacitor was placed on it. The board was then passed through a reflow oven at 240°C to mount the multilayer ceramic capacitor.
• the bending and retention test was performed by pressing a pressing tool with a radius R of 1 mm against the backside of the board at a speed of 1 mm/sec, and holding the board in a 2 mm bending state for 5 seconds.
• the number of substrates tested was 100 for each of Comparative Example 1, Comparative Example 2, and Example 1.
• One multilayer ceramic capacitor was mounted on each substrate.
• the number of multilayer ceramic capacitors mounted on the substrate was 100 for each of Comparative Example 1, Comparative Example 2, and Example 1.
• each tested board was placed on a hot plate at 240°C to melt the solder, and the multilayer ceramic capacitor was removed from the board.
• the cross section was polished from the surface perpendicular to the mounting surface of the board, i.e., from the first or second side to the center of the multilayer ceramic capacitor (halfway along the width direction W). After polishing the cross section, the polished cross section was observed using an SEM (electron microscope), focusing on cracks that originated at the end of the external electrode and progressed from the outer layer toward the effective layer.
• SEM electron microscope
• the rate of crack occurrence was determined as the percentage of 100 samples in each of Comparative Example 1, Comparative Example 2 and Example 1 in which cracks were observed.
• the specifications of the sample multilayer ceramic capacitors of Comparative Example 1, Comparative Example 2, and Example 1 are described below.
• the specifications of the multilayer ceramic capacitor (Comparative Example 1) are as follows: Dimensions: length L (L dimension) 1.0 mm, width W (W dimension) 0.5 mm, height H (T dimension) 0.5 mm Ceramic material: barium titanate Capacitance: 10nF Rated voltage: 16V ⁇
• the specifications of the external electrodes are as follows: Base electrode layer material: Material containing conductive metal (copper) and glass component Base electrode layer thickness: 30 ⁇ m at the center of the end face Base electrode layer and plating layer: two layers of nickel plating layer (3 ⁇ m) + tin plating layer (3 ⁇ m) Formation of organic layer: none Gap between organic layer and plating layer: no Gap formed between organic layer and plating layer As described above, Comparative Example 1 has no organic layer and no gap.
• the specifications of the multilayer ceramic capacitor are as follows: Dimensions: length L 1.0 mm, width W 0.5 mm, height H 0.5 mm Ceramic material: barium titanate Capacitance: 10nF Rated voltage: 16V ⁇
• the specifications of the external electrodes are as follows: Base electrode layer material: Material containing conductive metal (copper) and glass component Base electrode layer thickness: 30 ⁇ m at the center of the end face Base electrode layer/plating layer: Two layers of nickel plating layer (3 ⁇ m) + tin plating layer (3 ⁇ m)/organic layer specifications are as follows: Organic layer material: polyfunctional alkoxysilane Si-(C n H 2n+1 ) 3 Recess height: 0.5 ⁇ m Distance between recesses: 2.5 ⁇ m Comparative Example 2 has an organic layer, no voids, a recess height of 0.5 ⁇ m, and a distance between recesses of 0.25 ⁇ m.
• Example 1 The specifications of the multilayer ceramic capacitor (Example 1) are as follows: Dimensions: length L 1.0 mm, width W 0.5 mm, height H 0.5 mm Ceramic material: barium titanate Capacitance: 10nF Rated voltage: 16V ⁇ The specifications of the external electrodes are as follows: Base electrode layer material: Material containing conductive metal (copper) and glass component Base electrode layer thickness: 30 ⁇ m at the center of the end face Base electrode layer/plating layer: Two layers of nickel plating layer (3 ⁇ m) + tin plating layer (3 ⁇ m)/organic layer specifications are as follows: Organic layer material: polyfunctional alkoxysilane Si-(C n H 2n+1 ) 3 Recess height: 0.5 ⁇ m Distance between recesses: 2.5 ⁇ m In Example 1, an organic layer is provided, gaps are provided, the gap size is 0.2 ⁇ m, the recess height is 0.5 ⁇ m, and the interval between the recesses is 0.25 ⁇ m.
• Example 1 shows that the crack occurrence rate, short circuit rate, and peeling rate of the multilayer ceramic capacitor are reduced by forming a gap between the base electrode layer and the nickel plating layer. This shows that the formation of a gap between the base electrode layer and the nickel plating layer further distributes the bending stress caused by substrate bending, making it possible to further suppress cracks from forming inside the laminate.
• Example 1 shows that it is a highly reliable multilayer ceramic capacitor in which cracks that occur in the laminate are less likely to reach the internal electrode layer, the rate of short circuit occurrence caused by moisture flowing in from the outside through the cracks is reduced, and peeling of the external electrodes is suppressed.
• FIG. 7 is a table showing the results of Experimental Example 2.
• Experimental Example 2 differences in characteristics due to differences in void size were evaluated in a multilayer ceramic capacitor according to an embodiment of the present invention. Examples 2 to 9 were fabricated to have the same configuration as Example 1 except for the void size between the organic layer and the plating layer.
• Experimental Example 2 the crack occurrence rate, short-circuit rate, and peeling rate of the multilayer ceramic capacitor after thermal stress were measured in the same manner as in Experimental Example 1.
• the test method for Experimental Example 2 was as follows: LF solder was applied to a thickness of 150 ⁇ m on a JEITA land FR4 board measuring 40 mm wide, 100 mm long, and 1.6 mm thick, and then the multilayer ceramic capacitor was placed on it. The board was then passed through a reflow oven at 240°C to mount the multilayer ceramic capacitor.
• the bending and retention test was performed by pressing a pressing tool with a radius R of 1 mm against the backside of the board at a speed of 1 mm/sec, and holding the board in a 2 mm bending state for 5 seconds.
• the number of boards tested was 100 for each example.
• One multilayer ceramic capacitor was mounted on each board.
• the number of multilayer ceramic capacitors mounted on the board was 100 for each example.
• the tested board is then placed on a hot plate at 240°C to melt the solder, and the multilayer ceramic capacitor is removed from the board.
• the cross section was polished from the surface perpendicular to the mounting surface of the board, i.e., from the first or second side surface to the center of the multilayer ceramic capacitor (half the width W).
• the polished cross section was then observed using an SEM (electron microscope), focusing on cracks that originated at the end of the external electrode and progressed from the outer layer toward the effective layer.
• SEM electron microscope
• the short-circuit rate for multilayer ceramic capacitors was measured using a multimeter to measure the resistance after applying a rated voltage of 6V, and samples with a resistance of 1M ⁇ or less were determined to have experienced a short circuit. The proportion of samples determined to have experienced a short circuit out of 100 samples for each example was calculated as the short-circuit rate.
• peeling rate Number of multilayer ceramic capacitors that peeled off from the soldered board and lost continuity on the board / Number of samples (100) ⁇ 100
• Example 2 The specifications of the sample multilayer ceramic capacitors of Examples 2 to 9 are described below.
• Example 2 The specifications of the multilayer ceramic capacitor (Example 2) are as follows: Dimensions: length L 1.0 mm, width W 0.5 mm, height H 0.5 mm Ceramic material: barium titanate Capacitance: 10nF Rated voltage: 16V Gap size: 0.1 ⁇ m Recess height: 0.5 ⁇ m Distance between recesses: 2.5 ⁇ m
• an organic layer is provided, gaps are provided, the gap size is 0.1 ⁇ m, the recess height is 0.5 ⁇ m, and the interval between the recesses is 0.25 ⁇ m.
• Example 3 The specifications of the multilayer ceramic capacitor (Example 3) are as follows: Dimensions: length L 1.0 mm, width W 0.5 mm, height H 0.5 mm Ceramic material: barium titanate Capacitance: 10nF Rated voltage: 16V Gap size: 0.2 ⁇ m Recess height: 0.5 ⁇ m Distance between recesses: 2.5 ⁇ m In Example 3, an organic layer and gaps are present, the gap size is 0.2 ⁇ m, the recess height is 0.5 ⁇ m, and the interval between the recesses is 0.25 ⁇ m.
• Example 4 The specifications of the multilayer ceramic capacitor (Example 4) are as follows: Dimensions: length L 1.0 mm, width W 0.5 mm, height H 0.5 mm Ceramic material: barium titanate Capacitance: 10nF Rated voltage: 16V Gap size: 0.3 ⁇ m Recess height: 0.5 ⁇ m Distance between recesses: 2.5 ⁇ m In Example 4, an organic layer was provided, gaps were provided, the gap size was 0.3 ⁇ m, the recess height was 0.5 ⁇ m, and the interval between the recesses was 0.25 ⁇ m.
• Example 5 The specifications of the multilayer ceramic capacitor (Example 5) are as follows: Dimensions: length L 1.0 mm, width W 0.5 mm, height H 0.5 mm Ceramic material: barium titanate Capacitance: 10nF Rated voltage: 16V Gap size: 1 ⁇ m Recess height: 0.5 ⁇ m Distance between recesses: 2.5 ⁇ m In Example 5, an organic layer was provided, gaps were provided, the gap size was 1 ⁇ m, the recess height was 0.5 ⁇ m, and the interval between the recesses was 0.25 ⁇ m.
• Example 6 The specifications of the multilayer ceramic capacitor (Example 6) are as follows: Dimensions: length L 1.0 mm, width W 0.5 mm, height H 0.5 mm Ceramic material: barium titanate Capacitance: 10nF Rated voltage: 16V Gap size: 1.5 ⁇ m Recess height: 0.5 ⁇ m Distance between recesses: 2.5 ⁇ m In Example 6, an organic layer and gaps are present, the gap size is 1.5 ⁇ m, the recess height is 0.5 ⁇ m, and the interval between the recesses is 0.25 ⁇ m.
• Example 7 The specifications of the multilayer ceramic capacitor (Example 7) are as follows: Dimensions: length L 1.0 mm, width W 0.5 mm, height H 0.5 mm Ceramic material: barium titanate Capacitance: 10nF Rated voltage: 16V Gap size: 2 ⁇ m Recess height: 0.5 ⁇ m Distance between recesses: 2.5 ⁇ m In Example 7, an organic layer was provided, gaps were provided, the gap size was 2 ⁇ m, the recess height was 0.5 ⁇ m, and the interval between the recesses was 0.25 ⁇ m.
• Example 8 The specifications of the multilayer ceramic capacitor (Comparative Example 8) are as follows: Dimensions: length L 1.0 mm, width W 0.5 mm, height H 0.5 mm Ceramic material: barium titanate, capacitance: 10 nF Rated voltage: 16V Gap size: 2.1 ⁇ m Recess height: 0.5 ⁇ m Distance between recesses: 2.5 ⁇ m Example 8 has an organic layer and voids, the void size is 2.1 ⁇ m, the recess height is 0.5 ⁇ m, and the interval between the recesses is 0.25 ⁇ m.
• Example 9 The specifications of the multilayer ceramic capacitor (Comparative Example 8) are as follows: Dimensions: length L 1.0 mm, width W 0.5 mm, height H 0.5 mm Ceramic material: barium titanate Capacitance: 10nF Rated voltage: 16V Gap size: 2.1 ⁇ m Recess height: 0.5 ⁇ m Distance between recesses: 2.5 ⁇ m Example 9 has an organic layer and voids, the void size is 2.5 ⁇ m, the recess height is 0.5 ⁇ m, and the interval between the recesses is 0.25 ⁇ m.
• Example 8 and 9 of Experimental Example 2 the crack occurrence rate was similar to that of Examples 4 to 7, but the void size was large, exceeding 2.0 ⁇ m, which could result in insufficient bonding between the base electrode layer and the plating layer. In Examples 8 and 9, the peeling rate increased, confirming a decrease in the reliability of the multilayer ceramic capacitor.
• Experimental Example 2 confirmed that the crack occurrence rate and short circuit rate were proportional, and that the peeling rate was also high.
• FIG. 8 is a table showing the results of Experimental Example 3.
• Experimental Example 3 differences in characteristics due to differences in the spacing between recesses in a multilayer ceramic capacitor according to an embodiment of the present invention were evaluated. Examples 10 to 18 were fabricated to have the same configuration as Example 4, except for the spacing between recesses.
• Experimental Example 3 the crack occurrence rate, short circuit rate, and peeling rate of the multilayer ceramic capacitor after thermal stress were measured in the same manner as in Experimental Example 2. The crack occurrence rate, short circuit rate, and peeling rate of the multilayer ceramic capacitor were measured using the same methods as in Experimental Example 2.
• experimental example 3 shows that the peeling rate was suppressed in Examples 12 to 18, but the crack occurrence rate increased in Examples 17 and 18. This shows that when the distance between recesses is too large, the stress generated by the bending of the board is difficult to disperse, and excessive stress ends up concentrating in each recess. This results in cracks occurring, which are thought to be causing short-circuit defects.
• an organic layer is formed on the base electrode layer, a nickel plating layer is formed on the organic layer, and a gap is formed between the organic layer and the nickel plating layer.
• the presence of the organic layer prevents the deflection stress caused by bending of the substrate when the multilayer ceramic capacitor is subjected to external impact, which induces delamination between the nickel plating layer (plating layer) and the organic layer.
• the delamination between the plating layer and the organic layer disperses the deflection stress, thereby suppressing cracks in the multilayer ceramic capacitor.
• the formation of a gap between the organic layer and the nickel plating layer further disperses the deflection stress caused by bending of the substrate. Therefore, the multilayer ceramic capacitor of this embodiment can further suppress the occurrence of cracks within the laminate. It is believed that the presence of the gap also makes it easier for the generated stress to be evenly distributed at the interface between the plating layer and the base electrode layer or the organic layer.
• the multilayer ceramic capacitor of this embodiment can reduce the incidence of short circuits in the multilayer ceramic capacitor and suppress the deterioration of reliability caused by peeling of the external electrodes due to cracks, making it possible to provide a highly reliable multilayer ceramic capacitor.
• a multilayer ceramic capacitor comprising: a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers, the laminate having a first main surface and a second main surface opposing each other in the lamination direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the lamination direction and the width direction; and external electrodes provided on the first end surface and the second end surface and connected to the internal electrode layers, the external electrodes comprising a base electrode layer, an organic layer formed on the base electrode layer, and a plating layer formed on the organic layer, with a gap formed between the organic layer and the plating layer of the base electrode layer.
• ⁇ 2> The multilayer ceramic capacitor described in ⁇ 1>, wherein a recess is formed on the surface of the base electrode layer, and a gap is formed between the organic layer formed on the recess and the plating layer.
• ⁇ 3> A multilayer ceramic capacitor according to ⁇ 1> or ⁇ 2>, wherein the size of the void is 0.3 ⁇ m or more and 2 ⁇ m or less.
• ⁇ 5> The multilayer ceramic capacitor according to any one of ⁇ 1> to ⁇ 4>, wherein the organic layer has a structure of polyfunctional alkoxysilane Si—(C n H 2n+1 ) 3 and contains an organosilicon compound containing a nitrogen element.

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