WO2025112271A1 - 图形处理器的线路板及服务器系统 - Google Patents

图形处理器的线路板及服务器系统 Download PDF

Info

Publication number
WO2025112271A1
WO2025112271A1 PCT/CN2024/088058 CN2024088058W WO2025112271A1 WO 2025112271 A1 WO2025112271 A1 WO 2025112271A1 CN 2024088058 W CN2024088058 W CN 2024088058W WO 2025112271 A1 WO2025112271 A1 WO 2025112271A1
Authority
WO
WIPO (PCT)
Prior art keywords
connector
circuit board
group
board
slot
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/088058
Other languages
English (en)
French (fr)
Inventor
郭伯亚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Metabrain Intelligent Technology Co Ltd
Original Assignee
Suzhou Metabrain Intelligent Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Metabrain Intelligent Technology Co Ltd filed Critical Suzhou Metabrain Intelligent Technology Co Ltd
Priority to US19/139,143 priority Critical patent/US20260030192A1/en
Publication of WO2025112271A1 publication Critical patent/WO2025112271A1/zh
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/409—Mechanical coupling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/02—Arrangements of circuit components or wiring on supporting structure
    • H05K7/10—Plug-in assemblages of components, e.g. IC sockets
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/14—Mounting supporting structure in casing or on frame or rack
    • H05K7/1485—Servers; Data center rooms, e.g. 19-inch computer racks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Definitions

  • the embodiments of the present application relate to the field of computers, and more specifically, to a circuit board of a graphics processor and a server system.
  • GPU Graphics Processing Unit
  • multiple GPUs need to be used in the face of complex computing needs.
  • multiple GPUs need to adopt different machine topologies. Therefore, the switching of GPU connection topologies on servers is very frequent.
  • the GPUs on servers are connected by complex cables. When switching between different topologies, the cables need to be reconnected. The whole operation process involves multiple cables with different cable lengths. Cables of different models need to be switched. The operation plan is relatively complicated, and the complex connection operation is also prone to damage to the cables and GPU board interfaces.
  • the embodiments of the present application provide a circuit board of a graphics processor and a server system to at least solve the problem in the related art that changing the machine topology form requires complex operations and is prone to damage to cables and interfaces.
  • a circuit board of a graphics processor on which a connector group, a switching chipset and a device slot group are deployed, the connector group includes: a first connector, a second connector, a third connector and a fourth connector, the switching chipset includes: a first switching chip and a second switching chip, the device slot group includes: a first slot set and a second slot set, the first slot set includes M+P device slots, the second slot set includes N device slots, N is equal to M+P; the first switching chip is connected to the first connector, the third connector and the M device slots in the first slot set respectively through circuit board routing, the second switching chip is connected to the fourth connector and the N device slots in the second slot set respectively through circuit board routing, and the second connector is connected to the P device slots in the first slot set through circuit board routing; the first connector is configured to connect to a central processing unit; the second connector is configured to connect to the third connector; the third connector is configured to connect to the second connector, or, the fourth connector; the
  • the second connector, the third connector and the fourth connector are all board-to-board connectors, the second connector, the third connector and the fourth connector are arranged in a straight line and in the same direction, and the spacing between the second connector and the third connector and the spacing between the third connector and the fourth connector are both target spacings.
  • the connectors in the connector group are connected via a connector circuit board, wherein the connector circuit board
  • the fifth connector and the sixth connector are deployed on the same side of the board.
  • the fifth connector and the sixth connector are connected through circuit board routing.
  • the fifth connector and the sixth connector are both board-to-board connectors.
  • the spacing between the fifth connector and the sixth connector is the target spacing.
  • the connector circuit board is configured to slide on the circuit board of the graphics processor, and switching between the third connector and the second connector and between the third connector and the fourth connector is achieved by sliding.
  • the connector circuit board is configured to achieve connection between the third connector and the second connector, and between the third connector and the fourth connector by plugging and unplugging.
  • the connectors in the connector group are connected via a connecting cable comprising two connecting heads, wherein a first connecting head of the connecting cable is connected to the third connector, and a second connecting head of the connecting cable is configured to be connected to the second connector or the fourth connector.
  • connection structure between the second connector and the third connector is used to form a balanced topology structure, or a common topology structure, of the graphics processor.
  • the second connector is connected to the third connector, and the first connector and the fourth connector are respectively connected to different central processors to form a balanced topology structure.
  • the second connector is connected to the third connector, and the first connector and the fourth connector are connected to the same central processor to form a common topology structure.
  • connection structure between the third connector and the fourth connector is used to form a series topology structure of the graphics processor.
  • the third connector is connected to the fourth connector, and the first connector is connected to the central processor to form a series topology structure.
  • M is equal to N-1 and P is equal to 1.
  • N is equal to 5.
  • a server system comprising: a central processing unit group, a circuit board of a graphics processing unit and a graphics processing unit group, wherein the circuit board of the graphics processing unit is connected between the central processing unit group and the graphics processing unit group,
  • a connector group, a switching chipset and a device slot group are deployed on the circuit board of the graphics processor, wherein the connector group includes: a first connector, a second connector, a third connector and a fourth connector, the switching chipset includes: a first switching chip and a second switching chip, and the device slot group includes: a first slot set and a second slot set, the first slot set includes M+P device slots, the second slot set includes N device slots, and N is equal to M+P;
  • the first switching chip is respectively connected to the first connector, the third connector, and the M device slots in the first slot set through circuit board wiring
  • the second switching chip is respectively connected to the fourth connector and the N device slots in the second slot set through circuit board wiring
  • the second connector is connected to the P device slots in the first slot set through circuit board wiring
  • the first connector is configured to connect to a central processor in a central processor group;
  • the second connector is configured to connect to a third connector;
  • the third connector is configured to connect to the second connector or a fourth connector;
  • the fourth connector is configured to connect to the third connector or a central processor in the central processor group;
  • a device slot group is configured to connect graphics processors in a graphics processor group.
  • the second connector is connected to the third connector
  • the first connector is connected to the first central processor in the central processor group
  • the fourth connector is connected to the second central processor in the central processor group to form a balanced topology structure of the graphics processor group.
  • the second connector is connected to the third connector, and the first connector and the fourth connector are both connected to the third central processor in the central processor group to form a common topology structure of the graphics processor group.
  • the third connector is connected to the fourth connector, and the first connector is connected to the fourth central processor in the central processor group to form a series topology structure of the graphics processor group.
  • the server system further includes: a connector circuit board, wherein:
  • the second connector, the third connector and the fourth connector are all board-to-board connectors, the second connector, the third connector and the fourth connector are arranged in a straight line and in the same direction, and the spacing between the second connector and the third connector and the spacing between the third connector and the fourth connector are both target spacings;
  • the connectors in the connector group are connected through a connector circuit board, wherein a fifth connector and a sixth connector are deployed on the same side of the connector circuit board, the fifth connector and the sixth connector are connected through circuit board routing, the fifth connector and the sixth connector are both board-to-board connectors, and the spacing between the fifth connector and the sixth connector is the target spacing.
  • the connector circuit board is configured to slide on the circuit board of the graphics processor, and switching between the third connector and the second connector and between the third connector and the fourth connector is achieved by sliding.
  • the connector circuit board is configured to achieve connection between the third connector and the second connector, and between the third connector and the fourth connector by plugging and unplugging.
  • a circuit board for connecting a graphics processor and a central processing unit is provided.
  • a connector group, a switching chipset and a device slot are deployed on the circuit board.
  • the connector group includes a first connector, a second connector, a third connector and a fourth connector.
  • the switching chipset includes a first switching chip and a second switching chip.
  • the device slot group includes a first slot set and a second slot set.
  • the first switching chip is respectively connected to the first connector, the third connector and M device slots in the first slot set through circuit board routing
  • the second switching chip is respectively connected to the fourth connector and N device slots in the second slot set through circuit board routing
  • the second connector is connected to P device slots in the first slot set through circuit board routing.
  • the first connector is configured to be used for connecting to the central processing unit
  • the second connector is configured to be used for connecting to the third connector
  • the third connector is configured to be used for connecting to the second connector or the fourth connector
  • the fourth connector is configured to be used for connecting to the third connector or the central processing unit.
  • the structure of the circuit board of the graphics processor is simplified under the premise of meeting the connection topology requirements of the graphics processor, and the problem of high complexity of switching operation of the connection topology of multiple graphics processors on a server can be solved, so as to reduce the complexity of switching operation of the connection topology of multiple graphics processors on the server.
  • FIG1 is a schematic diagram of a circuit board of a graphics processor according to an embodiment of the present application.
  • FIG2 is a schematic diagram of a bridge according to an embodiment of the present application.
  • FIG3 is a schematic diagram of an optional balanced topology structure according to an embodiment of the present application.
  • FIG4 is a schematic diagram of an optional common topology structure according to an embodiment of the present application.
  • FIG5 is a schematic diagram of an optional series topology structure according to an embodiment of the present application.
  • FIG6 is a schematic diagram of an optional server system according to an embodiment of the present application.
  • FIG. 7 is a detailed diagram of an optional circuit board according to the present application.
  • FIG1 is a schematic diagram of a circuit board of a graphics processor according to an embodiment of the present application.
  • a connector group, a switching chipset and a device slot group are deployed on the circuit board, wherein the connector group includes: a first connector, a second connector, a third connector and a fourth connector, the switching chipset includes: a first switching chip and a second switching chip, and the device slot group includes: a first slot set and a second slot set, the first slot set includes M+P device slots, and the second slot set includes N device slots, where N is equal to M+P;
  • the first switching chip is respectively connected to the first connector, the third connector, and the M device slots in the first slot set through circuit board wiring
  • the second switching chip is respectively connected to the fourth connector and the N device slots in the second slot set through circuit board wiring
  • the second connector is connected to the P device slots in the first slot set through circuit board wiring
  • the first connector is configured to connect to a central processing unit;
  • the second connector is configured to connect to a third connector;
  • the third connector is configured to connect to the second connector, or a fourth connector;
  • the fourth connector is configured to connect to the third connector, or a central processing unit;
  • a device slot group that is configured to connect to a graphics processor.
  • a circuit board for connecting a graphics processor and a central processing unit is provided.
  • a connector group, a switching chipset and a device slot are deployed on the circuit board.
  • the connector group includes a first connector, a second connector, a third connector and a fourth connector.
  • the switching chipset includes a first switching chip and a second switching chip.
  • the device slot group includes a first slot set and a second slot set. Some components on the circuit board are connected through circuit board routing.
  • the first switching chip is respectively connected to the first connector, the third connector and M device slots in the first slot set through circuit board routing, the second switching chip is respectively connected to the fourth connector and N device slots in the second slot set through circuit board routing, and the second connector is connected to P device slots in the first slot set through circuit board routing.
  • the first connector is configured to be used for connecting to the central processing unit
  • the second connector is configured to be used for connecting to the third connector
  • the third connector is configured to be used for connecting to the second connector or the fourth connector
  • the fourth connector is configured to be used for connecting to the third connector or the central processing unit.
  • the port on the connector group side of the circuit board is configured to connect The central processor
  • the port on the device slot group side of the circuit board is configured to connect to the graphics processor
  • the device slot group includes multiple device slots for connecting to the graphics processor, thereby realizing the connection between the central processor and multiple graphics processors.
  • connection relationship among the second connector, the third connector and the fourth connector may be changed to realize different connection topology requirements of the graphics processor.
  • the second connector, the third connector and the fourth connector can be arranged in sequence in a straight line on the circuit board, and the second connector, the third connector and the fourth connector can be connected by a cable or by a connecting device.
  • the second connector, the third connector and the fourth connector can adopt a connector with an external connection interface (such as a board-to-board connector).
  • the connecting device can be a connecting device with two connection interfaces, and the connection interface on the connecting device is configured to be connected to the external connection interface on the connector.
  • the connecting device can be a connecting cable including two connecting heads, the first connecting head of the connecting cable is connected to the third connector, and the second connecting head on the connecting cable is configured to be connected to the second connector or the fourth connector.
  • the connection topology of the graphics processor is switched;
  • the connector may also be a connection board including two connection heads, in which case the second connector, the third connector and the fourth connector are arranged in a straight line, and the spacing between the second connector, the third connector and the fourth connector is equal, and the spacing between the two connection joints on the connection board is equal to the spacing between the third connector and the second connector or the spacing between the third connector and the connector.
  • connection topology of the graphics processor can be changed by changing the connection relationship between the connection board and the second connector, the third connector and the fourth connector, or the connection board can be configured to be slidable on the circuit board, and the connection topology of the graphics processor can be changed by sliding the connection board between the second connector, the third connector and the fourth connector, thereby changing the connection relationship between the connection board and the second connector, the third connector and the fourth connector.
  • the above-mentioned graphics processing circuit board supports a GPU board with 8 ⁇ 16 GPUs and 2 ⁇ 16 network cards, and supports three topologies of balance, cascade, and common.
  • the above-mentioned switching chip is two 96 lane PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) switch (96-channel PCIe switch) chips.
  • the second connector, the third connector and the fourth connector are all board-to-board connectors, the second connector, the third connector and the fourth connector are arranged in a straight line and in the same direction, and the spacing between the second connector and the third connector and the spacing between the third connector and the fourth connector are both target spacings.
  • the board-to-board connector can be a vertical connector or a right angle connector.
  • the board-to-board connector may be a MCIO (Mini Cool Edge IO) connector or a gen-z connector.
  • the third connector is spaced equal to the second connector and the fourth connector, and the orientations are consistent, so that the third connector and the second connector are connected, and the third connector and the fourth connector are connected.
  • the specifications of the connector used when connecting the third connector and the fourth connector are unified, so the same connector can be configured and connected to different connectors under different graphics processor topology structures, thereby meeting the topology requirements of different graphics connectors and simplifying the operating structure of the circuit board of the graphics processor.
  • the connectors in the connector group are connected through a connector circuit board, wherein the fifth connector and the sixth connector are deployed on the same side of the connector circuit board, the fifth connector and the sixth connector are connected through circuit board routing, the fifth connector and the sixth connector are both board-to-board connectors, and the spacing between the fifth connector and the sixth connector is the target spacing.
  • the connector circuit board can realize the connection between the third connector and the second connector, and the third connector and the fourth connector by plugging and unplugging, or the connecting circuit board can also be configured to slide on the circuit board of the graphics processor, and when in use, the connection between the third connector and the second connector can be switched to the connection between the third connector and the fourth connector by sliding.
  • This solution is not limited to this.
  • FIG. 2 is a schematic diagram of a bridge according to an embodiment of the present application.
  • the fifth connector and the sixth connector are two board-to-board connectors, and the fifth connector and the sixth connector are welded on a PCB and connected via a ⁇ 16 PCIe signal.
  • the spacing between the fifth connector and the sixth connector is equal to the spacing between the second connector and the third connector.
  • the bridge includes but is not limited to a bridge that can use a 4C connector (SFF-TA-1002 (an edge connector system)), and this solution does not limit this.
  • SFF-TA-1002 an edge connector system
  • the fifth connector and the sixth connector are arranged on the connecting circuit board, and the spacing between the fifth connector and the sixth connector is the target spacing, and the fifth connector and the sixth connector are both arranged as board-to-board connectors, so that the connection between the second connector and the third connector can be realized through the connecting circuit board by plugging and unplugging, and the connection between the third connector and the fourth connector can be realized through the connecting circuit board, and the topology structure of the image processor can be changed by plugging and unplugging the same connecting circuit board on different connectors.
  • connection structure between the second connector and the third connector is used to form a balanced topology structure, or a common topology structure, of the graphics processor.
  • both the balanced topology and the ordinary topology are connected through the second connector and the third connector, the difference being that in the balanced topology the first connector and the fourth connector are respectively connected to different central processing units, while in the ordinary topology the first connector and the fourth connector are connected to the same central processing unit.
  • the second connector is connected to the third connector, and the first connector and the fourth connector are respectively connected to different central processors to form a balanced topology structure.
  • connection between the first connector and the central processing unit can be
  • the connection between the fourth connector and the central processing unit can be a cable connection.
  • Connecting wires can be configured at the ports of the first connector and the fourth connector on the circuit board. By connecting the other end of the connecting wire to the corresponding processor, the function of the balanced topology structure can be achieved.
  • FIG3 is a schematic diagram of an optional balanced topology structure according to an embodiment of the present application.
  • two PCIe switch chips on the circuit board constitute a switching chipset, PCIe switch0 (first switching chip) and PCIe switch1 (second switching chip), four connectors constitute a connector group C0 connector (first connector), C1 (second connector), C2 (third connector), C3 connector (fourth connector), 10 ⁇ 16 PCIe slots constitute a device slot group, wherein the PCIe switch chip should support at least 96 lanes PCIe signals, wherein C1, C2, and C3 are arranged in a straight line and in the same direction, and the spacing between C1 and C2 is equal to the spacing between C2 and C3.
  • PCIe switch 0 is connected to slots 0 to 3 via ⁇ 16 PCIe signals; PCIe switch 0 is connected to C0 and C2 via ⁇ 16 PCIe signals; PCIe switch 1 is connected to slots 6 to 9 via ⁇ 16 PCIe signals; PCIe switch 1 is connected to C3 via ⁇ 16 PCIe signals; C1 is connected to slot 4 via ⁇ 16 PCIe signals.
  • the C0 connector (first connector) on the GPU board is connected to CPU0 via a cable
  • the C3 connector (fourth connector) is connected to CPU1 via a cable
  • the two connectors (fifth connector and sixth connector) on the bridge (connector circuit board) correspond to the GPU board C1 (second connector) and C2 (third connector) connectors respectively.
  • the connector circuit board includes two board-to-board connectors, which are matched with C0 to C3 of the aforementioned GPU board and can be connected to each other; the two board-to-board connectors are soldered on a PCB (Printed Circuit Board) and are connected through ⁇ 16 PCIe signals; the spacing between the two board-to-board connectors is equal to the spacing between C1 and C2 on the aforementioned GPU board; optionally, TX and RX on the bridge PCB can be reversible to facilitate GPU board wiring.
  • PCB Print Circuit Board
  • the second connector is connected to the third connector, and the first connector and the fourth connector are connected to the same central processor to form a common topology structure.
  • FIG4 is a schematic diagram of an optional common topology structure according to an embodiment of the present application.
  • two PCIe switch chips on the circuit board constitute a switching chipset
  • PCIe switch0 first switching chip
  • PCIe switch1 second switching chip
  • four connectors constitute a connector group C0 connector (first connector)
  • C1 second connector
  • C2 third connector
  • C3 connector fourth connector
  • 10 ⁇ 16 PCIe slots constitute a device slot group
  • the PCIe switch chip should support at least 96 lane PCIe signals, wherein C1, C2, and C3 are arranged in a straight line and in the same direction, and the spacing between C1 and C2 is equal to the spacing between C2 and C3.
  • PCIe switch 0 is connected to slots 0 to Slot 3 via ⁇ 16 PCIe signals; PCIe switch 0 is connected to C0, C2 via ⁇ 16 PCIe signals; PCIe switch 1 is connected to slots Slot 6 to Slot 9 via ⁇ 16 PCIe signals; PCIe switch 1 is connected to C3 via ⁇ 16 PCIe signals; C1 is connected to slot 4 via ⁇ 16 PCIe signals.
  • the C0 connector on the GPU board is connected to CPU0 via a cable
  • the C3 connector is not plugged into a cable
  • the two connectors on the bridge correspond to the C2 and C3 connectors on the GPU board, respectively.
  • the connector circuit board includes two board-to-board connectors, and the board-to-board connection
  • the connector is matched with C0 to C3 of the aforementioned GPU board and can be connected to each other; two of the board-to-board connectors are soldered on a PCB and connected through ⁇ 16 PCIe signals; the spacing between the two board-to-board connectors is equal to the spacing between C1 and C2 on the aforementioned GPU board; optionally, TX and RX on the bridge PCB can be reversible to facilitate GPU board wiring.
  • connection structure between the third connector and the fourth connector is used to form a series topology structure of the graphics processor.
  • the third connector is connected to the fourth connector, and the first connector is connected to the central processor to form a series topology structure.
  • FIG5 is a schematic diagram of an optional series topology structure according to an embodiment of the present application.
  • two PCIe switch chips on the circuit board constitute a switching chipset, PCIe switch0 (first switching chip) and PCIe switch1 (second switching chip), four connectors constitute a connector group C0 connector (first connector), C1 (second connector), C2 (third connector), C3 connector (fourth connector), 10 ⁇ 16 PCIe slots constitute a device slot group, wherein the PCIe switch chip should support at least 96 lanes PCIe signals, wherein C1, C2, C3 are arranged in a straight line and in the same direction, and the spacing between C1 and C2 is equal to the spacing between C2 and C3.
  • PCIe switch 0 is connected to slots 0 to 3 via ⁇ 16 PCIe signals; PCIe switch 0 is connected to C0 and C2 via ⁇ 16 PCIe signals; PCIe switch 1 is connected to slots 6 to 9 via ⁇ 16 PCIe signals; PCIe switch 1 is connected to C3 via ⁇ 16 PCIe signals; C1 is connected to slot 4 via ⁇ 16 PCIe signals.
  • the design is a common topology, the C0 connector on the GPU board is connected to CPU0 via a cable, the C3 connector is connected to CPU0 via a cable, and the two connectors on the bridge correspond to the C1 and C2 connectors on the GPU board.
  • the connector circuit board includes two board-to-board connectors, which are matched with C0 to C3 of the aforementioned GPU board and can be connected to each other; the two board-to-board connectors are soldered on a PCB and connected through ⁇ 16 PCIe signals; the spacing between the two board-to-board connectors is equal to the spacing between C1 and C2 on the aforementioned GPU board; optionally, TX and RX on the bridge PCB can be reversible to facilitate GPU board wiring.
  • M is equal to N-1, and P is equal to 1.
  • N is equal to 5.
  • a server system comprising: a central processing unit group, a circuit board of a graphics processing unit and a graphics processing unit group, wherein the circuit board of the graphics processing unit is connected between the central processing unit group and the graphics processing unit group,
  • a connector group, a switching chipset and a device slot group are deployed on the circuit board of the graphics processor, wherein the connector group includes: a first connector, a second connector, a third connector and a fourth connector, the switching chipset includes: a first switching chip and a second switching chip, and the device slot group includes: a first slot set and a second slot set, the first slot set includes M+P device slots, the second slot set includes N device slots, and N is equal to M+P;
  • the first switching chip is connected to the first connector, the third connector, and the M device slots in the first slot set through circuit board wiring
  • the second switching chip is connected to the fourth connector and the N device slots in the second slot set through circuit board wiring
  • the second connector is connected to the first slot through circuit board wiring.
  • the P device slots in the set are connected;
  • the first connector is configured to connect to a central processor in a central processor group;
  • the second connector is configured to connect to a third connector;
  • the third connector is configured to connect to the second connector or a fourth connector;
  • the fourth connector is configured to connect to the third connector or a central processor in the central processor group;
  • a device slot group is configured to connect graphics processors in a graphics processor group.
  • a circuit board for connecting a graphics processor and a central processing unit is provided.
  • a connector group, a switching chipset and a device slot are deployed on the circuit board.
  • the connector group includes a first connector, a second connector, a third connector and a fourth connector.
  • the switching chipset includes a first switching chip and a second switching chip.
  • the device slot group includes a first slot set and a second slot set. Some components on the circuit board are connected through circuit board routing.
  • the first switching chip is respectively connected to the first connector, the third connector and M device slots in the first slot set through circuit board routing, the second switching chip is respectively connected to the fourth connector and N device slots in the second slot set through circuit board routing, and the second connector is connected to P device slots in the first slot set through circuit board routing.
  • the first connector is configured to be used for connecting to the central processing unit
  • the second connector is configured to be used for connecting to the third connector
  • the third connector is configured to be used for connecting to the second connector or the fourth connector
  • the fourth connector is configured to be used for connecting to the third connector or the central processing unit.
  • FIG6 is a schematic diagram of an optional server system according to an embodiment of the present application.
  • the server system includes: a central processing unit group, a circuit board of a graphics processing unit and a graphics processing unit group, wherein the circuit board of the graphics processing unit is connected between the central processing unit group and the graphics processing unit group, and a connector group, a switching chipset and a device slot group are deployed on the circuit board of the graphics processing unit, wherein the connector group includes: a first connector, a second connector, a third connector and a fourth connector, the switching chipset includes: a first switching chip and a second switching chip, and the device slot group includes: a first slot set and a second slot set, the first slot set includes M+P device slots, and the second slot set includes N device slots, where N is equal to M+P; A switching chip is connected to the first connector, the third connector, and M device slots in the first slot set respectively through circuit board routing, a second switching chip is connected to the fourth connector and N device slots in the second
  • the port on the connector group side of the circuit board is configured to connect to a central processing unit
  • the port on the device slot group side of the circuit board is configured to connect to a graphics processor
  • the device slot group includes a plurality of device slots for connecting to the graphics processor, thereby achieving connection between the central processing unit and multiple graphics processors.
  • connection relationship among the second connector, the third connector and the fourth connector may be changed to realize different connection topology requirements of the graphics processor.
  • the second connector, the third connector and the fourth connector can be arranged in sequence in a straight line on the circuit board, and the second connector, the third connector and the fourth connector can be connected by a cable or by a connecting device.
  • the second connector, the third connector and the fourth connector can adopt a connector with an external connection interface (such as a board-to-board connector).
  • the connecting device can be a connecting device with two connection interfaces, and the connection interface on the connecting device is configured to be connected to the external connection interface on the connector.
  • the connecting device can be a connecting cable including two connecting heads, the first connecting head of the connecting cable is connected to the third connector, and the second connecting head on the connecting cable is configured to be connected to the second connector or the fourth connector.
  • the connection topology of the graphics processor is switched;
  • the connector may also be a connection board including two connection heads, in which case the second connector, the third connector and the fourth connector are arranged in a straight line, and the spacing between the second connector, the third connector and the fourth connector is equal, and the spacing between the two connection joints on the connection board is equal to the spacing between the third connector and the second connector or the spacing between the third connector and the connector.
  • connection topology of the graphics processor can be changed by changing the connection relationship between the connection board and the second connector, the third connector and the fourth connector, or the connection board can be configured to be slidable on the circuit board, and the connection topology of the graphics processor can be changed by sliding the connection board between the second connector, the third connector and the fourth connector, thereby changing the connection relationship between the connection board and the second connector, the third connector and the fourth connector.
  • the above-mentioned graphics processing circuit board supports a GPU board with 8 ⁇ 16 GPUs and 2 ⁇ 16 network cards, and supports three topologies of balance, cascade, and common.
  • the above-mentioned switching chip is 2 96 lane PCIe switch chips.
  • the second connector is connected to the third connector
  • the first connector is connected to the first central processor in the central processor group
  • the fourth connector is connected to the second central processor in the central processor group to form a balanced topology structure of the graphics processor group.
  • the C0 (first connector) connector on the GPU board is connected to CPU0 through a cable
  • the C3 (fourth connector) connector is connected to CPU1 through a cable
  • the two connectors on the bridge correspond to the C1 (second connector) and C2 (third connector) connectors of the GPU board respectively.
  • the second connector is connected to the third connector, and the first connector and the fourth connector are both connected to the third central processor in the central processor group to form a common topology structure of the graphics processor group.
  • the C0 connector (first connector) on the GPU board is connected to CPU0 through a cable
  • the C3 connector (fourth connector) is not plugged with a cable
  • the two connectors on the bridge correspond to the GPU board C2 (third connector) and C3 (fourth connector) connectors respectively.
  • the third connector is connected to the fourth connector, and the first connector is connected to The fourth CPU in the CPU group forms a serial topology structure of the GPU group.
  • the C0 connector (first connector) on the GPU board is connected to CPU0 through a cable
  • the C3 connector (fourth connector) is connected to CPU0 through a cable
  • the two connectors on the bridge correspond to the GPU board C1 (second connector) and C2 (third connector) connectors respectively.
  • the server system further includes: a connector circuit board, wherein:
  • the second connector, the third connector and the fourth connector are all board-to-board connectors, the second connector, the third connector and the fourth connector are arranged in a straight line and in the same direction, and the spacing between the second connector and the third connector and the spacing between the third connector and the fourth connector are both target spacings;
  • the connectors in the connector group are connected through a connector circuit board, wherein a fifth connector and a sixth connector are deployed on the same side of the connector circuit board, the fifth connector and the sixth connector are connected through circuit board routing, the fifth connector and the sixth connector are both board-to-board connectors, and the spacing between the fifth connector and the sixth connector is the target spacing.
  • the connector circuit board can realize the connection between the third connector and the second connector, and the third connector and the fourth connector by plugging and unplugging, or the connecting circuit board can also be configured to slide on the circuit board of the graphics processor, and when in use, the connection between the third connector and the second connector can be switched to the connection between the third connector and the fourth connector by sliding.
  • This solution is not limited to this.
  • the bridge includes but is not limited to a bridge that can use a 4C connector (SFF-TA-1002), and this solution does not limit this.
  • FIG7 is a detailed diagram of an optional circuit board according to the present application. As shown in FIG7 , the present application embodiment designs a GPU board that supports 8 ⁇ 16 GPUs and 2 ⁇ 16 network cards, and supports three topological forms of balance, cascade, and common.
  • the GPU board is designed with 2 96 lane PCIe switch chips, which are respectively recorded as PCIe switch 0 (first switching chip) and PCIe switch 1 (second switching chip); in the design scheme, the GPU board is designed with 4 board-to-board connectors that support ⁇ 16 PCIe signals, which are respectively recorded as C0 (first connector) to C3; wherein C1 (second connector), C2 (third connector), and C3 (fourth connector) are arranged in the same direction and are in a straight line, C2 is in the middle, and C1 and C3 are on both sides; optionally, the board-to-board connector can be vertical or right angle; optionally, the board-to-board connector can be an MCIO connector or a gen-z connector; in the design scheme, the GPU board is designed with 10 ⁇ 16 PCIe slots, which are respectively recorded as Slot 0 to Slot 9; Optionally, a double-width AIC (Add-In Card, a product form of a solid-state drive) space is reserved
  • This example also designs a bridge, including two board-to-board connectors, which are matched with C0 to C3 of the aforementioned GPU board and can be connected to each other; the two board-to-board connectors are welded on a PCB and connected through ⁇ 16 PCIe signals; the spacing between the two board-to-board connectors is equal to the spacing between C1 and C2 on the aforementioned GPU board; optionally, TX and RX on the bridge PCB can be reversible, To facilitate GPU board wiring.
  • the C0 connector on the GPU board is connected to CPU0 through a cable
  • the C3 connector is connected to CPU1 through a cable
  • the two connectors on the bridge correspond to the C1 and C2 connectors on the GPU board.
  • the design is a cascade topology
  • the C0 connector on the GPU board is connected to CPU0 through a cable
  • the C3 connector is not plugged with a cable
  • the two connectors on the bridge correspond to the C2 and C3 connectors on the GPU board.
  • the C0 connector on the GPU board is connected to CPU0 through a cable
  • the C3 connector is connected to CPU0 through a cable
  • the two connectors on the bridge correspond to the C1 and C2 connectors on the GPU board.
  • the newly added bridge design increases connection reliability and reduces the number of steps when changing topologies.
  • the board-to-board connectors are designed side by side and matched with a bridge with a matching connector, which effectively simplifies the board design and can easily support switching between different topologies.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Multi Processors (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

本申请提供一种图形处理器的线路板，其上部署了第一连接器，第二连接器，第三连接器和第四连接器，第一交换芯片和第二交换芯片，第一插槽集合，包括M+P个插槽，第二插槽集合，包括N个插槽，N等于M+P；第一交换芯片与第一连接器、第三连接器、第一插槽集合M个插槽连接，第二交换芯片与第四连接器、第二插槽集合N个插槽连接，第二连接器与第一插槽集合P个插槽连接；第一连接器，连接中央处理器；第二连接器，连接第三连接器；第三连接器，连接第二连接器，或，第四连接器。通过本申请，解决服务器上多个图形处理器的连接拓扑结构的切换操作复杂度较高问题，达到降低服务器上多个图形处理器的连接拓扑结构的切换操作的复杂度的效果。

Description

图形处理器的线路板及服务器系统
相关申请的交叉引用
本申请要求于2023年12月01日提交中国专利局，申请号为202311634161.1，申请名称为“图形处理器的线路板及服务器系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及计算机领域，具体而言，涉及一种图形处理器的线路板及一种服务器系统。
背景技术
近年来，GPU(Graphics Processing Unit，图形处理器)因其高度的并行计算能力被广泛应用于计算机游戏、影视特效、科学计算、机器学习等领域。对于服务器而言，出于对算法效率的考虑，面对复杂的计算需求需要使用多个GPU，在不同的应用场景下多个GPU需要采用不同的机器拓扑结构。因此服务器上的GPU连接拓扑结构的切换非常频繁，现阶段，服务器上的GPU之间通过复杂的线缆连接，在不同的拓扑结构切换时，需要重新插接线缆，整个操作过程涉及到多根线缆，且线缆长度不同，需要机型不同型号的线缆切换，操作方案较为复杂，并且复杂的连接操作也易造成线缆损坏以及GPU板接口损坏。
发明内容
本申请实施例提供了一种图形处理器的线路板及一种服务器系统，以至少解决相关技术中更换机器拓扑形式操作复杂易损坏线缆及接口的问题。
根据本申请的一个实施例，提供了一种图形处理器的线路板，线路板上部署了连接器组，交换芯片组和设备插槽组，连接器组包括：第一连接器，第二连接器，第三连接器和第四连接器，交换芯片组包括：第一交换芯片和第二交换芯片，设备插槽组包括：第一插槽集合和第二插槽集合，第一插槽集合包括M+P个设备插槽，第二插槽集合包括N个设备插槽，N等于M+P；第一交换芯片通过线路板走线分别与第一连接器、第三连接器、第一插槽集合中的M个设备插槽连接，第二交换芯片通过线路板走线分别与第四连接器、第二插槽集合中的N个设备插槽连接，第二连接器通过线路板走线与第一插槽集合中的P个设备插槽连接；第一连接器，被配置为连接中央处理器；第二连接器，被配置为连接第三连接器；第三连接器，被配置为连接第二连接器，或者，第四连接器；第四连接器，被配置为连接第三连接器，或者，中央处理器；设备插槽组，被配置为连接图形处理器。
可选的，第二连接器，第三连接器和第四连接器均为板对板连接器，第二连接器，第三连接器和第四连接器排列承一条直线，且朝向一致，第二连接器和第三连接器之间的间距与第三连接器和第四连接器之间的间距均为目标间距。
可选的，连接器组中的连接器通过连接器线路板连接，其中，连接器线路 板上在同侧部署了第五连接器和第六连接器，第五连接器和第六连接器通过线路板走线连接，第五连接器和第六连接器均为板对板连接器，第五连接器和第六连接器之间的间距为目标间距。
可选的，连接器线路板被设置为在图形处理器的线路板上滑动，通过滑动的方式实现第三连接器和第二连接器之间的连接与第三连接器和第四连接器之间的连接的切换。
可选的，连接器线路板被设置为通过插拔方式实现第三连接器和第二连接器、第三连接器和第四连接器之间的连接。
可选的，连接器组中的连接器通过包括两个连接头的连接线缆连接，其中，连接线缆的第一连接头与第三连接器连接，连接线缆的第二连接头被配置为与第二连接器连接或者第四连接器连接。
可选的，第二连接器与第三连接器之间连接的结构用于形成图形处理器的平衡拓扑结构，或者，普通拓扑结构。
可选的，第二连接器与第三连接器连接，第一连接器和第四连接器分别连接不同的中央处理器形成平衡拓扑结构。
可选的，第二连接器与第三连接器连接，第一连接器和第四连接器连接相同的中央处理器形成普通拓扑结构。
可选的，第三连接器与第四连接器之间连接的结构用于形成图形处理器的串联拓扑结构。
可选的，第三连接器与第四连接器连接，第一连接器连接中央处理器形成串联拓扑结构。
可选的，M等于N-1，P等于1。
可选的，N等于5。
根据本申请的另一个实施例，提供了一种服务器系统，包括：中央处理器组，图形处理器的线路板和图形处理器组，其中，图形处理器的线路板连接在中央处理器组和图形处理器组之间，
图形处理器的线路板上部署了连接器组，交换芯片组和设备插槽组，其中，连接器组包括：第一连接器，第二连接器，第三连接器和第四连接器，交换芯片组包括：第一交换芯片和第二交换芯片，设备插槽组包括：第一插槽集合和第二插槽集合，第一插槽集合包括M+P个设备插槽，第二插槽集合包括N个设备插槽，N等于M+P；
第一交换芯片通过线路板走线分别与第一连接器、第三连接器、第一插槽集合中的M个设备插槽连接，第二交换芯片通过线路板走线分别与第四连接器、第二插槽集合中的N个设备插槽连接，第二连接器通过线路板走线与第一插槽集合中的P个设备插槽连接；
第一连接器，被配置为连接中央处理器组中的中央处理器；第二连接器，被配置为连接第三连接器；第三连接器，被配置为连接第二连接器，或者，第四连接器；第四连接器，被配置为连接第三连接器，或者，中央处理器组中的中央处理器；
设备插槽组，被配置为连接图形处理器组中的图形处理器。
可选的，第二连接器与第三连接器连接，第一连接器连接中央处理器组中的第一中央处理器，第四连接器连接中央处理器组中的第二中央处理器形成图形处理器组的平衡拓扑结构。
可选的，第二连接器与第三连接器连接，第一连接器和第四连接器均连接中央处理器组中的第三中央处理器形成图形处理器组的普通拓扑结构。
可选的，第三连接器与第四连接器连接，第一连接器连接中央处理器组中的第四中央处理器形成图形处理器组的串联拓扑结构。
可选的，服务器系统，还包括：连接器线路板，其中，
第二连接器，第三连接器和第四连接器均为板对板连接器，第二连接器，第三连接器和第四连接器排列承一条直线，且朝向一致，第二连接器和第三连接器之间的间距与第三连接器和第四连接器之间的间距均为目标间距；
连接器组中的连接器通过连接器线路板连接，其中，连接器线路板上在同侧部署了第五连接器和第六连接器，第五连接器和第六连接器通过线路板走线连接，第五连接器和第六连接器均为板对板连接器，第五连接器和第六连接器之间的间距为目标间距。
可选的，连接器线路板被设置为在图形处理器的线路板上滑动，通过滑动的方式实现第三连接器和第二连接器之间的连接与第三连接器和第四连接器之间的连接的切换。
可选的，连接器线路板被设置为通过插拔方式实现第三连接器和第二连接器、第三连接器和第四连接器之间的连接。
通过本申请，设置用于连接图形处理器和中央处理器的线路板，在线路板上通过部署连接器组、交换芯片组和设备插槽，连接器组包括第一连接器、第二连接器、第三连接器和第四连接器、交换芯片组包括第一交换芯片和第二交换芯片，设备插槽组包括第一插槽集合和第二插槽集合，在线路板上部分元件通过线路板走线连接，通过将第一交换芯片通过线路板走线分别和第一连接器、第三连接器和第一插槽集合中M个设备插槽连接，将第二交换芯片通过线路板走线分别与第四连接器和第二插槽集合中的N各设备插槽连接，将第二连接器通过线路板走线与第一插槽集合中的P各设备插槽连接，进而通过将第一连接器配置为用于连接中央处理器，第二连接器配置为用于连接第三连接器，第三连接器配置为用于连接第二连接器或者第四连接器，第四连接器配置为用于连接第三连接器或者中央处理器，从而实现在满足图形处理器的连接拓扑结构需求的前提下简化图形处理器的线路板的结构，可以解决服务器上多个图形处理器的连接拓扑结构的切换操作复杂度较高问题，达到降低服务器上多个图形处理器的连接拓扑结构的切换操作的复杂度的效果。
附图说明
图1是根据本申请实施例的一种图形处理器的线路板的示意图；
图2是根据本申请实施例的一种桥接器示意图；
图3是根据本申请实施例的一种可选的平衡拓扑结构示意图；
图4是根据本申请实施例的一种可选的普通拓扑结构示意图；
图5是根据本申请实施例的一种可选的串联拓扑结构示意图；
图6是根据本申请实施例的一种可选的服务器系统示意图；
图7是根据本申请的一种可选的线路板详图。
具体实施方式
下文中将参考附图并结合实施例来详细说明本申请的实施例。
需要说明的是，本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
在本申请实施例中提供了一种图形处理器的线路板，图1是根据本申请实施例的一种图形处理器的线路板的示意图，如图1所示，该线路板上部署了连接器组，交换芯片组和设备插槽组，其中，连接器组包括：第一连接器，第二连接器，第三连接器和第四连接器，交换芯片组包括：第一交换芯片和第二交换芯片，设备插槽组包括：第一插槽集合和第二插槽集合，第一插槽集合包括M+P个设备插槽，第二插槽集合包括N个设备插槽，N等于M+P；
第一交换芯片通过线路板走线分别与第一连接器、第三连接器、第一插槽集合中的M个设备插槽连接，第二交换芯片通过线路板走线分别与第四连接器、第二插槽集合中的N个设备插槽连接，第二连接器通过线路板走线与第一插槽集合中的P个设备插槽连接；
第一连接器，被配置为连接中央处理器；第二连接器，被配置为连接第三连接器；第三连接器，被配置为连接第二连接器，或者，第四连接器；第四连接器，被配置为连接第三连接器，或者，中央处理器；
设备插槽组，被配置为连接图形处理器。
通过上述设计，设置用于连接图形处理器和中央处理器的线路板，在线路板上通过部署连接器组、交换芯片组和设备插槽，连接器组包括第一连接器、第二连接器、第三连接器和第四连接器、交换芯片组包括第一交换芯片和第二交换芯片，设备插槽组包括第一插槽集合和第二插槽集合，在线路板上部分元件通过线路板走线连接，通过将第一交换芯片通过线路板走线分别和第一连接器、第三连接器和第一插槽集合中M个设备插槽连接，将第二交换芯片通过线路板走线分别与第四连接器和第二插槽集合中的N各设备插槽连接，将第二连接器通过线路板走线与第一插槽集合中的P各设备插槽连接，进而通过将第一连接器配置为用于连接中央处理器，第二连接器配置为用于连接第三连接器，第三连接器配置为用于连接第二连接器或者第四连接器，第四连接器配置为用于连接第三连接器或者中央处理器，从而实现在满足图形处理器的连接拓扑结构需求的前提下简化图形处理器的线路板的结构，可以解决服务器上多个图形处理器的连接拓扑结构的切换操作复杂度较高问题，达到降低服务器上多个图形处理器的连接拓扑结构的切换操作的复杂度的效果。
可选地，在本申请实施例中，线路板的连接器组侧的端口被配置为连接中 央处理器，线路板的设备插槽组侧的端口被配置为连接图形处理器，并且设备插槽组包括多个用于连接图形处理器设备插槽，从而实现中央处理器和多个图形处理器之间的连接。
可选地，在本申请实施例中，为了实现图形处理器不同的连接拓扑结构，可以通过改变第二连接器、第三连接器和第四连接器之间的连接关系，从而实现图形处理器的不同的连接拓扑需求。
可选地，在本申请实施例中，第二连接器、第三连接器和第四连接器可以在线路板上按照顺序依次排列成一条直线，第二连接器、第三连接器和第四连接器之间可以通过线缆连接或者还可以通过连接器具连接，比如，第二连接器、第三连接器和第四连接器可以采用具有对外连接接口的连接器(比如板对板连接器)，此时连接器具可以是设置了两个连接接口的连接器具，连接器具上的连接接口被配置为和连接器上的对外连接接口连接，比如，连接器具可以是包括两个连接头的连接线缆，连接线缆的第一连接头与第三连接器连接，连接线缆上的第二连接头被配置为与第二连接器或者和第四连接器连接，通过切换第二连接头和第二连接器或者第四连接器的连接关系，从而切换图形处理器的连接拓扑；连接器还可以是包括两个连接头的连接板，此时第二连接器、第三连接器和第四连接器之间排列成一条直线，并且第二连接器、第三连接器和第四连接器之间的间距相等，连接板上的两个连接接头之间间距和第三连接器与第二连接器之间的间距或者第三连接器与连接器之间的间距相等，在使用中，可以通过改变连接板与第二连接器、第三连接器和第四连接器之间的连接关系从而改变图形处理器的连接拓扑结构，或者，连接板可以被配置为在线路板上可滑动，通过将连接板在第二连接器、第三连接器和第四连接器之间滑动，从而通过改变连接板对第二连接器、第三连接器和第四连接器的连接关系的方式改变图形处理器的连接拓扑结构。
可选地，在本申请实施例中，上述图形处理的线路板支持8张×16 GPU和2张×16网卡的GPU板，并支持balance(平衡)，cascade(串联)，common(普通)三种拓扑形式，上述交换芯片2颗96 lane PCIe(Peripheral Component Interconnect Express，一种高速串行计算机扩展总线标准)switch(96通道PCIe交换器)芯片。
作为一种可选的实施例，第二连接器，第三连接器和第四连接器均为板对板连接器，第二连接器，第三连接器和第四连接器排列承一条直线，且朝向一致，第二连接器和第三连接器之间的间距与第三连接器和第四连接器之间的间距均为目标间距。
可选地，在本申请实施例中，板对板连接器可以是vertical(垂直式连接器)或者right angle(直角式连接器)。
可选地，在本申请实施例中，板对板连接器可以是MCIO(Mini Cool Edge IO)连接器或者gen-z连接器。
可选地，在本申请实施例中，第三连接器与第二连接器以及第四连接器之间的间距相等，且朝向一致，进而将第三连接器和第二连接器连接，以及将第 三连接器和第四连接器连接时所使用的连接器具的规格统一，因此可以配置同一个连接器具，在不同的图形处理器拓扑结构下，将连接器具连接在不同的连接器上，从而满足不同的图形连接器的拓扑需求，简化了图形处理器的线路板的操作结构。
作为一种可选的实施例，连接器组中的连接器通过连接器线路板连接，其中，连接器线路板上在同侧部署了第五连接器和第六连接器，第五连接器和第六连接器通过线路板走线连接，第五连接器和第六连接器均为板对板连接器，第五连接器和第六连接器之间的间距为目标间距。
可选地，在本申请实施例中，连接器线路板可以通过插拔的方式实现第三连接器和第二连接器、第三连接器和第四连接器之间的连接，或者连接线路板还可以被设置为在图形处理器的线路板上滑动，使用时可以通过滑动的方式实现将第三连接器和第二连接器之间的连接切换为第三连接器和第四连接器之间的连接，本方案对此不作限定。
可选的，在本申请实施例中，图2是根据本申请实施例的一种桥接器示意图，如图2所示，第五连接器和第六连接器为两个板对板连接器，第五连接器和第六连接器焊接在一块PCB上，之间通过×16 PCIe信号连接。第五连接器和第六连接器的间距等于第二连接器和第三连接器之间的间距。对于桥接器PCB上数据传输(Transmit，TX)和接收(Receive，RX)可以做成可以通过改变连接的方式来改变数据传输的方向的设计(reversal)以方便GPU板布线。
可选的，在本申请实施例中，桥接器包括但不限于可采用4C连接器(SFF-TA-1002(一种边缘连接器系统))的桥接器，本方案对此不做限定。
通过上述内容，连接线路板上设置有第五连接器和第六连接器，并且第五连接器和第六连接器之间的间距为目标间距，并且设置第五连接器和第六连接器均为板对板连接器，从而能够通过插拔的方式通过连接线路板实现第二连接器和第三连接器之间的连接，以及通过连接线路板实现对第三连接器和第四连接器之间的连接，实现通过同一个连接线路板在不同连接器上的插拔实现对图像处理器的拓扑结构的更改。
作为一种可选的实施例，第二连接器与第三连接器之间连接的结构用于形成图形处理器的平衡拓扑结构，或者，普通拓扑结构。
可选的，在本申请实施例中，平衡拓扑和普通拓扑结构中均通过第二连接器和第三连接器之间连接的方式，区别在于平衡拓扑结构中第一连接器和第四连接器分别连接在不同的中央处理器上，而普通拓扑结构中第一连接器和第四连接器连接在同一个中央处理器上。
通过上述内容，通过将第二连接器和第四连接器之间连接，可以实现平衡拓扑结构和普通拓扑结构的功能，从而实际使用中对于这两种拓扑结构可以有效的简化外部的连线数量，从而简化两种拓扑结构的更改操作内容。
作为一种可选的实施例，第二连接器与第三连接器连接，第一连接器和第四连接器分别连接不同的中央处理器形成平衡拓扑结构。
可选地，在本申请实施例中，第一连接器与中央处理器之间的连接方式可 以是线缆连接，第四连接器与中央处理器之间的连接方式可以是线缆连接，在线路板上第一连接器和第四连接器的端口处可以配置有连接线，通过将连接线的另一端连接到对应的处理器上，从而实现平衡拓扑结构的功能。
图3是根据本申请实施例的一种可选的平衡拓扑结构示意图，如图3所示，线路板上两颗PCIe switch芯片构成交换芯片组，PCIe switch0(第一交换芯片)和PCIe switch1(第二交换芯片)，四个连接器构成连接器组C0连接器(第一连接器)、C1(第二连接器)、C2(第三连接器)、C3连接器(第四连接器)，10个×16 PCIe插槽构成设备插槽组，其中，PCIe switch芯片应当至少支持96 lane PCIe信号，其中C1,C2,C3排列承一条至直线，且朝向一致，C1与C2的间距等于C2与C3的间距。其中10个×16 PCIe插槽依次记为Slot(插槽)0至Slot 9。其中PCIe switch 0与Slot 0至Slot 3插槽之间通过×16PCIe信号连接；其中PCIe switch 0与C0,C2之间通过×16 PCIe信号连接；其中PCIe switch 1与Slot 6至Slot9插槽之间通过×16 PCIe信号连接；其中PCIe switch 1与C3之间通过×16 PCIe信号连接；其中C1与slot 4之间通过×16 PCIe信号连接。当设计为balance拓扑时，GPU板上C0连接器(第一连接器)通过线缆连接到CPU0，C3连接器(第四连接器)通过线缆连接到CPU1，桥接器(连接器线路板)上2个连接器(第五连接器和第六连接器)分别对应GPU板C1(第二连接器)和C2(第三连接器)连接器连接。在本申请实施例中，连接器线路板包括2个板对板连接器，板对板连接器与前述GPU板的C0至C3是配套关系，可以相互连接；其中2个板对板连接器焊接在一块PCB(Printed Circuit Board，印刷电路板)上，之间通过×16 PCIe信号连接；其中2个板对板连接器的间距等于前述GPU板上C1与C2的间距；可选的，桥接器PCB上TX和RX可以做reversal，以方便GPU板布线。
作为一种可选的实施例，第二连接器与第三连接器连接，第一连接器和第四连接器连接相同的中央处理器形成普通拓扑结构。
图4是根据本申请实施例的一种可选的普通拓扑结构示意图，如图4所示，线路板上两颗PCIe switch芯片构成交换芯片组，PCIe switch0(第一交换芯片)和PCIe switch1(第二交换芯片)，四个连接器构成连接器组C0连接器(第一连接器)、C1(第二连接器)、C2(第三连接器)、C3连接器(第四连接器)，10个×16 PCIe插槽构成设备插槽组，其中，PCIe switch芯片应当至少支持96 lane PCIe信号，其中C1,C2,C3排列承一条至直线，且朝向一致，C1与C2的间距等于C2与C3的间距。其中10个×16 PCIe插槽依次记为Slot 0至Slot 9。其中PCIe switch 0与Slot 0至Slot 3插槽之间通过×16 PCIe信号连接；其中PCIe switch 0与C0,C2之间通过×16 PCIe信号连接；其中PCIe switch 1与Slot 6至Slot9插槽之间通过×16 PCIe信号连接；其中PCIe switch 1与C3之间通过×16 PCIe信号连接；其中C1与slot 4之间通过×16PCIe信号连接。当设计为cascade拓扑时，GPU板上C0连接器通过线缆连接到CPU0，C3连接器不插接线缆，桥接器上2个连接器分别对应GPU板C2和C3连接器连接。在本申请实施例中，连接器线路板包括2个板对板连接器，板对板连 接器与前述GPU板的C0至C3是配套关系，可以相互连接；其中2个板对板连接器焊接在一块PCB上，之间通过×16 PCIe信号连接；其中2个板对板连接器的间距等于前述GPU板上C1与C2的间距；可选的，桥接器PCB上TX和RX可以做reversal，以方便GPU板布线。
作为一种可选的实施例，第三连接器与第四连接器之间连接的结构用于形成图形处理器的串联拓扑结构。
作为一种可选的实施例，第三连接器与第四连接器连接，第一连接器连接中央处理器形成串联拓扑结构。
图5是根据本申请实施例的一种可选的串联拓扑结构示意图，如图5所示，线路板上两颗PCIe switch芯片构成交换芯片组，PCIe switch0(第一交换芯片)和PCIe switch1(第二交换芯片)，四个连接器构成连接器组C0连接器(第一连接器)、C1(第二连接器)、C2(第三连接器)、C3连接器(第四连接器)，10个×16 PCIe插槽构成设备插槽组，其中，PCIe switch芯片应当至少支持96 lane PCIe信号，其中C1,C2,C3排列承一条至直线，且朝向一致，C1与C2的间距等于C2与C3的间距。其中10个×16 PCIe插槽依次记为Slot 0至Slot 9。其中PCIe switch 0与Slot 0至Slot 3插槽之间通过×16 PCIe信号连接；其中PCIe switch 0与C0,C2之间通过×16 PCIe信号连接；其中PCIe switch 1与Slot 6至Slot9插槽之间通过×16 PCIe信号连接；其中PCIe switch 1与C3之间通过×16 PCIe信号连接；其中C1与slot 4之间通过×16 PCIe信号连接。当设计为common拓扑时，GPU板上C0连接器通过线缆连接到CPU0，C3连接器通过线缆连接到CPU0，桥接器上2个连接器分别对应GPU板C1和C2连接器连接。在本申请实施例中，连接器线路板包括2个板对板连接器，板对板连接器与前述GPU板的C0至C3是配套关系，可以相互连接；其中2个板对板连接器焊接在一块PCB上，之间通过×16 PCIe信号连接；其中2个板对板连接器的间距等于前述GPU板上C1与C2的间距；可选的，桥接器PCB上TX和RX可以做reversal，以方便GPU板布线。
作为一种可选的实施例，M等于N-1，P等于1。
作为一种可选的实施例，N等于5。
在本申请的一个示例性的实施例中，提供了一种服务器系统，包括：中央处理器组，图形处理器的线路板和图形处理器组，其中，图形处理器的线路板连接在中央处理器组和图形处理器组之间，
图形处理器的线路板上部署了连接器组，交换芯片组和设备插槽组，其中，连接器组包括：第一连接器，第二连接器，第三连接器和第四连接器，交换芯片组包括：第一交换芯片和第二交换芯片，设备插槽组包括：第一插槽集合和第二插槽集合，第一插槽集合包括M+P个设备插槽，第二插槽集合包括N个设备插槽，N等于M+P；
第一交换芯片通过线路板走线分别与第一连接器、第三连接器、第一插槽集合中的M个设备插槽连接，第二交换芯片通过线路板走线分别与第四连接器、第二插槽集合中的N个设备插槽连接，第二连接器通过线路板走线与第一插槽 集合中的P个设备插槽连接；
第一连接器，被配置为连接中央处理器组中的中央处理器；第二连接器，被配置为连接第三连接器；第三连接器，被配置为连接第二连接器，或者，第四连接器；第四连接器，被配置为连接第三连接器，或者，中央处理器组中的中央处理器；
设备插槽组，被配置为连接图形处理器组中的图形处理器。
通过上述设计，设置用于连接图形处理器和中央处理器的线路板，在线路板上通过部署连接器组、交换芯片组和设备插槽，连接器组包括第一连接器、第二连接器、第三连接器和第四连接器、交换芯片组包括第一交换芯片和第二交换芯片，设备插槽组包括第一插槽集合和第二插槽集合，在线路板上部分元件通过线路板走线连接，通过将第一交换芯片通过线路板走线分别和第一连接器、第三连接器和第一插槽集合中M个设备插槽连接，将第二交换芯片通过线路板走线分别与第四连接器和第二插槽集合中的N各设备插槽连接，将第二连接器通过线路板走线与第一插槽集合中的P各设备插槽连接，进而通过将第一连接器配置为用于连接中央处理器，第二连接器配置为用于连接第三连接器，第三连接器配置为用于连接第二连接器或者第四连接器，第四连接器配置为用于连接第三连接器或者中央处理器，从而实现在满足图形处理器的连接拓扑结构需求的前提下简化图形处理器的线路板的结构，可以解决服务器上多个图形处理器的连接拓扑结构的切换操作复杂度较高问题，达到降低服务器上多个图形处理器的连接拓扑结构的切换操作的复杂度的效果。
图6是根据本申请实施例的一种可选的服务器系统示意图，如图6所示，服务器系统，包括：中央处理器组，图形处理器的线路板和图形处理器组，其中，图形处理器的线路板连接在中央处理器组和图形处理器组之间，图形处理器的线路板上部署了连接器组，交换芯片组和设备插槽组，其中，连接器组包括：第一连接器，第二连接器，第三连接器和第四连接器，交换芯片组包括：第一交换芯片和第二交换芯片，设备插槽组包括：第一插槽集合和第二插槽集合，第一插槽集合包括M+P个设备插槽，第二插槽集合包括N个设备插槽，N等于M+P；第一交换芯片通过线路板走线分别与第一连接器、第三连接器、第一插槽集合中的M个设备插槽连接，第二交换芯片通过线路板走线分别与第四连接器、第二插槽集合中的N个设备插槽连接，第二连接器通过线路板走线与第一插槽集合中的P个设备插槽连接；第一连接器，被配置为连接中央处理器组中的中央处理器；第二连接器，被配置为连接第三连接器；第三连接器，被配置为连接第二连接器，或者，第四连接器；第四连接器，被配置为连接第三连接器，或者，中央处理器组中的中央处理器；设备插槽组，被配置为连接图形处理器组中的图形处理器。
可选地，在本申请实施例中，线路板的连接器组侧的端口被配置为连接中央处理器，线路板的设备插槽组侧的端口被配置为连接图形处理器，并且设备插槽组包括多个用于连接图形处理器设备插槽，从而实现中央处理器和多个图形处理器之间的连接。
可选地，在本申请实施例中，为了实现图形处理器不同的连接拓扑结构，可以通过改变第二连接器、第三连接器和第四连接器之间的连接关系，从而实现图形处理器的不同的连接拓扑需求。
可选地，在本申请实施例中，第二连接器、第三连接器和第四连接器可以在线路板上按照顺序依次排列成一条直线，第二连接器、第三连接器和第四连接器之间可以通过线缆连接或者还可以通过连接器具连接，比如，第二连接器、第三连接器和第四连接器可以采用具有对外连接接口的连接器(比如板对板连接器)，此时连接器具可以是设置了两个连接接口的连接器具，连接器具上的连接接口被配置为和连接器上的对外连接接口连接，比如，连接器具可以是包括两个连接头的连接线缆，连接线缆的第一连接头与第三连接器连接，连接线缆上的第二连接头被配置为与第二连接器或者和第四连接器连接，通过切花第二连接头和第二连接器或者第四连接器的连接关系，从而切换图形处理器的连接拓扑；连接器还可以是包括两个连接头的连接板，此时第二连接器、第三连接器和第四连接器之间排列成一条直线，并且第二连接器、第三连接器和第四连接器之间的间距相等，连接板上的两个连接接头之间间距和第三连接器与第二连接器之间的间距或者第三连接器与连接器之间的间距相等，在使用中，可以通过改变连接板与第二连接器、第三连接器和第四连接器之间的连接关系从而改变图形处理器的连接拓扑结构，或者，连接板可以被配置为在线路板上可滑动，通过将连接板在第二连接器、第三连接器和第四连接器之间滑动，从而通过改变连接板对第二连接器、第三连接器和第四连接器的连接关系的方式改变图形处理器的连接拓扑结构。
可选地，在本申请实施例中，上述图形处理的线路板支持8张×16 GPU和2张×16网卡的GPU板，并支持balance，cascade，common三种拓扑形式，上述交换芯片2颗96 lane PCIe switch芯片。
作为一种可选的实施例，第二连接器与第三连接器连接，第一连接器连接中央处理器组中的第一中央处理器，第四连接器连接中央处理器组中的第二中央处理器形成图形处理器组的平衡拓扑结构。
可选地，在本申请实施例中，当设计为balance拓扑(平衡拓扑结构)时，GPU板上C0(第一连接器)连接器通过线缆连接到CPU0，C3(第四连接器)连接器通过线缆连接到CPU1，桥接器上2个连接器分别对应GPU板C1(第二连接器)和C2(第三连接器)连接器连接。
作为一种可选的实施例，第二连接器与第三连接器连接，第一连接器和第四连接器均连接中央处理器组中的第三中央处理器形成图形处理器组的普通拓扑结构。
可选地，在本申请实施例中，当设计为cascade拓扑(普通拓扑结构)时，GPU板上C0连接器(第一连接器)通过线缆连接到CPU0，C3连接器(第四连接器)不插接线缆，桥接器上2个连接器分别对应GPU板C2(第三连接器)和C3(第四连接器)连接器连接。
作为一种可选的实施例，第三连接器与第四连接器连接，第一连接器连接 中央处理器组中的第四中央处理器形成图形处理器组的串联拓扑结构。
可选地，在本申请实施例中，当设计为common拓扑(串联拓扑结构)时，GPU板上C0连接器(第一连接器)通过线缆连接到CPU0，C3连接器(第四连接器)通过线缆连接到CPU0，桥接器上2个连接器分别对应GPU板C1(第二连接器)和C2(第三连接器)连接器连接。
作为一种可选的实施例，服务器系统，还包括：连接器线路板，其中，
第二连接器，第三连接器和第四连接器均为板对板连接器，第二连接器，第三连接器和第四连接器排列承一条直线，且朝向一致，第二连接器和第三连接器之间的间距与第三连接器和第四连接器之间的间距均为目标间距；
连接器组中的连接器通过连接器线路板连接，其中，连接器线路板上在同侧部署了第五连接器和第六连接器，第五连接器和第六连接器通过线路板走线连接，第五连接器和第六连接器均为板对板连接器，第五连接器和第六连接器之间的间距为目标间距。
可选地，在本申请实施例中，连接器线路板可以通过插拔的方式实现第三连接器和第二连接器、第三连接器和第四连接器之间的连接，或者连接线路板还可以被设置为在图形处理器的线路板上滑动，使用时可以通过滑动的方式实现将第三连接器和第二连接器之间的连接切换为第三连接器和第四连接器之间的连接，本方案对此不作限定。
可选的，在本申请实施例中，桥接器包括但不限于可采用4C连接器(SFF-TA-1002)的桥接器，本方案对此不做限定。
图7是根据本申请的一种可选的线路板详图，如图7所示，本申请实施例设计一张支持8张×16 GPU和2张×16网卡的GPU板，并支持balance，cascade，common三种拓扑形式的线路板，设计方案中，GPU板设计有2颗96 lane PCIe switch芯片，分别记为PCIe switch 0(第一交换芯片)和PCIe switch 1(第二交换芯片)；设计方案中，GPU板设计有4个支持×16 PCIe信号的板对板连接器，分别记为C0(第一连接器)至C3；其中C1(第二连接器),C2(第三连接器),C3(第四连接器)按同一方向布置，并且处在一条直线上，C2在中间，C1和C3在两侧；可选的，板对板连接器可以是vertical或者right angle；可选的，板对板连接器可以是MCIO连接器或者gen-z连接器；设计方案中，GPU板设计有10个×16 PCIe插槽，依次记为Slot 0至Slot 9；可选的，安装GPU的插槽预留双宽AIC(Add-In Card，一种固态硬盘的产品形态)的空间；其中PCIe switch 0与Slot 0至Slot 3插槽之间通过×16 PCIe信号连接；其中PCIe switch 0与C0,C2之间通过×16 PCIe信号连接；其中PCIe switch 1与Slot 6至Slot9插槽之间通过×16 PCIe信号连接；其中PCIe switch 1与C3之间通过×16 PCIe信号连接；其中C1与slot 4之间通过×16 PCIe信号连接。本实例还配套设计一款桥接器，包括2个板对板连接器，所属板对板连接器与前述GPU板的C0至C3是配套关系，可以相互连接；其中2个板对板连接器焊接在一块PCB上，之间通过×16 PCIe信号连接；其中2个板对板连接器的间距等于前述GPU板上C1与C2的间距；可选的，桥接器PCB上TX和RX可以做reversal， 以方便GPU板布线。选用4C连接器(SFF-TA-1002)的桥接器。当设计为balance拓扑时，GPU板上C0连接器通过线缆连接到CPU0，C3连接器通过线缆连接到CPU1，桥接器上2个连接器分别对应GPU板C1和C2连接器连接，当设计为cascade拓扑时，GPU板上C0连接器通过线缆连接到CPU0，C3连接器不插接线缆，桥接器上2个连接器分别对应GPU板C2和C3连接器连接，当设计为common拓扑时，GPU板上C0连接器通过线缆连接到CPU0，C3连接器通过线缆连接到CPU0，桥接器上2个连接器分别对应GPU板C1和C2连接器连接。
通过上述实施例，1)减少连接器数量，并将原有的×8连接器改为×16连接器，减少线缆数量2)通过采用板对板连接器设计，简化设计方案3)
新增桥接器设计，增加连接可靠性，减少更换拓扑时的操作步骤，并且板对板连接器并排设计，搭配配对连接器的桥接器，有效简化板卡设计方案，并且能很方便的支持不同拓扑之间的切换。
以上所述仅为本申请的可选实施例而已，并不用于限制本申请，对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的原则之内，所作的任何修改、等同替换、改进等，均应包括在本申请的保护范围之内。

Claims (20)

  1. 一种图形处理器的线路板，其特征在于，
    所述线路板上部署了连接器组，交换芯片组和设备插槽组，其中，
    所述连接器组包括：第一连接器，第二连接器，第三连接器和第四连接器，所述交换芯片组包括：第一交换芯片和第二交换芯片，所述设备插槽组包括：第一插槽集合和第二插槽集合，所述第一插槽集合包括M+P个设备插槽，所述第二插槽集合包括N个设备插槽，N等于M+P；
    所述第一交换芯片通过线路板走线分别与所述第一连接器、所述第三连接器、所述第一插槽集合中的M个设备插槽连接，所述第二交换芯片通过线路板走线分别与所述第四连接器、所述第二插槽集合中的N个设备插槽连接，所述第二连接器通过线路板走线与所述第一插槽集合中的P个设备插槽连接；
    所述第一连接器，被配置为连接中央处理器；所述第二连接器，被配置为连接所述第三连接器；所述第三连接器，被配置为连接所述第二连接器，或者，所述第四连接器；所述第四连接器，被配置为连接所述第三连接器，或者，中央处理器；
    所述设备插槽组，被配置为连接图形处理器。
  2. 根据权利要求1所述的线路板，其特征在于，
    所述第二连接器，所述第三连接器和所述第四连接器均为板对板连接器，所述第二连接器，所述第三连接器和所述第四连接器排列承一条直线，且朝向一致，所述第二连接器和所述第三连接器之间的间距与所述第三连接器和所述第四连接器之间的间距均为目标间距。
  3. 根据权利要求2所述的线路板，其特征在于，
    所述连接器组中的连接器通过连接器线路板连接，其中，所述连接器线路板上在同侧部署了第五连接器和第六连接器，所述第五连接器和所述第六连接器通过线路板走线连接，所述第五连接器和所述第六连接器均为板对板连接器，所述第五连接器和所述第六连接器之间的间距为所述目标间距。
  4. 根据权利要求3所述的线路板，其特征在于，
    所述连接器线路板被设置为在所述图形处理器的线路板上滑动，通过滑动的方式实现所述第三连接器和所述第二连接器之间的连接与所述第三连接器和所述第四连接器之间的连接的切换。
  5. 根据权利要求3所述的线路板，其特征在于，
    所述连接器线路板被设置为通过插拔方式实现所述第三连接器和所述第二连接器、所述第三连接器和所述第四连接器之间的连接。
  6. 根据权利要求2所述的线路板，其特征在于，
    所述连接器组中的连接器通过包括两个连接头的连接线缆连接，其中，所述连接线缆的第一连接头与所述第三连接器连接，所述连接线缆的第二连接头被配置为与所述第二连接器连接或者所述第四连接器连接。
  7. 根据权利要求1所述的线路板，其特征在于，
    所述第二连接器与所述第三连接器之间连接的结构用于形成图形处理器的平衡拓扑结构，或者，普通拓扑结构。
  8. 根据权利要求7所述的线路板，其特征在于，
    所述第二连接器与所述第三连接器连接，所述第一连接器和所述第四连接器分别连接不同的中央处理器形成所述平衡拓扑结构。
  9. 根据权利要求7所述的线路板，其特征在于，
    所述第二连接器与所述第三连接器连接，所述第一连接器和所述第四连接器连接相同的中央处理器形成所述普通拓扑结构。
  10. 根据权利要求1所述的线路板，其特征在于，
    所述第三连接器与所述第四连接器之间连接的结构用于形成图形处理器的串联拓扑结构。
  11. 根据权利要求10所述的线路板，其特征在于，
    所述第三连接器与所述第四连接器连接，所述第一连接器连接中央处理器形成所述串联拓扑结构。
  12. 根据权利要求1所述的线路板，其特征在于，
    M等于N-1，P等于1。
  13. 根据权利要求12所述的线路板，其特征在于，
    N等于5。
  14. 一种服务器系统，其特征在于，
    包括：中央处理器组，图形处理器的线路板和图形处理器组，其中，所述图形处理器的线路板连接在所述中央处理器组和所述图形处理器组之间，
    图形处理器的线路板上部署了连接器组，交换芯片组和设备插槽组，其中，所述连接器组包括：第一连接器，第二连接器，第三连接器和第四连接器，所述交换芯片组包括：第一交换芯片和第二交换芯片，所述设备插槽组包括：第一插槽集合和第二插槽集合，所述第一插槽集合包括M+P个设备插槽，所述第二插槽集合包括N个设备插槽，N等于M+P；
    所述第一交换芯片通过线路板走线分别与所述第一连接器、所述第三连接器、所述第一插槽集合中的M个设备插槽连接，所述第二交换芯片通过线路板走线分别与所述第四连接器、所述第二插槽集合中的N个设备插槽连接，所述第二连接器通过线路板走线与所述第一插槽集合中的P个设备插槽连接；
    所述第一连接器，被配置为连接所述中央处理器组中的中央处理器；所述第二连接器，被配置为连接所述第三连接器；所述第三连接器，被配置为连接所述第二连接器，或者，所述第四连接器；所述第四连接器，被配置为连接所述第三连接器，或者，所述中央处理器组中的中央处理器；
    所述设备插槽组，被配置为连接所述图形处理器组中的图形处理器。
  15. 根据权利要求14所述的服务器系统，其特征在于，
    所述第二连接器与所述第三连接器连接，所述第一连接器连接所述中央处理器组中的第一中央处理器，所述第四连接器连接所述中央处理器组中的第二中央处理器形成所述图形处理器组的平衡拓扑结构。
  16. 根据权利要求14所述的服务器系统，其特征在于，
    所述第二连接器与所述第三连接器连接，所述第一连接器和所述第四连接器均连接所述中央处理器组中的第三中央处理器形成所述图形处理器组的普通拓扑结构。
  17. 根据权利要求14所述的服务器系统，其特征在于，
    所述第三连接器与所述第四连接器连接，所述第一连接器连接所述中央处理器组中的第四中央处理器形成所述图形处理器组的串联拓扑结构。
  18. 根据权利要求14所述的服务器系统，其特征在于，
    所述服务器系统，还包括：连接器线路板，其中，
    所述第二连接器，所述第三连接器和所述第四连接器均为板对板连接器，所述第二连接器，所述第三连接器和所述第四连接器排列承一条直线，且朝向一致，所述第二连接器和所述第三连接器之间的间距与所述第三连接器和所述第四连接器之间的间距均为目标间距；
    所述连接器组中的连接器通过所述连接器线路板连接，其中，所述连接器线路板上在同侧部署了第五连接器和第六连接器，所述第五连接器和所述第六连接器通过线路板走线连接，所述第五连接器和所述第六连接器均为板对板连接器，所述第五连接器和所述第六连接器之间的间距为所述目标间距。
  19. 根据权利要求18所述的服务器系统，其特征在于，
    所述连接器线路板被设置为在所述图形处理器的线路板上滑动，通过滑动的方式实现所述第三连接器和所述第二连接器之间的连接与所述第三连接器和所述第四连接器之间的连接的切换。
  20. 根据权利要求18所述的服务器系统，其特征在于，
    所述连接器线路板被设置为通过插拔方式实现所述第三连接器和所述第二连接器、所述第三连接器和所述第四连接器之间的连接。
PCT/CN2024/088058 2023-12-01 2024-04-16 图形处理器的线路板及服务器系统 Pending WO2025112271A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US19/139,143 US20260030192A1 (en) 2023-12-01 2024-04-16 Circuit Board of Graphics Processing Unit and Server System

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202311634161.1A CN117333348B (zh) 2023-12-01 2023-12-01 图形处理器的线路板及服务器系统
CN202311634161.1 2023-12-01

Publications (1)

Publication Number Publication Date
WO2025112271A1 true WO2025112271A1 (zh) 2025-06-05

Family

ID=89279719

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2024/088058 Pending WO2025112271A1 (zh) 2023-12-01 2024-04-16 图形处理器的线路板及服务器系统

Country Status (3)

Country Link
US (1) US20260030192A1 (zh)
CN (1) CN117333348B (zh)
WO (1) WO2025112271A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117333348B (zh) * 2023-12-01 2024-02-20 苏州元脑智能科技有限公司 图形处理器的线路板及服务器系统

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016037503A1 (zh) * 2014-09-10 2016-03-17 华为技术有限公司 PCIe拓扑的配置方法和装置
US20170322899A1 (en) * 2016-05-06 2017-11-09 Quanta Computer Inc. Dynamic pcie switch reconfiguration mechanism
CN108845970A (zh) * 2018-05-30 2018-11-20 郑州云海信息技术有限公司 一种自由切换gpu服务器拓扑的装置及方法
CN109002591A (zh) * 2018-06-26 2018-12-14 郑州云海信息技术有限公司 一种从服务器主板端调整PCIe拓扑的方法和系统
CN112765074A (zh) * 2020-12-26 2021-05-07 苏州浪潮智能科技有限公司 一种图形处理器拓扑切换设备和图形处理器板卡
CN115639880A (zh) * 2022-09-27 2023-01-24 超聚变数字技术有限公司 服务器
CN117333348A (zh) * 2023-12-01 2024-01-02 苏州元脑智能科技有限公司 图形处理器的线路板及服务器系统

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109993685A (zh) * 2019-03-26 2019-07-09 苏州浪潮智能科技有限公司 一种gpu服务器
CN210038633U (zh) * 2019-04-19 2020-02-07 苏州浪潮智能科技有限公司 一种应用在GPU服务器中可灵活配置的Riser卡
CN112069107A (zh) * 2020-08-21 2020-12-11 苏州浪潮智能科技有限公司 一种可自动识别外插卡的服务器板卡及外插卡自动识别方法
CN219574741U (zh) * 2023-05-19 2023-08-22 苏州浪潮智能科技有限公司 一种耦合gpu服务器架构、数据中心

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016037503A1 (zh) * 2014-09-10 2016-03-17 华为技术有限公司 PCIe拓扑的配置方法和装置
US20170322899A1 (en) * 2016-05-06 2017-11-09 Quanta Computer Inc. Dynamic pcie switch reconfiguration mechanism
CN108845970A (zh) * 2018-05-30 2018-11-20 郑州云海信息技术有限公司 一种自由切换gpu服务器拓扑的装置及方法
CN109002591A (zh) * 2018-06-26 2018-12-14 郑州云海信息技术有限公司 一种从服务器主板端调整PCIe拓扑的方法和系统
CN112765074A (zh) * 2020-12-26 2021-05-07 苏州浪潮智能科技有限公司 一种图形处理器拓扑切换设备和图形处理器板卡
CN115639880A (zh) * 2022-09-27 2023-01-24 超聚变数字技术有限公司 服务器
CN117333348A (zh) * 2023-12-01 2024-01-02 苏州元脑智能科技有限公司 图形处理器的线路板及服务器系统

Also Published As

Publication number Publication date
US20260030192A1 (en) 2026-01-29
CN117333348B (zh) 2024-02-20
CN117333348A (zh) 2024-01-02

Similar Documents

Publication Publication Date Title
US20150347345A1 (en) Gen3 pci-express riser
US20050270298A1 (en) Daughter card approach to employing multiple graphics cards within a system
US20130080675A1 (en) Dual PCI-X/PCI-E Card
TWI437426B (zh) 伺服器機櫃系統
JP2013541742A (ja) 動的マルチリンク編集パーティション分割システム及び方法
US11983130B2 (en) Multi-image output system and USB hub thereof
TWI603202B (zh) 具有通道資源重定向的設備及系統
US9954295B2 (en) Midplane interconnect system with conductor twist mitigation
US20260101441A1 (en) Board and server
CN111538689B (zh) 两端异构的多通道pcie转接卡
KR102318130B1 (ko) 외부 전기 커넥터 및 컴퓨터 시스템
WO2024041077A1 (zh) 服务器及数据中心
WO2025112271A1 (zh) 图形处理器的线路板及服务器系统
CN109992060B (zh) 层叠式多路服务器系统及服务器
CN213276461U (zh) 一种双路服务器主板及服务器
CN115696737A (zh) 电路板和计算设备
CN110633246B (zh) 具互连端口弹性连接方式的运算装置
CN221884301U (zh) 高速接口扩展板卡与电子设备
EP4174667B1 (en) Dis-aggregated switching and protocol configurable input/output module
CN116107943B (zh) 一种信号传输电路及计算设备
WO2022242190A1 (zh) 电子组件、交换机及计算机系统
CN120321874B (zh) 电路板和交换机
TWI880468B (zh) 記憶體裝置及系統
CN119416729B (zh) 多功能复用的主板和工控计算机
US12299299B1 (en) Memory system

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 24895382

Country of ref document: EP

Kind code of ref document: A1