WO2025079715A1 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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Publication number
WO2025079715A1
WO2025079715A1 PCT/JP2024/036553 JP2024036553W WO2025079715A1 WO 2025079715 A1 WO2025079715 A1 WO 2025079715A1 JP 2024036553 W JP2024036553 W JP 2024036553W WO 2025079715 A1 WO2025079715 A1 WO 2025079715A1
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Prior art keywords
region
thinning
trench
contact
semiconductor device
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English (en)
French (fr)
Japanese (ja)
Inventor
秀平 立道
達也 内藤
泰彦 大西
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Priority to JP2025551704A priority Critical patent/JPWO2025079715A1/ja
Priority to CN202480021270.2A priority patent/CN120937521A/zh
Publication of WO2025079715A1 publication Critical patent/WO2025079715A1/ja
Priority to US19/334,931 priority patent/US20260020293A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60—Impurity distributions or concentrations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/50—PIN diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/161—IGBT having built-in components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.
  • Patent Document 1 JP 2021-144998 A
  • Patent Document 2 JP 2022-181457 A
  • a semiconductor device in a first aspect of the present invention, includes a transistor portion and a diode portion, the semiconductor device including a first conductivity type drift region provided in a semiconductor substrate, and a plurality of trench portions extending in a predetermined trench extension direction on the front surface side of the semiconductor substrate.
  • the transistor portion may include a second conductivity type base region provided above the drift region, a plurality of emitter regions of the first conductivity type that are discretely provided in the trench extension direction and have a doping concentration higher than that of the drift region, a contact region of the second conductivity type that has a doping concentration higher than that of the base region, a trench contact portion that is provided in a mesa portion between two adjacent trench portions among the plurality of trench portions and extends from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate, and a thinning region that is provided between two adjacent emitter regions among the plurality of emitter regions in the trench extension direction and has a doping concentration of the second conductivity type lower than that of the contact region.
  • the thinning region may be the base region.
  • the thinning region may have a first thinning portion provided between the two adjacent emitter regions and in contact with the contact region on the front surface of the semiconductor substrate.
  • the thinning region may have a second thinning portion provided between the two adjacent emitter regions and in contact with the first thinning portion on the front surface of the semiconductor substrate, and has a doping concentration different from that of the first thinning portion.
  • the first thinning portion may include a plurality of first thinning portions.
  • the second thinning portion may be provided on the front surface between two of the plurality of first thinning portions that are adjacent in the trench extension direction.
  • the first thinning-out portion may be the base region.
  • the second thinning-out portion may have a first conductivity type that has a lower doping concentration than the emitter region.
  • the second thinning section may be the drift region.
  • the first thinning-out portion may be the base region.
  • the second thinning-out portion may have a second conductivity type that has a lower doping concentration than the base region.
  • the diode section may have an anode region of a second conductivity type provided above the drift region.
  • the second thinning section may be the anode region.
  • the contact region may have a plurality of contact regions.
  • the plurality of contact regions may be provided at both ends of the emitter region in the trench extension direction and may contact the emitter region on the front surface.
  • the contact region may be provided between the emitter region and the first thinning portion, which are adjacent in the trench extension direction, and on the front surface, one end of the contact region may be in contact with the emitter region, and the other end of the contact region may be in contact with the first thinning portion.
  • the first thinning portion may be provided below the contact region.
  • the length of the first thinning portion provided on the front surface in the trench extension direction may be equal to or greater than the thickness of the first thinning portion provided below the contact region in the depth direction of the semiconductor substrate.
  • the length of the first thinning portion provided on the front surface in the trench extension direction may be 0.1 ⁇ m or more and 2.0 ⁇ m or less.
  • the length of the second thinning portion in the trench extension direction may be greater than the length of the first thinning portion in the trench extension direction.
  • the length of the second thinning portion in the trench extension direction may be greater than the length of the emitter region in the trench extension direction.
  • any of the above semiconductor devices may include an interlayer insulating film provided above the first thinning portion and the second thinning portion, covering both the first thinning portion and the second thinning portion provided on the front surface.
  • the interlayer insulating film may have a contact hole.
  • the trench contact portion When viewed from above, the trench contact portion may be provided in a region where the contact hole is provided, and when viewed from above, the region where the contact hole is not provided may be a trench contact non-formation region where the trench contact portion is not provided.
  • the ratio ⁇ of the distance between two adjacent emitter regions in the trench extension direction to the length in the trench extension direction of a non-thinning region in which one or more emitter regions and one or more contact regions are continuously formed may be 1.5 or more and 20 or less.
  • any of the above semiconductor devices may include an accumulation region of a first conductivity type above the drift region, the accumulation region having a doping concentration higher than that of the drift region.
  • any of the above semiconductor devices may include a plug region of a second conductivity type provided at the lower end of the trench contact portion and having a doping concentration higher than that of the base region.
  • the diode portion may have an anode region of a second conductivity type having a lower doping concentration than the base region.
  • the transistor portion may have a boundary region provided on the diode portion side of the transistor portion.
  • the semiconductor substrate does not need to have a lifetime killer region on the front surface side of the center in the depth direction.
  • a method for manufacturing a semiconductor device having a transistor portion and a diode portion comprising the steps of forming a base region of a second conductivity type above a drift region of a first conductivity type provided in a semiconductor substrate, forming a plurality of trench portions on the front surface side of the semiconductor substrate, extending in a predetermined trench extension direction, forming a plurality of emitter regions of a first conductivity type having a doping concentration higher than that of the drift region in a discrete manner in the trench extension direction, forming a contact region of a second conductivity type having a doping concentration higher than that of the base region, forming a trench contact portion in the transistor portion by extending from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate in a mesa portion between two adjacent trench portions among the plurality of trench portions, and forming a thinning-out region having a doping concentration of the second conductivity type lower than that of the contact region between two
  • the thinning region may include the base region, and the step of forming the thinning region may include a step of forming an anode region in the transistor section and the diode section, and then forming the base region by ion-implanting a dopant of a second conductivity type into the anode region of the transistor section.
  • FIG. 1 shows an example of a top view of a semiconductor device 100.
  • FIG. FIG. 2 is an enlarged view of area A in FIG.
  • FIG. 2B is a diagram showing an example of an XZ cross section including the aa' cross section in FIG. 2A.
  • 2B shows an example of a YZ cross section including the bb' cross section in FIG. 2A.
  • 2B shows a modified example of the YZ cross section including the bb' cross section in FIG. 2A.
  • 2B shows a modified example of the YZ cross section including the bb' cross section in FIG. 2A.
  • 2 is a modified example of an enlarged view of area A in FIG. 1 .
  • 4B shows an example of a YZ cross section including the dd' cross section in FIG.
  • 4A. 4B shows a modified example of the YZ cross section including the dd' cross section in FIG. 4A.
  • 4B shows a modified example of the YZ cross section including the dd' cross section in FIG. 4A.
  • 4B shows a modified example of the YZ cross section including the dd' cross section in FIG. 4A.
  • 4B shows a modified example of the YZ cross section including the dd' cross section in FIG. 4A.
  • 4B shows a modified example of the YZ cross section including the dd' cross section in FIG. 4A.
  • 13 shows a modified top view of the mesa portion 71.
  • 13 shows a modified top view of the mesa portion 71.
  • 1 shows the dependence of the switching loss Err during reverse recovery on the ratio ⁇ . 1 shows the dependence of the saturation current Isat of the collector current on the ratio ⁇ .
  • one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "upper” and the other side as “lower.”
  • the upper surface is referred to as the upper surface and the other surface is referred to as the lower surface.
  • the directions of "upper” and “lower” are not limited to the direction of gravity or the directions when the semiconductor device is mounted.
  • the orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction.
  • the Z-axis does not limit the height direction relative to the ground.
  • the +Z-axis direction and the -Z-axis direction are opposite directions.
  • the Z-axis direction is described without indicating positive or negative, it means the direction parallel to the +Z-axis and -Z-axis.
  • the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis.
  • the axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis.
  • the direction of the Z-axis may be referred to as the depth direction.
  • the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis may be referred to as the horizontal direction.
  • the conductivity type of a doped region doped with impurities is described as P type or N type.
  • impurities may specifically mean either N type donors or P type acceptors, and may be described as dopants.
  • doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor that exhibits N type conductivity or a semiconductor that exhibits P type conductivity.
  • the doping concentration means the concentration of the donor or the concentration of the acceptor in a thermal equilibrium state.
  • the net doping concentration means the net concentration obtained by adding up the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charge.
  • the donor concentration is N D and the acceptor concentration is N A
  • the net doping concentration at any position is N D -N A.
  • the net doping concentration may be simply referred to as the doping concentration.
  • chemical concentration refers to the atomic density of an impurity measured regardless of the state of electrical activation.
  • the chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS).
  • SIMS secondary ion mass spectrometry
  • the above-mentioned net doping concentration can be measured by a voltage-capacitance measurement method (CV method).
  • the carrier concentration measured by a spreading resistance measurement method (SR method) may be the net doping concentration.
  • Carriers refer to charge carriers of electrons or holes.
  • the carrier concentration measured by the CV method or the SR method may be a value in a thermal equilibrium state.
  • the carrier concentration in that region may be the donor concentration.
  • the carrier concentration in that region may be the acceptor concentration.
  • the doping concentration in an N-type region may be referred to as the donor concentration
  • the doping concentration in a P-type region may be referred to as the acceptor concentration.
  • the peak value may be taken as the concentration of the donor, acceptor or net doping in the region.
  • the average value of the concentration of the donor, acceptor or net doping in the region may be taken as the concentration of the donor, acceptor or net doping.
  • the carrier concentration measured by the SR method may be lower than the donor or acceptor concentration.
  • the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state.
  • the decrease in carrier mobility occurs when the carriers are scattered due to a disturbance (disorder) in the crystal structure caused by lattice defects, etc.
  • the reason for the decrease in carrier concentration is as follows.
  • the spreading resistance is measured and the carrier concentration is calculated from the measured value of the spreading resistance.
  • the mobility in the crystalline state is used as the carrier mobility.
  • the carrier concentration is calculated based on the carrier mobility in the crystalline state, even though the carrier mobility is decreased. Therefore, the value is lower than the actual carrier concentration, i.e., the concentration of the donor or acceptor.
  • the donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element indicating the donor or acceptor.
  • the donor concentration of phosphorus or arsenic, which is a donor in a silicon semiconductor, or the acceptor concentration of boron, which is an acceptor is about 99% of these chemical concentrations.
  • the donor concentration of hydrogen, which is a donor in a silicon semiconductor is about 0.1% to 10% of the chemical concentration of hydrogen.
  • the SI system of units is adopted.
  • the unit of distance or length may be expressed in cm (centimeter). In this case, various calculations may be calculated by converting it to m (meter).
  • the numerical representation of powers of 10 for example, the representation of 1E+16 indicates 1 ⁇ 10 16 , and the representation of 1E-16 indicates 1 ⁇ 10 -16 .
  • FIG. 1 shows an example of a top view of a semiconductor device 100.
  • the semiconductor device 100 is a semiconductor chip that includes a transistor section 70 and a diode section 80.
  • the transistor section 70 includes a transistor such as an IGBT (Insulated Gate Bipolar Transistor).
  • the diode section 80 includes a diode such as a free wheel diode (FWD).
  • the semiconductor device 100 of this example is a reverse conducting IGBT (RC-IGBT) that has the transistor section 70 and the diode section 80 on the same chip.
  • RC-IGBT reverse conducting IGBT
  • the semiconductor substrate 10 is a substrate formed of a semiconductor material.
  • the semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a diamond substrate, a nitride semiconductor substrate such as gallium nitride, an inorganic compound semiconductor substrate such as gallium oxide, or an organic compound semiconductor substrate.
  • the semiconductor substrate 10 in this example is a silicon substrate.
  • the semiconductor substrate 10 may be a wafer cut from a semiconductor ingot, or a chip cut from a wafer.
  • the semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), the magnetic field-applied Czochralski method (MCZ method), or the float zone method (FZ method).
  • the semiconductor substrate 10 has end edges 102 when viewed from above. When simply referred to as a top view in this specification, it means that the semiconductor substrate 10 is viewed from the top surface side. In this example, the semiconductor substrate 10 has two sets of end edges 102 that face each other when viewed from above. In FIG. 1, the X-axis and Y-axis are parallel to one of the end edges 102. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10.
  • the semiconductor substrate 10 has an active portion 160 and an edge termination structure portion 170.
  • the active portion 160 is a region in which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation.
  • An emitter electrode is provided above the active portion 160, but is omitted in FIG. 1.
  • the active section 160 is provided with at least one of a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as a free wheel diode (FWD).
  • a transistor section 70 including a transistor element such as an IGBT and a diode section 80 including a diode element such as a free wheel diode (FWD).
  • the transistor section 70 and the diode section 80 are arranged alternately along a predetermined arrangement direction (the X-axis direction in this example) on the upper surface of the semiconductor substrate 10.
  • the region in which the transistor section 70 is arranged is marked with the symbol "I”
  • the region in which the diode section 80 is arranged is marked with the symbol "F”.
  • the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (the Y-axis direction in FIG. 1).
  • the transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction.
  • the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction.
  • the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction.
  • the extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section described later.
  • the diode section 80 has an N+ type cathode region in a region that contacts the underside of the semiconductor substrate 10.
  • the region in which the cathode region is provided is referred to as the diode section 80.
  • the diode section 80 is a region that overlaps with the cathode region when viewed from above.
  • a P+ type collector region may be provided in the region other than the cathode region on the underside of the semiconductor substrate 10.
  • the transistor section 70 has a P+ type collector region in a region that contacts the bottom surface of the semiconductor substrate 10.
  • the transistor section 70 has a gate structure that has an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film periodically arranged on the top surface side of the semiconductor substrate 10.
  • the semiconductor device 100 may have one or more pads above the semiconductor substrate 10.
  • the semiconductor device 100 in this example has a gate pad 112.
  • the semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad.
  • Each pad is disposed near the edge 102.
  • the vicinity of the edge 102 refers to the area between the edge 102 and the emitter electrode in a top view.
  • each pad may be connected to an external circuit via wiring such as a wire.
  • a gate potential is applied to the gate pad 112.
  • the gate pad 112 is electrically connected to the conductive portion of the gate trench portion of the active portion 160.
  • the semiconductor device 100 includes a gate wiring 130 that connects the gate pad 112 and the gate trench portion.
  • the gate wiring 130 is electrically connected to the gate conductive portion of the transistor portion 70 and applies a gate voltage to the transistor portion 70.
  • the gate wiring 130 is provided so as to surround the outer periphery of the active portion 160 in a top view.
  • the gate wiring 130 is electrically connected to the gate pad 112 provided in the edge termination structure portion 170.
  • the semiconductor device 100 may also include a temperature sensor (not shown) that is a PN junction diode formed of polysilicon or the like, and a current detector (not shown) that simulates the operation of a transistor section provided in the active section 160.
  • a temperature sensor not shown
  • a current detector not shown
  • the semiconductor device 100 of this example includes an edge termination structure 170 between the active portion 160 and the edge 102 when viewed from above.
  • the edge termination structure 170 of this example is disposed between the gate wiring 130 and the edge 102.
  • the edge termination structure 170 reduces electric field concentration on the upper surface side of the semiconductor substrate 10.
  • the edge termination structure 170 may include at least one of a guard ring, a field plate, and a resurf that are arranged in a ring shape surrounding the active portion 160.
  • FIG. 2A is an enlarged view of region A in FIG. 1.
  • Region A is a region that includes the transistor portion 70, the diode portion 80, and the gate wiring 130.
  • the gate wiring 130 includes the gate metal layer 50 and the gate runner portion 51.
  • a boundary region 90 is provided between the transistor section 70 and the diode section 80 on the front surface 21 of the semiconductor substrate 10.
  • the front surface 21 of the semiconductor substrate 10 refers to one of the two opposing main surfaces of the semiconductor substrate 10. The front surface 21 will be described later.
  • the semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 17, an emitter region 12, a base region 14, a contact region 15, and an anode region 19 formed inside the front surface 21 side of the semiconductor substrate 10.
  • the semiconductor device 100 of this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.
  • An interlayer insulating film is formed between the emitter electrode 52 and the gate metal layer 50 and the front surface 21 of the semiconductor substrate 10, but the interlayer insulating film is omitted in FIG. 2A.
  • contact holes 54, 55, and 56 are formed in the interlayer insulating film, penetrating the interlayer insulating film.
  • the emitter electrode 52 is electrically connected to the emitter region 12, contact region 15, base region 14, and anode region 19 on the front surface 21 of the semiconductor substrate 10 through a contact hole 54 opened in the interlayer insulating film.
  • the emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole 56.
  • a connection portion 25 made of a conductive material, such as polysilicon doped with impurities, may be provided between the emitter electrode 52 and the dummy conductive portion.
  • the gate metal layer 50 contacts the gate runner portion 51 through the contact hole 55.
  • the gate runner portion 51 is formed of a semiconductor such as polysilicon doped with impurities.
  • the gate runner portion 51 is connected to the gate conductive portion in the gate trench portion 40 on the front surface 21 of the semiconductor substrate 10.
  • the emitter electrode 52 and the gate metal layer 50 are formed of a material containing a metal. At least a portion of the emitter electrode 52 may be formed of a metal such as aluminum (Al) or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 may be formed of a metal such as aluminum (Al) or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu).
  • the emitter electrode 52 and the gate metal layer 50 may have a barrier metal made of titanium or a titanium compound under the region made of aluminum. Each electrode may further have a plug formed by embedding tungsten or the like in the contact hole so as to contact the barrier metal and aluminum or the like.
  • the well region 17 is provided so as to overlap the gate metal layer 50 and the gate runner portion 51.
  • the well region 17 is also provided so as to extend by a predetermined width into an area where it does not overlap with the gate metal layer 50 and the gate runner portion 51.
  • the well region 17 is provided away from the end of the contact hole 54 in the Y-axis direction toward the gate metal layer 50.
  • the well region 17 is a region of a second conductivity type having a higher doping concentration than the base region 14.
  • the base region 14 is P- type
  • the well region 17 is P+ type.
  • Each of the transistor section 70 and the diode section 80 has multiple trench sections arranged in the arrangement direction on the front surface 21 of the semiconductor substrate 10.
  • one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the arrangement direction.
  • the diode section 80 of this example multiple dummy trench sections 30 are provided along the arrangement direction.
  • no gate trench section 40 is provided in the diode section 80 of this example.
  • one or more gate trench sections 40 are arranged at a predetermined interval along the arrangement direction of each trench.
  • the gate conductive section inside the gate trench section 40 is electrically connected to the gate metal layer 50, and a gate potential is applied to it.
  • one or more dummy trench sections 30 may be arranged at a predetermined interval along the arrangement direction. A potential different from the gate potential is applied to the dummy conductive section inside the dummy trench section 30.
  • the dummy conductive section in this example is electrically connected to the emitter electrode 52, and an emitter potential is applied to it.
  • one or more gate trench sections 40 and one or more dummy trench sections 30 may be alternately formed along the arrangement direction.
  • the dummy trench sections 30 are arranged at predetermined intervals along the arrangement direction in the diode section 80 and the boundary region 90.
  • the transistor section 70 may be composed of only the gate trench sections 40 without the dummy trench sections 30.
  • the gate trench portion 40 in this example may have two extension portions 41 (parts of the trench that are linear along the extension direction) that extend along an extension direction perpendicular to the arrangement direction, and a connection portion 43 that connects the two extension portions 41.
  • the extension direction in FIG. 2A is the Y-axis direction.
  • connection portion 43 is curved when viewed from above.
  • the dummy trench section 30 is provided between the extension portions 41 of the gate trench section 40.
  • One dummy trench section 30 or multiple dummy trench sections 30 may be provided between the extension portions 41.
  • the dummy trench section 30 may have a linear shape extending in the extension direction, and may have an extension portion 31 and a connection portion 33, similar to the gate trench section 40.
  • the semiconductor device 100 may include both a linear dummy trench section 30 that does not have a connection portion 33 and a dummy trench section 30 that has a connection portion 33.
  • the direction in which the extension portion 41 of the gate trench section 40 or the extension portion 31 of the dummy trench section 30 extends long in the extension direction is defined as the longitudinal direction of the trench section.
  • the longitudinal direction of the gate trench section 40 or the dummy trench section 30 may coincide with the extension direction.
  • the extension direction and the longitudinal direction are the Y-axis direction.
  • the arrangement direction in which multiple gate trench portions 40 or dummy trench portions 30 are arranged is the transverse direction of the trench portion.
  • the transverse direction may coincide with the arrangement direction.
  • the transverse direction may also be perpendicular to the longitudinal direction.
  • the longitudinal direction and the transverse direction are perpendicular.
  • the arrangement direction and the transverse direction are the X-axis direction.
  • the gate conductive portion in the gate trench portion 40 and the gate runner portion 51 are connected at a connection portion 43 at the tip of the gate trench portion 40.
  • the gate trench portion 40 may be provided so as to protrude toward the gate runner portion 51 side in the extension direction (Y-axis direction) beyond the dummy trench portion 30.
  • the protruding portion of the gate trench portion 40 is connected to the gate runner portion 51.
  • the diffusion depth of the well region 17 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30.
  • the ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 17 when viewed from above. In other words, at the ends of each trench portion in the Y-axis direction, the bottoms of each trench portion in the depth direction are covered by the well region 17. This makes it possible to reduce electric field concentration at the bottoms of each trench portion.
  • a mesa portion refers to a region inside the semiconductor substrate 10 that is sandwiched between two adjacent trench portions.
  • the upper end of the mesa portion is the upper surface of the semiconductor substrate 10.
  • the depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion.
  • the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending in the extension direction (Y-axis direction) along the trench portion.
  • the boundary region 90 is provided on the diode section 80 side in the transistor section 70. That is, the boundary region 90 is provided adjacent to the diode section 80 in the transistor section 70.
  • the boundary region 90 may have a dummy trench section 30 and may be a region in which a collector region 22 is provided on the back side of the semiconductor substrate 10. Both ends of the mesa section of the boundary region 90 in the trench arrangement direction may be in contact with the dummy trench section 30. All of the trench sections of the boundary region 90 may be dummy trench sections 30.
  • the boundary region 90 may include a gate trench section 40. In the boundary region 90 of this example, the first conductivity type emitter region 12 is not provided in the mesa section on the front surface 21 side of the semiconductor substrate 10.
  • the boundary region 90 may have a base region 14 on the front surface 21 and may have an anode region 19.
  • the boundary region 90 may have an emitter region 12 or a contact region 15 on the front surface 21.
  • the boundary region 90 has an anode region 19 and a contact region 15 on the front surface 21.
  • FIG. 2A shows the positions of the collector region 22 and the cathode region 82 provided on the back surface side of the semiconductor substrate 10 when projected onto the front surface 21.
  • Mesa portion 71 is a mesa portion provided in transistor portion 70.
  • Mesa portion 81 is a mesa portion provided in diode portion 80.
  • Mesa portion 91 is a mesa portion provided in boundary region 90.
  • the extension portion of each trench portion may be considered as one trench portion. In other words, the region sandwiched between two extension portions may be considered as a mesa portion.
  • Each mesa portion is provided with a base region 14 or an anode region 19.
  • the region located closest to the gate metal layer 50 is referred to as the base region 14-e or anode region 19-e.
  • the base region 14-e or anode region 19-e located at one end in the extension direction of each mesa portion is shown, but the base region 14-e or anode region 19-e is also located at the other end of each mesa portion.
  • At least one of the emitter region 12 of the first conductivity type and the contact region 15 of the second conductivity type may be provided in the region sandwiched between the base region 14-e or the anode region 19-e in a top view.
  • the emitter region 12 is N+ type
  • the contact region 15 is P+ type.
  • the emitter region 12 and the contact region 15 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.
  • the mesa portion 71 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10.
  • the emitter region 12 is provided in contact with the gate trench portion 40.
  • the mesa portion 71 in contact with the gate trench portion 40 may have a contact region 15 exposed on the upper surface of the semiconductor substrate 10.
  • the contact regions 15 and emitter regions 12 in the mesa portion 71 are each provided from one trench portion to the other trench portion in the X-axis direction. As an example, the contact regions 15 and emitter regions 12 in the mesa portion 71 are alternately arranged along the trench extension direction (Y-axis direction).
  • the mesa portion 71 in this example has thinned regions 60 and non-thinned regions 65.
  • the thinned regions 60 and non-thinned regions 65 are arranged alternately in the trench extension direction.
  • the thinned regions 60 will be described later.
  • the non-thinning region 65 has an emitter region 12 and a contact region 15. In the trench extension direction, one or more emitter regions and one or more contact regions are arranged alternately in a continuous manner. Contact regions 15 may be provided at both ends of the non-thinning region 65 in the trench extension direction. That is, the emitter region 12 of the non-thinning region 65 may be sandwiched between two adjacent contact regions 15 in the trench extension direction. The number of repetitions of the emitter region 12 and the contact region 15 in the non-thinning region 65 is not limited to this example.
  • one emitter region 12 and two contact regions 15 are arranged in a continuous manner, but two emitter regions 12 and three contact regions 15 may be arranged in a continuous manner, or three emitter regions 12 and four contact regions 15 may be arranged in a continuous manner.
  • the mesa portion 81 of the diode portion 80 does not have an emitter region 12, but may have an emitter region 12.
  • An anode region 19 is provided on the upper surface of the mesa portion 81.
  • a contact region 15 may be provided on the upper surface of the mesa portion 81.
  • a contact region 15 may be provided in contact with each anode region 19-e.
  • an anode region 19 may be provided in the region sandwiched between the contact regions 15 on the upper surface of the mesa portion 81.
  • the anode region 19 may be disposed in the entire region sandwiched between the contact regions 15 in the trench extension direction.
  • a contact hole 54 is provided above each mesa portion.
  • the contact hole 54 is arranged in a region sandwiched between the base region 14-e or the anode region 19-e along the trench extension direction.
  • the contact holes 54 are provided above the contact region 15, the base region 14, the anode region 19, and the emitter region 12.
  • the contact holes 54 are not provided in the regions corresponding to the base region 14-e, the anode region 19-e, and the well region 17.
  • the contact holes 54 may be arranged in the center of the mesa portion 71 in the trench arrangement direction (X-axis direction).
  • the contact holes 54 are provided with a trench contact portion 58. The trench contact portion 58 will be described later.
  • an N+ type cathode region 82 is provided in a region adjacent to the underside of the semiconductor substrate 10.
  • the doping concentration of the cathode region 82 is higher than the doping concentration of the drift region 18.
  • a P+ type collector region 22 may be provided in the region of the underside of the semiconductor substrate 10 where the cathode region 82 is not provided.
  • the cathode region 82 and the collector region 22 are provided between the rear surface 23 of the semiconductor substrate 10 and a buffer region 20 described below.
  • the boundary 78 between the cathode region 82 and the collector region 22 is indicated by a dashed line.
  • the cathode region 82 is disposed away from the well region 17 in the Y-axis direction. This ensures a distance between the cathode region 82 and the P-type region (well region 17) that has a relatively high doping concentration and is formed deep, improving the breakdown voltage and suppressing the injection of holes from the well region 17.
  • the end of the cathode region 82 in the Y-axis direction is disposed farther from the well region 17 than the end of the contact hole 54 in the Y-axis direction.
  • the end of the cathode region 82 in the Y-axis direction may be disposed between the well region 17 and the contact hole 54.
  • the mesa portion 91 of the boundary region 90 is provided with an anode region 19.
  • the boundary region 90 may have multiple mesa portions 91.
  • the mesa portion 91 may have a base region 14 instead of the anode region 19.
  • the anode region 19 will be described later.
  • FIG. 2B is a diagram showing an example of an XZ cross section including the a-a' cross section in FIG. 2A.
  • the XZ cross section including the a-a' cross section is an XZ plane passing through the emitter region 12 in the transistor section 70.
  • the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the XZ cross section including the a-a' cross section.
  • the emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.
  • the drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10.
  • the drift region 18 is, as an example, N-type.
  • the drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein.
  • the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.
  • the buffer region 20 is a region of the first conductivity type provided closer to the rear surface 23 of the semiconductor substrate 10 than the drift region 18.
  • the buffer region 20 is provided closer to the rear surface 23 of the semiconductor substrate 10 than the center in the depth direction of the semiconductor substrate 10.
  • the buffer region 20 is, as an example, N-type.
  • the doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18.
  • the buffer region 20 may function as a field stop layer that prevents the depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type and the cathode region 82 of the first conductivity type.
  • the collector region 22 and the cathode region 82 are provided on the rear surface 23 of the semiconductor substrate 10.
  • the collector region 22 is provided below the buffer region 20 in the transistor section 70.
  • the cathode region 82 is provided below the buffer region 20 in the diode section 80.
  • the boundary 78 between the collector region 22 and the cathode region 82 may be the boundary between the transistor section 70 and the diode section 80.
  • the collector electrode 24 is formed on the rear surface 23 of the semiconductor substrate 10.
  • the collector electrode 24 is formed of a conductive material such as a metal. At least a portion of the collector electrode 24 may be formed of a metal such as aluminum (Al) or a metal alloy such as an aluminum-silicon alloy (AlSi) or an aluminum-silicon-copper alloy (AlSiCu).
  • the base region 14 is a second conductivity type region provided above the drift region 18 in the mesa portion 71 and the mesa portion 91.
  • the base region 14 is provided in contact with the gate trench portion 40.
  • the base region 14 may be provided in contact with the dummy trench portion 30.
  • the anode region 19 is a second conductivity type region provided above the drift region 18 in the mesa portion 91 and the mesa portion 81.
  • the anode region 19 is provided in contact with the dummy trench portion 30.
  • the anode region 19 may be provided in contact with the gate trench portion 40.
  • the doping concentration of the anode region 19 may be the same as that of the base region 14, or may be lower than that of the base region 14.
  • the maximum doping concentration of the anode region 19 may be smaller than or equal to the maximum doping concentration of the base region 14.
  • the maximum doping concentration of the anode region 19 in this example is smaller than the maximum doping concentration of the base region 14.
  • the depth of the anode region 19 may be deeper, shallower, or equal to that of the base region 14.
  • the depth of the anode region 19 in this example is substantially equal to the depth of the base region 14.
  • the integral value of the doping concentration of the anode region 19 integrated along the depth direction of the semiconductor substrate 10 may be smaller than or equal to the integral value of the doping concentration of the base region 14. In this example, the integral value of the doping concentration of the anode region 19 is smaller than the integral value of the doping concentration of the base region 14.
  • the emitter region 12 is provided closer to the front surface 21 than the drift region 18, and has a higher doping concentration than the drift region 18.
  • the emitter region 12 is provided above the base region 14 in the mesa portion 71.
  • the emitter region 12 may be provided in contact with the gate trench portion 40.
  • the emitter region 12 may or may not be in contact with the dummy trench portion 30.
  • the emitter region 12 does not have to be provided in the mesa portion 91.
  • the contact region 15 is provided above the base region 14 in the mesa portion 91.
  • the contact region 15 is provided in contact with the gate trench portion 40 in the mesa portion 91.
  • the contact region 15 may be provided on the front surface 21 of the mesa portion 71.
  • the accumulation region 16 is a region of a first conductivity type that is provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18.
  • the accumulation region 16 is an N+ type, for example.
  • the accumulation region 16 is provided in the mesa portion 71.
  • the accumulation region 16 may also be provided in the mesa portion 81 and the mesa portion 91.
  • the accumulation region 16 is provided in contact with the gate trench portion 40.
  • the accumulation region 16 may or may not be in contact with the dummy trench portion 30.
  • the doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18.
  • One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the front surface 21.
  • Each trench portion is provided from the front surface 21 to the drift region 18.
  • each trench portion also penetrates these regions to reach the drift region 18.
  • the trench portion penetrating the doped region is not limited to being manufactured in the order of forming the doped region and then the trench portion.
  • the trench portion penetrating the doped region also includes a case where a doped region is formed between the trench portions after the trench portions are formed.
  • the gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 formed on the front surface 21.
  • the gate insulating film 42 is formed to cover the inner wall of the gate trench.
  • the gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench.
  • the gate conductive portion 44 is formed inside the gate trench, further inward than the gate insulating film 42.
  • the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10.
  • the gate conductive portion 44 is formed of a conductive material such as polysilicon.
  • the gate trench portion 40 is covered by an interlayer insulating film 38 on the front surface 21.
  • the gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side, across the gate insulating film 42, in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer on the surface layer of the interface of the base region 14 that contacts the gate trench.
  • the dummy trench portion 30 may have the same structure as the gate trench portion 40.
  • the dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side.
  • the dummy insulating film 32 is formed to cover the inner wall of the dummy trench.
  • the dummy conductive portion 34 is formed inside the dummy trench and is formed further inward than the dummy insulating film 32.
  • the dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10.
  • the dummy trench portion 30 is covered by an interlayer insulating film 38 on the front surface 21.
  • the interlayer insulating film 38 is provided on the front surface 21.
  • An emitter electrode 52 is provided above the interlayer insulating film 38.
  • One or more contact holes 54 are provided in the interlayer insulating film 38 to electrically connect the emitter electrode 52 to the semiconductor substrate 10.
  • Contact holes 55 and 56 may also be provided penetrating the interlayer insulating film 38.
  • the trench contact portion 58 is provided in a mesa portion between two adjacent trench portions among the multiple trench portions, extending from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10.
  • the trench contact portion 58 may be provided extending from the upper end of the interlayer insulating film 38 to the inside of the semiconductor substrate 10.
  • the trench contact portion 58 is provided in the contact hole 54.
  • the trench contact portion 58 may have a plug portion 59.
  • the plug portion 59 may be tungsten.
  • the trench contact portion 58 may have a barrier metal 53 formed of titanium or a titanium compound, etc.
  • the plug region 13 is provided at the lower end of the trench contact portion 58 and is a region of the second conductivity type having a higher doping concentration than the base region 14.
  • the plug region 13 may be provided at the lower end of the trench contact portion 58, extending in the trench extension direction.
  • the plug region 13 may be provided over the entire lower end of the trench contact portion 58.
  • the plug region 13 may be formed in a region overlapping with a region into which a first conductivity type dopant for forming the emitter region 12 is ion-implanted, and may be formed in a region overlapping with a region into which a second conductivity type dopant for forming the contact region 15 is ion-implanted.
  • the plug region 13 may also be provided in the boundary region 90 and the diode portion 80.
  • the semiconductor device 100 of this example does not have a lifetime control section with a lifetime killer, but may have a lifetime control section.
  • the semiconductor device 100 does not need to have a lifetime killer region on the front surface 21 side of the center in the depth direction of the semiconductor substrate 10.
  • the semiconductor device 100 of this example can suppress the injection of holes without forming a lifetime control section, thereby reducing the switching loss Err during reverse recovery.
  • the semiconductor device 100 of this example can improve the latch-up resistance by providing the trench contact portion 58. In this way, by providing the thinning region 60 and the trench contact portion 58, the semiconductor device 100 can reduce the switching loss Err during reverse recovery while suppressing the decrease in latch-up resistance caused by providing the thinning region 60.
  • FIG. 3A shows an example of a YZ cross section including the b-b' cross section in FIG. 2A.
  • the YZ cross section including the b-b' cross section is a YZ plane that passes through the mesa portion 71 of the transistor portion 70.
  • the b-b' cross section is a cross section that does not pass through the contact hole 54.
  • the lower end of the trench contact portion 58 is indicated by a dashed line.
  • the thinning region 60 is provided between two adjacent non-thinning regions 65 in the trench extension direction.
  • the thinning region 60 may be provided between two of the multiple emitter regions 12 that are adjacent in the trench extension direction.
  • the thinning region 60 may also be provided between two of the multiple contact regions 15 that are adjacent in the trench extension direction.
  • the thinning region 60 may be of the first conductivity type, may be of the second conductivity type, or may include both a region of the first conductivity type and a region of the second conductivity type.
  • the thinning region 60 may have a lower doping concentration of the second conductivity type than the contact region 15.
  • a lower doping concentration of the second conductivity type may mean that the doping concentration of the second conductivity type is lower than the contact region 15 when the thinning region 60 is of the second conductivity type.
  • the thinning region 60 may include at least one of the base region 14, the drift region 18, or the anode region 19.
  • the thinning region 60 in this example is the base region 14.
  • the interval P12 is the interval between two adjacent emitter regions 12 in the trench extension direction.
  • the interval P12 may be the interval between the emitter region 12 of one of two adjacent non-thinning regions 65 and the emitter region 12 of the other non-thinning region 65.
  • the interval P12 affects the saturation voltage of the transistor section 70 and the magnitude of the main current flowing through the transistor section 70 during a short circuit, and may therefore be determined according to the required electrical characteristics of the transistor section 70.
  • the ratio ⁇ is the ratio of the spacing P12 to the length L65 of the non-thinning region 65 in the trench extension direction.
  • the ratio ⁇ may be 1.5 or more and 20 or less.
  • the ratio ⁇ may be 2 or more and 2.5 or more.
  • the ratio ⁇ may be 5 or less and 3 or less.
  • the spacing P12 may be 3 ⁇ m or more and 10 ⁇ m or less. If the spacing P12 becomes large and the area of the contact region 15 increases, holes become more likely to be injected, but by providing the thinning region 60, the injection of holes can be more effectively suppressed.
  • Length L15 is the length of the contact region 15 on the front surface 21 in the trench extension direction.
  • Length L12 is the length of the emitter region 12 on the front surface 21 in the trench extension direction. Length L15 may be greater than length L12.
  • Length L60 is the length of the thinned region 60 on the front surface 21 in the trench extension direction.
  • Length L65 is the length of the non-thinned region 65 on the front surface 21 in the trench extension direction. Length L60 may be shorter or longer than length L65.
  • Thickness Z14 is the thickness of the base region 14 below the contact region 15. In this example, thickness Z14 is the distance from the bottom end of the contact region 15 to the top end of the accumulation region 16 in the depth direction of the semiconductor substrate 10. In this example, the base region 14 covers both the bottom and side surfaces of the non-thinning region 65.
  • the multiple contact regions 15 may be provided at both ends of the emitter region 12 in the trench extension direction.
  • the contact regions 15 may be in contact with the emitter region 12 at the front surface 21. If the emitter region 12 and the contact regions 15 are not in contact with each other at the front surface 21, the dimensions of the emitter region 12 are likely to vary due to the influence of diffusion of the implanted ions. On the other hand, if the emitter region 12 and the contact regions 15 are in contact with each other at the front surface 21, the dimensions of the emitter region 12 can be determined by the position of the contact regions 15, making it easier to reduce the variation in saturation current.
  • the accumulation region 16 in this example is provided above the drift region 18.
  • the accumulation region 16 in this example is provided between the base region 14 and the drift region 18, but may be omitted.
  • the contact region 15 may cover the end of the emitter region 12 in the extension direction from the underside. This reduces the voltage drop when holes pass through and suppresses latch-up.
  • FIG. 3B shows a modified YZ cross section including the b-b' cross section in FIG. 2A.
  • the semiconductor device 100 of this example differs from the semiconductor device 100 of FIG. 3A in the structure of the thinning region 60. In this example, differences from the semiconductor device 100 of FIG. 3A will be particularly described, and other points may be the same as those of the semiconductor device 100 of FIG. 3A.
  • the thinning region 60 of this example has a first thinning portion 61 and a second thinning portion 62.
  • the first thinning portion 61 is provided between two adjacent emitter regions 12.
  • the first thinning portion 61 may be provided in contact with the contact region 15 on the front surface 21 of the semiconductor substrate 10.
  • the thinning region 60 may have a plurality of first thinning portions 61 sandwiching second thinning portions 62 in the trench extension direction.
  • the first thinning portion 61 may be the base region 14 or the anode region 19. In this example, the first thinning portion 61 is the base region 14.
  • the second thinning portion 62 is provided between two adjacent emitter regions 12 and is provided in contact with the first thinning portion 61 on the front surface 21.
  • the doping concentration of the second thinning portion 62 is different from the doping concentration of the first thinning portion 61.
  • the second thinning portion 62 may be provided on the front surface 21 between two first thinning portions 61 that are adjacent in the trench extension direction among the multiple first thinning portions 61.
  • the second thinning portion 62 in this example has a first conductivity type that has a lower doping concentration than the emitter region 12.
  • the second thinning portion 62 in this example is a drift region 18.
  • the drift region 18, which is the second thinning portion 62 is provided between the multiple base regions 14, which are the first thinning portions 61, in the trench extension direction.
  • the length L14 is the length of the base region 14 in the trench extension direction.
  • the length L14 may be greater than the length L65.
  • the second thinning portion 62 may be sandwiched between the first thinning portions 61 along the extension direction of the gate trench portion 40.
  • the contact region 15 is provided between the emitter region 12 and the first thinning portion 61, which are adjacent in the trench extension direction. On the front surface 21, one end of the contact region 15 may contact the emitter region 12, and the other end of the contact region 15 may contact the first thinning portion 61.
  • the first thinning portion 61 may be provided below the contact region 15. In this example, the first thinning portion 61 covers the side and bottom surfaces of the contact region 15.
  • the electric field strength will be high. However, by sandwiching the first thinning section 61 between the second thinning section 62 and the contact region 15, the electric field strength can be alleviated.
  • Length L60 is the length of thinning region 60 provided on front surface 21 in the trench extension direction.
  • Length L61 is the length of first thinning portion 61 provided on front surface 21 in the trench extension direction.
  • Thickness Z61 is the thickness of first thinning portion 61 provided below contact region 15 in the depth direction of semiconductor substrate 10.
  • Length L61 may be greater than or equal to thickness Z61.
  • Length L61 may be greater than or equal to 0.1 ⁇ m and less than or equal to 2.0 ⁇ m. In this way, by adjusting length L61, electric field concentration on the side surface of contact region 15 can be alleviated, improving the electric field strength.
  • Length L61 is the length of the first thinning portion 61 on the front surface 21 in the trench extension direction.
  • Length L62 is the length of the second thinning portion 62 on the front surface 21 in the trench extension direction.
  • length L62 of the second thinning portion 62 in the trench extension direction may be greater than length L61 of the first thinning portion 61 in the trench extension direction.
  • length L62 of the second thinning portion 62 in the trench extension direction may be greater than length L12 of the emitter region 12 in the trench extension direction.
  • FIG. 3C shows a modified YZ cross section including the b-b' cross section in FIG. 2A.
  • the semiconductor device 100 of this example differs from the semiconductor device 100 of FIG. 3B in the structure of the second thinning section 62. In this example, differences from the semiconductor device 100 of FIG. 3B will be particularly described, and other points may be the same as the semiconductor device 100 of FIG. 3B.
  • the second thinning-out portion 62 may have a second conductivity type with a lower doping concentration than the base region 14.
  • the second thinning-out portion 62 is the anode region 19.
  • the anode region 19 is P-- type.
  • the lower ends of the first thinning portion 61 and the second thinning portion 62 may be at the same depth position.
  • the lower end of the anode region 19, which is the second thinning portion 62 coincides with the lower end of the base region 14.
  • the lower end of the anode region 19, which is the second thinning portion 62 may be the upper end of the accumulation region 16.
  • FIG. 4A is a modified example of an enlarged view of region A in FIG. 1.
  • the semiconductor device 100 of this example differs from the semiconductor device 100 of FIG. 2A in the position where the contact hole 54 is provided.
  • the differences from the semiconductor device 100 of FIG. 2A will be particularly described, and other points may be the same as the semiconductor device 100 of FIG. 2A.
  • the structure of the c-c' cross section may be the same as the structure of the a-a' cross section of FIG. 2A, or it may be different.
  • the contact hole 54 in this example is provided above the non-thinning region 65, but is not provided above the thinning region 60.
  • the trench contact portion 58 in this example is provided above the non-thinning region 65, but is not provided above the thinning region 60.
  • the contact hole 54 and the trench contact portion 58 may be formed in the same region.
  • the trench contact portion 58 may be formed using the interlayer insulating film 38 as a mask.
  • the region in which the contact hole 54 is provided in the top view may be a trench contact formation region, and the region in which the contact hole 54 is not provided in the top view may be a trench contact non-formation region.
  • the region in which the trench contact portion 58 is provided is referred to as a trench contact formation region, and the region in which the trench contact portion 58 is not provided in the top view is referred to as a trench contact non-formation region.
  • the plug region 13 may be formed using the interlayer insulating film 38 as a mask.
  • the plug region 13 is formed in the region in which the contact hole 54 is provided in the top view, but the plug region 13 is not formed in the region in which the contact hole 54 is not provided.
  • the plug region 13 does not need to be provided in the thinning region 60. By not providing the plug region 13 in the thinning region 60, it becomes easier to further suppress the injection of holes.
  • contact holes 54 are provided in the thinning region 60, a Schottky junction may be formed, increasing leakage current.
  • the mesa portion 71 does not have contact holes 54 in the thinning region 60, making it easier to suppress leakage current from the thinning region 60.
  • FIG. 4B shows an example of a YZ cross section including the d-d' cross section in FIG. 4A.
  • the YZ cross section including the d-d' cross section is a YZ plane passing through the mesa portion 71 of the transistor portion 70.
  • the d-d' cross section is a cross section passing through the contact hole 54.
  • the thinned-out region 60 in this example has a base region 14 as the first thinned-out portion 61, as in FIG. 3B, and has a drift region 18 as the second thinned-out portion 62.
  • the semiconductor device 100 in this example does not have an accumulation region 16, but may have an accumulation region 16.
  • the semiconductor device 100 of this example has a plug region 13 below the trench contact portion 58.
  • the plug region 13 may extend in the trench extension direction below the trench contact portion 58 from one end to the other end of the trench contact portion 58.
  • the plug region 13 may be provided in contact with the sidewall of the trench contact portion 58 at the end of the trench contact portion 58 in the trench extension direction.
  • the plug region 13 of this example is provided in the non-thinning region 65, but a part of it may be provided in the thinning region 60.
  • the interlayer insulating film 38 is provided above the thinning region 60 on the front surface 21.
  • the interlayer insulating film 38 is provided above the first thinning portion 61 and the second thinning portion 62.
  • the interlayer insulating film 38 covers both the first thinning portion 61 and the second thinning portion 62 provided on the front surface 21.
  • the interlayer insulating film 38 has a contact hole 54 formed above the non-thinning region 65, and does not cover the non-thinning region 65 in the d-d' cross section.
  • the semiconductor device 100 of this example does not have a Schottky junction between the drift region 18 (the second thinning-out portion 62) and the emitter electrode 52, making it easier to suppress leakage current.
  • the contact hole 54 and the trench contact portion 58 are provided only above the non-thinning-out region 65, but they may also be provided above the first thinning-out portion 61 and may also be provided above the second thinning-out portion 62.
  • FIG. 4C shows a modified YZ cross section including the d-d' cross section in FIG. 4A.
  • the semiconductor device 100 of this example differs from the semiconductor device 100 of FIG. 4B in that it has an accumulation region 16.
  • the differences from the semiconductor device 100 of FIG. 4B will be particularly described, and other points may be the same as the semiconductor device 100 of FIG. 4B.
  • the accumulation region 16 is provided extending in the trench extension direction below the thinning regions 60 and non-thinning regions 65 that are repeatedly arranged in the trench extension direction.
  • the lower end of the base region 14 is provided in contact with the upper end of the accumulation region 16.
  • the lower end of the second thinning portion 62 which is the drift region 18, is provided in contact with the upper end of the accumulation region 16.
  • the lower end of the base region 14 may be the same as the lower end of the second thinning portion 62, which is the drift region 18. Note that, although the accumulation region 16 in this example is provided below both the thinning region 60 and the non-thinning region 65, it may be provided below only one of them.
  • FIG. 4D shows a modified YZ cross section including the d-d' cross section in FIG. 4A.
  • the semiconductor device 100 of this example differs from the semiconductor device 100 of FIG. 4C in that it has a first conductivity type region 162 as the second thinning section 62.
  • the differences from the semiconductor device 100 of FIG. 4C will be particularly described, and other points may be the same as the semiconductor device 100 of FIG. 4C.
  • the first conductivity type region 162 is a region of the first conductivity type having a higher doping concentration than the drift region 18.
  • the first conductivity type region 162 may be formed by ion implantation of a first conductivity type dopant separately from the accumulation region 16.
  • the first conductivity type dopant for forming the first conductivity type region 162 may be selectively ion implanted using a mask.
  • the first conductivity type dopant for forming the first conductivity type region 162 may be selectively ion implanted only into the region where the second thinning out portion 62 is to be formed.
  • the first conductivity type dopant for forming the first conductivity type region 162 may also be ion implanted into regions other than the second thinning out portion 62, such as the first thinning out portion 61 or the non-thinning out region 65.
  • FIG. 4E shows a modified YZ cross section including the d-d' cross section in FIG. 4A.
  • the semiconductor device 100 of this example differs from the semiconductor device 100 of FIG. 4B in that it has an anode region 19 as the second thinning section 62.
  • the differences from the semiconductor device 100 of FIG. 4B will be particularly described, and other points may be the same as the semiconductor device 100 of FIG. 4B.
  • the anode region 19 may be sandwiched between two adjacent base regions 14 in the trench extension direction.
  • the base region 14 and the anode region 19 may be formed by ion implanting a dopant for forming the anode region 19 into the entire surface of the mesa portion 71, and then selectively ion implanting a dopant for forming the base region 14.
  • the base region 14 and the anode region 19 may be formed by selectively ion implanting a dopant for forming the anode region 19 into the region where the anode region 19 is to be formed, and then selectively ion implanting a dopant for forming the base region 14 into the region where the base region 14 is to be formed.
  • Depth D19 is the distance from the front surface 21 to the lower end of the anode region 19 in the depth direction of the semiconductor substrate 10.
  • Depth D14 is the distance from the front surface 21 to the lower end of the base region 14 in the depth direction of the semiconductor substrate 10.
  • Depth D19 may be greater than depth D14. That is, the lower end of the anode region 19 may be deeper than the lower end of the base region 14 in the depth direction of the semiconductor substrate 10.
  • the lower end of the anode region 19 may be deeper than the lower ends of the emitter region 12 and the contact region 15 in the depth direction of the semiconductor substrate 10.
  • the lower end of the anode region 19 may be deeper than the lower end of the trench contact portion 58 in the depth direction of the semiconductor substrate 10.
  • FIG. 4F shows a modified YZ cross section including the d-d' cross section in FIG. 4A.
  • the depth of the anode region 19 differs from that of the semiconductor device 100 of FIG. 4E.
  • differences from the semiconductor device 100 of FIG. 4E will be particularly described, and other points may be the same as those of the semiconductor device 100 of FIG. 4E.
  • Depth D19 is smaller than depth D14. That is, the lower end of the anode region 19 may be shallower than the lower end of the base region 14 in the depth direction of the semiconductor substrate 10. The lower end of the anode region 19 may be deeper than the lower ends of the emitter region 12 and the contact region 15 in the depth direction of the semiconductor substrate 10. The lower end of the anode region 19 may be deeper than the lower end of the trench contact portion 58 in the depth direction of the semiconductor substrate 10.
  • FIG. 4G shows a modified YZ cross section including the d-d' cross section in FIG. 4A.
  • the semiconductor device 100 of this example differs from the semiconductor device 100 of FIG. 4F in that it has an accumulation region 16.
  • the differences from the semiconductor device 100 of FIG. 4F will be particularly described, and other points may be the same as the semiconductor device 100 of FIG. 4F.
  • the accumulation region 16 is provided extending in the trench extension direction below the thinning out regions 60 and non-thinning out regions 65 which are repeatedly arranged in the trench extension direction.
  • the lower end of the base region 14 is provided in contact with the upper end of the accumulation region 16.
  • the lower end of the anode region 19 is provided in contact with the upper end of the accumulation region 16.
  • the lower end of the base region 14 may be the same as the lower end of the anode region 19. Note that although the accumulation region 16 in this example is provided below both the thinning out regions 60 and the non-thinning out regions 65, it may be provided below only one of them.
  • FIG. 5A shows a modified top view of the mesa portion 71.
  • This example shows an example of the structure of the mesa portion 71, and may be applied to the mesa portion 71 of other semiconductor devices 100.
  • the semiconductor device 100 of this example has a non-thinning region 67.
  • the non-thinning region 67 is a region in which some of the thinning regions 60, which are regularly arranged in the trench extension direction, have been changed to non-thinning regions 65.
  • the non-thinning region 67 includes an emitter region 12 and a contact region 15.
  • the emitter region 12 of the non-thinning region 67 is sandwiched between two contact regions 15 adjacent to each other in the trench extension direction.
  • the non-thinning region 67 in this example has the same structure as the non-thinning region 65, but may be different.
  • the doping concentration of each region of the non-thinning region 67 and the width of each region in the trench extension direction may be the same as those of the non-thinning region 65.
  • Length L67 is the length of the non-thinning region 67 on the front surface 21 in the trench extension direction. Length L67 may be the same as or different from length L65. In this example, length L67 is the same as length L65.
  • the length L12' of the emitter region 12 in the non-thinning region 67 may be the same as or different from the length L12 of the emitter region 12 in the non-thinning region 65.
  • the length L12' of the emitter region 12 in the non-thinning region 67 in this example is the same as the length L12 of the emitter region 12 in the non-thinning region 65.
  • the length L15' of the contact region 15 in the non-thinning region 67 may be the same as or different from the length L15 of the contact region 15 in the non-thinning region 65.
  • the length L15' of the contact region 15 in the non-thinning region 67 in this example is the same as the length L15 of the contact region 15 in the non-thinning region 65.
  • FIG. 5B shows a modified top view of the mesa portion 71.
  • an example of the structure of the mesa portion 71 is shown, and may be applied to the mesa portion 71 of other semiconductor devices 100.
  • the mesa portion 71 of this example differs from the mesa portion 71 of FIG. 5A in the structure of the non-thinning region 67.
  • the differences from the mesa portion 71 of FIG. 5A will be particularly described, and other points may be the same as the mesa portion 71 of FIG. 5A.
  • the non-thinning region 67 has a different structure from the non-thinning region 65. At least one of the doping concentration of each region of the non-thinning region 67 or the width of each region in the trench extension direction may be different from that of the non-thinning region 65. In this example, each region of the non-thinning region 67 has the same doping concentration as each region of the non-thinning region 65, but may be different.
  • the length L15' of the contact region 15 in the non-thinning region 67 is different from the length L15 of the contact region 15 in the non-thinning region 65.
  • the length L15' of the contact region 15 in the non-thinning region 67 in this example is smaller than the length L15 of the contact region 15 in the non-thinning region 65, but may be larger.
  • the length L12' of the emitter region 12 in the non-thinning region 67 in this example is the same as the length L12 of the emitter region 12 in the non-thinning region 65, but may be different.
  • the length L12' of the emitter region 12 in the non-thinning region 67 may be larger or smaller than the length L12 of the emitter region 12 in the non-thinning region 65.
  • adjusting the area of the contact region 15 in the non-thinning region 67 makes it easier to adjust the magnitude of hole injection.
  • FIG. 6A shows the dependence of the switching loss Err during reverse recovery on the ratio ⁇ .
  • the vertical axis shows the switching loss Err (a.u.) during reverse recovery, and the horizontal axis shows the ratio ⁇ .
  • Graph Gc shows the characteristics of the semiconductor device of the comparative example, and graph G100 shows the characteristics of the semiconductor device 100.
  • the semiconductor device of the comparative example is a semiconductor device that does not have the thinning region 60. When the ratio ⁇ of the spacing P12 to the length L65 in the trench extension direction of the non-thinning region 65 increases, the P-type region in the transistor section 70 increases and the injection of holes increases, which tends to increase the switching loss Err during reverse recovery.
  • the semiconductor device 100 is more likely to reduce the switching loss Err during reverse recovery even when the ratio ⁇ increases.
  • the ratio ⁇ exceeds 1.5, the effect of reducing the switching loss Err during reverse recovery in the graph G100 of the semiconductor device 100 becomes more noticeable compared to the graph Gc of the semiconductor device of the comparative example.
  • the ratio ⁇ may be 1.5 or more, 2.0 or more, 2.5 or more, or 3.0 or more.
  • the ratio ⁇ may be 20 or less, 10 or less, 7.0 or less, 5.0 or less, or 3.0 or less.
  • Figure 6B shows the dependence of the saturation current Isat of the collector current on the ratio ⁇ .
  • the vertical axis shows the saturation current Isat (a.u.) of the collector current, and the horizontal axis shows the ratio ⁇ .
  • the saturation current Isat decreases. The reduction in the saturation current Isat improves the short circuit resistance.
  • the semiconductor device 100 includes a thinning region 60, which increases the ratio ⁇ and improves short-circuit resistance while suppressing the switching loss Err during reverse recovery.
  • the semiconductor device 100 also includes a trench contact portion 58, which further improves latch-up resistance.
  • FIG. 7 shows an example of a method for manufacturing the semiconductor device 100.
  • an example of a method for manufacturing the semiconductor device 100 is shown, and the order of each step may be changed as appropriate.
  • Steps S100 and S102 are an example of a stage for forming the thinning region 60.
  • the anode region 19 is formed above the drift region 18.
  • the base region 14 is formed above the drift region 18. If the base region 14 and the anode region 19 have the same doping concentration, the base region 14 and the anode region 19 may be formed simultaneously in a common process.
  • the base region 14 and the anode region 19 may be formed by selectively ion-implanting a dopant of the second conductivity type according to the structure of the thinning region 60.
  • the base region 14 is formed after the anode region 19 is formed, but the anode region 19 may be formed after the base region 14 is formed.
  • the region of the base region 14 and the anode region 19 with a lower doping concentration may be formed first.
  • the thinning region 60 may form the base region 14 by ion-implanting a dopant of the second conductivity type into the anode region 19 of the transistor section 70 after the anode region 19 is formed in the transistor section 70 and the diode section 80.
  • the doping concentration of the base region 14 may be higher than the doping concentration of the anode region 19.
  • step S104 a plurality of trench portions are formed on the front surface 21 of the semiconductor substrate 10.
  • the dummy trench portion 30 and the gate trench portion 40 may be formed simultaneously in a common process, or the dummy trench portion 30 and the gate trench portion 40 may be formed separately.
  • the thinning region 60 may be formed.
  • a non-thinning region 65 is formed on the front surface 21 of the semiconductor substrate 10.
  • the non-thinning region 65 is formed in a mesa portion 71 between multiple trench portions.
  • the contact region 15 may be formed after the emitter region 12 is formed, or the emitter region 12 may be formed after the contact region 15 is formed.
  • the non-thinning region 67 may be formed simultaneously with the non-thinning region 65.
  • trench contact portion 58 is formed.
  • Plug region 13 may be formed by forming contact hole 54 for trench contact portion 58 and then ion-implanting a dopant of the second conductivity type into the lower end of contact hole 54.
  • trench contact portion 58 may be formed by filling contact hole 54 with barrier metal 53 and plug portion 59.

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011136272A1 (ja) * 2010-04-28 2011-11-03 日産自動車株式会社 半導体装置
JP2019021931A (ja) * 2012-09-12 2019-02-07 富士電機株式会社 逆導通型絶縁ゲートバイポーラトランジスタの製造方法および逆導通型絶縁ゲートバイポーラトランジスタ
JP2020072137A (ja) * 2018-10-30 2020-05-07 三菱電機株式会社 半導体装置
JP2021073714A (ja) * 2017-12-14 2021-05-13 富士電機株式会社 半導体装置およびその製造方法
JP2021144998A (ja) * 2020-03-10 2021-09-24 株式会社デンソー 半導体装置
JP2023135082A (ja) * 2022-03-15 2023-09-28 富士電機株式会社 半導体装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011136272A1 (ja) * 2010-04-28 2011-11-03 日産自動車株式会社 半導体装置
JP2019021931A (ja) * 2012-09-12 2019-02-07 富士電機株式会社 逆導通型絶縁ゲートバイポーラトランジスタの製造方法および逆導通型絶縁ゲートバイポーラトランジスタ
JP2021073714A (ja) * 2017-12-14 2021-05-13 富士電機株式会社 半導体装置およびその製造方法
JP2020072137A (ja) * 2018-10-30 2020-05-07 三菱電機株式会社 半導体装置
JP2021144998A (ja) * 2020-03-10 2021-09-24 株式会社デンソー 半導体装置
JP2023135082A (ja) * 2022-03-15 2023-09-28 富士電機株式会社 半導体装置

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