WO2025041217A1 - Circuit à semi-conducteur quantique - Google Patents

Circuit à semi-conducteur quantique Download PDF

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Publication number
WO2025041217A1
WO2025041217A1 PCT/JP2023/029960 JP2023029960W WO2025041217A1 WO 2025041217 A1 WO2025041217 A1 WO 2025041217A1 JP 2023029960 W JP2023029960 W JP 2023029960W WO 2025041217 A1 WO2025041217 A1 WO 2025041217A1
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Prior art keywords
node
quantum
amplifier circuit
potential
circuit
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English (en)
Japanese (ja)
Inventor
悟 秋山
雄介 菅野
大 久本
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Hitachi Ltd
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Hitachi Ltd
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Priority to PCT/JP2023/029960 priority Critical patent/WO2025041217A1/fr
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/40—Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control

Definitions

  • This disclosure relates to quantum semiconductor circuits.
  • Patent Document 2 JP Patent Publication 2023-3726A discloses a method in which quantum bit information, which is a complementary signal from a quantum bit array that holds complementary information, is output from a single-electron element connected to the quantum bit, and the signal is further amplified by a differential amplifier circuit connected to this.
  • the drain-source voltage of the single-electron element becomes the input differential potential of the differential amplifier circuit.
  • an input differential potential necessary for the differential circuit operation is generated, which causes the sweep current value of the single-electron element to fluctuate, and may prevent the desired read operation from being performed.
  • FIG. 1 is a circuit diagram of a quantum bit unit of a quantum semiconductor according to an embodiment.
  • FIG. 2 is a diagram of a readout circuit for amplifying a quantum bit signal of a quantum semiconductor according to an embodiment.
  • FIG. 3 is a diagram showing an operation sequence of a readout circuit for amplifying a quantum bit signal of a quantum semiconductor according to an embodiment.
  • FIG. 4 is a block circuit diagram of an integrated quantum bit of a quantum semiconductor and a readout circuit according to an embodiment.
  • FIG. 5 is a block circuit diagram of an integrated quantum bit array of a quantum semiconductor according to an embodiment.
  • FIG. 6 is a block circuit diagram of the entire quantum semiconductor chip according to the embodiment.
  • FIG. 7 is a block diagram showing a quantum computer using a quantum semiconductor according to an embodiment.
  • FIG. 8 is a diagram showing a method of mounting a quantum semiconductor chip in a dilution refrigerator according to the embodiment.
  • the common portion (part excluding the branch number) of the reference sign including the branch number may be used, and when describing elements of the same type with distinction, the reference sign including the branch number may be used.
  • the quantum bit transistor shown in Figure 1 when describing individual quantum bit transistors without making any distinction between them, they may be written as "quantum bit transistor MQ", and when describing individual quantum bit transistors with distinction between them, they may be written as "quantum bit transistor MQ0", “quantum bit transistor MQ1", etc.
  • Figure 1 is a circuit diagram SQBA of the quantum bit section of the quantum semiconductor according to the embodiment.
  • Figure 1 shows a reservoir RSEV that supplies electrons or holes, which are charged particles that form the quantum bit, a quantum bit transistor MQ for storing the quantum bit and drive wiring XQ0 to XQ3 that drives them, a quantum control transistor MJ and control wiring XJ0 to XJ4 that drives them, single electron elements SETU0 to SETU10 and SETD0 to SETD10 arranged above and below the quantum bit transistor MQ and the quantum control transistor MJ, drive end wiring XQE0 to XQE3 electrically connected to the gate electrodes, and the control wiring XJ0 to XJ4.
  • reservoir elements MR00, MR10 and source control elements MS00, MS10 for forming a potential distribution required to send charged particles to the quantum bit transistor MQ, and reservoir control lines GRE and source control lines GSR for controlling them.
  • the Source in the figure is a terminal line for controlling the potential relationship with RSEV. Note that in the configuration of Figure 1, two transistor elements are shown as one unit. This is because in advanced silicon semiconductor processes, it is difficult to physically separate the gate electrodes (metal gates) of each transistor element, and a configuration like that of Figure 1 may be easier to manufacture.
  • the charged particles which are quantum bits
  • the quantum bit transistor MQ from the reservoir RSEV.
  • an appropriate potential is applied to the gate electrodes of the quantum bit transistor MQ and the quantum control transistor MJ, and the charged particles are transferred one by one from the reservoir.
  • a standby potential e.g., negative potential
  • the quantum bits are stored (initialized) one by one in the quantum transistor, a standby potential (e.g., negative potential) is applied to the gate electrode of the quantum control transistor MJ, and the potential barriers on both ends of the quantum bit are set high, so that the quantum bit is controlled to stay at a specified position in the quantum transistor MQ.
  • a static magnetic field is applied to the entire quantum semiconductor using a superconducting magnet installed in the dilution refrigerator that implements the quantum semiconductor.
  • the static magnetic field aligns the spin state of the charged particles to the ground state (for example, all quantum bits are in an up spin state), so the state of the quantum bit is initialized.
  • the initialized quantum bit precesses at a certain resonance frequency.
  • a current in the opposite direction is passed through the quantum bit control wiring XJ0 and the quantum bit drive wiring XJ1.
  • a current in the opposite direction By passing a current in the opposite direction, a local magnetic field is generated in the quantum bit transistors MQ00 and MQ10.
  • the resonance frequency of the quantum bits MQ00 and MQ10 is shifted by a certain amount due to the influence of the generated local magnetic field.
  • microwaves By irradiating microwaves with the same frequency as this shifted resonance frequency, it becomes possible to selectively rotate the quantum bits.
  • the quantum bits MQ00 and MQ10 all have the same resonance frequency, so the two quantum bits are rotated in the same way.
  • MQ00 and MQ10 are rotated to be in an up spin state.
  • the quantum bits MQ01, MQ11, MQ02, MQ12, MQ03, and MQ13 which do not generate a local magnetic field, the quantum bits will maintain their ground state even if they are irradiated with microwaves for the same period of time because their resonance frequencies are different from the microwaves.
  • the arrows in the example in Figure 1 show that MQ01 and MQ11 are downspins, MQ02 and MQ12 are upspins, and MQ03 and MQ13 are downspins.
  • the quantum state is maintained while the quantum bit drive wiring XQ and quantum bit control wiring XJ are controlled to the desired potential to move the quantum information to the positions of MQ03 and MQ13.
  • the quantum bits stored in MQ03 and MQ13 move to the source terminal line Source by the tunnel current mechanism with a certain probability, and then return to the specified position of the original quantum bit element (Elsermann mechanism).
  • This behavior of the quantum bit causes the gate potential of the single electron element SU13 arranged opposite MQ03 to fluctuate, and a specified current fluctuation (for example, 500pA fluctuates to 50pA) appears on the quantum read data line QDOU.
  • the gate potential of the single electron element SD03 arranged opposite MQ13 fluctuates, and a specified current fluctuation (for example, 500pA fluctuates to 50pA) appears on the quantum read data line QDOD.
  • a specified current fluctuation for example, 500pA fluctuates to 50pA
  • the same quantum bit information is output to the quantum read data lines QDOU and QDOD.
  • the tunnel current mechanism described above does not occur, and no current fluctuations appear in the quantum read data lines.
  • FIG. 2 shows a quantum bit read current amplifier circuit according to an embodiment of the present invention.
  • the amplifier circuit of this embodiment is composed of a first amplifier circuit that controls the gate electrode TPA, a second amplifier circuit that controls the gate electrode TRD, a local data line LDO that electrically connects the first amplifier circuit and the second amplifier circuit, and a third amplifier circuit that is composed of a so-called differential amplifier to which a PMOS level holder is connected and in which the gate electrodes of an NMOS pair are differential inputs.
  • the gate potential of the NMOS transistor on one side of the third amplifier circuit is connected to the drain of the second amplifier circuit to form the read data line RDO.
  • the quantum bit read line QDO, local data line LDO, and read data line RDO are connected to precharge circuits that precharge to the array precharge voltage VPCHA, half precharge voltage VPCH, and precharge voltage VPCHS, respectively, and precharge activation signals PCH, PCH1, and PCH2 are connected to the gate electrodes.
  • the third amplifier circuit starts amplifying by asserting the amplifier circuit activation signal PSN high, and outputs an amplified difference potential to the data lines DT and DB.
  • the amplified difference potential output to the data line pair is amplified to the full amplitude potential of the power supply voltages VCCA and VSSA by asserting the common source activation signals CSN and CSP of the so-called cross-coupled amplifier circuit in the subsequent stage, and the information is latched in the cross-coupled amplifier circuit.
  • the latched signal potential is further transmitted to an information device outside the quantum semiconductor via the external data line EXRT in the buffer circuit in the subsequent stage.
  • the data line pair DT and DB are precharged, for example to the VCCA level, using a data line precharge circuit consisting of a pMOS equalizer and a level holder pMOS element.
  • the quantum bit readout line QDO may also be referred to as the "first node,” the local data line LDO may also be referred to as the "second node,” and the readout data line RDO may also be referred to as the "third node.”
  • a node refers to an element (such as a connection line) that allows electrical connection of elements that make up a circuit.
  • the first precharge potential (array precharge voltage VPCHA) of the first node may be 0.1 mV to 20 mV
  • the second precharge potential (half precharge voltage VPCH) of the second node may be greater than the first precharge potential of the first node and less than the third precharge potential of the third node (for example, it may be around 1/2 or 1/2 of the high level of the power supply voltage)
  • the third precharge potential (precharge voltage VPCHS) of the third node may be equivalent to the high level of the power supply voltage.
  • MOS transistors (Metal Oxide Semiconductor Field Effect Transistor) (NMOS transistors) 21a and 21b in the first amplifier circuit are a type of MISFET (Metal Insulator Semiconductor Field Effect Transistor).
  • MISFET Metal Insulator Semiconductor Field Effect Transistor
  • the circuit including the MOS transistor 21b is sometimes referred to as the "first charge transfer MIS circuit.”
  • the MOS transistor (PMOS transistor) 22a and the MOS transistor (NMOS transistor) 22b in the second amplifier circuit are a type of MISFET, and the circuit including the MOS transistor 22b is sometimes referred to as the "second charge transfer MIS circuit.”
  • each precharge circuit which is a component circuit of the amplifier circuit, is activated, and the quantum read data line QDO is precharged to approximately 10 mV, the local data line LDO to 0.375 V, and the read data line RDO to 0.75 V. Since the state of the quantum bit transistor MQ is determined, by setting the gate electrode of the single-electron element to the desired potential, the gate potential of the single-electron element SETU8 or SETD8 changes depending on the state of the quantum bit element, and a signal is output to the quantum read data line QDO.
  • the TPA potential is set to, for example, 270 mV to activate the first amplifier circuit.
  • the capacitance value of the capacitor for stable operation is on the order of femtofarads (10 ⁇ 15 ). Furthermore, it is preferable to ensure that these capacitance values have the relationship CQDL > CLDL.
  • the principle of the amplification operation at this time is the same as that of the first amplifier circuit, and it is preferable to set the value of the stabilizing capacitance CLDL to be larger than the parasitic capacitance value of the read data line RDO. By setting it in this way, the charge amount of the read data line RDO is efficiently discharged to the local data line LDO. Also, as shown in FIG. 3, after the signal level corresponding to the information stored in the quantum bit is amplified and output to the read data line RDO, a reference voltage (for example, 600 mV) is input to the reference potential side of the NMOS differential input of the third amplifier circuit.
  • a reference voltage for example, 600 mV
  • the activation signal PSN of the third amplifier circuit is turned on at a timing when it can be determined whether the potential of the read data line RDO is higher (dashed line) or lower (solid line) than the reference voltage VREF.
  • the activation signal PSN of the third amplifier circuit is turned on at a timing when the potential difference between the reference voltage and the high potential and the potential difference between the low potential become the same potential difference.
  • FIG. 4 is a block circuit diagram showing the connection relationship between the quantum bit array SQBA and the quantum bit read current amplifier circuit of this embodiment.
  • Each drive wiring and control wiring of the quantum bit array SQBA is input to so-called NAND circuits arranged in the drive circuits DRVU and DRVD arranged above and below it.
  • selector circuits SELU and SELD are arranged adjacent to the drive circuits.
  • a low active signal line MWLB is input to this selector circuit, and its inverted signal line SXJT is input to the drive circuit.
  • each control wiring of the quantum bit read current amplifier circuit is illustrated as being arranged and wired so as to pass over the amplifier circuit, but it is also advisable to arrange the aforementioned low active signal line MWLB so as to pass over this amplifier circuit.
  • FIG. 5 is a block circuit diagram QBITARRAY that integrates a quantum semiconductor quantum bit array according to this embodiment.
  • quantum bit arrays SQBA are arranged in 256 rows x 256 columns. Since one quantum bit array SQBA has 4 quantum bits, the total is 256k quantum bits. Since there are some circuit blocks that are not necessary at the ends of the repeated arrangement, an example is shown in which dummy quantum bit read current amplifier circuits DMYSA and dummy selector circuits DMYSELU and DMYSELD are arranged to prevent manufacturing defects. Arranging the circuit blocks in this orderly manner has the advantage of improving chip yield.
  • FIG. 6 is a block circuit diagram QBA of the entire quantum semiconductor chip of this embodiment.
  • the block circuit diagram QBA includes the address buffer ADDRESS BUFFER, column address buffer COLUMN ADDRESS BUFFER, column address counter COLUMN ADDRESS COUNTER, row address buffer ROW ADDRESS BUFFER, refresh counter REFRESH COUNTER, quantum bit bank select QBANK SELECT, quantum mode register QMODE RESISTER, row decoder ROW DEC, column decoder COLUMN DEC, main sense amplifier MAIN AMP, quantum bit array QBIT ARRAY, data input buffer Din BUFFER, data output buffer Dout BUFFER, data buffer DQS BUFFER, delay locked loop DLL, control logic CONTROL LOGIC, clock CLK, /CLK, clock enable signal CKE, chip select signal /CS, row address strobe signal /RAS, column address strobe signal /CAS, write enable signal /WE, data strobe signal DQS, and data DQ.
  • the block circuit diagram of this embodiment is an application of the configuration of a general-purpose DRAM.
  • the clocks CLK and /CLK are input from the part equivalent to the system bus, and the clock enable signal CKE is asserted to control the control logic to generate commands.
  • Various signals such as chip select signals, row address strobe signals, column address strobe signals, and write enable signals are input in the desired bit pattern, and the control logic generates various commands such as precharging the QBITARRAY, activating the QBITARRAY (in this case, activating the quantum bit drive signal XQ), and read operations (in this case, activating the quantum bit read current amplifier circuit).
  • the data is transferred to various address buffers (ROW ADDRESS BUFFER, COLUMN ADDRESS BUFFER), and the drive signals and control signals for the selected bits are appropriately asserted in the row decoder circuit, column address counter, and column decoder circuit in the subsequent stages.
  • the quantum mode register selects the mode of the QBA circuit of this embodiment, such as operating in a test mode or in an error correction mode. It also sets the quantum operation mode, such as rotating the quantum bit by 90 degrees or swapping with an adjacent quantum bit.
  • the signal latched to the power supply level by the quantum bit read current amplifier of this embodiment is transferred to the main amplifier.
  • the data of the main amplifier is transferred to the outside of the quantum semiconductor chip QBA as a data DQ signal via the data output buffer. By appropriately using the timing and data strobe signal generated by the delay-locked loop circuit, the data signal can be exchanged with an external device at the desired timing.
  • the data to be written to the quantum semiconductor chip QBA is input from the data input buffer and written to the quantum bit array QBTARRAY via the main amplifier.
  • an appropriate command generation pattern is input to the quantum mode register, and the quantum bit drive signal and quantum bit control signal are set to the desired potential.
  • the quantum bit array of this embodiment is increased in capacity, stable data transmission and reception can be performed by applying the embodiment of FIG. 6.
  • Figure 7 shows the connection relationship between the quantum semiconductor QBA of the present invention, the analog chip CAC that inputs control signals for controlling the quantum semiconductor QBA, and the digital processing device CDU that inputs control signals for controlling the analog chip CAC.
  • a quantum computer is configured as an entire system by logically and electrically connecting these.
  • the analog chip CAC is preferably configured using a classical computer, that is, an integrated LSI using the so-called CMOS process.
  • the digital processing device CDU is preferably a processing device that applies semiconductor chips using the CMOS process, like the analog chip CAC.
  • the digital processing device CDU may be a general personal computer (PC). It is also possible to incorporate a software module that generates the desired control signals into the PC and use it.
  • PC personal computer
  • FIG 8 shows an implementation method using the quantum semiconductor QBA, analog chip CAC, digital processing unit CDU, and dilution refrigerator 10 according to the embodiment.
  • the dilution refrigerator 10 is separated by a housing Frame and a room temperature plate RT-PL to separate the air atmosphere outside the dilution refrigerator 10 from the vacuum atmosphere inside the dilution refrigerator 10.
  • the degree of vacuum inside the housing Frame of the dilution refrigerator 10 is controlled by discharging air through a vacuum tube VC using a pump device installed outside the refrigerator 10.
  • the temperature inside the dilution refrigerator 10 is controlled by circulating diluted liquid helium in a pulse tube PulseTube shown in Figure 8.
  • Figure 8 shows an example in which two pulse tubes PulseTube are connected.
  • the diluted liquid helium is obtained by liquefying two isotopes of helium, 3He and 4He, and pouring the 3He phase into the 4He phase to dilute it.
  • multiple metal (mainly oxygen-free copper) plates (50K-PL (held at -223°C), 4K-PL (held at -269°C), PLA, PLB, mKPL (held at approximately -273°C)) are installed and stored inside the housing Frame of the dilution refrigerator 10.
  • the metal plates PLA and PLB are controlled at temperatures between 4K (-269°C) and mK (approximately -273°C).
  • the temperature is controlled and maintained in thermal equilibrium using temperature control heaters (not shown) mounted on each plate (50K-PL, 4K-PL, PLA, PLB, mKPL) and a temperature controller (not shown) installed outside the dilution refrigerator 10 that controls the amount of power input to the temperature control heaters.
  • diluted liquid helium is circulated from the pulse tube PulseTube to the heat sink Heatsink.
  • the metal plate 4K-PL and the metal plate mKPL, to which the heat sink Heatsink is connected are brought to an extremely low temperature via the heat sink Heatsink, through which diluted liquid helium circulates. Therefore, the metal plate 4K-PL and the metal plate mKPL can be placed in an extremely low temperature atmosphere of 10 mK to 100 mK.
  • the heat sink Heatsink can be said to be the first refrigerating tube, and the pulse tube PulseTube can be said to be the second refrigerating tube.
  • the metal plate mKPL can be said to be the first metal plate, and the metal plate 4K-PL can be said to be the second metal plate.
  • the quantum semiconductor QBA is mounted on the first cooling plate FGNDPLT of the quantum semiconductor QBA, which is placed below the metal plate mKPL.
  • the cooling plate FGNDPLT is thermally connected to the metal plate mKPL via cooling rods C0 to C3 (even-numbered sides C0 and C2 are not shown).
  • the heat sink Heatsink is a refrigerating tube that uses diluted liquid helium to cool the cooling plate FGNDPLT, which is a metal body.
  • the cooling plate FGNDPLT which is a metal body, is thermally connected to the metal plate mKPL via the cooling rods C0 to C3.
  • the quantum semiconductor QBA is not mounted directly on the metal plate mKPL, but is placed below the metal plate mKPL because quantum operation is performed while applying a static magnetic field to the quantum semiconductor QBA. Due to space limitations to place the magnet MAGNET for generating a static magnetic field on the bottom layer of the dilution refrigerator 10, the quantum semiconductor QBA is placed as shown in Figure 8 in the configuration example of the dilution refrigerator 10 of this embodiment.
  • the electrical signals required for quantum operation of the quantum semiconductor QBA are output from a control device (not shown) installed outside the dilution refrigerator 10, and the control signal among the electrical signals is electrically connected to the quantum semiconductor QBA via coaxial wiring CXE, CXO, and the power supply voltage and power supply current among the electrical signals are electrically connected to the quantum semiconductor QBA via DC twisted wiring TWE, TWO.
  • This disclosure provides a circuit that amplifies the read current when increasing the capacity of quantum semiconductors using an integrated LSI, and a technology that amplifies minute output currents in quantum bit cell circuits consisting of quantum bit elements and single-electron elements while minimizing fluctuations in the drain-source voltage of the single-electron element as much as possible so as not to impair the current amplification effect of the single-electron element.
  • the present disclosure makes it possible to provide a quantum computer with high quantum fidelity by maintaining a temperature extremely close to absolute zero when a large-capacity quantum semiconductor is operated in quantum mode.
  • ⁇ Modifications>> The invention (disclosure) made by the present inventor has been specifically described above based on an embodiment, but it goes without saying that the present disclosure is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the disclosure.
  • the present disclosure may be a silicon quantum bit semiconductor integrated circuit having the following configuration:
  • the silicon semiconductor quantum bit integrated circuit has a plurality of MISFETs of a first conductivity type and a plurality of MISFETs of a second conductivity type, and a first amplifier circuit, a second amplifier circuit, and a third amplifier circuit section that are composed of these.
  • the multiple MISFETs are composed of at least a first MISFET (Barrier), a second MISFET (Plunger), and a third MISFET (Barrier), and a reservoir node that shares electrons with the first MISFET is electrically connected to the drain of the first MISFET and the reservoir, the source of the first MISFET is connected to the drain of the second MISFET, the source of the second MISFET is connected to the drain of the third MISFET, and the drain of the third MISFET is connected to a ground potential (Drain).
  • the gate potentials of the first MISFET and the third MISFET are controlled to a desired level so that the electrons for quantum bit operation supplied from the reservoir are present at the interface between the semiconductor substrate on which the second MISFET is constructed and the gate oxide film of the second MISFET, and a fourth MISFET, a fifth MISFET (SET), and a sixth MISFET are positioned to face the first MISFET, the second MISFET, and the third MISFET.
  • the source of the fourth MISFET is connected to the drain of the fifth MISFET, the source of the fifth MISFET is connected to the drain of the sixth MISFET, and the source of the sixth MISFET is connected to a ground potential (VSSA).
  • VSSA ground potential
  • the second amplifier circuit is composed of a ninth MISFET (T_RD) of a first conductivity type and a tenth MISFET (PCH1) of a second conductivity type, the drain of the eighth MISFET, the source of the ninth MISFET and the drain of the tenth MISFET are electrically connected to form a second node (LDO), and the source of the tenth MISFET is connected to a second precharge potential (VPCH) of the second node.
  • T_RD MISFET
  • PCH1 tenth MISFET
  • the third amplifier circuit has a gate of an eleventh MISFET of a first conductivity type connected to the drain of the ninth MISFET, and a drain of a fourteenth MISFET of a second conductivity type electrically connected to the gate of the eleventh MISFET to form a third node (RDO), a source of the fourteenth MISFET connected to a third precharge potential (VPCHS) of the third node, and further has a twelfth MISFET of a first conductivity type and a thirteenth MISFET of a first conductivity type, a source of the twelfth MISFET, a source of the eleventh MISFET and a drain of the thirteenth MISFET are electrically connected, the eleventh MISFET and a drain are connected to a first data line (DT) and a second data line (DB), respectively, a first MISFET pair of first conductivity type having one gate and the other drain connected to each other and sources connected to the first source line, and a second MISFET pair of
  • the mutually connected nodes of the first MISFET pair are connected to the first data line (DT), the mutually connected nodes of the second MISFET pair are connected to the second data line (DB), a first stabilizing capacitance (CQDL) is connected to the first node (QDO), a second stabilizing capacitance (CLDL) is connected to the second node (LDO), a first power supply voltage (VCCA) and a second power supply voltage (VSSA) are supplied to the third amplifier circuit, the first power supply voltage and the third precharge potential are at the same level of potential, and the second precharge potential is a potential approximately intermediate between the first power supply voltage and the second power supply voltage, the first precharge potential is a potential lower than the second precharge potential, and when the electrons stored in the second MISFET are in an up spin state, an on current (ISET on) flows through the fifth MISFET to drive the first node (QDO) to a low level at a relatively high speed, and when the electrons stored in the second MISFET are in
  • the gate potential of the eighth MISFET is changed from the second power supply voltage to a first drive voltage, and the first difference potential is amplified to a second difference potential by transferring the charged charge of the second node LDO to the first node QDO, and immediately after the second difference potential of the second node LDO is sufficiently amplified, the gate potential of the eighth MISFET is changed from the first drive voltage to the second power supply voltage, and immediately thereafter, the gate potential of the ninth MISFET is changed to the second power supply voltage to a second drive voltage, and the charge at the third node RDO is transferred to the second node LDO, thereby amplifying the second difference potential to a third difference potential, and after the third node RDO reaches the third difference potential state, the gate potential of the thirteenth MISFET is changed from the second power supply voltage to a third drive voltage, thereby outputting a fourth difference potential to the first data line and the second
  • the circuit including the eighth MISFET may be referred to as the "first charge transfer MIS circuit.”
  • the circuit including the ninth MISFET may be referred to as the "second charge transfer MIS circuit.”
  • This disclosure can also have the following configurations:
  • a quantum bit array circuit including a plurality of quantum bit elements and a plurality of single-electron elements that detect the spin states of the plurality of quantum bit elements; a first node which is a quantum bit readout line that outputs a readout current representing a spin state from the quantum bit device; a quantum bit read current amplifier circuit connected to the first node; having The quantum bit read current amplifier circuit includes: configured to set the first node to a first precharge potential; The quantum bit read current amplifier circuit includes: a second node coupled to a second precharge potential higher than the first precharge potential; a first amplifier circuit including a first charge transfer MIS circuit electrically connected to the single-electron device via the first node and configured to transfer a charge stored in the second node to the first node; a second amplifier circuit including a second charge transfer MIS circuit electrically connected to the first amplifier circuit via the second node and electrically connected to a third amplifier circuit via a third node, the second charge transfer MIS circuit transferring a charge at the third node

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Abstract

L'invention concerne un circuit à semi-conducteur quantique qui comprend : un dispositif à électron unique (SET) qui détecte l'état d'un bit quantique de silicium ; un premier nœud (QDO) qui est connecté à un premier potentiel de précharge (VPCHA); un deuxième nœud (LDO) connecté à un deuxième potentiel de précharge (VPCH) étant supérieur au premier potentiel de précharge ; un premier circuit d'amplification qui est électriquement connecté au transistor à électron unique (SET) par l'intermédiaire du premier nœud (QDO) et a un premier circuit MIS de transfert de charge pour transférer la charge du second nœud (LDO) au premier nœud (QDO); un deuxième circuit d'amplification qui est électriquement connecté au premier circuit d'amplification par l'intermédiaire du deuxième nœud (LDO) et a un deuxième circuit MIS de transfert de charge pour transférer la charge d'un troisième nœud (RDO) au deuxième nœud (LDO); et un troisième circuit d'amplification qui délivre un potentiel à une ligne de données et effectue une amplification d'amplitude en réponse au fait que le troisième nœud (RDO) atteint un potentiel prescrit au moyen du premier circuit d'amplification et du deuxième circuit d'amplification.
PCT/JP2023/029960 2023-08-21 2023-08-21 Circuit à semi-conducteur quantique Pending WO2025041217A1 (fr)

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Publication number Priority date Publication date Assignee Title
US20200322144A1 (en) * 2017-10-17 2020-10-08 Crypto Quantique Limited Unique identifiers based on quantum effects
JP2022537172A (ja) * 2019-06-17 2022-08-24 マイクロソフト テクノロジー ライセンシング，エルエルシー 量子ビットのための電荷ロック回路及び制御システム
JP2023003726A (ja) * 2021-06-24 2023-01-17 学校法人帝京大学 量子装置、量子ビット読み出し装置および電子回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200322144A1 (en) * 2017-10-17 2020-10-08 Crypto Quantique Limited Unique identifiers based on quantum effects
JP2022537172A (ja) * 2019-06-17 2022-08-24 マイクロソフト テクノロジー ライセンシング，エルエルシー 量子ビットのための電荷ロック回路及び制御システム
JP2023003726A (ja) * 2021-06-24 2023-01-17 学校法人帝京大学 量子装置、量子ビット読み出し装置および電子回路

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