WO2025041217A1 - Quantum semiconductor circuit - Google Patents

Abstract

This quantum semiconductor circuit comprises: a single-electron device (SET) that senses the state of a silicon qubit; a first node (QDO) that is connected to a first precharge potential (VPCHA); a second node (LDO) that is connected to a second precharge potential (VPCH) being higher than the first precharge potential; a first amplification circuit that is electrically connected to the single-electron transistor (SET) via the first node (QDO) and has a first charge transfer MIS circuit for transferring the charge of the second node (LDO) to the first node (QDO); a second amplification circuit that is electrically connected to the first amplification circuit via the second node (LDO) and has a second charge transfer MIS circuit for transferring the charge of a third node (RDO) to the second node (LDO); and a third amplification circuit that outputs a potential to a data line and performs amplitude amplification in response to the third node (RDO) reaching a prescribed potential by means of the first amplification circuit and the second amplification circuit.

Description

Quantum Semiconductor Circuits

This disclosure relates to quantum semiconductor circuits.

There is great interest in building quantum computers that can perform at high speeds and in a cost-effective manner. Quantum computers use superconducting logic-based devices, which are typically cooled to cryogenic temperatures to function in a superconducting state. Patent Document 1 (JP 2021-523572 A) discloses a system that includes at least two sets of superconducting logic devices, a cooling apparatus adapted to cool the logic devices to a first operating temperature, and an interconnect that couples the superconducting logic devices.

Special Publication No. 2021-523572 JP 2023-3726 A

Sushil Subramanian, “Spin Qubits: Principles, Control/Readout Architectures, and Cryoelectronic Solutions”, The IEEE International Solid-State Circuits Conference (ISSCC), 2023

　So far, quantum semiconductors have been demonstrated to perform quantum operations of 1 to 100 qubits in an absolute zero atmosphere achieved by using dilution refrigerators and the like. However, a system with a medium number of qubits does not provide sufficient computer resources to analyze complex phenomena. On the other hand, if we try to secure sufficient computer resources by further increasing the number of qubits, it becomes important to highly integrate the readout circuit that detects and amplifies the output current that indicates the difference in the spin state of the qubits, the so-called Elsermann current. If the circuit scale (dimensions) of this readout circuit that reads out the information of one qubit is large, the size of the quantum semiconductor chip will increase due to the large qubit capacity, and as a result, there is a problem that the temperature of the absolute zero atmosphere, which is a necessary condition for quantum operation, will rise due to the increased current consumption of the chip.

Non-Patent Document 1 discloses a method of converting the difference in spin information within a quantum bit into a large or small current using a single-electron transistor, and reading out the large or small value of the single-electron transistor current outside the chip as a large or small impedance. This method requires large passive components such as inductors and capacitors, and has the problem of increasing chip size due to increased capacity, making it unsuitable for large-scale silicon quantum bits.

Patent Document 2 (JP Patent Publication 2023-3726A) discloses a method in which quantum bit information, which is a complementary signal from a quantum bit array that holds complementary information, is output from a single-electron element connected to the quantum bit, and the signal is further amplified by a differential amplifier circuit connected to this. In this method, the drain-source voltage of the single-electron element becomes the input differential potential of the differential amplifier circuit. As a result, an input differential potential necessary for the differential circuit operation is generated, which causes the sweep current value of the single-electron element to fluctuate, and may prevent the desired read operation from being performed.

In light of the above background, the objective of this disclosure is to provide a semiconductor quantum circuit that can amplify the minute current of a SET (Single Electron Transistor) and read out the quantum bit state with high precision, toward the realization of large-scale silicon quantum bits.

In order to solve the above problem, the semiconductor quantum circuit disclosed herein has a quantum bit array circuit including a plurality of quantum bit elements and a plurality of single-electron elements that detect the spin states of the plurality of quantum bit elements, a first node that is a quantum bit read line that outputs a read current representing the spin state from the quantum bit element, and a quantum bit read current amplifier circuit connected to the first node, the quantum bit read current amplifier circuit being configured to set the first node to a first precharge potential, and the quantum bit read current amplifier circuit being configured to connect a second node to a second precharge potential that is higher than the first precharge potential. The device includes a node, a first amplifier circuit electrically connected to the single-electron element via the first node and having a first charge transfer MIS circuit that transfers the charge of the second node to the first node, a second amplifier circuit electrically connected to the first amplifier circuit via the second node and a third amplifier circuit via a third node and having a second charge transfer MIS circuit that transfers the charge of the third node to the second node, and a third amplifier circuit that outputs a potential to a data line and amplifies the amplitude when the third node reaches a predetermined potential by the first amplifier circuit and the second amplifier circuit.

According to the present disclosure, in order to realize large-scale silicon quantum bits, it is possible to amplify the minute current of a SET (Single Electron Transistor) and read out the quantum bit state with high precision. Note that the effects described here are not necessarily limited to those described, and may be any of the effects described in this disclosure.

FIG. 1 is a circuit diagram of a quantum bit unit of a quantum semiconductor according to an embodiment. FIG. 2 is a diagram of a readout circuit for amplifying a quantum bit signal of a quantum semiconductor according to an embodiment. FIG. 3 is a diagram showing an operation sequence of a readout circuit for amplifying a quantum bit signal of a quantum semiconductor according to an embodiment. FIG. 4 is a block circuit diagram of an integrated quantum bit of a quantum semiconductor and a readout circuit according to an embodiment. FIG. 5 is a block circuit diagram of an integrated quantum bit array of a quantum semiconductor according to an embodiment. FIG. 6 is a block circuit diagram of the entire quantum semiconductor chip according to the embodiment. FIG. 7 is a block diagram showing a quantum computer using a quantum semiconductor according to an embodiment. FIG. 8 is a diagram showing a method of mounting a quantum semiconductor chip in a dilution refrigerator according to the embodiment.

In the following embodiments, where necessary for convenience, they will be explained divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc., of the other. Furthermore, in the following embodiments, when the number of elements, etc. (including numbers, values, amounts, ranges, etc.) is mentioned, it is not limited to that specific number, and may be more or less than the number of characteristics, except when otherwise specified or when it is clearly limited in principle to a specific number.

Furthermore, it goes without saying that in the following embodiments, the components (including element steps, etc.) are not necessarily essential, unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numerical values and ranges.

When describing elements of the same type without distinguishing between them, the common portion (part excluding the branch number) of the reference sign including the branch number may be used, and when describing elements of the same type with distinction, the reference sign including the branch number may be used. For example, taking the quantum bit transistor shown in Figure 1 as an example, when describing individual quantum bit transistors without making any distinction between them, they may be written as "quantum bit transistor MQ", and when describing individual quantum bit transistors with distinction between them, they may be written as "quantum bit transistor MQ0", "quantum bit transistor MQ1", etc.

The circuit configuration of the quantum semiconductor in this embodiment and its layout and wiring method will be described with reference to Figures 1 to 8. Figure 1 is a circuit diagram SQBA of the quantum bit section of the quantum semiconductor according to the embodiment. Figure 1 shows a reservoir RSEV that supplies electrons or holes, which are charged particles that form the quantum bit, a quantum bit transistor MQ for storing the quantum bit and drive wiring XQ0 to XQ3 that drives them, a quantum control transistor MJ and control wiring XJ0 to XJ4 that drives them, single electron elements SETU0 to SETU10 and SETD0 to SETD10 arranged above and below the quantum bit transistor MQ and the quantum control transistor MJ, drive end wiring XQE0 to XQE3 electrically connected to the gate electrodes, and the control wiring XJ0 to XJ4. Also shown are reservoir elements MR00, MR10 and source control elements MS00, MS10 for forming a potential distribution required to send charged particles to the quantum bit transistor MQ, and reservoir control lines GRE and source control lines GSR for controlling them. The Source in the figure is a terminal line for controlling the potential relationship with RSEV. Note that in the configuration of Figure 1, two transistor elements are shown as one unit. This is because in advanced silicon semiconductor processes, it is difficult to physically separate the gate electrodes (metal gates) of each transistor element, and a configuration like that of Figure 1 may be easier to manufacture.

There are various methods for quantum operations (quantum computation) using quantum bits, but in this embodiment in Figure 1, we will explain the case where the magnetic resonance method is used. First, the charged particles, which are quantum bits, are stored in the quantum bit transistor MQ from the reservoir RSEV. To store them, an appropriate potential is applied to the gate electrodes of the quantum bit transistor MQ and the quantum control transistor MJ, and the charged particles are transferred one by one from the reservoir. After the quantum bits are stored (initialized) one by one in the quantum transistor, a standby potential (e.g., negative potential) is applied to the gate electrode of the quantum control transistor MJ, and the potential barriers on both ends of the quantum bit are set high, so that the quantum bit is controlled to stay at a specified position in the quantum transistor MQ. Although not shown in the figure to avoid complicating the drawing, a static magnetic field is applied to the entire quantum semiconductor using a superconducting magnet installed in the dilution refrigerator that implements the quantum semiconductor. The static magnetic field aligns the spin state of the charged particles to the ground state (for example, all quantum bits are in an up spin state), so the state of the quantum bit is initialized. The initialized quantum bit precesses at a certain resonance frequency.

After storing the quantum bit in a specified position, for example, a current in the opposite direction is passed through the quantum bit control wiring XJ0 and the quantum bit drive wiring XJ1. By passing a current in the opposite direction, a local magnetic field is generated in the quantum bit transistors MQ00 and MQ10. The resonance frequency of the quantum bits MQ00 and MQ10 is shifted by a certain amount due to the influence of the generated local magnetic field. By irradiating microwaves with the same frequency as this shifted resonance frequency, it becomes possible to selectively rotate the quantum bits. In the example of Figure 1, the quantum bits MQ00 and MQ10 all have the same resonance frequency, so the two quantum bits are rotated in the same way. For example, MQ00 and MQ10 are rotated to be in an up spin state. Note that for the quantum bits MQ01, MQ11, MQ02, MQ12, MQ03, and MQ13, which do not generate a local magnetic field, the quantum bits will maintain their ground state even if they are irradiated with microwaves for the same period of time because their resonance frequencies are different from the microwaves. Using similar control, the arrows in the example in Figure 1 show that MQ01 and MQ11 are downspins, MQ02 and MQ12 are upspins, and MQ03 and MQ13 are downspins.

When reading out the information of the quantum manipulated quantum bits MQ00 and MQ10, the quantum state is maintained while the quantum bit drive wiring XQ and quantum bit control wiring XJ are controlled to the desired potential to move the quantum information to the positions of MQ03 and MQ13. The quantum bits stored in MQ03 and MQ13 move to the source terminal line Source by the tunnel current mechanism with a certain probability, and then return to the specified position of the original quantum bit element (Elsermann mechanism). This behavior of the quantum bit causes the gate potential of the single electron element SU13 arranged opposite MQ03 to fluctuate, and a specified current fluctuation (for example, 500pA fluctuates to 50pA) appears on the quantum read data line QDOU. Similarly, the gate potential of the single electron element SD03 arranged opposite MQ13 fluctuates, and a specified current fluctuation (for example, 500pA fluctuates to 50pA) appears on the quantum read data line QDOD. Thus, in the example of Figure 1, the same quantum bit information is output to the quantum read data lines QDOU and QDOD. On the other hand, if down spin information is stored in the quantum bit transistors MQ03 and MQ13, the tunnel current mechanism described above does not occur, and no current fluctuations appear in the quantum read data lines. In this way, if the difference in output current fluctuations due to differences in quantum bit states can be read and amplified to logic levels, that is, the power supply voltage levels of the LSI circuit, VCCA (0.75V) and VSSA (0V), it will be possible to output the quantum operation results outside the quantum semiconductor.

Figure 2 shows a quantum bit read current amplifier circuit according to an embodiment of the present invention. The amplifier circuit of this embodiment is composed of a first amplifier circuit that controls the gate electrode TPA, a second amplifier circuit that controls the gate electrode TRD, a local data line LDO that electrically connects the first amplifier circuit and the second amplifier circuit, and a third amplifier circuit that is composed of a so-called differential amplifier to which a PMOS level holder is connected and in which the gate electrodes of an NMOS pair are differential inputs.

The gate potential of the NMOS transistor on one side of the third amplifier circuit is connected to the drain of the second amplifier circuit to form the read data line RDO. In addition, the quantum bit read line QDO, local data line LDO, and read data line RDO are connected to precharge circuits that precharge to the array precharge voltage VPCHA, half precharge voltage VPCH, and precharge voltage VPCHS, respectively, and precharge activation signals PCH, PCH1, and PCH2 are connected to the gate electrodes. The third amplifier circuit starts amplifying by asserting the amplifier circuit activation signal PSN high, and outputs an amplified difference potential to the data lines DT and DB. The amplified difference potential output to the data line pair is amplified to the full amplitude potential of the power supply voltages VCCA and VSSA by asserting the common source activation signals CSN and CSP of the so-called cross-coupled amplifier circuit in the subsequent stage, and the information is latched in the cross-coupled amplifier circuit. The latched signal potential is further transmitted to an information device outside the quantum semiconductor via the external data line EXRT in the buffer circuit in the subsequent stage. The data line pair DT and DB are precharged, for example to the VCCA level, using a data line precharge circuit consisting of a pMOS equalizer and a level holder pMOS element.

The quantum bit readout line QDO may also be referred to as the "first node," the local data line LDO may also be referred to as the "second node," and the readout data line RDO may also be referred to as the "third node." A node refers to an element (such as a connection line) that allows electrical connection of elements that make up a circuit.

The first precharge potential (array precharge voltage VPCHA) of the first node may be 0.1 mV to 20 mV, the second precharge potential (half precharge voltage VPCH) of the second node may be greater than the first precharge potential of the first node and less than the third precharge potential of the third node (for example, it may be around 1/2 or 1/2 of the high level of the power supply voltage), and the third precharge potential (precharge voltage VPCHS) of the third node may be equivalent to the high level of the power supply voltage.

The MOS transistors (Metal Oxide Semiconductor Field Effect Transistor) (NMOS transistors) 21a and 21b in the first amplifier circuit are a type of MISFET (Metal Insulator Semiconductor Field Effect Transistor). The circuit including the MOS transistor 21b is sometimes referred to as the "first charge transfer MIS circuit."

The MOS transistor (PMOS transistor) 22a and the MOS transistor (NMOS transistor) 22b in the second amplifier circuit are a type of MISFET, and the circuit including the MOS transistor 22b is sometimes referred to as the "second charge transfer MIS circuit."

Next, the operational sequence of the amplifier circuit of this embodiment will be explained using Figure 3. Before operating this amplifier circuit, the spin state of the desired quantum bit is determined. During this period, each precharge circuit, which is a component circuit of the amplifier circuit, is activated, and the quantum read data line QDO is precharged to approximately 10 mV, the local data line LDO to 0.375 V, and the read data line RDO to 0.75 V. Since the state of the quantum bit transistor MQ is determined, by setting the gate electrode of the single-electron element to the desired potential, the gate potential of the single-electron element SETU8 or SETD8 changes depending on the state of the quantum bit element, and a signal is output to the quantum read data line QDO.

In this state, the TPA potential is set to, for example, 270 mV to activate the first amplifier circuit. At this time, it is preferable to additionally connect a stabilizing capacitance CQDL to the quantum bit read data line QDO and a stabilizing capacitance CLDL to the local data line LDO. Preferably, the capacitance value of the capacitor for stable operation is on the order of femtofarads (10 ⁻¹⁵ ). Furthermore, it is preferable to ensure that these capacitance values have the relationship CQDL > CLDL. With such circuit connections and potential relationships of each node, when the first amplifier circuit is activated, a signal potential that is amplified to a certain extent from the maximum initial difference potential that can be output to the quantum read data line, that is, within the range in which the single-electron device can operate, is output to the local data line LDO.

Specifically, in a situation where only an initial differential potential of 5 mV appears on the quantum read data line, a differential potential of about 20 mV is generated on the local data line LDO. If the potential fluctuation on the quantum read data line exceeds 5 mV, the amplification effect of the single electron device decreases, and there is a risk of erroneously amplifying the information held by the quantum bit. For this reason, in this embodiment, by adding a CQDL, it is possible to prevent the potential of the quantum read data line from fluctuating more than necessary. Also, preferably, the activation signal TPA of the first amplifier circuit, which has been asserted once, is negated. In this way, it is possible to hold a differential potential on the local data line LDO according to the information held in the quantum bit. A signal that is further amplified by this held potential difference can be output to the read data line RDO by asserting the activation signal TRD of the second amplifier circuit.

The principle of the amplification operation at this time is the same as that of the first amplifier circuit, and it is preferable to set the value of the stabilizing capacitance CLDL to be larger than the parasitic capacitance value of the read data line RDO. By setting it in this way, the charge amount of the read data line RDO is efficiently discharged to the local data line LDO. Also, as shown in FIG. 3, after the signal level corresponding to the information stored in the quantum bit is amplified and output to the read data line RDO, a reference voltage (for example, 600 mV) is input to the reference potential side of the NMOS differential input of the third amplifier circuit. The activation signal PSN of the third amplifier circuit is turned on at a timing when it can be determined whether the potential of the read data line RDO is higher (dashed line) or lower (solid line) than the reference voltage VREF. Preferably, the activation signal PSN of the third amplifier circuit is turned on at a timing when the potential difference between the reference voltage and the high potential and the potential difference between the low potential become the same potential difference. By controlling in this way, complementary signals are output to the data line pair DT, DB. After that, the latch-type cross-coupled amplifier circuit is activated, and the data line pair is fully amplified to the power supply voltage of the LSI circuit.

Figure 4 is a block circuit diagram showing the connection relationship between the quantum bit array SQBA and the quantum bit read current amplifier circuit of this embodiment. Each drive wiring and control wiring of the quantum bit array SQBA is input to so-called NAND circuits arranged in the drive circuits DRVU and DRVD arranged above and below it. In addition, selector circuits SELU and SELD are arranged adjacent to the drive circuits. A low active signal line MWLB is input to this selector circuit, and its inverted signal line SXJT is input to the drive circuit. By inputting this inverted signal line to the NAND circuit in the drive circuit, the gate electrode potential of the desired quantum bit transistor can be selectively controlled. Note that the block circuits shown with dashed lines in the figure are quantum bit read current amplifier circuits ((SACKTU), (SACTKD)), selector circuits ((SELU), (SELD)), and quantum read data lines ((QDOU), (QDOD)) connected to another quantum bit array arranged adjacent to the quantum bit array SQBA. In addition, each control wiring of the quantum bit read current amplifier circuit is illustrated as being arranged and wired so as to pass over the amplifier circuit, but it is also advisable to arrange the aforementioned low active signal line MWLB so as to pass over this amplifier circuit. By arranging and wiring in this way, it is possible to repeatedly arrange the block circuit of the embodiment of Figure 4 up, down, left, and right, making it possible to increase the quantum bit capacity.

FIG. 5 is a block circuit diagram QBITARRAY that integrates a quantum semiconductor quantum bit array according to this embodiment. The symbols in the figure are the same as those described in the embodiments of FIGS. 1 to 4, so their explanation will be omitted here. In the example shown in the figure, quantum bit arrays SQBA are arranged in 256 rows x 256 columns. Since one quantum bit array SQBA has 4 quantum bits, the total is 256k quantum bits. Since there are some circuit blocks that are not necessary at the ends of the repeated arrangement, an example is shown in which dummy quantum bit read current amplifier circuits DMYSA and dummy selector circuits DMYSELU and DMYSELD are arranged to prevent manufacturing defects. Arranging the circuit blocks in this orderly manner has the advantage of improving chip yield.

Figure 6 is a block circuit diagram QBA of the entire quantum semiconductor chip of this embodiment. The block circuit diagram QBA includes the address buffer ADDRESS BUFFER, column address buffer COLUMN ADDRESS BUFFER, column address counter COLUMN ADDRESS COUNTER, row address buffer ROW ADDRESS BUFFER, refresh counter REFRESH COUNTER, quantum bit bank select QBANK SELECT, quantum mode register QMODE RESISTER, row decoder ROW DEC, column decoder COLUMN DEC, main sense amplifier MAIN AMP, quantum bit array QBIT ARRAY, data input buffer Din BUFFER, data output buffer Dout BUFFER, data buffer DQS BUFFER, delay locked loop DLL, control logic CONTROL LOGIC, clock CLK, /CLK, clock enable signal CKE, chip select signal /CS, row address strobe signal /RAS, column address strobe signal /CAS, write enable signal /WE, data strobe signal DQS, and data DQ.

The block circuit diagram of this embodiment is an application of the configuration of a general-purpose DRAM. The clocks CLK and /CLK are input from the part equivalent to the system bus, and the clock enable signal CKE is asserted to control the control logic to generate commands. Various signals such as chip select signals, row address strobe signals, column address strobe signals, and write enable signals are input in the desired bit pattern, and the control logic generates various commands such as precharging the QBITARRAY, activating the QBITARRAY (in this case, activating the quantum bit drive signal XQ), and read operations (in this case, activating the quantum bit read current amplifier circuit). When the desired address information ADDRESS is input from an external control LSI chip, the data is transferred to various address buffers (ROW ADDRESS BUFFER, COLUMN ADDRESS BUFFER), and the drive signals and control signals for the selected bits are appropriately asserted in the row decoder circuit, column address counter, and column decoder circuit in the subsequent stages.

The quantum mode register selects the mode of the QBA circuit of this embodiment, such as operating in a test mode or in an error correction mode. It also sets the quantum operation mode, such as rotating the quantum bit by 90 degrees or swapping with an adjacent quantum bit. The signal latched to the power supply level by the quantum bit read current amplifier of this embodiment is transferred to the main amplifier. The data of the main amplifier is transferred to the outside of the quantum semiconductor chip QBA as a data DQ signal via the data output buffer. By appropriately using the timing and data strobe signal generated by the delay-locked loop circuit, the data signal can be exchanged with an external device at the desired timing. The data to be written to the quantum semiconductor chip QBA is input from the data input buffer and written to the quantum bit array QBTARRAY via the main amplifier. As described above, for the quantum operation required for writing data, an appropriate command generation pattern is input to the quantum mode register, and the quantum bit drive signal and quantum bit control signal are set to the desired potential. As described above, even when the quantum bit array of this embodiment is increased in capacity, stable data transmission and reception can be performed by applying the embodiment of FIG. 6.

Figure 7 shows the connection relationship between the quantum semiconductor QBA of the present invention, the analog chip CAC that inputs control signals for controlling the quantum semiconductor QBA, and the digital processing device CDU that inputs control signals for controlling the analog chip CAC. A quantum computer is configured as an entire system by logically and electrically connecting these. The analog chip CAC is preferably configured using a classical computer, that is, an integrated LSI using the so-called CMOS process. Similarly, the digital processing device CDU is preferably a processing device that applies semiconductor chips using the CMOS process, like the analog chip CAC. Simply put, the digital processing device CDU may be a general personal computer (PC). It is also possible to incorporate a software module that generates the desired control signals into the PC and use it.

Figure 8 shows an implementation method using the quantum semiconductor QBA, analog chip CAC, digital processing unit CDU, and dilution refrigerator 10 according to the embodiment. The dilution refrigerator 10 is separated by a housing Frame and a room temperature plate RT-PL to separate the air atmosphere outside the dilution refrigerator 10 from the vacuum atmosphere inside the dilution refrigerator 10. The degree of vacuum inside the housing Frame of the dilution refrigerator 10 is controlled by discharging air through a vacuum tube VC using a pump device installed outside the refrigerator 10. The temperature inside the dilution refrigerator 10 is controlled by circulating diluted liquid helium in a pulse tube PulseTube shown in Figure 8. Figure 8 shows an example in which two pulse tubes PulseTube are connected. The diluted liquid helium is obtained by liquefying two isotopes of helium, 3He and 4He, and pouring the 3He phase into the 4He phase to dilute it.

In the example of the dilution refrigerator 10 in Figure 8, multiple metal (mainly oxygen-free copper) plates (50K-PL (held at -223°C), 4K-PL (held at -269°C), PLA, PLB, mKPL (held at approximately -273°C)) are installed and stored inside the housing Frame of the dilution refrigerator 10. The metal plates PLA and PLB are controlled at temperatures between 4K (-269°C) and mK (approximately -273°C). The temperature is controlled and maintained in thermal equilibrium using temperature control heaters (not shown) mounted on each plate (50K-PL, 4K-PL, PLA, PLB, mKPL) and a temperature controller (not shown) installed outside the dilution refrigerator 10 that controls the amount of power input to the temperature control heaters. In the example of Figure 8, diluted liquid helium is circulated from the pulse tube PulseTube to the heat sink Heatsink. As a result, the metal plate 4K-PL and the metal plate mKPL, to which the heat sink Heatsink is connected, are brought to an extremely low temperature via the heat sink Heatsink, through which diluted liquid helium circulates. Therefore, the metal plate 4K-PL and the metal plate mKPL can be placed in an extremely low temperature atmosphere of 10 mK to 100 mK.

The heat sink Heatsink can be said to be the first refrigerating tube, and the pulse tube PulseTube can be said to be the second refrigerating tube. The metal plate mKPL can be said to be the first metal plate, and the metal plate 4K-PL can be said to be the second metal plate. The quantum semiconductor QBA is mounted on the first cooling plate FGNDPLT of the quantum semiconductor QBA, which is placed below the metal plate mKPL. The cooling plate FGNDPLT is thermally connected to the metal plate mKPL via cooling rods C0 to C3 (even-numbered sides C0 and C2 are not shown). In other words, the heat sink Heatsink is a refrigerating tube that uses diluted liquid helium to cool the cooling plate FGNDPLT, which is a metal body. The cooling plate FGNDPLT, which is a metal body, is thermally connected to the metal plate mKPL via the cooling rods C0 to C3. In this embodiment, the quantum semiconductor QBA is not mounted directly on the metal plate mKPL, but is placed below the metal plate mKPL because quantum operation is performed while applying a static magnetic field to the quantum semiconductor QBA. Due to space limitations to place the magnet MAGNET for generating a static magnetic field on the bottom layer of the dilution refrigerator 10, the quantum semiconductor QBA is placed as shown in Figure 8 in the configuration example of the dilution refrigerator 10 of this embodiment. Note that the electrical signals required for quantum operation of the quantum semiconductor QBA are output from a control device (not shown) installed outside the dilution refrigerator 10, and the control signal among the electrical signals is electrically connected to the quantum semiconductor QBA via coaxial wiring CXE, CXO, and the power supply voltage and power supply current among the electrical signals are electrically connected to the quantum semiconductor QBA via DC twisted wiring TWE, TWO. By implementing in the above manner, quantum operations and quantum computers as described in Figures 1 to 7 can be realized.

This disclosure provides a circuit that amplifies the read current when increasing the capacity of quantum semiconductors using an integrated LSI, and a technology that amplifies minute output currents in quantum bit cell circuits consisting of quantum bit elements and single-electron elements while minimizing fluctuations in the drain-source voltage of the single-electron element as much as possible so as not to impair the current amplification effect of the single-electron element.

The present disclosure makes it possible to provide a quantum computer with high quantum fidelity by maintaining a temperature extremely close to absolute zero when a large-capacity quantum semiconductor is operated in quantum mode.
<<Modifications>>
The invention (disclosure) made by the present inventor has been specifically described above based on an embodiment, but it goes without saying that the present disclosure is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the disclosure.

The above-mentioned embodiment has been described in detail to explain the present disclosure in an easy-to-understand manner, and is not necessarily limited to having all of the configurations described. In addition, it is possible to add, delete, or replace part of the configuration of the embodiment with other configurations.

In addition, for example, in the above embodiment, a silicon quantum semiconductor is used as an example, but the present invention is not limited to this and can also be applied to superconducting quantum semiconductors, etc.

The present disclosure may be a silicon quantum bit semiconductor integrated circuit having the following configuration:

The silicon semiconductor quantum bit integrated circuit has a plurality of MISFETs of a first conductivity type and a plurality of MISFETs of a second conductivity type, and a first amplifier circuit, a second amplifier circuit, and a third amplifier circuit section that are composed of these.

The multiple MISFETs are composed of at least a first MISFET (Barrier), a second MISFET (Plunger), and a third MISFET (Barrier), and a reservoir node that shares electrons with the first MISFET is electrically connected to the drain of the first MISFET and the reservoir, the source of the first MISFET is connected to the drain of the second MISFET, the source of the second MISFET is connected to the drain of the third MISFET, and the drain of the third MISFET is connected to a ground potential (Drain).

The gate potentials of the first MISFET and the third MISFET are controlled to a desired level so that the electrons for quantum bit operation supplied from the reservoir are present at the interface between the semiconductor substrate on which the second MISFET is constructed and the gate oxide film of the second MISFET, and a fourth MISFET, a fifth MISFET (SET), and a sixth MISFET are positioned to face the first MISFET, the second MISFET, and the third MISFET.

The source of the fourth MISFET is connected to the drain of the fifth MISFET, the source of the fifth MISFET is connected to the drain of the sixth MISFET, and the source of the sixth MISFET is connected to a ground potential (VSSA).

The first amplifier circuit is composed of a seventh MISFET (PCH) of a first conductivity type and an eighth MISFET (TPA) of a first conductivity type, and the drain of the fourth MISFET, the drain of the seventh MISFET, and the source of the eighth MISFET are electrically connected to form a first node (QDO), and the source of the seventh MISFET is connected to the first precharge potential (VPCHA) of the first node.

The second amplifier circuit is composed of a ninth MISFET (T_RD) of a first conductivity type and a tenth MISFET (PCH1) of a second conductivity type, the drain of the eighth MISFET, the source of the ninth MISFET and the drain of the tenth MISFET are electrically connected to form a second node (LDO), and the source of the tenth MISFET is connected to a second precharge potential (VPCH) of the second node.

the third amplifier circuit has a gate of an eleventh MISFET of a first conductivity type connected to the drain of the ninth MISFET, and a drain of a fourteenth MISFET of a second conductivity type electrically connected to the gate of the eleventh MISFET to form a third node (RDO), a source of the fourteenth MISFET connected to a third precharge potential (VPCHS) of the third node, and further has a twelfth MISFET of a first conductivity type and a thirteenth MISFET of a first conductivity type, a source of the twelfth MISFET, a source of the eleventh MISFET and a drain of the thirteenth MISFET are electrically connected, the eleventh MISFET and a drain are connected to a first data line (DT) and a second data line (DB), respectively, a first MISFET pair of first conductivity type having one gate and the other drain connected to each other and sources connected to the first source line, and a second MISFET pair of first conductivity type having one gate and the other drain connected to each other and sources connected to the second source line.

The mutually connected nodes of the first MISFET pair are connected to the first data line (DT), the mutually connected nodes of the second MISFET pair are connected to the second data line (DB), a first stabilizing capacitance (CQDL) is connected to the first node (QDO), a second stabilizing capacitance (CLDL) is connected to the second node (LDO), a first power supply voltage (VCCA) and a second power supply voltage (VSSA) are supplied to the third amplifier circuit, the first power supply voltage and the third precharge potential are at the same level of potential, and the second precharge potential is a potential approximately intermediate between the first power supply voltage and the second power supply voltage, the first precharge potential is a potential lower than the second precharge potential, and when the electrons stored in the second MISFET are in an up spin state, an on current (ISET on) flows through the fifth MISFET to drive the first node (QDO) to a low level at a relatively high speed, and when the electrons stored in the second MISFET are in a down spin state, an off current (ISET off) flows through the fifth MISFET to drive the first node to a low level at a relatively slower speed than in the up spin state. level, and immediately after the first node QDO becomes a different potential (first difference potential) in the up spin and down spin states, the gate potential of the eighth MISFET is changed from the second power supply voltage to a first drive voltage, and the first difference potential is amplified to a second difference potential by transferring the charged charge of the second node LDO to the first node QDO, and immediately after the second difference potential of the second node LDO is sufficiently amplified, the gate potential of the eighth MISFET is changed from the first drive voltage to the second power supply voltage, and immediately thereafter, the gate potential of the ninth MISFET is changed to the second power supply voltage to a second drive voltage, and the charge at the third node RDO is transferred to the second node LDO, thereby amplifying the second difference potential to a third difference potential, and after the third node RDO reaches the third difference potential state, the gate potential of the thirteenth MISFET is changed from the second power supply voltage to a third drive voltage, thereby outputting a fourth difference potential to the first data line and the second data line, and then the first MISFET pair and the second MISFET pair are activated, thereby amplifying the first data line and the second data line to the first power supply voltage and the second power supply voltage.

The circuit including the eighth MISFET (TPA) may be referred to as the "first charge transfer MIS circuit." The circuit including the ninth MISFET (T_RD) may be referred to as the "second charge transfer MIS circuit."

This disclosure can also have the following configurations:

a quantum bit array circuit including a plurality of quantum bit elements and a plurality of single-electron elements that detect the spin states of the plurality of quantum bit elements;
a first node which is a quantum bit readout line that outputs a readout current representing a spin state from the quantum bit device;
a quantum bit read current amplifier circuit connected to the first node;
having
The quantum bit read current amplifier circuit includes:
configured to set the first node to a first precharge potential;
The quantum bit read current amplifier circuit includes:
a second node coupled to a second precharge potential higher than the first precharge potential;
a first amplifier circuit including a first charge transfer MIS circuit electrically connected to the single-electron device via the first node and configured to transfer a charge stored in the second node to the first node;
a second amplifier circuit including a second charge transfer MIS circuit electrically connected to the first amplifier circuit via the second node and electrically connected to a third amplifier circuit via a third node, the second charge transfer MIS circuit transferring a charge at the third node to the second node;
a third amplifier circuit that outputs a potential to a data line and amplifies the amplitude of the potential when the third node reaches a predetermined potential by the first amplifier circuit and the second amplifier circuit;
A quantum semiconductor circuit comprising:

TP1...gate electrode, TRD...gate electrode, LDO...local data line, RDO...data line, QDO...qubit readout line, LDO...local data line, RDO...readout data line, VPCHA...array precharge voltage, VPCH...half precharge voltage, VPCHS...precharge voltage, PCH, PCH1, PCH2...precharge activation signal, PSN...amplifier activation signal, DT, DB...data line, CSN, CSP...common source activation signal

Claims (9)

a quantum bit array circuit including a plurality of quantum bit elements and a plurality of single-electron elements that detect the spin states of the plurality of quantum bit elements;
a first node which is a quantum bit readout line that outputs a readout current representing a spin state from the quantum bit device;
a quantum bit read current amplifier circuit connected to the first node;
having
The quantum bit read current amplifier circuit includes:
configured to set the first node to a first precharge potential;
The quantum bit read current amplifier circuit includes:
a second node coupled to a second precharge potential higher than the first precharge potential;
a first amplifier circuit including a first charge transfer MIS circuit electrically connected to the single-electron device via the first node and configured to transfer a charge stored in the second node to the first node;
a second amplifier circuit including a second charge transfer MIS circuit electrically connected to the first amplifier circuit via the second node and electrically connected to a third amplifier circuit via a third node, the second charge transfer MIS circuit transferring a charge at the third node to the second node;
a third amplifier circuit that outputs a potential to a data line and amplifies the amplitude of the potential when the third node reaches a predetermined potential by the first amplifier circuit and the second amplifier circuit;
A quantum semiconductor circuit comprising: 2. The quantum semiconductor circuit according to claim 1,
The quantum bit read current amplifier circuit includes:
a first stabilization capacitor connected to the first node;
a second stabilization capacitor connected to the second node;
A quantum semiconductor circuit comprising: 3. The quantum semiconductor circuit according to claim 2,
The capacitance value of the capacitor for the first stable operation and the capacitance value of the capacitor for the second stable operation are on the order of femtofarads ( ^10-15 ).
Quantum semiconductor circuits. 2. The quantum semiconductor circuit according to claim 1,
the first precharge potential of the first node is 0.1 mV to 20 mV, the second precharge potential of the second node is higher than the first precharge potential and lower than a third precharge potential of the third node, and the third precharge potential of the third node is equivalent to a high level of a power supply voltage;
Quantum semiconductor circuits. 2. The quantum semiconductor circuit according to claim 1,
a control voltage during an amplifying operation of each of the first amplifier circuit and the second amplifier circuit is a voltage between a high level and a low level of a power supply voltage;
Quantum semiconductor circuits. 6. The quantum semiconductor circuit according to claim 5,
The quantum bit read current amplifier circuit includes:
applying the control voltage to the gate electrode of the first amplifier circuit, and then outputting and transferring a desired differential potential to the second node, and then transitioning the control voltage of the gate electrode to a low level of the power supply voltage;
It was configured as follows:
Quantum semiconductor circuits. 7. The quantum semiconductor circuit according to claim 6,
a gate electrode of the second amplifier circuit transitions to a high level of the power supply voltage after the gate electrode of the first amplifier circuit transitions to the low level, thereby starting an amplifying operation of the second amplifier circuit;
Quantum semiconductor circuits. 2. The quantum semiconductor circuit according to claim 1,
The third node reaching a predetermined potential means that a state has been reached in which it is possible to determine whether the potential of the third node is higher or lower than a predetermined reference voltage.
Quantum semiconductor circuits. 3. The quantum semiconductor circuit according to claim 2,
The capacitance value of the capacitor for the first stable operation is greater than the capacitance value of the capacitor for the second stable operation.
Quantum semiconductor circuits.