WO2025033511A1 - 蒸着マスク及び、電子デバイスの製造方法 - Google Patents

蒸着マスク及び、電子デバイスの製造方法 Download PDF

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Publication number
WO2025033511A1
WO2025033511A1 PCT/JP2024/028534 JP2024028534W WO2025033511A1 WO 2025033511 A1 WO2025033511 A1 WO 2025033511A1 JP 2024028534 W JP2024028534 W JP 2024028534W WO 2025033511 A1 WO2025033511 A1 WO 2025033511A1
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WIPO (PCT)
Prior art keywords
deposition
deposition mask
substrate
opening
vapor deposition
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PCT/JP2024/028534
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English (en)
French (fr)
Japanese (ja)
Inventor
葵 佐野
数馬 碓氷
浩之 道
涼真 茂木
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Toppan Holdings Inc
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Toppan Holdings Inc
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Priority to JP2024573595A priority Critical patent/JP7708339B2/ja
Priority to KR1020257014032A priority patent/KR20250078513A/ko
Priority to CN202480037864.2A priority patent/CN121285649A/zh
Publication of WO2025033511A1 publication Critical patent/WO2025033511A1/ja
Priority to JP2025112686A priority patent/JP2025129320A/ja
Priority to JP2025179713A priority patent/JP2026012862A/ja
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C23C14/042—Coating on selected surface areas, e.g. using masks using masks
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/12—Organic material
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/24—Deposition of silicon only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/16—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering
    • H10K71/166—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering using selective deposition, e.g. using a mask

Definitions

  • the present invention relates to a deposition mask and a method for manufacturing an electronic device.
  • deposition masks are known that are used to paint three colors, RGB, when making organic electroluminescence displays.
  • the deposition mask has multiple openings, and the deposition material passes through the openings to form a film on the substrate.
  • Variations in the opening width of the deposition mask can cause mutual effects between adjacent pixels in the deposited film formed on the substrate, which can increase the risk of color mixing, for example. For this reason, a deposition mask was needed that could improve the pattern dimensions of the deposited film while suppressing mutual effects between adjacent pixels.
  • the present invention aims to provide a deposition mask that can form a deposition film with excellent pattern dimensions and suppress mutual influence between adjacent pixels, and a method for manufacturing an electronic device using the deposition mask.
  • the deposition mask of this embodiment is a deposition mask that is placed between a substrate to be deposited and a deposition source, and is used to deposit a deposition material from the deposition source onto the surface of the non-deposited substrate through openings.
  • the deposition mask has a first surface facing the substrate to be deposited and a second surface facing the deposition source, located on the opposite side of the first surface, and has a plurality of openings formed therethrough between the first surface and the second surface.
  • the sidewall surfaces of the openings are inclined so that the opening width narrows from the second surface side toward the first surface side, and the opening width defined on the first surface side is greater than 3 ⁇ m and smaller than 15 ⁇ m.
  • the present invention by controlling the opening width and the variation ⁇ , it is possible to stably form a deposition film that has excellent pattern dimensions while suppressing the risk of color mixing between adjacent pixels.
  • FIG. 2 is a cross-sectional view showing an example of a deposition mask according to the present embodiment.
  • 2 is an enlarged cross-sectional view showing a part of the deposition mask shown in FIG. 1 .
  • 4 is a partially enlarged cross-sectional view showing an enlarged portion of an opening of the deposition mask of the present embodiment.
  • FIG. 1A to 1C are cross-sectional views showing a method for manufacturing an electronic device using the deposition mask of the present embodiment.
  • FIG. 2 is an image diagram of adjacent pixels formed on a substrate to be deposited;
  • 1A to 1C are process diagrams illustrating an example of a method for manufacturing a deposition mask according to an embodiment of the present invention.
  • FIG. 11 is a cross-sectional view illustrating an example of a deposition mask according to another embodiment.
  • FIG. 11 is a cross-sectional view illustrating an example of a deposition mask according to another embodiment.
  • FIG. 11 is a cross-sectional view illustrating an example of a deposition mask according to another embodiment.
  • FIG. 11 is a cross-sectional view illustrating an example of a deposition mask according to another embodiment.
  • VR/AR Virtual reality/augmented reality
  • PPI Pixels Per Inch
  • OLED silicon-based organic light-emitting diode
  • Silicon-based OLED microdisplay technology is expected to achieve further miniaturization and high PPI. Furthermore, to effectively prepare for AR and VR as high-value-added industries, it is expected to realize ultra-high resolution displays of, for example, 1000 ppi or more. As a result, there is a growing need for deposition masks for RGB color separation used in the manufacturing process of OLED microdisplays.
  • the deposition mask has multiple openings that correspond to the deposited film, and the accuracy of the openings in the deposition mask is important for improving the pattern dimensions of the deposited film.
  • the deposition mask is placed between the substrate to be deposited and the deposition source, and the deposition material passes from the deposition source through the openings in the deposition mask and reaches the surface of the substrate to be deposited.
  • the width of the openings in the deposition mask in this embodiment is becoming narrower to meet the needs of the OLED microdisplays described above, but if it is too small, the deposition material will accumulate on the sidewall surface of the opening, making the opening width narrower than the actual width, and making it difficult to form a deposition film with excellent pattern dimensions.
  • the variation in aperture width tends to increase.
  • the effect of variation on the evaporated film formed on the evaporated substrate is small if the light-emitting area is large, but the risk of color mixing with adjacent pixels increases.
  • the risk of color mixing is determined by the absolute value of the variation ⁇ in the aperture width, so it was necessary to reduce the variation ⁇ .
  • the inventors have focused on the aperture width and the variation ⁇ and have developed a deposition mask that has excellent pattern dimensions while suppressing the mutual influence between adjacent pixels (e.g., the risk of color mixing).
  • Fig. 1 is a cross-sectional view of a deposition mask 1 in the present embodiment.
  • Fig. 2 is a cross-sectional view showing an enlarged portion of the deposition mask shown in Fig. 1.
  • Fig. 3 is a partially enlarged cross-sectional view showing an enlarged portion of an opening of the deposition mask in the present embodiment.
  • Fig. 4 is a cross-sectional view showing a method for manufacturing an electronic device using the deposition mask in the present embodiment.
  • the deposition mask 1 has a layered structure of a semiconductor layer 2, an insulating layer 3, and a support substrate 4, and is preferably constructed from an SOI (Silicon on Insulator) substrate 9.
  • SOI Silicon on Insulator
  • the semiconductor layer 2 is preferably a silicon single crystal layer, and is also called an active layer or membrane. There is no limitation on the thickness of the semiconductor layer 2, but it is about 1 ⁇ m to 300 ⁇ m.
  • the deposition mask 1 has multiple opening regions 15 and surrounding regions 16 located around the opening regions 15, and the surrounding regions 16 have a structure in which a semiconductor layer 2, an insulating layer 3, and a support substrate 4 are stacked.
  • the semiconductor layer 2 is disposed in the opening regions 15, that is, the insulating layer 3 and the support substrate 4 have been removed, and furthermore, multiple minute openings 5 are formed in each opening region 15.
  • FIG. 2 is an enlarged view of one of the opening regions 15 shown in FIG. 2, the semiconductor layer 2 has a first surface 2a and a second surface 2b that face each other in the thickness direction.
  • An insulating layer 3 and a support substrate 4 are provided on the second surface 2b side.
  • the first surface 2 a is a front surface facing a deposition target substrate 10
  • the second surface 2 b is a rear surface facing a deposition source 11 .
  • the semiconductor layer 2 has a plurality of openings 5 formed between the first surface 2a and the second surface 2b.
  • the opening width of each opening 5 gradually narrows from the second surface 2b to the first surface 2a.
  • the sidewall surface 6 of the opening 5 is inclined.
  • the opening width W1 is defined by the width dimension in the planar direction along the first surface 2a.
  • the opening width W1 is illustrated at the point where the width dimension is the narrowest.
  • the reference numerals for the opening width W1 and the sidewall surface 6 are illustrated for only one opening 5, but they apply to the other openings 5 in the same way. Note that the shape of the sidewall surface 6 of the opening 5 will be described in detail later.
  • the planar pattern of the openings 5 (the shape seen from directly above the semiconductor layer 2 toward the first surface 2a) is not limited, and examples thereof include a rectangle (including a square), a polygon other than a rectangle, a circle, and an ellipse. All the openings 5 may have the same planar pattern, or some of them may be different.
  • the openings 5 may be regularly arranged, irregularly arranged, or a mixture of regular and irregular arrangements. Although there are no limitations on the distance between adjacent openings 5, the distance is about 1 ⁇ m to 20 ⁇ m when viewed from the first surface 2a side.
  • the outer peripheral shape of the semiconductor layer 2 is preferably a rectangular or disk-shaped wafer, and although there are no limitations on the diameter (the length of one side if rectangular), it is preferable for it to be approximately 100 mm to 500 mm. In this way, even if the diameter of the semiconductor layer 2 is large, each opening 5 can be formed uniformly.
  • the insulating layer 3 may be an oxide layer or a nitride layer, but is preferably an oxide layer, and more specifically, is preferably a silicon oxide (SiO 2 ) layer.
  • the insulating layer 3 is also called a BOX layer (Buried Oxide Layer).
  • the thickness of the insulating layer 3 is not limited, but is, for example, about 100 nm to 20 ⁇ m.
  • the insulating layer 3 shown in FIG. 2 is not provided in the opening region facing the opening 5 of the semiconductor layer 2, but has been removed, and is left only in the surrounding region of the opening region on the second surface 2b of the semiconductor layer 2.
  • the insulating layer 3 serves as an etching stopper for the semiconductor layer 2, and the presence of the insulating layer 3 enables stable processing.
  • the support substrate 4 shown in FIG. 2 is a semiconductor substrate, for example a silicon substrate.
  • the thickness of the support substrate 4 is not limited, but is, for example, about 100 ⁇ m to 1000 ⁇ m.
  • the support substrate 4 can function as the pillars 16a and the peripheral frame 16b surrounding the peripheral region 16 of the opening region 15 on the second surface 2b of the semiconductor layer 2. Therefore, the semiconductor layer 2 can be kept in a taut state by the support substrate 4, making tensioning unnecessary, and the deposition mask 1 of this embodiment can be attached to the deposition substrate 10 using an electrostatic chuck that utilizes electrostatic force.
  • the pillars 16a are located inside the peripheral frame 16b, and they all have the same length (height), but for example, the height of the pillars 16a may be lower than the peripheral frame. However, by making the heights uniform, strength can be maintained.
  • an alignment mark for positioning can be formed in the peripheral region on the first surface 2a side of the semiconductor layer 2.
  • the alignment mark can be formed, for example, in a concave shape on the first surface 2a, and can be formed to a depth that reaches the insulating layer 3.
  • the opening 5 gradually narrows from the second surface 2b toward the first surface 2a, and the opening width varies depending on the measurement location. For this reason, as shown in Fig. 2, the opening width W1 was obtained as the dimension in the planar direction along the first surface 2a where the opening width is narrowest.
  • the opening width W1 can be determined from a SEM image obtained using an eCD-2 manufactured by KLA-Tencor.
  • the variation ⁇ of the opening width W1 of the deposition mask 1 is specified.
  • a predetermined range is defined in the plane of the deposition mask 1 shown in Fig. 1, and the opening widths W1 of the multiple openings 5 located within the predetermined range are measured to obtain a standard deviation ⁇ . Then, this standard deviation ⁇ is defined as the variation ⁇ of the opening width W1.
  • the "predetermined range” can be defined as the central region of the deposition mask 1. In this case, it is preferable that the central region is large enough to include at least 100 openings 5.
  • a predetermined number of adjacent openings 5 included in the central region were selected, the opening width W1 of these openings 5 was measured, and the variation ⁇ was obtained.
  • the "predetermined number” is about 10 to 100, and specifically, about 50 to 150.
  • 100 adjacent openings 5 were selected to obtain the variation ⁇ .
  • Adjacent openings can be defined as openings contained within a rectangular, square, circular, elliptical, or polygonal outline, or openings lined up in a row. Preferably, multiple openings that exist within a square or rectangular outline are picked up, and when selecting 100 openings 5, for example, 100 openings arranged in a 10 x 10 matrix in the vertical and horizontal directions can be selected.
  • FIG. 3 is a partially enlarged cross-sectional view of one opening 5 formed in the deposition mask 1, showing the center point of the opening 5 in the height direction (thickness direction of the semiconductor layer 2). Note that reference numerals are mainly attached only to the side wall surface 6 of the opening 5 on the left side of the figure, but the cross-sectional shape is symmetrical, and the side wall surface 6 on the right side of the figure has the same configuration.
  • the side wall surface 6 of the opening 5 is formed in an uneven shape. That is, on the side wall surface 6, a plurality of convex portions 7 protruding inwardly of the opening 5 and concave portions 8 located between the convex portions 7 are repeatedly formed continuously along the height direction of the opening 5.
  • the unevenness height difference and the like of the opening 5 are calculated as follows.
  • pitches of the uneven shape were measured with an SEM at a midpoint located exactly in the middle of the thickness between the first surface 2a and the second surface 2b of the opening 5.
  • the number of pitches is not limited to five, but if the number of pitches is too small, parameter noise will be large, and if the number of pitches is too large, depending on the thickness, it may not be possible to ensure that number of pitches.
  • parameter calculations will be time-consuming and complicated, so it is preferable to have a number of pitches within about 10 pitches.
  • measurements are basically taken at five pitches, but if this is difficult, the number of pitches can be changed as appropriate.
  • the pitch concept described above it is also possible to measure the height at, for example, five points in the center of the thickness using an SEM image.
  • the points with height can be regarded as convex portions, and the areas between them as concave portions.
  • an approximate straight line T1 was drawn connecting the lowest positions (bottoms A) of each recess 8a, 8b within the measurement range.
  • Bottom A is, for example, the farthest position when viewed from the center line O in the width direction of the opening 5.
  • the approximate straight line T1 can be found using the least squares method. Note that if an irregular recess 8 is formed within the measurement range (for example, if bottom A is at an extremely low position), the approximate straight line T1 can be drawn excluding that recess 8.
  • the highest position (apex) B of the convex portion 7a was determined in the first half pitch P1.
  • the apex B is the closest position when viewed from the center line O in the width direction of the opening 5.
  • a straight line S1 was drawn perpendicular to the approximated straight line T1 so as to intersect with the apex B.
  • the length of the straight line S1 from the approximated straight line T1 to the apex B was determined.
  • the length of this straight line S1 was defined as the unevenness height difference D1 in the first half pitch P1.
  • the unevenness height difference can be calculated in the same way as for the first half pitch P1. That is, the length of a straight line perpendicular to the approximate straight line T1 to the top B of each convex portion is calculated, and this straight line length is used as the unevenness height difference for each pitch.
  • Figure 3 shows the unevenness height difference D2 for the second half pitch P2.
  • fine irregularities may be formed on the surface of each recess 8a, 8b (or the bottom of the protruding portions 7a, 7b), but these fine irregularities can be ignored. For example, fine irregularities on the order of a few nm in wavelength or smaller can be cut off, and a waviness curve can be created to determine the difference in unevenness height.
  • the taper angle ⁇ 1 of the opening 5 is determined as follows. That is, as shown in Fig. 3, a straight line is connected between an end of the opening width W1 in the surface direction along the first surface 2a and an end of the opening width W2 in the surface direction along the second surface 2b, and the inclination angle between the straight line and the first surface 2a can be set as the taper angle ⁇ 1 of the opening 5.
  • the taper angle ⁇ 1 was determined by measuring the length of an SEM image obtained using a Hitachi High-Technologies Regulus 8220.
  • the unevenness angle ⁇ 2 can be determined as the angle between a straight line L1 connecting the top B of the convex portion 7a and the lowest (farthest from the center line O in the width direction of the opening 5) bottom A of the concave portion 8a located on the deposition substrate 10 side (upper side in the figure) as viewed from the convex portion 7a, and an approximated straight line T1. Also, as shown in Fig. 3, the unevenness angle ⁇ 2 can be determined as the angle between a straight line L1 connecting the top B of the convex portion 7a and the lowest (farthest from the center line O in the width direction of the opening 5) bottom A of the concave portion 8a located on the deposition substrate 10 side (upper side in the figure) as viewed from the convex portion 7a, and an approximated straight line T1. Also, as shown in Fig.
  • the unevenness angle ⁇ 3 can be determined as the angle between a straight line L2 connecting the top B of the convex portion 7a and the lowest (farthest from the center line O in the width direction of the opening 5) bottom A of the concave portion 8b located on the deposition source 11 side (lower side in the figure, see Fig. 4) as viewed from the convex portion 7a, and an approximated straight line T1.
  • a small concave-convex angle ⁇ 2, ⁇ 3 means that the height of the convex portion 7 is low (the depth of the concave portion 8 is shallow) and the waviness of the side wall surface 6 is small.
  • the deposition mask 1 in this embodiment is (1)
  • the side wall surface 6 of the opening 5 is inclined so as to become narrower from the second surface 2b side to the first surface 2a side.
  • the opening width W1 is greater than 3 ⁇ m and smaller than 15 ⁇ m.
  • the opening width W1 is set to a range greater than 3 ⁇ m and less than 15 ⁇ m. This satisfies the needs of the deposition mask 1 having the semiconductor layer 2, and in particular, as a deposition mask for RGB color separation used in the manufacturing process of OLED microdisplays, it is necessary to further reduce the opening width W1.
  • the opening width W1 is preferably greater than or equal to 4 ⁇ m and less than or equal to 10 ⁇ m.
  • the opening width W1 is preferably set as the width dimension in the planar direction along the first surface 2a that faces the deposition substrate 10.
  • FIG. 4 is a cross-sectional view of the deposition mask 1 of this embodiment, positioned between a deposition substrate 10 and a deposition source 11, showing one step in the method for manufacturing an electronic device.
  • the deposition material (deposition particles) 12 from the deposition source 11 passes through the openings 5 of the deposition mask 1 and reaches the surface 10a of the deposition substrate 10, where a deposition film 13 is formed.
  • the pattern width W3 of the deposition film 13 is measured and the ratio to the opening width W1 is calculated, an opening width W1 where the pattern width ratio ((pattern width W3/opening width W1) ⁇ 100(%)) is 80% or more is considered to be the present embodiment, and an opening width W1 where the pattern width ratio is less than 80% is considered to be the comparative example.
  • the opening width W1 is set in the range of more than 3 ⁇ m and less than 15 ⁇ m, and preferably 4 ⁇ m to 10 ⁇ m, so that the pattern width ratio can be made 80% or more and the variation ⁇ of the opening width W1 can be reduced.
  • the reason for setting the pattern width ratio at 80% or more is that if it is less than 80%, the deviation from the desired pattern width W3 of the deposition film 13 will be too large, leading to a decrease in yield, and also because it will lead to a decrease in the area that should emit light at the design position, such as coordinate position accuracy, leading to a decrease in the brightness of the light-emitting element itself, or because it is a numerical value required for product quality assurance.
  • the pattern width ratio is set to 85% or more, preferably 90% or more, and more preferably 95% or more.
  • the pattern width ratio is likely to fall below 80% because the narrower the opening width W1, the greater the influence of the deposition material 12 deposited on the side wall surface 6.
  • the side wall surface 6 is formed with an uneven shape, so the deposition material 12 is likely to adhere to the side of the convex portion 7 located on the deposited substrate side (upper side in FIG. 3) as viewed from the recess 8. Therefore, in this embodiment, it is preferable to control the average value Ave of the unevenness height difference Dn along with setting the opening width W1.
  • the average value Ave of the unevenness height difference Dn is preferably 0.200 ⁇ m or less, more preferably 0.195 ⁇ m or less, even more preferably 0.190 or less, even more preferably 0.180 ⁇ m or less, and most preferably 0.175 ⁇ m or less.
  • the lower limit of the average value Ave of the unevenness height difference Dn is not limited, the average value Ave of the unevenness height difference Dn can be specified to be 0.003 ⁇ m or more, or 0.005 ⁇ m or more, or 0.008 ⁇ m or more.
  • the variation ⁇ of the opening width W1 is preferably smaller than 0.09 ⁇ m.
  • the variation ⁇ can be calculated, for example, as the standard deviation ⁇ of the opening width W1 of 100 adjacent openings 5.
  • FIG. 5 is an image diagram of RGB pixels 23 arranged in a matrix on a deposition film 13 formed on the surface of a deposition substrate using a deposition mask 1.
  • the opening width W1 of the deposition mask 1 is large, the light-emitting area of each pixel 23 is less susceptible to the effect of the variation ⁇ , but the risk of color mixing with adjacent pixels 23 shown in FIG. 5, for example, increases.
  • the risk of color mixing is determined by the absolute value of the variation ⁇ , and the greater the variation ⁇ , the higher the risk of color mixing. Therefore, in this embodiment, the variation ⁇ is set to a range smaller than 0.09 ⁇ m, and preferably set to 0.01 ⁇ m or more and 0.08 ⁇ m or less.
  • the openings 5 are formed in the semiconductor layer 2 by dry etching.
  • the opening widths W1 will not all be the same and variations are likely to occur.
  • the variation ⁇ will be large. For this reason, in this embodiment, it has been found that the variation ⁇ can be kept smaller by setting the opening width W1 in the range greater than 3 ⁇ m and less than 15 ⁇ m.
  • the unevenness angles ⁇ 2 and ⁇ 3 described in FIG. 3 are within the range of about 0.5° to 50°, and are preferably 45° or less, more preferably 40° or less, even more preferably 30° or less, even more preferably 20° or less, and even more preferably 10° or less.
  • the most preferable range of the unevenness angles ⁇ 2 and ⁇ 3 is about 0.5° to 2°.
  • the unevenness angle ⁇ 3 shown in FIG. 3 is preferably smaller than the unevenness angle ⁇ 2. This makes it possible to suppress the deposition material 12 from depositing on the side wall surface 6.
  • the opening width of the opening 5 is gradually narrowed from the second surface 2b side toward the first surface 2a side. That is, as shown in FIG. 4, the opening width W1 on the side of the deposition mask 1 facing the deposition substrate 10 is narrowed, and the side wall surface 6 of the opening 5 is formed by an inclined surface. This makes it easier to stably form the deposition film 13 having the desired pattern width W3.
  • the side wall surface 6 of the opening 5 is inclined, making it easier to form the side wall surface 6.
  • the taper angle ⁇ 1 of the side wall surface 6 is preferably 60° or more, more preferably 70° or more, and even more preferably 80° or more.
  • the taper angle ⁇ 1 is preferably smaller than 90°, and more preferably 88° or less. If the taper angle ⁇ 1 is less than 60°, the amount of deposition material 12 deposited on the sidewall surface 6 increases, and the pattern width ratio of the deposition film tends to be smaller than 80%.
  • the taper angle ⁇ 1 can be set to about 90°, i.e., the sidewall surface 6 can be formed almost vertically.
  • the effect of the unevenness height difference Dn of the sidewall surface 6 during deposition is considered to be large, and it is necessary to make the average value Ave of the unevenness height difference Dn as small as possible, especially as the opening width W1 becomes narrower.
  • the thickness of the semiconductor layer 2 There is also a relationship with the thickness of the semiconductor layer 2. In other words, if the thickness of the semiconductor layer 2 increases, it becomes difficult to form the sidewall surface 6 as a vertical surface. Therefore, in this embodiment, the taper angle ⁇ 1 of the sidewall surface 6 is controlled to be smaller than 90°, and preferably controlled to be 88° or less.
  • FIG. 6A and 6B are process diagrams showing a first manufacturing method of the deposition mask 1 of the present embodiment.
  • the deposition mask 1 in the manufacturing process shown in FIG. 6 and FIG. 7 described later shows only one opening region 15 and its vicinity, as in FIG. 2, but in reality, the multiple opening regions 15 shown in FIG. 1 are formed simultaneously.
  • FIG. 6A an SOI substrate 9 is prepared.
  • the SOI substrate 9 has a laminated structure of a semiconductor layer 2, an insulating layer 3, and a support substrate 4. The materials and thicknesses of each layer have been explained in FIG. 1, so please refer to that.
  • the diameter is not limited, but in this embodiment, it can accommodate up to about 500 mm.
  • a mask layer 14 is patterned on the surface of the semiconductor layer 2.
  • the mask layer 14 is preferably a resist, and can be patterned by exposure and development.
  • a plurality of through holes 14a are formed in the mask layer 14.
  • the through holes 14a are an opening pattern for forming the openings 5 in the semiconductor layer 2, and the width dimension W4 of the through holes 14a is formed to be greater than 3 ⁇ m and less than 15 ⁇ m.
  • the semiconductor layer 2 exposed from the through hole 14a of the mask layer 14 is dry etched.
  • the semiconductor layer 2 is deep etched. It is preferable to use a method in which, for example, etching of Si with SF6 and generation of a polymer film with C4F8 are repeated to deeply dig silicon, and sidewall protection and bottom etching proceed alternately, by the so-called Bosch process.
  • Bosch process the sidewall surface 6 of the opening 5 formed in the semiconductor layer 2 has an uneven shape.
  • the composition of the etching gas, the flow rate, the pressure inside the etching chamber, the power of the high frequency power source, etc. are appropriately adjusted so as to form an inverse tapered surface. Furthermore, by adjusting these, it is possible to control the taper angle ⁇ 1 of the inverse tapered surface and the unevenness height difference Dn.
  • the Bosch process was carried out in a dry etching apparatus by alternately using SF6 gas and C4F8 gas.
  • Anisotropic dry etching using fluorine ions was carried out by applying a bias to the substrate to be etched using the same gas as that used in the mode in which isotropic dry etching using fluorine radicals is carried out using SF6 gas.
  • the processing conditions were SF6 gas at 0 to 500 sccm , C4F8 gas at 0 to 300 sccm, Platen LF at 0 to 1500 W, Coil RF at 300 to 1500 W, and chamber pressure at 1 to 10 Pa, and various conditions were adjusted.
  • multiple openings 5 can be deeply formed in the semiconductor layer 2, and at this time, the taper angle ⁇ 1 of the sidewall surface 6 of the openings 5 and the height difference between the protrusions and recesses can be appropriately adjusted.
  • the unevenness height difference Dn can also be reduced by, for example, performing deep etching of the silicon and then smoothing (processing to reduce the unevenness height difference) using a laser hydrogen annealing process.
  • the mask layer 14 is removed. This completes the SOI substrate 9 with multiple openings 5 formed in the semiconductor layer 2.
  • a protective layer 20 is formed on the surface of the semiconductor layer 2. This allows the entire surface of the semiconductor layer 2 to be appropriately protected.
  • the protective layer 20 is, for example, a resist film.
  • a mask layer 21 is formed on the surface of the support substrate 4, which corresponds to the back surface of the SOI substrate 9.
  • the mask layer 21 is a resist pattern.
  • the mask layer 21 is not formed in the opening region 15 that faces the opening 5 formed in the semiconductor layer 2 in the thickness direction, but is provided only in the surrounding region 16 (see also FIG. 1).
  • the mask layer 21 may be formed together with the mask layer 14 during the step shown in FIG. 6(b).
  • the support substrate 4 that is not covered with the mask layer 21 is removed by dry etching, and in the step shown in Fig. 6(h), the insulating layer 3 that is revealed by removing the support substrate 4 is removed by wet etching. At this time, the semiconductor layer 2 is not affected by the wet etching and maintains the shape having the multiple openings 5. 6I, the protective layer 20 and the mask layer 21 are removed, thereby completing the deposition mask 1.
  • FIG. 7 is a process diagram showing a second manufacturing method of the deposition mask 1 of this embodiment.
  • an SOI substrate 9 is prepared.
  • the SOI substrate 9 has a layered structure of a semiconductor layer 2, an insulating layer 3, and a support substrate 4.
  • the materials and thicknesses of each layer are explained in FIG. 1, so please refer to that.
  • the diameter of the SOI substrate 9 there is no limit to the diameter of the SOI substrate 9, but in this embodiment, it can accommodate a diameter of up to approximately 500 mm.
  • a mask layer 21 is formed on the surface of the support substrate 4, which corresponds to the back surface of the SOI substrate 9.
  • the mask layer 21 is a resist pattern.
  • the mask layer 21 is provided only in the peripheral region of the SOI substrate 9.
  • the support substrate 4 that is not covered by the mask layer 21 is removed by dry etching
  • the insulating layer 3 that is revealed by removing the support substrate 4 is removed by wet etching.
  • a mask layer 22 is formed on the back surface of the semiconductor layer 2.
  • the mask layer 22 can be formed of a resist pattern.
  • a plurality of openings 22a are patterned in the mask layer 22 by exposure and development.
  • the semiconductor layer 2 exposed from the opening 22a is etched.
  • This etching is dry etching, and although not limited thereto, it is preferable to use an etching gas that contains a fluorine compound and oxygen, and optionally a rare gas.
  • the fluorine compound may be, for example, one or more selected from CF 4 , SF 6 , NF 3 , BF 3 , PF 5 , and F 2
  • the rare gas may be, for example, one or more selected from helium and argon.
  • etching was performed using CF4 gas, O2 gas, and Ar gas in a dry etching apparatus.
  • the processing conditions were CF4 gas at 10 to 100 sccm, O2 gas at 0 to 100 sccm, Ar gas at 0 to 200 sccm, IPC power at 200 to 1000 W, RIE power at 0 to 1000 W, and chamber pressure at 1 to 10 Pa, and various conditions were adjusted.
  • an opening 5 is formed in the semiconductor layer 2, the width of which gradually decreases as it moves away from the mask layer 22 (towards the first surface 2a of the semiconductor layer 2). This allows the sidewall surface 6 of the opening 5 to be formed as an inclined surface. Then, in the step of FIG. 7(g), the mask layer 22 is removed. This completes the deposition mask 1.
  • a plurality of openings 5 can be formed in the semiconductor layer 2, and the sidewall surface 6 of the openings 5 can be formed as an inclined surface such that the opening width gradually narrows from the back surface (second surface 2b) of the semiconductor layer 2 facing the deposition source 11 toward the front surface (first surface 2a) facing the deposition substrate 10.
  • the opening width W1, the opening variation ⁇ , and the taper angle ⁇ 1 can be adjusted by the various gas flow rates, the chamber pressure, the power of the plasma generation source, etc.
  • the deposition mask 1 is disposed between a deposition substrate 10 and a deposition source 11. At this time, the first surface 2a of the semiconductor layer 2 of the deposition mask 1 faces the deposition substrate 10, and the second surface 2b of the semiconductor layer 2 faces the deposition source 11. A plurality of openings 5 are formed in the semiconductor layer 2, and the opening width is narrower on the first surface side than on the second surface side.
  • the deposition mask 1 is placed in a holder (not shown) of the deposition device, and the deposition mask 1 and the deposition substrate 10 can be fixed with an electrostatic chuck.
  • the deposition mask 1 and the deposition substrate 10 are rotated around the axial center of the holder as the rotation axis.
  • the deposition material (deposition particles) 12 from the deposition source 11 passes through the openings 5 in the deposition mask 1 and reaches the surface 10a of the deposition substrate 10, forming a deposition film 13.
  • examples of electronic devices include OLED microdisplay panels, liquid crystal panels, solar cells, etc.
  • the present invention is particularly suitable for a manufacturing method for an OLED microdisplay panel as an organic electronic device.
  • the pattern width W3 of the deposition film 13 can be ensured to be 80% or more of the opening width W1, preferably 85% or more, and more preferably 90% or more. In this way, a deposition film 13 with excellent pattern dimensions can be formed.
  • the opening width W1 of the opening 5 of the deposition mask 1 is set to be greater than 3 ⁇ m and smaller than 15 ⁇ m, so that a deposition film having excellent pattern dimensions and suppressing mutual influence between adjacent pixels can be stably formed.
  • the opening width W1 was not set from the perspective of the pattern dimensions and the mutual influence between adjacent pixels (e.g., risk of color mixing).
  • the variation ⁇ of the opening width W1 was not taken into consideration. Therefore, with the conventional control method, it was not possible to stably form a deposition film 13 that had a high pattern dimension and a low risk of color mixing.
  • the opening width W1 by adjusting the opening width W1 to a range greater than 3 ⁇ m and less than 15 ⁇ m, it is possible to stably form a deposition film 13 having a pattern width W3 with a pattern width ratio of 80% or more and with reduced mutual influence between adjacent pixels.
  • the variation ⁇ in the opening width W1 can be made smaller than 0.09 ⁇ m, and preferably between 0.01 ⁇ m and 0.08 ⁇ m. This makes it possible to effectively reduce the mutual influence between adjacent pixels.
  • the deposition of the deposition material 12 can be suppressed, the frequency of cleaning the deposition mask can be reduced, and quality control of the deposition mask can be easily performed.
  • the occurrence of clogging of the openings can be reduced, and the life of the deposition mask can be extended.
  • the present invention is not limited to the above-mentioned embodiments and modifications, and may be modified, substituted, or altered in various ways without departing from the spirit of the technical idea. Furthermore, if the technical idea can be realized in a different way due to technological advances or derived other technologies, it may be implemented using that method. Therefore, the claims cover all embodiments that may fall within the scope of the technical idea.
  • a membrane 31 such as SiN or SiO2 may be formed on the surface of a frame-shaped silicon substrate 30, and a plurality of openings 32 may be formed in the membrane 31 in the central region where the silicon substrate 30 has been removed, or a single-layer structure in which a plurality of openings are formed in a semiconductor substrate (preferably a silicon substrate) may be used.
  • the membrane is formed by CVD, but it is preferable to use SiN from the viewpoint of easy stress control.
  • an SOI substrate 9 is used as in Fig. 1, but in Fig. 9, a SiN layer 33 is formed on the back side (support substrate 4 side, facing deposition source 11) of the SOI substrate 9, in Fig. 10, a SiN layer 33 is formed on the front side (semiconductor layer 2 side, facing deposition substrate 10) of the SOI substrate 9, and in Fig. 11, a SiN layer 33 is formed on both the back side and front side of the SOI substrate 9.
  • an opening 5 is formed in contiguous with the semiconductor layer 2 as shown in Figs. 10 and 11.
  • the SiN layer 33 By providing the SiN layer 33, it becomes easier to control the stress of the deposition mask, and distortion and the like can be suppressed. Moreover, it is preferable that the SiN layer 33 formed on the front side of the SOI substrate 9 is thinner than the SiN layer 33 formed on the back side of the SOI substrate 9. Although not limited thereto, the thickness of the SiN layer 33 formed on the front side of the SOI substrate 9 is about 0.05 ⁇ m to 0.5 ⁇ m, and the thickness of the SiN layer 33 formed on the back side of the SOI substrate 9 is about 0.05 ⁇ m to 3 ⁇ m.
  • the SiN layer 33 formed on the front side of the SOI substrate 9 is formed thinner than the SiN layer 33 formed on the back side of the SOI substrate 9 in order to control the stress in a well-balanced manner between the front side and the back side.
  • the SOI substrate used had a support substrate (625 ⁇ m)/insulating layer (0.5 ⁇ m)/semiconductor layer (15 ⁇ m or 5 ⁇ m).
  • the parentheses indicate the thickness.
  • the support substrate was a Si substrate
  • the semiconductor layer was a Si layer
  • the insulating layer was a SiO2 layer.
  • the outer diameter of the SOI substrate was 200 mm.
  • two types of SOI substrates were prepared, one with a semiconductor layer thickness of 15 ⁇ m and the other with a thickness of 5 ⁇ m.
  • an opening pattern is formed in the mask layer (resist layer) by i-line exposure, and the opening width of the master used in forming this opening pattern is adjusted within the range of 2.0 ⁇ m to 30 ⁇ m.
  • the deposition mask 1 was formed using the manufacturing method shown in FIG. 6.
  • the opening width W1 was changed depending on the original plate used.
  • the opening width W1 and taper angle formed in the semiconductor layer 2 were adjusted by adjusting the flow rates of various gases, the chamber pressure, and the power of the plasma generation source.
  • anisotropic dry etching using fluorine ions was performed by applying a bias to the substrate to be etched using the same gas as that used in the mode in which isotropic dry etching using fluorine radicals was performed using SF6 gas.
  • the processing conditions were SF6 gas at 0 to 500 sccm , C4F8 gas at 0 to 300 sccm, Platen LF at 0 to 1500 W, Coil RF at 300 to 1500 W, and chamber pressure at 1 to 10 Pa, and various conditions were adjusted.
  • the opening width W1 was the width dimension in the surface direction along the first surface 2a of the semiconductor layer 2.
  • the standard deviation ⁇ of the opening width W1 was calculated from the opening width W1 of each of the adjacent openings of 10 ⁇ 10 (100 pieces) in the vertical and horizontal directions in the central region of the deposition mask 1.
  • the opening width W1 was calculated from an SEM image obtained using an eCD-2 manufactured by KLA-Tencor.
  • the average value Ave of the unevenness height difference Dn and the taper angle were determined from SEM images taken using a Hitachi High-Tech Regulus 8220.
  • Alq3 tris(8-hydroxyquinoline)aluminum
  • the pattern width W3 of the evaporated film was measured, and the pattern width ratio of the evaporated film to the opening width W1 of the evaporation mask ((W3/W1) x 100 (%)) was calculated.
  • Experimental examples in which the pattern width ratio was less than 80% were marked with an X, experimental examples in which the pattern width ratio was 80% to 90% with an O, and experimental examples in which the pattern width ratio was over 90% with an ⁇ .
  • Tables 1 to 6 are representative values, and it was confirmed that all experimental examples fell within a range of ⁇ 3° from each representative value.
  • Tables 1 to 3 show the experimental results when the semiconductor layer thickness is 15 ⁇ m, and Tables 4 to 6 show the experimental results when the semiconductor layer thickness is 5 ⁇ m.
  • the opening width W1 is greater than 3 ⁇ m and smaller than 15 ⁇ m, deposition of the deposition material 12 on the side wall surface 6 of the opening 5 can be suppressed, and a deposition film can be stably formed in which the pattern width W3 relative to the opening width W1 is 80% or more, preferably more than 90%.
  • the variation ⁇ of the opening width W1 can be reduced, specifically, the variation ⁇ can be set to 0.09 ⁇ m or less.
  • the variation ⁇ is preferably 0.01 ⁇ m or more and 0.08 ⁇ m or less.
  • the needs required for the deposition mask 1 having the semiconductor layer 2 can be met, and in particular, it can be preferably used as a deposition mask for RGB color separation used in the manufacturing process of OLED microdisplays.
  • the average value Ave of the unevenness height difference Dn is 0.200 ⁇ m or less, more preferably 0.180 ⁇ m or less, and even more preferably 0.170 ⁇ m or less.
  • the taper angle is preferably 60° or more, and more preferably 70° or more.
  • the lower limit of the taper angle (inclination angle) can be less than 90°, or 88° or less. An error of about ⁇ 3° is permitted for the taper angle.
  • the concave-convex angles ⁇ 2 and ⁇ 3 described in FIG. 3 can be set within a range of about 0.5° to 50°. They are preferably set to 10° or less, and a more preferable range is about 0.5° to 2°. It was also found that the concave-convex angle ⁇ 3 is smaller than the concave-convex angle ⁇ 2, which makes it possible to suppress the deposition of the deposition material.

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PCT/JP2024/028534 2023-08-10 2024-08-08 蒸着マスク及び、電子デバイスの製造方法 Pending WO2025033511A1 (ja)

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CN202480037864.2A CN121285649A (zh) 2023-08-10 2024-08-08 蒸镀掩模以及电子器件的制造方法
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US20200044010A1 (en) * 2017-04-14 2020-02-06 Shanghai Seeo Optronics Technology Co., Ltd Shadow mask for oled evaporation and manufacturing method therefor, and oled panel manufacturing method
JP2020158807A (ja) * 2019-03-25 2020-10-01 大日本印刷株式会社 マスク
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WO2023145951A1 (ja) * 2022-01-31 2023-08-03 大日本印刷株式会社 蒸着マスク、フレーム付き蒸着マスク、蒸着マスクの製造方法、有機デバイスの製造方法及びフレーム付き蒸着マスクの製造方法

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KR20250078513A (ko) * 2023-08-10 2025-06-02 도판 홀딩스 가부시키가이샤 증착 마스크, 및 전자 디바이스의 제조 방법

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JP2008189990A (ja) * 2007-02-05 2008-08-21 Seiko Epson Corp 蒸着用マスクおよび蒸着用マスクの製造方法
US20200044010A1 (en) * 2017-04-14 2020-02-06 Shanghai Seeo Optronics Technology Co., Ltd Shadow mask for oled evaporation and manufacturing method therefor, and oled panel manufacturing method
JP2020158807A (ja) * 2019-03-25 2020-10-01 大日本印刷株式会社 マスク
JP2022184708A (ja) * 2021-05-31 2022-12-13 キヤノン株式会社 蒸着マスク、及び有機電子デバイスの製造方法
WO2023145951A1 (ja) * 2022-01-31 2023-08-03 大日本印刷株式会社 蒸着マスク、フレーム付き蒸着マスク、蒸着マスクの製造方法、有機デバイスの製造方法及びフレーム付き蒸着マスクの製造方法

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