WO2025033509A1 - 蒸着マスク及び、電子デバイスの製造方法 - Google Patents

蒸着マスク及び、電子デバイスの製造方法 Download PDF

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Publication number
WO2025033509A1
WO2025033509A1 PCT/JP2024/028531 JP2024028531W WO2025033509A1 WO 2025033509 A1 WO2025033509 A1 WO 2025033509A1 JP 2024028531 W JP2024028531 W JP 2024028531W WO 2025033509 A1 WO2025033509 A1 WO 2025033509A1
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Prior art keywords
deposition
opening
deposition mask
substrate
vapor deposition
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PCT/JP2024/028531
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English (en)
French (fr)
Japanese (ja)
Inventor
葵 佐野
数馬 碓氷
浩之 道
涼真 茂木
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Toppan Holdings Inc
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Toppan Holdings Inc
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Priority to JP2024573596A priority Critical patent/JP7708340B2/ja
Priority to KR1020257020411A priority patent/KR20250112824A/ko
Priority to CN202480037831.8A priority patent/CN121263548A/zh
Publication of WO2025033509A1 publication Critical patent/WO2025033509A1/ja
Priority to JP2025112685A priority patent/JP2025129319A/ja
Priority to JP2025179712A priority patent/JP2026012861A/ja
Anticipated expiration legal-status Critical
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C23C14/042—Coating on selected surface areas, e.g. using masks using masks
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/228—Gas flow assisted PVD deposition
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/24—Vacuum evaporation
    • C23C14/243—Crucibles for source material

Definitions

  • the present invention relates to a deposition mask and a method for manufacturing an electronic device.
  • deposition masks are known that are used to paint three colors, RGB, when producing organic EL displays.
  • Patent Document 1 discloses a configuration in which, when forming multiple openings in a deposition mask, the openings are formed separately into a first portion and a second portion, and the first portion is tilted. However, the taper angle is not disclosed.
  • Patent document 2 discloses a deposition mask in which the sidewall surfaces of a grid thin film layer made of silicon nitride are formed as inclined surfaces.
  • the inclination of the sidewalls of the openings formed in the semiconductor layer causes deposition material to accumulate on the sidewalls, resulting in a problem of deterioration in the pattern dimensions of the deposited film.
  • the present invention aims to provide a deposition mask capable of depositing a deposition film with excellent pattern dimensions, and a method for manufacturing an electronic device using the deposition mask.
  • the deposition mask of this embodiment is a deposition mask that is disposed between a substrate to be deposited and a deposition source, and is used to deposit a deposition material from the deposition source onto the surface of the non-deposited substrate through openings.
  • the deposition mask has a first surface facing the substrate to be deposited and a second surface facing the deposition source, located on the opposite side of the first surface, and has a plurality of openings formed therethrough that penetrate between the first surface and the second surface, the opening width being greater than 3 ⁇ m and less than 5 ⁇ m, the sidewall surface of the opening being inclined so that the opening width narrows from the second surface side toward the first surface side, and the taper angle of the opening being greater than 50°.
  • a deposition film having excellent pattern dimensions can be stably formed.
  • the frequency of cleaning the deposition mask can be reduced, making it easier to control the quality of the deposition mask.
  • the occurrence of clogging of the openings can be reduced, and the life of the deposition mask can be extended.
  • FIG. 2 is a cross-sectional view showing an example of a deposition mask according to the present embodiment.
  • 2 is an enlarged cross-sectional view showing a part of the deposition mask of the present embodiment shown in FIG. 1.
  • 4 is a partially enlarged cross-sectional view showing an enlarged portion of an opening of the deposition mask of the present embodiment.
  • FIG. 1A to 1C are cross-sectional views showing a method for manufacturing an electronic device using the deposition mask of the present embodiment.
  • 1A to 1C are process diagrams illustrating an example of a method for manufacturing a deposition mask according to an embodiment of the present invention.
  • 1A to 1C are process diagrams illustrating an example of a method for manufacturing a deposition mask according to an embodiment of the present invention.
  • FIG. 1A to 1C are process diagrams illustrating an example of a method for manufacturing a deposition mask according to an embodiment of the present invention.
  • FIG. 11 is a cross-sectional view illustrating an example of a deposition mask according to another embodiment.
  • FIG. 11 is a cross-sectional view illustrating an example of a deposition mask according to another embodiment.
  • FIG. 11 is a cross-sectional view illustrating an example of a deposition mask according to another embodiment.
  • FIG. 11 is a cross-sectional view illustrating an example of a deposition mask according to another embodiment.
  • VR/AR Virtual reality/augmented reality
  • PPI Pixels Per Inch
  • OLED silicon-based organic light-emitting diode
  • Silicon-based OLED microdisplay technology is expected to achieve further miniaturization and high PPI. Furthermore, to effectively prepare for AR and VR as high-value-added industries, it is expected to realize ultra-high resolution displays of, for example, 1000 ppi or more. As a result, there is a growing need for deposition masks for RGB color separation used in the manufacturing process of OLED microdisplays.
  • the deposition mask has multiple openings that correspond to the deposited film, and the accuracy of the openings in the deposition mask is important for improving the pattern dimensions of the deposited film.
  • the deposition mask is placed between the substrate and the deposition source, and the deposition material travels from the deposition source through the openings in the deposition mask to reach the surface of the substrate. If the deposition material accumulates on the sidewall of the opening, the opening width becomes narrower than the actual width, making it difficult to form a deposition film with excellent pattern dimensions.
  • each opening is formed with a first portion in which the opening width gradually decreases, and a second portion in which the opening width is approximately constant. This shape is said to be able to prevent the deposition material from blocking the opening.
  • Patent Document 1 does not mention the relationship between the taper angle and the deposition material deposition.
  • Patent Document 1 has a fairly wide opening width, for example, 100 ⁇ m (0.1 mm) or more, and does not take into consideration the deposition material deposition in narrow opening widths of a few ⁇ m.
  • Patent document 2 also does not mention or suggest the relationship between the opening width and taper angle and the pattern dimensions.
  • the inventors have focused on the opening width and taper angle and developed a deposition mask that can increase the pattern dimensions of the deposited film.
  • Fig. 1 is a cross-sectional view of a deposition mask 1 in the present embodiment.
  • Fig. 2 is a cross-sectional view showing an enlarged portion of the deposition mask shown in Fig. 1.
  • Fig. 3 is a partially enlarged cross-sectional view showing an enlarged portion of an opening of the deposition mask in the present embodiment.
  • Fig. 4 is a cross-sectional view showing a method for manufacturing an electronic device using the deposition mask in the present embodiment.
  • the deposition mask 1 has a layered structure of a semiconductor layer 2, an insulating layer 3, and a support substrate 4, and is preferably constructed from an SOI (Silicon on Insulator) substrate 9.
  • SOI Silicon on Insulator
  • the semiconductor layer 2 is preferably a silicon single crystal layer, and is also called an active layer or membrane. There is no limitation on the thickness of the semiconductor layer 2, but it is about 1 ⁇ m to 300 ⁇ m.
  • the deposition mask 1 has multiple opening regions 15 and surrounding regions 16 located around the opening regions 15, and the surrounding regions 16 have a structure in which a semiconductor layer 2, an insulating layer 3, and a support substrate 4 are stacked.
  • the semiconductor layer 2 is disposed in the opening regions 15, that is, the insulating layer 3 and the support substrate 4 have been removed, and furthermore, multiple minute openings 5 are formed in each opening region 15.
  • FIG. 2 is an enlarged view of one of the opening regions 15 shown in FIG. 2, the semiconductor layer 2 has a first surface 2a and a second surface 2b that face each other in the thickness direction. An insulating layer 3 and a support substrate 4 are provided on the second surface 2b side.
  • the first surface 2a is the front surface facing the deposition substrate 10
  • the second surface 2b is the back surface facing the deposition source 11.
  • a plurality of openings 5 are formed in the semiconductor layer 2, penetrating between the first surface 2a and the second surface 2b. As shown in FIG. 2, the opening width of each opening 5 gradually narrows from the second surface 2b to the first surface 2a. Therefore, the sidewall surface 6 of the opening 5 is inclined.
  • the planar pattern of the openings 5 (the shape when viewed from directly above the semiconductor layer 2 toward the first surface 2a) is not limited, but examples include rectangles (including squares), polygons other than rectangles, circles, and ellipses. All the openings 5 may have the same planar pattern, or some may have different patterns. The openings 5 may be regularly arranged, irregularly arranged, or a mixture of regular and irregular arrangements.
  • the distance between adjacent openings 5 is not limited, but when viewed from the first surface 2a side, the distance is approximately 1 ⁇ m to 20 ⁇ m.
  • the outer peripheral shape of the semiconductor layer 2 is preferably a rectangular or disk-shaped wafer, and although there are no limitations on the diameter (the length of one side if rectangular), it is preferable for it to be approximately 100 mm to 500 mm. In this way, even if the diameter of the semiconductor layer 2 is large, each opening 5 can be formed uniformly.
  • the insulating layer 3 may be an oxide layer or a nitride layer, but is preferably an oxide layer, and more specifically, is preferably a silicon oxide (SiO 2 ) layer.
  • the insulating layer 3 is also called a BOX layer (Buried Oxide Layer).
  • the thickness of the insulating layer 3 is not limited, but is, for example, about 100 nm to 20 ⁇ m.
  • the insulating layer 3 shown in FIG. 1 is not provided in the opening region facing the opening 5 of the semiconductor layer 2, but has been removed, and is left only in the surrounding region of the opening region on the second surface 2b of the semiconductor layer 2.
  • the insulating layer 3 serves as an etching stopper for the semiconductor layer 2, and the presence of the insulating layer 3 enables stable processing.
  • the support substrate 4 shown in FIG. 1 is a semiconductor substrate, for example a silicon substrate.
  • the thickness of the support substrate 4 is not limited, but is, for example, about 100 ⁇ m to 1000 ⁇ m.
  • the support substrate 4 can function as the pillars 16a and the peripheral frame 16b surrounding the peripheral region 16 of the opening region 15 on the second surface 2b of the semiconductor layer 2. Therefore, the semiconductor layer 2 can be kept in a taut state by the support substrate 4, making tensioning unnecessary, and the deposition mask 1 of this embodiment can be attached to the deposition substrate 10 using an electrostatic chuck that utilizes electrostatic force.
  • the pillars 16a are located inside the peripheral frame 16b, and they all have the same length (height), but for example, the height of the pillars 16a may be lower than the peripheral frame. However, by making the heights uniform, strength can be maintained.
  • an alignment mark for positioning can be formed in the peripheral region on the first surface 2a side of the semiconductor layer 2.
  • the alignment mark can be formed, for example, in a concave shape on the first surface 2a, and can be formed to a depth that reaches the insulating layer 3.
  • the opening width W1 and the taper angle ⁇ 1 of the opening 5 are defined.
  • Method of calculating opening width W1 As shown in Fig. 2, the opening 5 gradually narrows from the second surface 2b toward the first surface 2a, and the opening width varies depending on the measurement location. For this reason, as shown in Fig. 2, the opening width W1 was obtained as the dimension in the planar direction along the first surface 2a where the opening width is narrowest.
  • the opening width W1 can be determined from an SEM image obtained using eCD-2 manufactured by KLA-Tencor.
  • the taper angle ⁇ 1 of the opening 5 is determined as follows. That is, as shown in Fig. 2, a straight line is connected between an end of the opening width W1 in the surface direction along the first surface 2a and an end of the opening width W2 in the surface direction along the second surface 2b, and the inclination angle between the straight line and the first surface 2a can be set as the taper angle ⁇ 1 of the opening 5.
  • the taper angle ⁇ 1 was determined by measuring the length of an SEM image obtained using a Hitachi High-Technologies Regulus 8220.
  • FIG. 3 is a partially enlarged cross-sectional view of one opening 5 formed in the deposition mask 1, showing the center point of the opening 5 in the height direction (thickness direction of the semiconductor layer 2). Note that reference numerals are mainly attached only to the side wall surface 6 of the opening 5 on the left side of the figure, but the cross-sectional shape is symmetrical, and the side wall surface 6 on the right side of the figure has the same configuration.
  • the side wall surface 6 of the opening 5 is formed with an uneven shape. That is, on the side wall surface 6, a plurality of convex portions 7 protruding inwardly of the opening 5 and concave portions 8 located between the convex portions 7 are formed continuously and repeatedly along the height direction of the opening 5.
  • an approximate straight line T1 was drawn connecting the lowest positions (bottoms A) of each recess 8a, 8b within the measurement range.
  • Bottom A is, for example, the farthest position when viewed from the center line O in the width direction of the opening 5.
  • the approximate straight line T1 can be found using the least squares method. Note that if an irregular recess 8 is formed within the measurement range (for example, if bottom A is at an extremely low position), the approximate straight line T1 can be drawn excluding that recess 8.
  • the inclination angle ⁇ 4 of the side wall surface 6 can be determined from the inclination angle between the approximate straight line T1 shown in Figure 3 and the first surface 2a.
  • the taper angle ⁇ 1 and the inclination angle ⁇ 4 described above are either the same or approximate, but depending on, for example, the state of the uneven shape of the side wall surface 6 and the pitch, the inclination of the approximate straight line T1 may change, and the taper angle ⁇ 1 and the inclination angle ⁇ 4 may deviate from each other. Therefore, the inclination of the side wall surface 6 is determined by measuring the taper angle ⁇ 1 of the opening 5.
  • the unevenness height difference in addition to the opening width W1 and the taper angle ⁇ 1 described above, the unevenness height difference can be obtained as follows.
  • the highest position (apex) B of the convex portion 7a was determined at the first half pitch P1.
  • the apex B is the closest position when viewed from the center line O of the opening 5 in the width direction.
  • a straight line S1 was drawn perpendicular to the approximated line T1 so as to intersect with the apex B.
  • the length of the straight line S1 from the approximated line T1 to the apex B was determined.
  • the length of this straight line S1 was defined as the unevenness height difference D1 at the first half pitch P1.
  • the unevenness height difference can be calculated in the same way as for the first half pitch P1. That is, the length of a straight line perpendicular to the approximate straight line T1 to the top B of each convex portion is calculated, and this straight line length is used as the unevenness height difference for each pitch.
  • Figure 3 shows the unevenness height difference D2 for the second half pitch P2.
  • five pitches of the uneven shape were measured by SEM at a midpoint located exactly in the middle of the thickness between the first surface 2a and the second surface 2b of the opening 5.
  • the number of pitches is too small, parameter noise becomes large, and if the number of pitches is too large, depending on the thickness, it may not be possible to ensure that number of pitches.
  • parameter calculations are time-consuming and complicated, so it is preferable to have a number of pitches within about 10 pitches.
  • measurements are basically performed at five pitches, but if this is difficult, the number of pitches can be changed as appropriate.
  • the pitch concept described above it is also possible to measure the height at, for example, five points in the center of the thickness using an SEM image.
  • the points with height can be regarded as convex portions, and the areas between them as concave portions.
  • fine irregularities may be formed on the surface of each recess 8a, 8b (or the bottom of the protruding portions 7a, 7b), but these fine irregularities can be ignored. For example, fine irregularities on the order of a few nm in wavelength or smaller can be cut off, and a waviness curve can be created to determine the tangent and the unevenness height difference.
  • the unevenness angle ⁇ 2 can be calculated as the angle between a straight line L1 that connects the top B of the convex portion 7a and the lowest (farthest from the center line O in the width direction of the opening 5) bottom A of the recess 8a located on the deposition substrate 10 side (upper side in the figure) as viewed from the convex portion 7a, and an approximated straight line T1.
  • the unevenness angle ⁇ 3 can be calculated as the angle between a straight line L2 that connects the top B of the convex portion 7a and the lowest (farthest from the center line O in the width direction of the opening 5) bottom A of the recess 8b located on the deposition source 11 side (lower side in the figure, see Figure 4) as viewed from the convex portion 7a, and an approximated straight line T1.
  • a small concave-convex angle ⁇ 2, ⁇ 3 means that the height of the convex portion 7 is low (the depth of the concave portion 8 is shallow) and the waviness of the side wall surface 6 is small.
  • the deposition mask 1 in this embodiment is (1)
  • the opening width W1 is greater than 3 ⁇ m and less than or equal to 5 ⁇ m;
  • the side wall surface 6 of the opening 5 is inclined so that the opening width narrows from the second surface 2 b facing the deposition source 11 side to the first surface 2 a facing the deposition substrate 10 side, and the taper angle ⁇ 1 of the opening 5 is greater than 50°.
  • the opening width W1 is in the range of more than 3 ⁇ m and not more than 5 ⁇ m.
  • the opening width W1 is preferably 4 ⁇ m or more and not more than 5 ⁇ m, and more preferably in the range of 4.5 ⁇ m or more and not more than 5 ⁇ m. This ensures the needs required for a deposition mask 1 having a semiconductor layer 2, and is particularly suitable for use as a deposition mask for RGB color separation used in the manufacturing process of OLED microdisplays.
  • the sidewall surface 6 of the opening is inclined so that the opening width narrows from the second surface 2b to the first surface 2a.
  • This allows a deposition film 13 having a desired pattern width W3 to be formed stably.
  • the size of the deposition film 13 can be easily controlled.
  • the deposition material 12 deposited on the sidewall surface 6 peels off from the sidewall surface 6, it is less likely to fly toward the deposition substrate 10. From a manufacturing perspective, by inclining the sidewall surface 6 of the opening 5, multiple openings 5 can be efficiently formed in the semiconductor layer 2 by deep etching.
  • the taper angle ⁇ 1 is set to about 90°, i.e., the side wall surface 6 is formed almost vertically, it is believed that the effect of the unevenness height difference Dn of the side wall surface 6 during deposition will become greater.
  • the opening width W1 is extremely narrow at a few ⁇ m, it is necessary to make the average value Ave and maximum value of the unevenness height difference Dn as small as possible.
  • the thickness of the semiconductor layer 2 There is also a relationship with the thickness of the semiconductor layer 2. In other words, if the thickness of the semiconductor layer 2 increases, it becomes difficult to form the side wall surface 6 as a vertical surface.
  • the side wall surface 6 is inclined, and the taper angle ⁇ 1 of the opening 5 is set to be greater than 50°.
  • the upper limit of the taper angle ⁇ 1 is less than 90°, preferably 88° or less, and more preferably 85° or less.
  • the taper angle ⁇ 1 includes an error of about ⁇ 3°.
  • FIG. 4 is a cross-sectional view of the deposition mask 1 of this embodiment, positioned between a deposition substrate 10 and a deposition source 11, showing one step in the method for manufacturing an electronic device.
  • the deposition material (deposition particles) 12 from the deposition source 11 passes through the openings 5 of the deposition mask 1 and reaches the surface 10a of the deposition substrate 10, where a deposition film 13 is formed.
  • the pattern width W3 of the deposition film 13 is measured and the ratio to the opening width W1 is calculated, the combination of the opening width W1 and taper angle ⁇ 1 that results in a pattern width ratio ((pattern width W3/opening width W1) ⁇ 100(%)) of 80% or more is considered to be the present embodiment, and the combination of the opening width W1 and taper angle ⁇ 1 that results in a pattern width ratio of less than 80% is considered to be a comparative example.
  • the deposition mask 1 of this embodiment can form the side wall surface 6 with an inclined surface by a manufacturing method described later. At this time, if the taper angle ⁇ 1 becomes small, the deposition material 12 is easily deposited on the side wall surface 6, but by specifying the taper angle ⁇ 1 according to the opening width W1, a range having a pattern width ratio of 80% or more has been found.
  • the required pattern ratio is set to 80% or more is that if it is below 80%, the deviation from the desired pattern width W3 of the deposition film 13 is too large, leading to a decrease in yield, and also because it leads to a decrease in the area that should emit light at the design position, such as coordinate position accuracy, leading to a decrease in the brightness of the light-emitting element itself, or because of the numerical value required for product quality assurance.
  • the pattern width ratio is set to 85% or more, preferably 90% or more, and more preferably 95% or more.
  • the opening width W1 is 4 ⁇ m or more and 5 ⁇ m or less, and the taper angle ⁇ 1 is 60° or more. This effectively makes it possible to achieve a pattern width ratio of 80% or more. It is also preferable that the opening width W1 is 4 ⁇ m or more and 5 ⁇ m or less, and the taper angle ⁇ 1 is 70° or more. This makes it possible to obtain an embodiment in which the pattern width ratio exceeds 90%.
  • the prior art has not mentioned a combination of the taper angle ⁇ 1 of the opening 5 and the opening width W1 that can improve the pattern width ratio when the opening width W1 is narrowed to a few ⁇ m.
  • the uneven shape of the side wall surface 6 of the opening 5 is not particularly limited in this embodiment, but as an example, it can be adjusted as follows.
  • the average value Ave of the unevenness height difference Dn is preferably 0.200 ⁇ m or less, more preferably 0.180 ⁇ m or less, and even more preferably 0.170 ⁇ m or less.
  • the lower limit of the average value Ave of the unevenness height difference Dn is not limited, but can be, for example, about 0.003 ⁇ m.
  • the deposition material 12 can be deposited on the side wall surface 6 of the opening 5 as little as possible, and the number of times the deposition mask 1 needs to be cleaned can be more effectively reduced, thereby extending the life of the deposition mask 1.
  • the maximum unevenness height difference Dn is preferably 0.300 ⁇ m or less, more preferably 0.250 ⁇ m or less, even more preferably 0.200 ⁇ m or less, and most preferably 0.100 ⁇ m or less.
  • the maximum unevenness height difference Dn is the maximum unevenness height difference when the unevenness height difference Dn is calculated for the multiple pitches described in FIG. 3.
  • the concave-convex angles ⁇ 2 and ⁇ 3 described in FIG. 3 are in the range of about 0.5° to 50°, preferably 45° or less, more preferably 40° or less, even more preferably 30° or less, even more preferably 20° or less, and even more preferably 10° or less.
  • the most preferable range of the concave-convex angles ⁇ 2 and ⁇ 3 is about 0.5° to 2°.
  • the concave-convex angle ⁇ 3 shown in FIG. 3 is preferably smaller than the concave-convex angle ⁇ 2. This makes it possible to prevent the deposition material 12 from depositing on the side wall surface 6.
  • 5A and 5B are process diagrams showing a first manufacturing method of the deposition mask 1 of the present embodiment.
  • the deposition mask 1 in the manufacturing process shown in FIG. 5 and FIG. 6 described later shows only one opening region 15 and its vicinity, as in FIG. 2, but actually, the multiple opening regions 15 shown in FIG. 1 are formed simultaneously.
  • FIG. 5A an SOI substrate 9 is prepared.
  • the SOI substrate 9 has a laminated structure of a semiconductor layer 2, an insulating layer 3, and a support substrate 4. The materials and thicknesses of each layer have been explained in FIG. 1, so please refer to that.
  • the diameter is not limited, but in this embodiment, it can accommodate up to about 500 mm.
  • a mask layer 14 is patterned on the surface of the semiconductor layer 2.
  • the mask layer 14 is preferably a resist, and can be patterned by exposure and development.
  • a plurality of through holes 14a are formed in the mask layer 14. These through holes 14a are an opening pattern for forming the openings 5 in the semiconductor layer 2, and the width dimension W4 of the through holes 14a is formed to a dimension of approximately 2 ⁇ m to 6 ⁇ m.
  • the semiconductor layer 2 exposed from the through hole 14a of the mask layer 14 is dry etched.
  • the semiconductor layer 2 is deep etched. It is preferable to use a method in which, for example, etching of Si with SF6 and generation of a polymer film with C4F8 are repeated to deeply dig silicon, and sidewall protection and bottom etching proceed alternately, by the so-called Bosch process.
  • Bosch process the sidewall surface 6 of the opening 5 formed in the semiconductor layer 2 has an uneven shape.
  • the composition of the etching gas, the flow rate, the pressure inside the etching chamber, the power of the high frequency power source, etc. are appropriately adjusted so as to form an inverse tapered surface. Furthermore, by adjusting these, it is possible to control the inclination angle of the inverse tapered surface (taper angle ⁇ 1 of opening 5) and the unevenness height difference Dn.
  • the Bosch process was carried out in a dry etching apparatus by alternately using SF6 gas and C4F8 gas.
  • Anisotropic dry etching using fluorine ions was carried out by applying a bias to the substrate to be etched using the same gas as that used in the mode in which isotropic dry etching using fluorine radicals was carried out using SF6 gas.
  • the processing conditions were SF6 gas at 0 to 500 sccm, C4F8 gas at 0 to 300 sccm, Platen LF at 0 to 1500 W, Coil RF at 300 to 1500 W, and chamber pressure at 1 to 10 Pa, and various conditions were adjusted.
  • multiple openings 5 can be deeply formed in the semiconductor layer 2, and at this time, the taper angle ⁇ 1 of the sidewall surface 6 of the openings 5 and the height difference between the protrusions and recesses can be appropriately adjusted.
  • the unevenness height difference Dn can also be reduced by, for example, performing deep etching of the silicon and then smoothing (processing to reduce the unevenness height difference) using a laser hydrogen annealing process.
  • the mask layer 14 is removed. This completes the SOI substrate 9 with multiple openings 5 formed in the semiconductor layer 2.
  • a protective layer 20 is formed on the surface of the semiconductor layer 2. This allows the entire surface of the semiconductor layer 2 to be appropriately protected.
  • the protective layer 20 is, for example, a resist film.
  • a mask layer 21 is formed on the surface of the support substrate 4, which corresponds to the back surface of the SOI substrate 9.
  • the mask layer 21 is a resist pattern.
  • the mask layer 21 is not formed in the opening region 15 that faces the opening 5 formed in the semiconductor layer 2 in the thickness direction, but is provided only in the surrounding region 16 (see also FIG. 1).
  • the mask layer 21 may be formed together with the mask layer 14 during the process shown in FIG. 5(b).
  • the support substrate 4 that is not covered by the mask layer 21 is removed by dry etching, and in the process shown in FIG. 5(h), the insulating layer 3 that appears when the support substrate 4 is removed is removed by wet etching. At this time, the semiconductor layer 2 is not affected by the wet etching, and maintains its shape with multiple openings 5.
  • FIG. 6 is a process diagram showing a second manufacturing method of the deposition mask 1 of this embodiment.
  • an SOI substrate 9 is prepared.
  • the SOI substrate 9 has a layered structure of a semiconductor layer 2, an insulating layer 3, and a support substrate 4.
  • the materials and thicknesses of each layer are explained in FIG. 1, so please refer to that.
  • the diameter is not limited, but in this embodiment, it can accommodate up to about 500 mm.
  • a mask layer 21 is formed on the surface of the support substrate 4, which corresponds to the back surface of the SOI substrate 9.
  • the mask layer 21 is a resist pattern.
  • the mask layer 21 is provided only in the peripheral region of the SOI substrate 9.
  • the support substrate 4 that is not covered by the mask layer 21 is removed by dry etching
  • the insulating layer 3 that is revealed by removing the support substrate 4 is removed by wet etching.
  • a mask layer 22 is formed on the back surface of the semiconductor layer 2.
  • the mask layer 22 can be formed from a resist pattern.
  • a pattern of multiple openings 22a is formed in the mask layer 22 by exposure and development.
  • the semiconductor layer 2 exposed from the opening 22a is etched.
  • This etching is dry etching, and although not limited thereto, it is preferable to use an etching gas that contains a fluorine compound and oxygen, and optionally a rare gas.
  • the fluorine compound may be, for example, one or more selected from CF 4 , SF 6 , NF 3 , BF 3 , PF 5 , and F 2
  • the rare gas may be, for example, one or more selected from helium and argon.
  • etching was performed using CF4 gas, O2 gas, and Ar gas in a dry etching apparatus.
  • the processing conditions were CF4 gas at 10 to 100 sccm, O2 gas at 0 to 100 sccm, Ar gas at 0 to 200 sccm, IPC power at 200 to 1000 W, RIE power at 0 to 1000 W, and chamber pressure at 1 to 10 Pa, and various conditions were adjusted.
  • an opening 5 is formed in the semiconductor layer 2, the width of which gradually decreases as it moves away from the mask layer 22 (towards the first surface 2a of the semiconductor layer 2). This allows the sidewall surface 6 of the opening 5 to be formed as an inclined surface. Then, in the step of FIG. 6(g), the mask layer 22 is removed. This completes the deposition mask 1.
  • a plurality of openings 5 can be formed in the semiconductor layer 2, and the sidewall surface 6 of the openings 5 can be formed as an inclined surface such that the opening width gradually narrows from the back surface (second surface 2b) of the semiconductor layer 2 facing the deposition source 11 toward the front surface (first surface 2a) facing the deposition substrate 10.
  • the opening width W1 and taper angle ⁇ 1 can be adjusted by various gas flow rates, chamber pressure, and power of the plasma generation source, etc.
  • the deposition mask 1 is disposed between a deposition substrate 10 and a deposition source 11. At this time, the first surface 2a of the semiconductor layer 2 of the deposition mask 1 faces the deposition substrate 10, and the second surface 2b of the semiconductor layer 2 faces the deposition source 11. A plurality of openings 5 are formed in the semiconductor layer 2, and the opening width is narrower on the first surface 2a side than on the second surface 2b side.
  • the deposition mask 1 is placed in a holder (not shown) of the deposition device, and the deposition mask 1 and the deposition substrate 10 can be fixed with an electrostatic chuck.
  • the deposition mask 1 and the deposition substrate 10 are rotated around the axial center of the holder as the rotation axis.
  • the deposition material (deposition particles) 12 from the deposition source 11 passes through the openings 5 in the deposition mask 1 and reaches the surface 10a of the deposition substrate 10, forming a deposition film 13.
  • examples of electronic devices include OLED microdisplay panels, liquid crystal panels, solar cells, etc.
  • the present invention is particularly suitable for a manufacturing method for an OLED microdisplay panel as an organic electronic device.
  • the pattern width W3 of the deposition film 13 can be ensured to be 80% or more of the opening width W1, preferably 90% or more, and more preferably 95% or more. In this way, a deposition film 13 with excellent pattern dimensions can be formed.
  • the opening width W1 of the opening 5 of the deposition mask 1 is set to be greater than 3 ⁇ m and less than 5 ⁇ m, and the taper angle ⁇ 1 of the opening 5 is set to be greater than 50°, thereby obtaining a high pattern dimension of the deposition film 13.
  • the opening width W1 is set to 4 ⁇ m or more and 5 ⁇ m or less, and the taper angle ⁇ 1 of the opening 5 is set to 60° or more, so that a deposition film 13 having a pattern width ratio of 80% or more can be stably formed.
  • the unevenness formed on the sidewall surface 6 of the opening 5 was uniformly defined by roughness that made it difficult for the deposition material to deposit, but the taper angle ⁇ 1 was not adjusted.
  • the pattern width ratio fluctuates greatly with changes in the taper angle ⁇ 1, and therefore, with the conventional control method, it was not possible to stably form a deposition film 13 having high pattern dimensions for a narrow opening width of several ⁇ m units.
  • the opening width W1 and the taper angle ⁇ 1 by combining two factors, the opening width W1 and the taper angle ⁇ 1, it is possible to stably form a deposition film 13 having a pattern width W3 with a pattern width ratio of 80% or more, as described above.
  • the deposition mask 1 of this embodiment can suppress the deposition of the deposition material 12, reduce the frequency of cleaning the deposition mask, and facilitate quality control of the deposition mask. It also reduces clogging of the openings, allowing the deposition mask to have a longer life.
  • the present invention is not limited to the above-mentioned embodiments and modifications, and may be modified, substituted, or altered in various ways without departing from the spirit of the technical idea. Furthermore, if the technical idea can be realized in a different way due to technological advances or derived other technologies, it may be implemented using that method. Therefore, the claims cover all embodiments that may fall within the scope of the technical idea.
  • a membrane 31 made of SiN, SiO2, or the like may be formed on the surface of a frame-shaped silicon substrate 30, and a plurality of openings 32 may be formed in the membrane 31 in the central region from which the silicon substrate 30 has been removed, or a single-layer structure may be formed in which a plurality of openings are formed in a semiconductor substrate (preferably a silicon substrate).
  • the membrane is formed by CVD, but it is preferable to use SiN from the viewpoint of easy stress control.
  • an SOI substrate 9 is used as in Figure 1, but in Figure 8, a SiN layer 33 is formed on the back side (support substrate 4 side, facing deposition source 11) of the SOI substrate 9, in Figure 9, a SiN layer 33 is formed on the front side (semiconductor layer 2 side, facing deposition substrate 10) of the SOI substrate 9, and in Figure 10, a SiN layer 33 is formed on both the back side and front side of the SOI substrate 9.
  • a SiN layer 33 is formed on the front side (semiconductor layer 2 side) of the SOI substrate 9
  • an opening 5 is formed in contiguous with the semiconductor layer 2 as shown in Figures 9 and 10.
  • the SiN layer 33 By providing the SiN layer 33, it becomes easier to control the stress of the deposition mask, and distortion and the like can be suppressed. Moreover, it is preferable that the SiN layer 33 formed on the front side of the SOI substrate 9 is thinner than the SiN layer 33 formed on the back side of the SOI substrate 9. Although not limited thereto, the thickness of the SiN layer 33 formed on the front side of the SOI substrate 9 is about 0.05 ⁇ m to 0.5 ⁇ m, and the thickness of the SiN layer 33 formed on the back side of the SOI substrate 9 is about 0.05 ⁇ m to 3 ⁇ m.
  • the SiN layer 33 formed on the front side of the SOI substrate 9 is formed thinner than the SiN layer 33 formed on the back side of the SOI substrate 9 in order to control the stress in a well-balanced manner between the front side and the back side.
  • the SOI substrate used had a support substrate (625 ⁇ m)/insulating layer (0.5 ⁇ m)/semiconductor layer (15 ⁇ m or 5 ⁇ m).
  • the parentheses indicate the thickness.
  • the support substrate was a Si substrate
  • the semiconductor layer was a Si layer
  • the insulating layer was a SiO 2 layer.
  • the outer diameter of the SOI substrate was 200 mm.
  • two types of SOI substrates were prepared, one with a semiconductor layer thickness of 15 ⁇ m and the other with a thickness of 5 ⁇ m.
  • step (b) shown in FIG. 5 and step (e) shown in FIG. 6 an opening pattern is formed in the mask layer (resist layer) by i-line exposure, and the opening width of the master plate used in forming this opening pattern was adjusted within the range of 2.0 ⁇ m to 6.0 ⁇ m.
  • the deposition mask 1 was formed using the manufacturing method shown in FIG. 5 and FIG. 6.
  • the opening width W1 was changed depending on the master plate used.
  • the opening width W1 and the taper angle ⁇ 1 of the side wall surface 6 formed in the semiconductor layer 2 were adjusted by the gas flow rate under the switching conditions of SF 6 and C 4 F 8 , the non-switching conditions, the chamber pressure, and the power of the plasma generation source. For example, in the dry etching of FIG.
  • anisotropic dry etching using fluorine ions was performed by applying a bias to the substrate to be etched using the same gas as that used in the mode in which isotropic dry etching using fluorine radicals is performed using SF 6 gas.
  • the processing conditions were SF 6 gas at 0 to 500 sccm, C 4 F 8 gas at 0 to 300 sccm, Platen LF at 0 to 1500 W, Coil RF at 300 to 1500 W, and chamber pressure at 1 to 10 Pa, and various conditions were adjusted.
  • the opening width W1 was defined as the width dimension in the surface direction along the first surface 2a of the semiconductor layer 2.
  • the opening width W1 can be obtained from an SEM image obtained using eCD-2 manufactured by KLA-Tencor.
  • the unevenness height difference Dn and taper angle ⁇ 1 were determined from SEM images taken using a Hitachi High-Tech Regulus 8220, using the method described in Figures 2 and 3. As described in Figure 3, they were determined by observing the unevenness shape formed on the side wall surface 6 at the midpoint of the opening height, over five pitches in the middle of the thickness. For details on how to determine the unevenness height difference Dn and taper angle ⁇ 1, please refer to the explanations in Figures 2 and 3.
  • Alq3 tris(8-hydroxyquinoline)aluminum
  • the pattern width W3 of the evaporated film was measured using a laser microscope (model number VK-X210, manufactured by Keyence Corporation) to determine the pattern width ratio ((W3/W1) x 100(%)) of the evaporated film to the opening width W1 of the evaporation mask.
  • Experimental examples in which the pattern width ratio was less than 70% were marked with ⁇
  • experimental examples in which the pattern width ratio was 70% to 80% with ⁇ experimental examples in which the pattern width ratio was 80% to 90% with ⁇
  • experimental examples in which the pattern width ratio was more than 90% with ⁇ The experimental results are shown in the following Tables 1 and 2.
  • Tables 1 and 2 are given in units of 10°, but these are representative values, and it was confirmed that all experimental examples fell within a range of ⁇ 3° from each representative value.
  • Table 1 shows the experimental results when the semiconductor layer thickness is 15 ⁇ m
  • Table 2 shows the experimental results when the semiconductor layer thickness is 5 ⁇ m.
  • Tables 1 and 2 there were experimental examples No. 1 to No. 24, and the opening width W1 was in the range of 3 ⁇ m to 5 ⁇ m.
  • experimental examples with a pattern width ratio evaluation of ⁇ or ⁇ are comparative examples.
  • experimental examples No. 6 to No. 8, No. 10 to No. 12, and No. 18 to No. No. 20, No. 22 to No. 24 were evaluated as ⁇ or ⁇ for the pattern width ratio and are examples.
  • the needs required for the deposition mask 1 having the semiconductor layer 2 can be met, and in particular, in order to be preferably used as a deposition mask for RGB color separation used in the manufacturing process of an OLED microdisplay, the opening width W1 is set to be greater than 4 ⁇ m and less than 5 ⁇ m, and the taper angle ⁇ 1 is set to be greater than 60°.
  • the opening width W1 is set to be greater than 4 ⁇ m and less than 5 ⁇ m
  • the taper angle ⁇ 1 is set to be greater than 60°.
  • the average value Ave of the unevenness height difference Dn is preferably 0.200 ⁇ m or less, more preferably 0.180 ⁇ m or less, and even more preferably 0.170 ⁇ m or less.
  • the lower limit of the average value Ave of the unevenness height difference Dn is set to 0.100 ⁇ m or more, and 0.130 ⁇ m or more.
  • the maximum irregularity height difference Dn is preferably 0.500 ⁇ m or less, more preferably 0.450 ⁇ m or less, even more preferably 0.400 ⁇ m or less, even more preferably 0.350 ⁇ m or less, and most preferably 0.300 ⁇ m or less.
  • the concave/convex angle ⁇ 2 described with reference to FIG. 3 was 11° to 41°.

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  • Metallurgy (AREA)
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PCT/JP2024/028531 2023-08-10 2024-08-08 蒸着マスク及び、電子デバイスの製造方法 Pending WO2025033509A1 (ja)

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CN202480037831.8A CN121263548A (zh) 2023-08-10 2024-08-08 蒸镀掩模以及电子器件的制造方法
JP2025112685A JP2025129319A (ja) 2023-08-10 2025-07-03 蒸着マスク及び、電子デバイスの製造方法
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US20200044010A1 (en) * 2017-04-14 2020-02-06 Shanghai Seeo Optronics Technology Co., Ltd Shadow mask for oled evaporation and manufacturing method therefor, and oled panel manufacturing method
JP2020158807A (ja) * 2019-03-25 2020-10-01 大日本印刷株式会社 マスク
JP2022184708A (ja) * 2021-05-31 2022-12-13 キヤノン株式会社 蒸着マスク、及び有機電子デバイスの製造方法
WO2023145951A1 (ja) * 2022-01-31 2023-08-03 大日本印刷株式会社 蒸着マスク、フレーム付き蒸着マスク、蒸着マスクの製造方法、有機デバイスの製造方法及びフレーム付き蒸着マスクの製造方法

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US20200044010A1 (en) * 2017-04-14 2020-02-06 Shanghai Seeo Optronics Technology Co., Ltd Shadow mask for oled evaporation and manufacturing method therefor, and oled panel manufacturing method
JP2020158807A (ja) * 2019-03-25 2020-10-01 大日本印刷株式会社 マスク
JP2022184708A (ja) * 2021-05-31 2022-12-13 キヤノン株式会社 蒸着マスク、及び有機電子デバイスの製造方法
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