WO2025032444A1 - 半導体装置、及び半導体装置の作製方法 - Google Patents

半導体装置、及び半導体装置の作製方法 Download PDF

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Publication number
WO2025032444A1
WO2025032444A1 PCT/IB2024/057484 IB2024057484W WO2025032444A1 WO 2025032444 A1 WO2025032444 A1 WO 2025032444A1 IB 2024057484 W IB2024057484 W IB 2024057484W WO 2025032444 A1 WO2025032444 A1 WO 2025032444A1
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Prior art keywords
insulating layer
layer
conductive layer
opening
conductive
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PCT/IB2024/057484
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English (en)
French (fr)
Japanese (ja)
Inventor
古谷一馬
八窪裕人
倉田求
澤井寛美
村川努
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to CN202480045695.7A priority Critical patent/CN121464732A/zh
Priority to KR1020267000719A priority patent/KR20260048534A/ko
Priority to JP2025538905A priority patent/JPWO2025032444A1/ja
Publication of WO2025032444A1 publication Critical patent/WO2025032444A1/ja
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components

Definitions

  • One aspect of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device. Another aspect of the present invention relates to a method for manufacturing a semiconductor device.
  • one embodiment of the present invention is not limited to the above technical field.
  • Examples of technical fields of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input/output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.
  • a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Also, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.
  • a CPU is a collection of semiconductor elements that have semiconductor integrated circuits (at least transistors and memory) that are processed into chips from semiconductor wafers and have electrodes that serve as connection terminals.
  • IC chips Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components in a variety of electronic devices.
  • transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices.
  • ICs integrated circuits
  • Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.
  • Patent Document 1 discloses a low-power consumption CPU that utilizes the property of low leakage current of transistors using oxide semiconductors.
  • Patent Document 2 discloses a memory device that can retain stored contents for a long period of time by utilizing the property of low leakage current of transistors using oxide semiconductors.
  • Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple overlapping memory cells.
  • Patent Document 4 discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using an oxide semiconductor film.
  • An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated, and a manufacturing method thereof.
  • an object of one embodiment of the present invention is to provide a highly reliable semiconductor device and a manufacturing method thereof.
  • an object of one embodiment of the present invention is to provide a semiconductor device that operates at a high speed, and a manufacturing method thereof.
  • an object of one embodiment of the present invention is to provide a semiconductor device that consumes low power, and a manufacturing method thereof.
  • an object of one embodiment of the present invention is to provide a manufacturing method of a semiconductor device with a high yield.
  • an object of one embodiment of the present invention is to provide a novel semiconductor device, and a manufacturing method thereof.
  • One aspect of the present invention has a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer, wherein the first insulating layer is located on the first conductive layer, the second conductive layer is located on the first insulating layer, the second insulating layer is located on the second conductive layer and on the first insulating layer, and the third conductive layer is located on the second insulating layer, the first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer have a first opening that reaches the first conductive layer, and the third insulating layer contacts a side of the second conductive layer inside the first opening, and the first semiconductor layer is The semiconductor device is in contact with the first conductive layer, the first semiconductor layer is in contact with the upper surface of the third conductive layer, the first semiconductor layer has a first region
  • the semiconductor device may have a second semiconductor layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a sixth insulating layer, and a seventh insulating layer, the fourth conductive layer being located on the fifth insulating layer, the fourth conductive layer being in contact with the second region, the sixth insulating layer being located on the fourth conductive layer, the fifth conductive layer being located on the sixth insulating layer, the sixth insulating layer and the fifth conductive layer having a second opening that reaches the fourth conductive layer, the second semiconductor layer being in contact with the fourth conductive layer and the fifth conductive layer and having a region located inside the second opening, the seventh insulating layer being located on the second semiconductor layer and being located inside the second opening, and the sixth conductive layer being located on the seventh insulating layer and being located inside the seventh insulating layer inside the second opening.
  • the semiconductor device may have a third semiconductor layer, a seventh conductive layer, an eighth conductive layer, an eighth insulating layer, and a ninth insulating layer, the eighth insulating layer being located on the sixth conductive layer, the seventh conductive layer being located on the eighth insulating layer, the eighth insulating layer and the seventh conductive layer having a third opening reaching the sixth conductive layer, the third semiconductor layer having a region in contact with the sixth conductive layer and the seventh conductive layer and located inside the third opening, the ninth insulating layer being located on the third semiconductor layer and located inside the third opening, and the eighth conductive layer being located on the ninth insulating layer and located inside the third opening.
  • the semiconductor device may have a ninth conductive layer and a tenth insulating layer
  • the eighth insulating layer may have an eleventh insulating layer and a twelfth insulating layer on the eleventh insulating layer
  • the ninth conductive layer is located on the eleventh insulating layer
  • the twelfth insulating layer is located on the ninth conductive layer and on the eleventh insulating layer
  • the eleventh insulating layer, the ninth conductive layer, and the twelfth insulating layer may have a third opening
  • the tenth insulating layer contacts the side of the ninth conductive layer inside the third opening
  • the third semiconductor layer contacts the tenth insulating layer inside the third opening
  • the third semiconductor layer may have a third region that faces the eighth conductive layer across the ninth insulating layer and faces the ninth conductive layer across the tenth insulating layer.
  • the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer each use a metal oxide
  • the metal oxide has two or three elements selected from indium, element M, and zinc
  • element M may be one or more elements selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.
  • one aspect of the present invention includes forming a first conductive layer, forming a first insulating layer on the first conductive layer, forming a second conductive layer on the first insulating layer, forming a second insulating layer on the second conductive layer and on the first insulating layer, forming a third conductive layer on the second insulating layer, forming a first opening in the third conductive layer, the second insulating layer, the second conductive layer, and the first insulating layer, reaching the first conductive layer, forming the third insulating layer to cover the first opening,
  • the third insulating layer is processed by anisotropic etching to expose an upper surface of the third conductive layer and the first conductive layer, a first semiconductor layer is formed to cover the third insulating layer and to be in contact with the upper surface of the third conductive layer and the first conductive layer, a fourth insulating layer is formed to cover the first semiconductor layer, a fifth insulating layer is formed on the fourth insulating layer to have a region located
  • a method for manufacturing a semiconductor device comprising: performing planarization treatment on the fifth insulating layer to form a sixth insulating layer having a region located inside the first opening; removing a part of the fourth insulating layer to form a seventh insulating layer having a region located inside the first opening; exposing at least a part of the top surface of the first semiconductor layer; forming a fourth conductive layer so as to contact the top surface of the sixth insulating layer and the top surface of the first semiconductor layer; forming an eighth insulating layer on the fourth conductive layer; forming a fifth conductive layer on the eighth insulating layer; forming a second opening in the fifth conductive layer and the eighth insulating layer to reach the fourth conductive layer; forming a second semiconductor layer to cover the second opening and to contact the fourth conductive layer and the fifth conductive layer; forming a ninth insulating layer to cover the second semiconductor layer; and forming a sixth conductive layer on the ninth insulating layer so as to have a region located inside the second opening.
  • a tenth insulating layer may be formed on the sixth conductive layer
  • a seventh conductive layer may be formed on the tenth insulating layer
  • a third opening reaching the sixth conductive layer may be formed in the seventh conductive layer and the tenth insulating layer
  • a third semiconductor layer may be formed to cover the third opening and to contact the sixth conductive layer and the seventh conductive layer
  • an eleventh insulating layer may be formed to cover the third semiconductor layer
  • an eighth conductive layer may be formed on the eleventh insulating layer to have a region located inside the third opening.
  • a tenth insulating layer is formed on the sixth conductive layer, a seventh conductive layer is formed on the tenth insulating layer, an eleventh insulating layer is formed on the seventh conductive layer and on the tenth insulating layer, an eighth conductive layer is formed on the eleventh insulating layer, a third opening reaching the sixth conductive layer is formed in the eighth conductive layer, the eleventh insulating layer, the seventh conductive layer, and the tenth insulating layer, a twelfth insulating layer is formed to cover the third opening, the twelfth insulating layer is processed by anisotropic etching to expose the upper surface of the eighth conductive layer and the sixth conductive layer, a third semiconductor layer is formed to cover the twelfth insulating layer and to contact the upper surface of the eighth conductive layer and the sixth conductive layer, a thirteenth insulating layer is formed to cover the third semiconductor layer, and a ninth conductive layer is formed on the thirteenth insul
  • the fourth insulating layer may be processed to remove at least a portion of the area of the fourth insulating layer that does not overlap with the sixth insulating layer.
  • a planarization process may be performed on the fifth insulating layer to form a fourth opening in the fifth insulating layer that overlaps with the first semiconductor layer, and the fourth insulating layer may be processed to remove an area of the fourth insulating layer that does not overlap with either the fifth insulating layer or the sixth insulating layer.
  • a semiconductor device that can be miniaturized or highly integrated, and a manufacturing method thereof can be provided.
  • a highly reliable semiconductor device and a manufacturing method thereof can be provided.
  • a semiconductor device that has a high operating speed and a manufacturing method thereof can be provided.
  • a semiconductor device that consumes low power and a manufacturing method thereof can be provided.
  • a manufacturing method of a semiconductor device with a high yield can be provided.
  • a novel semiconductor device and a manufacturing method thereof can be provided.
  • Fig. 1A is a circuit diagram showing a configuration example of a memory cell
  • Figs. 1B to 1D are plan views showing configuration examples of a semiconductor device.
  • 2A and 2B are cross-sectional views showing a configuration example of a semiconductor device.
  • 3A to 3D are plan views showing configuration examples of a semiconductor device.
  • 4A and 4B are cross-sectional views showing a configuration example of a semiconductor device.
  • 5A and 5B are plan views showing an example of the configuration of a semiconductor device
  • Fig. 5C and Fig. 5D are cross-sectional views showing an example of the configuration of a semiconductor device.
  • 6A and 6B are cross-sectional views showing a configuration example of a semiconductor device.
  • Fig. 1A is a circuit diagram showing a configuration example of a memory cell
  • Figs. 1B to 1D are plan views showing configuration examples of a semiconductor device.
  • 2A and 2B are cross-sectional views showing a configuration example of a semiconductor device
  • FIG. 7A is a circuit diagram showing a configuration example of a memory cell
  • Fig. 7B is a plan view showing a configuration example of a semiconductor device
  • Fig. 7C and Fig. 7D are cross-sectional views showing the configuration example of a semiconductor device.
  • 8A and 8B are cross-sectional views showing a configuration example of a semiconductor device.
  • 9A and 9B are cross-sectional views showing a configuration example of a semiconductor device.
  • 10A and 10B are cross-sectional views showing a configuration example of a semiconductor device.
  • 11A and 11B are cross-sectional views showing a configuration example of a semiconductor device.
  • 12A and 12B are cross-sectional views showing a configuration example of a semiconductor device.
  • 13A and 13B are cross-sectional views showing a configuration example of a semiconductor device.
  • 14A and 14B are cross-sectional views showing a configuration example of a semiconductor device.
  • 15A and 15B are cross-sectional views showing a configuration example of a semiconductor device.
  • 16A and 16B are cross-sectional views showing a configuration example of a semiconductor device.
  • 17A to 17D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 18A to 18C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 19A to 19C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 20A and 20B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 21A and 21B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 22A to 22C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 23A to 23C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 24A to 24C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 25A to 25D are cross-sectional views showing a method for forming a metal oxide film.
  • 26A to 26D are cross-sectional views showing a method for forming a metal oxide film.
  • FIG. 27 is a cross-sectional view showing a configuration example of a semiconductor device.
  • FIG. 28 is a cross-sectional view showing a configuration example of a semiconductor device.
  • FIG. 29 is a block diagram showing a configuration example of a semiconductor device.
  • 30A and 30B are perspective views showing a configuration example of a semiconductor device.
  • FIG. 31 is a block diagram illustrating the CPU.
  • 32A and 32B are perspective views showing a configuration example of a semiconductor device.
  • 33A and 33B are perspective views showing a configuration example of a semiconductor device.
  • 34A and 34B are diagrams illustrating the hierarchy of storage devices.
  • 35A and 35B are diagrams illustrating an example of an electronic component.
  • Fig. 36A to Fig. 36C are diagrams showing an example of a mainframe computer
  • Fig. 36D is a diagram showing an example of space equipment
  • Fig. 36E is a diagram showing an example of a storage system applicable to a data center.
  • ordinal numbers “first” and “second” are used for convenience and do not limit the number of components or the order of the components (e.g., the order of processes or the order of stacking).
  • an ordinal number attached to a component in one place in this specification may not match an ordinal number attached to the same component in another place in this specification or in the claims.
  • a transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and switching operations that control conduction or non-conduction.
  • transistor includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT).
  • a transistor using an oxide semiconductor or a metal oxide in a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide in a channel formation region may be referred to as an OS transistor.
  • a transistor having silicon in a channel formation region may be referred to as a Si transistor.
  • a transistor is an element having at least three terminals including a gate, a drain, and a source.
  • a transistor has a region (also called a channel formation region) in which a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and drain through the channel formation region.
  • a channel formation region refers to a region through which a current mainly flows.
  • source and drain may be interchanged when transistors of different polarity are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms “source” and “drain” may be used interchangeably.
  • the impurity of a semiconductor refers to, for example, anything other than the main component constituting the semiconductor.
  • an element with a concentration of less than 0.1 atomic % can be said to be an impurity.
  • the defect state density of the semiconductor may be increased or the crystallinity may be reduced.
  • the semiconductor is an oxide semiconductor
  • examples of the impurity that changes the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor.
  • Specific examples of the impurity include, for example, hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.
  • water may also function as an impurity.
  • oxygen vacancies also referred to as V O
  • V O oxygen vacancies
  • an oxynitride refers to a material whose composition contains more oxygen than nitrogen.
  • An oxynitride refers to a material whose composition contains more nitrogen than oxygen.
  • SIMS secondary ion mass spectrometry
  • XPS X-ray photoelectron spectroscopy
  • film and “layer” can be interchanged depending on the circumstances.
  • conductive layer can be changed to the term “conductive film.”
  • insulating film can be changed to the term “insulating layer.”
  • parallel refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less.
  • approximately parallel refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less.
  • Perfect refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less.
  • approximately perpendicular refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.
  • electrically connected includes cases where the connection is made via "something that has some kind of electrical action.”
  • something that has some kind of electrical action is not particularly limited as long as it allows the transmission and reception of electrical signals between the objects to be connected.
  • something that has some kind of electrical action includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.
  • the off-state current refers to leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state).
  • the off state refers to a state in which the voltage Vgs between the gate and source of an n-channel transistor is lower than the threshold voltage Vth (higher than Vth for a p-channel transistor).
  • the normally-on characteristic refers to a state in which a channel exists and current flows through the transistor even when no voltage is applied to the gate.
  • the normally-off characteristic refers to a state in which no current flows through the transistor when no potential is applied to the gate or when a ground potential is applied to the gate.
  • a tapered shape refers to a shape in which at least a part of the side of the structure is inclined with respect to the substrate surface or the surface to be formed.
  • the side of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature, or approximately planar with fine irregularities.
  • A when it is stated that A is located on B, at least a part of A is located on B. Therefore, for example, it can be rephrased as A has an area located on B.
  • a contacts B or A overlaps B when it is stated that A contacts B or A overlaps B, at least a part of A contacts B or overlaps B. Therefore, it can be rephrased as A has an area contacting B or A has an area overlapping B, respectively.
  • a covers B at least a part of A covers B. Therefore, for example, it can be rephrased as A has an area covering B.
  • step discontinuity refers to the phenomenon in which a layer, film, or electrode is divided due to the shape of the surface on which it is formed (e.g., a step, etc.).
  • arrows indicating the X direction, Y direction, and Z direction may be used.
  • the "X direction” is the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction” and "Z direction.”
  • the X direction, Y direction, and Z direction are directions that intersect with each other.
  • the X direction, Y direction, and Z direction are directions that are perpendicular to each other.
  • One aspect of the present invention relates to a semiconductor device in which a memory cell having a first transistor, a second transistor, and a third transistor is provided.
  • the first transistor, the second transistor, and the third transistor are stacked in this order from the bottom.
  • the first transistor, the second transistor, and the third transistor have regions where they overlap each other.
  • a semiconductor device in which memory cells are provided is also called a memory device.
  • the source electrode and drain electrode are located at different heights, and the current flowing through the semiconductor layer flows in the height direction (vertical direction). In other words, it can be said that the channel length direction has a height component. Therefore, the first to third transistors can be called VFETs (Vertical Field Effect Transistors), vertical transistors, vertical channel transistors, or vertical channel transistors.
  • VFETs Very Field Effect Transistors
  • the electrode located on the lower side of the source electrode and drain electrode is called the lower electrode
  • the electrode located on the upper side is called the upper electrode.
  • the source electrode, semiconductor layer, and drain electrode can be provided overlapping each other.
  • the same conductive layer can be used for the upper electrode of the first transistor and the lower electrode of the second transistor.
  • the same conductive layer can be used for the gate electrode of the second transistor and the lower electrode of the third transistor.
  • the first to third transistors are vertical transistors and are stacked, and the other of the source and drain of the first transistor can be electrically connected to one of the source and drain of the second transistor.
  • the gate of the second transistor can be electrically connected to one of the source and drain of the third transistor.
  • the area occupied by the memory cell can be reduced compared to when, for example, two or three of the first, second, and third transistors are formed on the same formation surface and the first to third transistors are so-called planar type transistors.
  • a semiconductor device that can be miniaturized or highly integrated can be realized.
  • the gate electrode of the first transistor is provided between the lower electrode of the first transistor and the upper electrode of the first transistor.
  • the gate electrode of the first transistor is provided so as to surround the semiconductor layer of the first transistor.
  • the semiconductor layer of the first transistor has a recess that overlaps with the lower electrode of the first transistor.
  • An insulating layer is filled in the recess.
  • a conductive layer that serves both as the upper electrode of the first transistor and the lower electrode of the second transistor is provided on the insulating layer. This makes it possible to electrically connect the other of the source and drain of the first transistor to one of the source and drain of the second transistor while forming the first transistor and stacking them as vertical transistors.
  • the conductive layer can be prevented from contacting the channel formation region of the first transistor.
  • the conductive layer can be prevented from penetrating into the recess, and therefore the electric field of the conductive layer can be prevented from being applied to the channel formation region of the first transistor. As a result, a highly reliable semiconductor device can be realized.
  • ⁇ Configuration Example 1 of Semiconductor Device> A configuration example of a semiconductor device according to one embodiment of the present invention will be described below. Specifically, a configuration example of a memory cell included in the semiconductor device according to one embodiment of the present invention and a configuration example of a transistor included in the memory cell will be described.
  • FIG. 1A is a circuit diagram showing an example configuration of a memory cell 10.
  • the memory cell 10 has a transistor 100, a transistor 200, and a transistor 300.
  • One of the source and drain of transistor 100 is electrically connected to wiring RBL.
  • the other of the source and drain of transistor 100 is electrically connected to one of the source and drain of transistor 200.
  • the gate of transistor 100 is electrically connected to wiring RWL.
  • the other of the source and drain of transistor 200 is electrically connected to wiring PL.
  • the gate of transistor 200 is electrically connected to one of the source and drain of transistor 300.
  • the other of the source and drain of transistor 300 is electrically connected to wiring WBL.
  • Transistor 300 can be a dual-gate transistor having two gates (a first gate and a second gate).
  • the first gate of transistor 300 can be referred to as a front gate or simply as a gate
  • the second gate can be referred to as a back gate.
  • the first gate can be referred to as a back gate
  • the second gate can be referred to as a front gate or simply as a gate.
  • the gate of transistor 300 is electrically connected to the wiring WWL
  • the back gate is electrically connected to the wiring BGL.
  • the wiring WWL and the wiring RWL function as word lines.
  • a signal that controls the on/off state of the transistor 300 is supplied to the wiring WWL.
  • a signal that controls the on/off state of the transistor 100 is supplied to the wiring RWL.
  • the wiring WBL functions as a bit line.
  • a data signal to be supplied to the memory cell 10 is supplied to the wiring WBL.
  • the transistor 300 When the transistor 300 is on, data corresponding to the potential of the wiring WBL is written to the memory cell 10.
  • the transistor 300 is turned off, the data written to the memory cell 10 is retained. Specifically, the gate potential of the transistor 200 is retained.
  • the wiring WWL to which a signal that controls the on/off of the transistor 300 is supplied can be called a write word line, and the wiring WBL can be called a write bit line.
  • the wiring RBL functions as a bit line.
  • the wiring PL functions as a power supply line and is supplied with a power supply potential.
  • the gate potential of the transistor 200 becomes a potential corresponding to the data.
  • the transistor 100 is turned on, a current having a magnitude corresponding to the gate potential of the transistor 200 flows between the wiring RBL and the wiring PL.
  • the potential of the wiring RBL becomes a potential corresponding to the data stored in the memory cell 10. Therefore, the data stored in the memory cell 10 can be read.
  • the reading can be non-destructive.
  • the wiring RWL to which a signal that controls the on/off of the transistor 100 is supplied can be called a read word line, and the wiring RBL can be called a read bit line.
  • the threshold voltage of the transistor 300 can be controlled by controlling the potential of the wiring BGL electrically connected to the back gate of the transistor 300.
  • the threshold voltage of the transistor 300 can be shifted in the positive direction by supplying a potential lower than the source potential or a potential lower than 0 V (preferably a negative potential) to the wiring BGL, thereby making it possible to make the transistor 300 have normally-off characteristics. This allows the gate potential of the transistor 200 to be held for a long period of time. Therefore, data written to the memory cell 10 can be held for a long period of time.
  • FIG. 1B is a plan view showing an example of the configuration of transistor 100.
  • FIG. 1C is a plan view showing an example of the configuration of transistor 200.
  • FIG. 1D is a plan view showing an example of the configuration of transistor 300. Note that in the plan views of FIG. 1B to FIG. 1D, some elements are omitted for clarity. Some elements are also omitted in the subsequent plan views.
  • FIG. 2A is a cross-sectional view taken along dashed lines A1-A2 in FIGS. 1B to 1D.
  • FIG. 2B is a cross-sectional view taken along dashed lines B1-B2 in FIGS. 1B to 1D.
  • FIGS. 2A and 2B show an example of the configuration of a memory cell 10.
  • the memory cell 10 has an insulating layer 110 on a substrate (not shown), a transistor 100, an insulating layer 180a, and an insulating layer 181 on the insulating layer 110, an insulating layer 180b on the insulating layer 180a, an insulating layer 181A on the insulating layer 180b, an insulating layer 183 on the insulating layer 181, an insulating layer 183A on the insulating layer 181A, a transistor 200 on the transistor 100, an insulating layer 280 on the transistor 100 and on the insulating layer 183A, a transistor 300 on the transistor 200, an insulating layer 380a on the transistor 200 and on the insulating layer 280, and an insulating layer 380b on the insulating layer 380a. That is, the transistor 100, the transistor 200, and the transistor 300 are stacked in this order from the bottom.
  • the transistors 100, 200, and the transistor 300 are provided so as to have overlapping regions.
  • the memory cell 10 may have a capacitance.
  • the conductive layer 320 or another conductive layer electrically connected to the conductive layer 320 can be one electrode of the capacitance.
  • a conductive layer provided on the same formation surface as the conductive layer 320 or a conductive layer provided on the same formation surface as the conductive layer 355 can be the other electrode of the capacitance.
  • one electrode of the capacitance is electrically connected to the gate of the transistor 200 and one of the source and drain of the transistor 300.
  • a power supply potential can be supplied to the other electrode of the capacitance.
  • Insulating layer 180a, insulating layer 180b, insulating layer 280, insulating layer 380a, and insulating layer 380b function as interlayer films.
  • insulating layer 180a and insulating layer 180b are collectively referred to as insulating layer 180
  • insulating layer 380a and insulating layer 380b are collectively referred to as insulating layer 380.
  • the transistor 100 has a conductive layer 120a, a conductive layer 120b on the conductive layer 120a, a conductive layer 155 on the insulating layer 180a, a conductive layer 140a on the insulating layer 180b, a conductive layer 140b on the conductive layer 140a, an insulating layer 135, a semiconductor layer 130, a conductive layer 220a on the semiconductor layer 130, and a conductive layer 220b on the conductive layer 220a.
  • the conductive layers 120a and 120b are collectively referred to as the conductive layer 120
  • the conductive layers 140a and 140b are collectively referred to as the conductive layer 140
  • the conductive layers 220a and 220b are collectively referred to as the conductive layer 220.
  • the transistor 200 has a conductive layer 220a, a conductive layer 220b on the conductive layer 220a, a conductive layer 240a on the insulating layer 280, a conductive layer 240b on the conductive layer 240a, a semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, a conductive layer 320a on the insulating layer 250, and a conductive layer 320b on the conductive layer 320a.
  • the conductive layers 240a and 240b are collectively referred to as the conductive layer 240
  • the conductive layers 320a and 320b are collectively referred to as the conductive layer 320.
  • the transistor 300 has a conductive layer 320a, a conductive layer 320b on the conductive layer 320a, a conductive layer 355 on the insulating layer 380a, a conductive layer 340a on the insulating layer 380b, a conductive layer 340b on the conductive layer 340a, an insulating layer 335, a semiconductor layer 330, an insulating layer 350 on the semiconductor layer 330, a conductive layer 365a on the insulating layer 350, and a conductive layer 365b on the conductive layer 365a.
  • the conductive layers 340a and 340b are collectively referred to as the conductive layer 340
  • the conductive layers 365a and 365b are collectively referred to as the conductive layer 365.
  • the conductive layer 120, the conductive layer 140, the conductive layer 220, the conductive layer 240, the conductive layer 320, the conductive layer 340, and the conductive layer 365 may have a single-layer structure or a stacked structure of three or more layers.
  • the conductive layer 155 and the conductive layer 355 may have a single-layer structure in FIG. 2A and FIG. 2B, the conductive layer 155 and the conductive layer 355 may have a stacked structure of two or more layers.
  • the conductive layer 120 functions as one of the source electrode and the drain electrode
  • the conductive layer 140 and the conductive layer 220 function as the other of the source electrode and the drain electrode
  • the conductive layer 155 functions as a gate electrode
  • the insulating layer 135 functions as a gate insulating layer.
  • the conductive layer 220 does not necessarily have to be included as a component of the transistor 100.
  • the conductive layer 220 functions as one of the source electrode and the drain electrode
  • the conductive layer 240 functions as the other of the source electrode and the drain electrode
  • the conductive layer 320 functions as a gate electrode
  • the insulating layer 250 functions as a gate insulating layer.
  • the conductive layer 320 functions as one of the source electrode and the drain electrode
  • the conductive layer 340 functions as the other of the source electrode and the drain electrode
  • the conductive layer 365 functions as a first gate electrode
  • the conductive layer 355 functions as a second gate electrode
  • the insulating layer 350 functions as a first gate insulating layer
  • the insulating layer 335 functions as a second gate insulating layer. That is, the transistor 300 can be a dual-gate transistor.
  • the conductive layer 365 also functions as a gate wiring.
  • the conductive layer 365 can function as a gate electrode, and the conductive layer 355 can function as a back gate electrode.
  • the insulating layer 350 can function as a gate insulating layer, and the insulating layer 335 can function as a back gate insulating layer.
  • the conductive layer 365 may function as a back gate electrode, and the conductive layer 355 may function as a gate electrode.
  • the insulating layer 350 can function as a back gate insulating layer, and the insulating layer 335 can function as a gate insulating layer.
  • the same conductive layer 220 can be used for the other of the source electrode and drain electrode of the transistor 100 and one of the source electrode and drain electrode of the transistor 200.
  • the other of the source and drain of the transistor 100 is electrically connected to one of the source and drain of the transistor 200.
  • the same conductive layer 320 can be used for the gate electrode of the transistor 200 and one of the source and drain electrodes of the transistor 300.
  • the gate of the transistor 200 is electrically connected to one of the source and drain of the transistor 300.
  • At least a portion of the conductive layer 120 functions as the wiring RBL shown in FIG. 1A.
  • At least a portion of the conductive layer 155 functions as the wiring RWL shown in FIG. 1A.
  • At least a portion of the conductive layer 240 functions as the wiring PL shown in FIG. 1A.
  • At least a portion of the conductive layer 355 functions as the wiring BGL shown in FIG. 1A.
  • At least a portion of the conductive layer 340 functions as the wiring WBL shown in FIG. 1A.
  • At least a portion of the conductive layer 365 functions as the wiring WWL shown in FIG. 1A.
  • the insulating layer 180a is located on the conductive layer 120 and on the insulating layer 110.
  • the insulating layer 180a is provided to cover the upper surface of the conductive layer 120b, the side surface of the conductive layer 120b, the side surface of the conductive layer 120a, and the upper surface of the insulating layer 110.
  • the conductive layer 155 is located on the insulating layer 180a.
  • the insulating layer 180b is located on the conductive layer 155 and on the insulating layer 180a.
  • the insulating layer 180b is provided to cover the upper surface of the conductive layer 155, the side surface of the conductive layer 155, and the upper surface of the insulating layer 180a.
  • the conductive layer 140 is located on the insulating layer 180b.
  • the insulating layer 180b is located on the insulating layer 180a, and the insulating layer 180a is located on the conductive layer 120.
  • the insulating layer 180a and the insulating layer 180b which function as interlayer films, are provided between the conductive layer 120 and the conductive layer 140.
  • the conductive layer 140 and the conductive layer 220 which function as the other of the source electrode and drain electrode of the transistor 100, are located above the conductive layer 120, which functions as one of the source electrode and drain electrode of the transistor 100. Therefore, the conductive layer 120 can be said to be the lower electrode of the transistor 100, and the conductive layer 140 and the conductive layer 220 can be said to be the upper electrode of the transistor 100.
  • the insulating layer 180a, the conductive layer 155, the insulating layer 180b, and the conductive layer 140 have an opening 190 that reaches the conductive layer 120.
  • the conductive layer 120 has a conductive layer 120a and a conductive layer 120b on the conductive layer 120a.
  • Figures 2A and 2B show an example in which the conductive layer 120b has a recess that overlaps with the opening 190.
  • the conductive layer 120 has a recess, the bottom surface of which corresponds to the bottom surface of the recess of the conductive layer 120b, and the side surface of which corresponds to the side surface of the recess of the conductive layer 120b.
  • the bottom of the opening 190 includes the bottom surface of the recess of the conductive layer 120b.
  • the sidewalls of the opening 190 include the side surfaces of the recess of the conductive layer 120b, the side surfaces of the insulating layer 180a, the side surfaces of the conductive layer 155, the side surfaces of the insulating layer 180b, the side surfaces of the conductive layer 140a, and the side surfaces of the conductive layer 140b.
  • FIGS. 2A and 2B show an example in which the conductive layer 120b has a first recess and a second recess that is located outside the first recess and has a shallow depth.
  • the second recess is provided in the conductive layer 120b, and then, when processing the insulating layer 135, the first recess is provided in the conductive layer 120b. Therefore, in FIGS. 2A and 2B, the side of the first recess in the conductive layer 120b is aligned with the surface of the insulating layer 135 facing the semiconductor layer 130.
  • the side of the second recess in the conductive layer 120b is aligned with, for example, the side of the insulating layer 180a facing the opening 190.
  • the first recess and the second recess may be collectively referred to as recesses.
  • the opening 190 includes an opening in the insulating layer 180a, an opening in the conductive layer 155, an opening in the insulating layer 180b, an opening in the conductive layer 140a, and an opening in the conductive layer 140b.
  • the opening in the region where the insulating layer 180a overlaps with the conductive layer 120a is a part of the opening 190
  • the opening in the region where the conductive layer 155 overlaps with the conductive layer 120a is another part of the opening 190
  • the opening in the region where the insulating layer 180b overlaps with the conductive layer 120a is a part of the opening 190
  • the opening in the region where the conductive layer 140a overlaps with the conductive layer 120a is another part of the opening 190
  • the opening in the region where the conductive layer 140b overlaps with the conductive layer 120a is another part of the opening 190.
  • the shape and size of the opening 190 in plan view may differ depending on each layer. Furthermore, when the shape of the opening 190 in plan view is circular, the openings in each layer may or may not be concentric. For example, at least one of the centers of the openings in each layer may not overlap with the center of the openings in the other layers.
  • At least some of the components of the transistor 100 are disposed inside the opening 190.
  • the insulating layer 135 and the semiconductor layer 130 are disposed such that at least some of them are located inside the opening 190.
  • the insulating layer 135 has at least a region located between the semiconductor layer 130 and the conductive layer 155.
  • the insulating layer 135 contacts the side of the conductive layer 155 inside the opening 190.
  • the insulating layer 135 is formed so as to cover the opening 190 and to have a region located on the conductive layer 140 after the opening 190 is formed, as will be described in detail later.
  • the insulating layer 135 is then processed by, for example, anisotropic etching until the top surface of the conductive layer 140 is exposed. This removes the region of the insulating layer 135 located on the top surface of the conductive layer 140 and the region located on the bottom surface of the opening 190, and the insulating layer 135 can be left only on the side surface inside the opening 190.
  • the insulating layer 135 after forming the conductive layer 140, it is possible to suppress the anisotropic etching of the insulating layer 135 from continuing even after the region of the insulating layer 135 located outside the opening 190 is removed, compared to the case where the insulating layer 135 is formed without forming the conductive layer 140. Therefore, for example, it is possible to prevent the side surface of the conductive layer 155 on the opening 190 side from being exposed. Therefore, for example, the conductive layer 155 and the semiconductor layer 130 are prevented from contacting each other. As a result, a highly reliable semiconductor device can be realized. Note that the transistor 100 does not need to have the conductive layer 140. In this case, the number of manufacturing steps of the transistor 100 can be reduced.
  • the insulating layer 135 contacts the bottom and side of the recess (specifically, the second recess) of the conductive layer 120b, and contacts the side of the insulating layer 180a, the side of the conductive layer 155, the side of the insulating layer 180b, the side of the conductive layer 140a, and the side of the conductive layer 140b inside the opening 190.
  • the semiconductor layer 130 contacts the bottom and side of the recess (specifically, the first recess) of the conductive layer 120b, the insulating layer 135, and the upper surface of the conductive layer 140b.
  • the insulating layer 135 is provided along at least a portion of the sidewall of the opening 190.
  • the semiconductor layer 130 has a region inside the opening 190 that faces the conductive layer 155 with the insulating layer 135 in between. At least a portion of this region of the semiconductor layer 130 is in contact with the insulating layer 135.
  • the conductive layer 155 is provided to surround the semiconductor layer 130 with the insulating layer 135 in between.
  • the conductive layer 155 functions as the gate electrode of the transistor 100
  • the insulating layer 135 functions as the gate insulating layer of the transistor 100.
  • the region of the semiconductor layer 130 facing the conductive layer 155 across the insulating layer 135 functions as the channel formation region of the transistor 100.
  • the region of the semiconductor layer 130 in contact with the conductive layer 120 functions as one of the source region and drain region of the transistor 100.
  • the region of the semiconductor layer 130 in contact with at least one of the conductive layer 140 and the conductive layer 220 functions as the other of the source region and drain region of the transistor 100.
  • the channel formation region of the transistor 100 is sandwiched between the source region and the drain region.
  • the portion of the semiconductor layer 130 that is disposed inside the opening 190 is provided to reflect the shape of the opening 190. Specifically, the semiconductor layer 130 is provided along the bottom and sidewalls of the opening 190. This provides a recess in the semiconductor layer 130 at a position that overlaps with the opening 190.
  • the insulating layer 181 is located inside the opening 190 and on the inside of the semiconductor layer 130.
  • the insulating layer 183 is located inside the opening 190 and on the inside of the insulating layer 181.
  • the insulating layer 183 is located on the insulating layer 181.
  • the insulating layer 181 is provided along the semiconductor layer 130.
  • a recess is provided in the semiconductor layer 130 at a position overlapping the opening 190.
  • a recess is also provided in the insulating layer 181 at a position overlapping the opening 190.
  • the insulating layer 183 is provided inside the insulating layer 181 so as to fill the opening 190.
  • the insulating layer 183 is provided so as to fill the recess of the insulating layer 181.
  • the insulating layer 183 is a planarized layer.
  • the conductive layer 220 is located on the insulating layer 183.
  • the conductive layer 220 also contacts the area of the semiconductor layer 130 that overlaps with the conductive layer 140.
  • the conductive layer 220 can be prevented from contacting the channel formation region of the semiconductor layer 130. Furthermore, by providing the insulating layer 183 so as to fill the opening 190, the conductive layer 220 can be prevented from entering inside the opening 190. This prevents the electric field of the conductive layer 220 from being applied to the channel formation region of the transistor 100. Therefore, the threshold voltage of the transistor 100 can be prevented from fluctuating due to the potential of the conductive layer 220. Furthermore, the transistor 100 can be prevented from being turned on during periods other than the period during which data stored in the memory cell 10 is read. Furthermore, the transistor 100 can be prevented from being turned off during the period during which data stored in the memory cell 10 is read. As a result, a semiconductor device having the memory cell 10 can be a highly reliable semiconductor device.
  • the upper surface of the insulating layer 183 is located above the upper surface of the semiconductor layer 130 in the region where it overlaps with the conductive layer 140.
  • the upper surface of the insulating layer 183 can be located at a position higher than the upper surface of the semiconductor layer 130 in the region where it overlaps with the conductive layer 140, for example, by the film thickness of the insulating layer 181.
  • the difference between the height of the upper surface of the insulating layer 183 from the reference plane and the height of the upper surface of the semiconductor layer 130 in the region where it overlaps with the conductive layer 140 from the reference plane can be, for example, the film thickness of the insulating layer 181 or a value close to it.
  • the upper surface of the insulating layer 183A is located above the upper surface of the semiconductor layer 130 in the region where it overlaps with the conductive layer 140.
  • the reference plane can be, for example, the surface of the substrate or the top surface of an interlayer film such as the insulating layer 110. The same applies to the following explanations.
  • the semiconductor layer 130 is formed, and then a first insulating film that will become the insulating layer 181 and a second insulating film that will become the insulating layer 183 on the first insulating film are formed, as will be described later in detail.
  • the insulating layer 183 is formed by performing a planarization process on the second insulating film until at least a part of the top surface of the first insulating film is exposed.
  • a planarization process also called a CMP process
  • CMP chemical mechanical polishing
  • a region of the first insulating film that does not overlap with either the insulating layer 183 or the conductive layer 140 is removed.
  • the insulating layer 181 is formed so as to overlap with the insulating layer 183, and the region of the semiconductor layer 130 that overlaps with the conductive layer 140 is exposed.
  • the planarization process may be performed not only on the second insulating film but also on the semiconductor layer 130.
  • the region of the semiconductor layer 130 that contacts the conductive layer 140 may be removed.
  • the upper surface of the insulating layer 183 is located at a position higher than the upper surface of the semiconductor layer 130 in the region overlapping with the conductive layer 140, for example, by the thickness of the insulating layer 181.
  • the upper surface of the insulating layer 183A is located at a position higher than the upper surface of the semiconductor layer 130 in the region overlapping with the conductive layer 140, for example, by the thickness of the insulating layer 181A.
  • the shortest distance from the upper surface of the insulating layer 110 to the upper surface of the conductive layer 120b that contacts the insulating layer 180a is preferably longer than the shortest distance from the upper surface of the insulating layer 110 to the lower surface of the insulating layer 181 inside the opening 190. This makes it possible to increase the contact area between the side surface of the conductive layer 120b and the semiconductor layer 130, and to reduce the contact resistance between the conductive layer 120b and the semiconductor layer 130. Therefore, the on-current of the transistor 100 can be increased.
  • FIG. 3A is a plan view showing an example of the configuration of the semiconductor layer 130, the conductive layer 140, the insulating layer 181, the insulating layer 183, the insulating layer 181A, and the insulating layer 183A.
  • FIG. 3B is a plan view in which the semiconductor layer 130 is omitted from FIG. 3A.
  • the insulating layer 181A and the insulating layer 183A located on the insulating layer 181A are provided so as to surround the semiconductor layer 130 and the conductive layer 140.
  • the insulating layer 181A and the insulating layer 183A are provided so as to surround the side surface located outside the opening 190 of the semiconductor layer 130 and the side surface opposite to the side surface on the opening 190 side of the conductive layer 140 in a plan view.
  • the insulating layer 181A is provided, for example, in contact with the side surface located outside the opening 190 of the semiconductor layer 130 and the side surface opposite to the side surface on the opening 190 side of the conductive layer 140.
  • the insulating layer 181A and the insulating layer 183A can be considered to have an opening 191 that overlaps with the semiconductor layer 130.
  • the insulating layer 181A and the insulating layer 183A can be considered to have an opening 191 that overlaps with the conductive layer 140 and the opening 190. Then, it can be considered that an island-shaped insulating layer 181 and an insulating layer 183 on the insulating layer 181 are provided inside the opening 191.
  • an island-like layer refers to a layer that is provided so as to be surrounded by an opening in a planar view.
  • insulating layer 181 and insulating layer 183 can be called island-like layers because they are provided so as to be surrounded by opening 191 in a planar view.
  • Opening 191 includes an opening in insulating layer 181A and an opening in insulating layer 183A.
  • the opening in the area where insulating layer 181A overlaps with semiconductor layer 130 is a part of opening 191
  • the opening in the area where insulating layer 183A overlaps with semiconductor layer 130 is another part of opening 191.
  • the shape and size of opening 191 in a plan view may differ depending on each layer.
  • the insulating layers 181 and 183 can be formed without using photolithography, as described in detail below. Therefore, by configuring the memory cell 10 to have insulating layers 181A and 183A, the number of manufacturing steps for the semiconductor device can be reduced compared to a configuration in which the memory cell 10 does not have insulating layers 181A and 183A. Therefore, the manufacturing cost of the semiconductor device can be reduced, and a low-cost semiconductor device can be provided.
  • insulating layer 181 and insulating layer 181A can be layers formed in the same process using the same material. Also, insulating layer 183 and insulating layer 183A can be layers formed in the same process using the same material.
  • the conductive layer 220 is located on the insulating layer 183.
  • the conductive layer 220 is provided so as to cover the upper surface of the insulating layer 183 and the side surface located outside the opening 190 of the insulating layer 181.
  • the conductive layer 220 contacts the region of the semiconductor layer 130 that overlaps with the conductive layer 140.
  • the insulating layer 280 is located on the conductive layer 220 and on the insulating layer 180b. Specifically, the insulating layer 280 is located on the conductive layer 220, the conductive layer 140, the semiconductor layer 130, the insulating layer 181A, and the insulating layer 183A. The insulating layer 280 is provided to cover the upper surface of the conductive layer 220b, the side of the conductive layer 220b, the side of the conductive layer 220a, the upper surface of the semiconductor layer 130, the side of the insulating layer 181A, and the upper surface of the insulating layer 183A.
  • the conductive layer 240 is located on the insulating layer 280. As described above, the insulating layer 280 is located on the conductive layer 220. As a result, the insulating layer 280, which functions as an interlayer film, is provided between the conductive layer 220 and the conductive layer 240.
  • the conductive layer 240 which functions as the other of the source electrode and drain electrode of the transistor 200, is located above the conductive layer 220, which functions as one of the source electrode and drain electrode of the transistor 200. Therefore, the conductive layer 220 can be said to be the lower electrode of the transistor 200, and the conductive layer 240 can be said to be the upper electrode of the transistor 200.
  • the insulating layer 280 and the conductive layer 240 have an opening 290 that reaches the conductive layer 220.
  • the conductive layer 220 has a conductive layer 220a and a conductive layer 220b on the conductive layer 220a.
  • Figures 2A and 2B show an example in which the conductive layer 220b has a recess that overlaps with the opening 290.
  • the conductive layer 220 has a recess
  • the bottom surface of the recess corresponds to the bottom surface of the recess of the conductive layer 220b
  • the side surface of the recess corresponds to the side surface of the recess of the conductive layer 220b.
  • the bottom of the opening 290 includes the bottom surface of the recess of the conductive layer 220b.
  • the side wall of the opening 290 includes the side surface of the recess of the conductive layer 220b, the side surface of the insulating layer 280, the side surface of the conductive layer 240a, and the side surface of the conductive layer 240b.
  • Figures 2A and 2B show an example in which the opening 290 overlaps with the opening 190.
  • the opening 290 includes an opening in the insulating layer 280 and an opening in the conductive layer 240.
  • the opening in the region where the insulating layer 280 overlaps with the conductive layer 220a is a part of the opening 290
  • the opening in the region where the conductive layer 240a overlaps with the conductive layer 220a is another part of the opening 290
  • the opening in the region where the conductive layer 240b overlaps with the conductive layer 220a is another part of the opening 290.
  • the shape and size of the opening 290 in a planar view may differ depending on each layer.
  • the shape of the opening 290 in a planar view is circular, the openings in each layer may or may not be concentric. For example, at least one of the centers of the openings in each layer may not overlap with the center of the openings in the other layers.
  • At least some of the components of the transistor 200 are disposed inside the opening 290.
  • the semiconductor layer 230 and the insulating layer 250 are disposed such that at least a portion of each is located inside the opening 290.
  • the semiconductor layer 230 contacts the bottom and side surfaces of the recess in the conductive layer 220, the insulating layer 280, the conductive layer 240a, and the side surfaces of the conductive layer 240b on the opening 290 side, and the top surface of the conductive layer 240b.
  • the area in which the semiconductor layer 230 contacts the conductive layer 220b can be increased. Therefore, the contact resistance between the semiconductor layer 230 and the conductive layer 220b can be reduced.
  • the shortest distance from the upper surface of the insulating layer 110 to the upper surface of the conductive layer 220b that contacts the insulating layer 280 is longer than the shortest distance from the upper surface of the insulating layer 110 to the lower surface of the insulating layer 250 inside the opening 290.
  • the shortest distance from the top surface of the insulating layer 110 to the top surface of the conductive layer 220b that contacts the insulating layer 280 is more preferably equal to or greater than the shortest distance from the top surface of the insulating layer 110 to the bottom surface of the conductive layer 320a inside the opening 290, and is even more preferably longer than the shortest distance.
  • a gate electric field is also easier to be applied to the region of the semiconductor layer 230 that contacts the conductive layer 220b, the on-current of the transistor 200 can be increased.
  • the electrical characteristics of the transistor 200 can be improved.
  • the portion of the semiconductor layer 230 that is disposed inside the opening 290 is provided to reflect the shape of the opening 290. Specifically, the semiconductor layer 230 is provided along the bottom and sidewalls of the opening 290. This provides a recess in the semiconductor layer 230 at a position that overlaps with the opening 290.
  • the insulating layer 250 is located on the semiconductor layer 230 and on the insulating layer 280.
  • the insulating layer 250 is located inside the opening 290 and on the inner side of the semiconductor layer 230.
  • the insulating layer 250 is provided so as to cover the upper and side surfaces of the semiconductor layer 230, the side surfaces of the conductive layer 240b, the side surfaces of the conductive layer 240a, and the upper surface of the insulating layer 280.
  • the insulating layer 250 can have a region in contact with the semiconductor layer 230.
  • the insulating layer 250 can have a region in contact with the semiconductor layer 230, for example, inside the opening 290.
  • the insulating layer 250 is provided along the semiconductor layer 230. As described above, a recess is provided in the semiconductor layer 230 at a position overlapping the opening 290. As a result, a recess is also provided in the insulating layer 250 at a position overlapping the opening 290.
  • the conductive layer 320 is located on the insulating layer 250.
  • the conductive layer 320 is located inside the insulating layer 250 inside the opening 290.
  • the conductive layer 320 is provided so as to fill the opening 290 inside the insulating layer 250.
  • the conductive layer 320 is provided so as to fill the recess of the insulating layer 250.
  • Figures 2A and 2B show an example in which the conductive layer 320a is planarized.
  • the conductive layer 320 has a region inside the opening 290 that faces the semiconductor layer 230 with the insulating layer 250 sandwiched therebetween. This region functions as a channel formation region of the transistor 200.
  • the region of the semiconductor layer 230 in contact with the conductive layer 220 functions as one of the source region and drain region of the transistor 200.
  • the region of the semiconductor layer 230 in contact with the conductive layer 240 functions as the other of the source region and drain region of the transistor 200.
  • the channel formation region of the transistor 200 is sandwiched between the source region and the drain region, similar to the channel formation region of the transistor 100.
  • At least one layer constituting the conductive layer 320 is provided in the opening 290.
  • the conductive layer 320 has a stacked structure, it becomes more difficult to arrange all the layers constituting the conductive layer 320 in the opening 290 as the transistor 200 is miniaturized and the diameter of the opening 290 becomes smaller.
  • FIG. 2A and FIG. 2B an example is shown in which the conductive layer 320 has a two-layer structure, in which only the conductive layer 320a is provided in the opening 290, and the conductive layer 320b on the conductive layer 320a is provided in a position overlapping with the opening 290. Note that both the conductive layer 320a and the conductive layer 320b may be located in the opening 290 depending on the diameter of the opening 290 and the thickness of the conductive layer 320a.
  • the insulating layer 380a is located on the conductive layer 320 and on the insulating layer 250.
  • the insulating layer 380a is provided to cover the upper surface of the conductive layer 320b, the side surface of the conductive layer 320b, the side surface of the conductive layer 320a, and the upper surface of the insulating layer 250.
  • the conductive layer 355 is located on the insulating layer 380a.
  • the insulating layer 380b is located on the conductive layer 355 and on the insulating layer 380a.
  • the insulating layer 380b is provided so as to cover the upper surface of the conductive layer 355, the side surface of the conductive layer 355, and the upper surface of the insulating layer 380a.
  • the conductive layer 340 is located on the insulating layer 380b. As described above, the insulating layer 380b is located on the insulating layer 380a, and the insulating layer 380a is located on the conductive layer 320. As described above, the insulating layer 380a and the insulating layer 380b, which function as interlayer films, are provided between the conductive layer 320 and the conductive layer 340.
  • the conductive layer 340 which functions as the other of the source electrode and drain electrode of the transistor 300, is located above the conductive layer 320, which functions as one of the source electrode and drain electrode of the transistor 300. Therefore, the conductive layer 320 can be said to be the lower electrode of the transistor 300, and the conductive layer 340 can be said to be the upper electrode of the transistor 300.
  • the insulating layer 380a, the conductive layer 355, the insulating layer 380b, and the conductive layer 340 have an opening 390 that reaches the conductive layer 320.
  • the conductive layer 320 has a conductive layer 320a and a conductive layer 320b on the conductive layer 320a.
  • Figures 2A and 2B show an example in which the conductive layer 320b has a recess that overlaps with the opening 390. In other words, an example is shown in which the conductive layer 320 has a recess, the bottom surface of which corresponds to the bottom surface of the recess of the conductive layer 320b, and the side surface of which corresponds to the side surface of the recess of the conductive layer 320b.
  • the bottom of the opening 390 includes the bottom surface of the recess of the conductive layer 320b.
  • the sidewall of the opening 390 includes the side of the recess of the conductive layer 320b, the side of the insulating layer 380a, the side of the conductive layer 355, the side of the insulating layer 380b, the side of the conductive layer 340a, and the side of the conductive layer 340b.
  • Figures 2A and 2B show an example in which the opening 390 overlaps with the opening 190 and the opening 290.
  • FIGS. 2A and 2B show an example in which the conductive layer 320b has a first recess and a second recess that is located outside the first recess and has a shallow depth.
  • the second recess is provided in the conductive layer 320b, and then, when processing the insulating layer 335, the first recess is provided in the conductive layer 320b. Therefore, in FIGS. 2A and 2B, the side of the first recess in the conductive layer 320b is aligned with the surface of the insulating layer 335 facing the semiconductor layer 330.
  • the side of the second recess in the conductive layer 320b is aligned with, for example, the side of the insulating layer 380a facing the opening 390.
  • the opening 390 includes an opening in the insulating layer 380a, an opening in the conductive layer 355, an opening in the insulating layer 380b, an opening in the conductive layer 340a, and an opening in the conductive layer 340b.
  • the opening in the region where the insulating layer 380a overlaps with the conductive layer 320a is a part of the opening 390
  • the opening in the region where the conductive layer 355 overlaps with the conductive layer 320a is another part of the opening 390
  • the opening in the region where the insulating layer 380b overlaps with the conductive layer 320a is a part of the opening 390
  • the opening in the region where the conductive layer 340a overlaps with the conductive layer 320a is another part of the opening 390
  • the opening in the region where the conductive layer 340b overlaps with the conductive layer 320a is another part of the opening 390.
  • the shape and size of the opening 390 in a plan view may differ depending on each layer. Furthermore, when the shape of the opening 390 in a plan view is circular, the openings in each layer may or may not be concentric. For example, at least one of the centers of the openings in each layer may not overlap with the center of the openings in the other layers.
  • At least some of the components of the transistor 300 are disposed inside the opening 390.
  • the insulating layer 335, the semiconductor layer 330, the insulating layer 350, and the conductive layer 365 are disposed such that at least a portion of each of them is located inside the opening 390.
  • the insulating layer 335 has a region located between the semiconductor layer 330 and the conductive layer 355.
  • the insulating layer 335 contacts the side of the conductive layer 355 inside the opening 390.
  • the insulating layer 335 contacts the bottom and side of the recess (specifically, the second recess) of the conductive layer 320b, and contacts the side of the insulating layer 380a, the side of the conductive layer 355, the side of the insulating layer 380b, the side of the conductive layer 340a, and the side of the conductive layer 340b inside the opening 390.
  • the semiconductor layer 330 contacts the bottom and side of the recess (specifically, the first recess) of the conductive layer 320b, the insulating layer 335, and the upper surface of the conductive layer 340b.
  • the conductive layer 320b has a recess, so that the area in which the semiconductor layer 330 contacts the conductive layer 320b can be increased. Therefore, the contact resistance between the semiconductor layer 330 and the conductive layer 320b can be reduced.
  • the shortest distance from the upper surface of the insulating layer 110 to the upper surface of the conductive layer 320b that contacts the insulating layer 380a is longer than the shortest distance from the upper surface of the insulating layer 110 to the lower surface of the insulating layer 350 inside the opening 390.
  • the shortest distance from the top surface of the insulating layer 110 to the top surface of the conductive layer 320b that is in contact with the insulating layer 380 is more preferably equal to or greater than the shortest distance from the top surface of the insulating layer 110 to the bottom surface of the conductive layer 365a inside the opening 390, and is even more preferably longer than the shortest distance.
  • a gate electric field is also easier to be applied to the region of the semiconductor layer 330 that is in contact with the conductive layer 320b, the on-current of the transistor 200 can be increased.
  • the electrical characteristics of the transistor 300 can be improved.
  • the insulating layer 335 is provided along at least a portion of the sidewall of the opening 390.
  • the semiconductor layer 330 has a region inside the opening 390 that faces the conductive layer 355 with the insulating layer 335 in between. At least a portion of this region of the semiconductor layer 330 is in contact with the insulating layer 335.
  • the conductive layer 355 is provided to surround the semiconductor layer 330 with the insulating layer 335 in between.
  • the insulating layer 350 is located on the semiconductor layer 330 and on the insulating layer 380b.
  • the insulating layer 350 is located inside the opening 390 and on the inner side of the semiconductor layer 330.
  • the insulating layer 350 is provided so as to cover the upper and side surfaces of the semiconductor layer 330, the side surfaces of the conductive layer 340b, the side surfaces of the conductive layer 340a, and the upper surface of the insulating layer 380b.
  • the insulating layer 350 can have a region in contact with the semiconductor layer 330.
  • the insulating layer 350 can have a region in contact with the semiconductor layer 330, for example, inside the opening 390.
  • the insulating layer 350 is provided along the semiconductor layer 330. As described above, a recess is provided in the semiconductor layer 330 at a position overlapping the opening 390. As a result, a recess is also provided in the insulating layer 350 at a position overlapping the opening 390.
  • the conductive layer 365 is located on the insulating layer 350.
  • the conductive layer 365 is located inside the opening 390 and on the inner side of the insulating layer 350.
  • the conductive layer 365 is provided so as to fill the opening 390 on the inner side of the insulating layer 350.
  • the conductive layer 365 is provided so as to fill the recess of the insulating layer 350.
  • the conductive layer 365 has a region inside the opening 390 that faces the semiconductor layer 330 with the insulating layer 350 sandwiched therebetween. This region functions as a channel formation region of the transistor 300.
  • the region of the semiconductor layer 330 in contact with the conductive layer 320 functions as one of the source region and drain region of the transistor 300.
  • the region of the semiconductor layer 330 in contact with the conductive layer 340 functions as the other of the source region and drain region of the transistor 300.
  • the channel formation region of the transistor 300 is sandwiched between the source region and the drain region, similar to the channel formation regions of the transistors 100 and 200.
  • the conductive layer 355 is provided to face the conductive layer 365 that functions as the gate electrode of the transistor 300, sandwiching the insulating layer 335, the semiconductor layer 330, and the insulating layer 350.
  • the semiconductor layer 330 has a region that faces the conductive layer 365 across the insulating layer 350 and faces the conductive layer 355 across the insulating layer 335.
  • the conductive layer 355 is provided to surround at least a part of the channel formation region of the transistor 300 with the insulating layer 335 sandwiched therebetween. As described above, the conductive layer 355 functions as a backgate electrode of the transistor 300. Therefore, the threshold voltage of the transistor 300 can be controlled by controlling the potential of the conductive layer 355. By supplying the conductive layer 355 with a potential, for example, lower than the source potential or a potential lower than 0 V (preferably a negative potential), the threshold voltage of the transistor 300 can be shifted in the positive direction, and the transistor 300 can have normally-off characteristics. As a result, the gate potential of the transistor 200 can be held for a long period of time as described above. Therefore, data written to the memory cell 10 can be held for a long period of time.
  • a potential for example, lower than the source potential or a potential lower than 0 V (preferably a negative potential
  • At least one layer constituting the conductive layer 365 is provided in the opening 390.
  • the conductive layer 365 has a stacked structure, it becomes more difficult to arrange all layers constituting the conductive layer 365 in the opening 390 as the transistor 300 is miniaturized and the diameter of the opening 390 becomes smaller.
  • FIG. 2A and FIG. 2B an example is shown in which the conductive layer 365 has a two-layer structure, in which only the conductive layer 365a is provided in the opening 390, and the conductive layer 365b on the conductive layer 365a is provided in a position overlapping with the opening 390. Note that both the conductive layer 365a and the conductive layer 365b may be located in the opening 390 depending on the diameter of the opening 390 and the thickness of the conductive layer 365a.
  • the semiconductor layer 130 including the channel formation region of the transistor 100, the semiconductor layer 230 including the channel formation region of the transistor 200, and the semiconductor layer 330 including the channel formation region of the transistor 300 can each have a metal oxide (also called an oxide semiconductor) that functions as a semiconductor.
  • the transistor 100, the transistor 200, and the transistor 300 can be said to be OS transistors.
  • oxygen vacancies ( VO ) and impurities are present in a channel formation region in an oxide semiconductor, the electrical characteristics of an OS transistor are likely to fluctuate and the reliability may be reduced. Furthermore, hydrogen near the oxygen vacancies may form a defect in which hydrogen is inserted into the oxygen vacancies (hereinafter sometimes referred to as VOH ), and may generate electrons that serve as carriers. For this reason, when oxygen vacancies are present in the channel formation region in the oxide semiconductor, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region in the oxide semiconductor is reduced and the channel formation region in the oxide semiconductor is made i-type (intrinsic) or substantially i-type.
  • the source and drain regions of an OS transistor are preferably regions having a higher oxygen vacancy, a higher VOH content, or a higher concentration of impurities such as hydrogen, nitrogen, or metal elements than the channel formation region, thereby increasing the carrier concentration and lowering the resistance.
  • the source and drain regions of an OS transistor are preferably regions having a higher carrier concentration and lower resistance than the channel formation region.
  • the transistor 100 is an OS transistor
  • the transistor 200 is an OS transistor
  • the transistor 300 is an OS transistor
  • the conductive layer 120 and the conductive layer 140 have a stacked structure
  • a conductive material containing oxygen is used for the layer of the stacked structure closest to the channel formation region, and the contact resistance with the semiconductor layer 130 is reduced, thereby shortening the current path between the source and drain, and thus increasing the on-current of the transistor 100.
  • the conductive layer 220, the conductive layer 240, the conductive layer 320, and the conductive layer 340 it is preferable to use a conductive material containing oxygen for the conductive layer 220b, the conductive layer 240a, the conductive layer 320b, and the conductive layer 340a.
  • a metal oxide having electrical conductivity also called an oxide conductor
  • FIG. 2A and 2B show a configuration in which the ends of the conductive layer 140a, the conductive layer 140b, and the semiconductor layer 130 are aligned outside the opening 190. Also, in FIG. 2A and FIG. 2B, a configuration in which the ends of the conductive layer 240a, the conductive layer 240b, and the semiconductor layer 230 are aligned outside the opening 290 is shown. Furthermore, in FIG. 2A and FIG. 2B, a configuration in which the ends of the conductive layer 340a, the conductive layer 340b, and the semiconductor layer 330 are aligned outside the opening 390 is shown.
  • the conductive layer 140a, the conductive layer 140b, and the semiconductor layer 130 are processed using the same mask, and the ends of these can be formed into the configuration shown in FIG. 2A and FIG. 2B.
  • the above-mentioned ends can be configured as shown in FIG. 2A and FIG. 2B.
  • the above-mentioned ends can be configured as shown in FIG. 2A and FIG. 2B.
  • any of the ends of the semiconductor layer 130, the ends of the conductive layer 140a, and the ends of the conductive layer 140b may be located inside or outside the others.
  • any of the ends of the semiconductor layer 230, the ends of the conductive layer 240a, and the ends of the conductive layer 240b may be located inside or outside the others.
  • any one of the ends of the semiconductor layer 330, the conductive layer 340a, and the conductive layer 340b may be located on the inside or outside of the others.
  • the conductive layer 140 has an opening 190 in a region overlapping with the conductive layer 120.
  • the conductive layer 140 is not located inside the opening 190 of the insulating layer 180b, for example.
  • the conductive layer 140 does not have a region in contact with the side of the insulating layer 180b inside the opening 190.
  • the opening 190 can be formed in the conductive layer 140, the insulating layer 180b, the conductive layer 155, and the insulating layer 180a at once.
  • the film thickness distribution of the insulating layer 135, the semiconductor layer 130, etc. provided inside the opening 190 can be made uniform.
  • the conductive layer 240 has an opening 290 in the region where it overlaps with the conductive layer 220, and it is preferable that the opening 290 is not located inside the opening 290 of the insulating layer 280, for example.
  • the conductive layer 340 has an opening 390 in the region where it overlaps with the conductive layer 320, and it is preferable that the opening 390 is not located inside the opening 390 of the insulating layer 380b, for example.
  • FIGS. 2A and 2B show a configuration in which the side of the conductive layer 140 inside the opening 190 and the side of the insulating layer 180b inside the opening 190 are flush (aligned, or roughly aligned), but the present invention is not limited to this.
  • the side of the conductive layer 140 inside the opening 190 and the side of the insulating layer 180b inside the opening 190 may be discontinuous.
  • the inclination of the side of the conductive layer 140 inside the opening 190 and the inclination of the side of the insulating layer 180b inside the opening 190 may be different from each other.
  • the taper angle of the side of the conductive layer 140 inside the opening 190 is smaller than the taper angle of the side of the insulating layer 180b inside the opening 190.
  • the coverage of the semiconductor layer 130 on the side of the conductive layer 140 inside the opening 190 is improved, and defects such as voids can be reduced.
  • the inclination of the side surface of each layer inside opening 190 may be different.
  • the inclination of the side surface of each layer inside opening 190 may be different.
  • the above also applies to the inclination of the side surface of each layer inside opening 290 and the inclination of the side surface of each layer inside opening 390.
  • Transistor 100, transistor 200, and transistor 300 are each vertical transistors.
  • a source electrode, a semiconductor layer, and a drain electrode can be provided so as to overlap each other.
  • a conductive layer 120, a semiconductor layer 130, and a conductive layer 140 can be provided so as to overlap each other.
  • a conductive layer 220, a semiconductor layer 230, and a conductive layer 240 can be provided so as to overlap each other.
  • a conductive layer 320, a semiconductor layer 330, and a conductive layer 340 can be provided so as to overlap each other.
  • a conductive layer 120, a semiconductor layer 130, a conductive layer 140, a conductive layer 220, a semiconductor layer 230, a conductive layer 240, a conductive layer 320, a semiconductor layer 330, and a conductive layer 340 can be provided so as to overlap each other.
  • the transistor 100, the transistor 200, and the transistor 300 can be stacked.
  • the transistor 100, the transistor 200, and the transistor 300 can each be a vertical transistor, and the source electrode, the semiconductor layer, and the drain electrode can be stacked on top of each other.
  • the same conductive layer can be used for the other of the source electrode and drain electrode of the transistor 100 and one of the source electrode and drain electrode of the transistor 200.
  • the same conductive layer can be used for the gate electrode of the transistor 200 and one of the source electrode and drain electrode of the transistor 300.
  • the transistors 100, 200, and 300 are vertical transistors and are stacked, and the other of the source and drain of the transistor 100 can be electrically connected to one of the source and drain of the transistor 200.
  • the gate of the transistor 200 can be electrically connected to one of the source and drain of the transistor 300.
  • the area occupied by the memory cell can be made smaller than when, for example, two or three of the transistors 100, 200, and 300 are formed on the same formation surface and the transistors 100, 200, and 300 are so-called planar type transistors. Therefore, a semiconductor device that can be miniaturized or highly integrated can be realized.
  • Figure 3C is a plan view including a cross section between dashed lines A3-A4 shown in Figure 2A and a cross section between dashed lines B3-B4 shown in Figure 2B.
  • Figure 3D is a plan view including a cross section between dashed lines A5-A6 shown in Figure 2A and a cross section between dashed lines B5-B6 shown in Figure 2B.
  • Figures 3C and 3D can be said to be plan views of the XY plane.
  • Figure 4A is an enlarged view of a region including transistor 100 shown in Figure 2B.
  • Figure 4B is an enlarged view of a region including transistor 300 shown in Figure 2B.
  • an opening 190 is provided in the conductive layer 155 functioning as the gate electrode of the transistor 100, and the insulating layer 183, the insulating layer 181, the semiconductor layer 130, and the insulating layer 135 are concentrically provided inside the opening 190 in this order from the inside.
  • the entire circumference of the semiconductor layer 130 can be a channel formation region.
  • an opening 390 is provided in the conductive layer 355 functioning as the back gate electrode of the transistor 300, and the conductive layer 365a, the insulating layer 350, the semiconductor layer 330, and the insulating layer 335 are concentrically provided inside the opening 390 in this order from the inside.
  • the side surface of the conductive layer 365a provided in the center faces the side surface of the semiconductor layer 330 with the insulating layer 350 sandwiched therebetween. Therefore, in a plan view, the entire circumference of the semiconductor layer 330 becomes a channel formation region.
  • the channel width of the transistor 100 is determined by the periphery of the semiconductor layer 130, and the channel width of the transistor 300 is determined by the periphery of the semiconductor layer 330.
  • the channel width of the transistor 100 is determined by the width of the opening 190 (the diameter if the opening 190 is circular in plan view).
  • the channel width of the transistor 300 is determined by the width of the opening 390 (the diameter if the opening 390 is circular in plan view).
  • FIG. 3C shows the width D1 of the opening 190 and the channel width W1 of the transistor 100.
  • FIG. 3D shows the width D2 of the opening 390 and the channel width W2 of the transistor 300.
  • FIG. 4A also shows the width D1 of the opening 190
  • FIG. 4B also shows the width D2 of the opening 390.
  • the width D1 of the opening 190 and the width D2 of the opening 390 may vary in the depth direction (e.g., Z direction).
  • the shortest distance between the two side surfaces of the conductive layer 155 on the opening 190 side in a cross-sectional view can be used as the width D1 of the opening 190.
  • the minimum value of the width of the opening 190 in the conductive layer 155 can be used as the width D1 of the opening 190.
  • the width of the opening 190 at the highest position in the conductive layer 155, the width of the opening 190 at the lowest position, the width of the opening 190 at the midpoint between these, or the average value of these three widths may be used as the width D1.
  • the width D1 is determined using the width of the opening 190 in the conductive layer 155, but the method of determining the width D1 is not particularly limited.
  • the shortest distance between the two side surfaces on the opening 190 side of the insulating layer 180a, the insulating layer 180b, the conductive layer 140a, or the conductive layer 140b can be used as the width D1.
  • the width of the opening 190 at the highest position in the insulating layer 180a, the insulating layer 180b, the conductive layer 140a, or the conductive layer 140b, the width of the opening 190 at the lowest position, the width of the opening 190 at the midpoint between these, or the average value of these three widths may be used as the width D1.
  • the conductive layer 155, the opening 190, the insulating layer 180a, the insulating layer 180b, the conductive layer 140a, and the conductive layer 140b can be read as the conductive layer 355, the opening 390, the insulating layer 380a, the insulating layer 380b, the conductive layer 340a, and the conductive layer 340b, respectively, and the explanation of the width D1 can be referred to.
  • the width D1 of the opening 190 and the width D2 of the opening 390 are limited by the exposure limit of photolithography, and further miniaturization is difficult.
  • the width D1 of the opening 190 is set by the film thickness of each of the insulating layer 135, the semiconductor layer 130, the insulating layer 181, and the insulating layer 183 provided inside the opening 190.
  • the width D2 of the opening 390 is determined by the film thickness of each of the insulating layer 335, the semiconductor layer 330, the insulating layer 350, and the conductive layer 365a provided inside the opening 390.
  • the width D1 of the opening 190 and the width D2 of the opening 390 are, for example, 5 nm or more and 100 nm or less, preferably 5 nm or more and 60 nm or less, more preferably 10 nm or more and 50 nm or less, more preferably 10 nm or more and 40 nm or less, and even more preferably 20 nm or more and 30 nm or less.
  • the width D1 of the opening 190 corresponds to the diameter of the opening 190
  • the channel width W1 can be calculated as "D1 x ⁇ "
  • the width D2 of the opening 390 corresponds to the diameter of the opening 390
  • the channel width W2 can be calculated as "D2 x ⁇ ".
  • the above description of the channel width W2 of the transistor 300 and the width D2 of the opening 390 can be referred to.
  • the shortest distance between the two side surfaces of the insulating layer 280 on the opening 290 side in a cross-sectional view can be used as the width of the opening 290.
  • the minimum value of the width of the opening 290 in the insulating layer 280 can be used as the width of the opening 290.
  • the width of the opening 290 at the highest position in the insulating layer 280, the width of the opening 290 at the lowest position, the width of the opening 290 at the midpoint between these, or the average value of these three widths may be used as the width of the opening 290.
  • the shortest distance between the two side surfaces of the insulating layer 280, the conductive layer 240a, or the conductive layer 240b on the opening 290 side can be used as the width of the opening 290.
  • the width of the opening 290 at the highest position in the insulating layer 280, the conductive layer 240a, or the conductive layer 240b, the width of the opening 290 at the lowest position, the width of the opening 290 at the midpoint between these, or the average value of these three widths may be used as the width of the opening 290.
  • the openings 190, 290, and 390 are circular in plan view, but the present invention is not limited to this.
  • the openings 190, 290, and 390 can be, for example, a circle, an ellipse, or other nearly circular shape, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, a star-shaped polygon, or other polygonal shape with rounded corners.
  • the polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles equal to or less than 180 degrees).
  • the openings 190, 290, and 390 are preferably circular in plan view. By making them circular, the processing accuracy when forming the openings can be improved, and openings of a fine size can be formed.
  • a circle is not limited to a perfect circle.
  • FIG. 4A is an enlarged view of a region including the transistor 100 shown in FIG. 2B.
  • the regions of the semiconductor layer 130 are shown as regions 130i, 130n1, and 130n2. Note that in FIG. 4A, the hatching patterns of the regions 130n1 and 130n2 of the semiconductor layer 130 are different from, for example, the hatching pattern of the region 130i.
  • Region 130i is a region inside opening 190 that faces conductive layer 155 across insulating layer 135. At least a portion of region 130i can be in contact with insulating layer 135. Specifically, the outer (conductive layer 155 side) surface of region 130i in the region located inside opening 190 can be in contact with insulating layer 135.
  • Region 130n1 is a region in contact with conductive layer 120b and a region in its vicinity.
  • Region 130n2 is a region in contact with conductive layer 140b and a region in its vicinity.
  • the region that overlaps with conductive layer 140b of the semiconductor layer 130 can be included in region 130n2.
  • Region 130i can be a channel formation region of transistor 100.
  • Region 130n1 can be one of the source region and drain region of transistor 100.
  • Region 130n2 can be the other of the source region and drain region of transistor 100.
  • Regions 130n1 and 130n2 are low-resistance regions with a higher carrier concentration than region 130i.
  • the conductive layer 220 is provided so as to contact the region 130n2.
  • the upper surface of the insulating layer 183 is located above the upper surface of the semiconductor layer 130 in the region 130n2.
  • the upper surface of the insulating layer 183 can be located at a position higher than the upper surface of the semiconductor layer 130 in the region 130n2, for example, by the thickness of the insulating layer 181.
  • the difference between the height of the upper surface of the insulating layer 183 from the reference plane and the height of the upper surface of the semiconductor layer 130 in the region 130n2 from the quasi-plane can be set to, for example, the thickness of the insulating layer 181 or a value close to it.
  • the surface of the substrate or the upper surface of an interlayer film such as the insulating layer 110 can be used as the reference plane.
  • the upper surface of the insulating layer 183A is located above the upper surface of the semiconductor layer 130 in the region 130n2.
  • the upper surface of the insulating layer 183 By configuring the upper surface of the insulating layer 183 to be located above the upper surface of the semiconductor layer 130 in region 130n2, it is possible to prevent a decrease in the reliability of the semiconductor device due to the manufacturing process of the semiconductor device. Therefore, a highly reliable semiconductor device can be provided.
  • FIG. 4B is an enlarged view of a region including the transistor 300 shown in FIG. 2B.
  • the regions of the semiconductor layer 330 are shown as regions 330i, 330n1, and 330n2.
  • the hatching patterns of the regions 330n1 and 330n2 of the semiconductor layer 330 are different from the hatching pattern of, for example, region 330i.
  • Region 330i is a region inside opening 390 that faces conductive layer 365a across insulating layer 350.
  • Region 330n1 is a region that contacts conductive layer 320b and a region nearby it.
  • Region 330n2 is a region that contacts conductive layer 340b and a region nearby it.
  • the region that overlaps with conductive layer 340b of semiconductor layer 330 can be included in region 330n2.
  • Region 330i can be a channel formation region of transistor 300.
  • Region 330n1 can be one of the source region and drain region of transistor 300.
  • Region 330n2 can be the other of the source region and drain region of transistor 300.
  • Regions 330n1 and 330n2 are low-resistance regions with a higher carrier concentration than region 330i.
  • region 330dg is shown as a region of semiconductor layer 330.
  • Region 330dg faces conductive layer 365 across insulating layer 350, and faces conductive layer 355 across insulating layer 335.
  • Region 330dg can be a region included in region 330i.
  • channel formation region, source region, and drain region of transistor 200 refer to the above explanation of the channel formation region, source region, and drain region of transistor 300 by replacing semiconductor layer 330, opening 390, insulating layer 350, conductive layer 365a, conductive layer 320b, and conductive layer 340b with semiconductor layer 230, opening 290, insulating layer 250, conductive layer 320a, conductive layer 220b, and conductive layer 240b, respectively.
  • the channel length of the transistor 200 can be set by the film thickness of the insulating layer 280.
  • the channel length of the transistor 300 can be set by the film thicknesses of the insulating layer 380a, the conductive layer 355, and the insulating layer 380b. Therefore, the channel lengths of the transistors 200 and 300 can be made into very fine structures below the exposure limit of photolithography.
  • the channel lengths of the transistors 200 and 300 can be, for example, 0.1 nm to 60 nm, 0.1 nm to 50 nm, 1 nm to 40 nm, 1 nm to 30 nm, 5 nm to 20 nm, or 5 nm to 10 nm.
  • the channel length of the transistor 100 can be set by the film thickness of the conductive layer 155. Therefore, the channel length of transistor 100, like that of transistor 200 and transistor 300, can be made into an extremely fine structure below the exposure limit of photolithography.
  • the transistors 100, 200, and 300 in the memory cell 10 can have a larger on-state current than, for example, planar transistors. This makes it possible to provide a semiconductor device with a high operating speed.
  • the transistors 100, 200, and 300 can each have a channel formation region and one or both of a source region and a drain region inside the opening.
  • the area occupied by the memory cell 10 can be made smaller than when the transistors 100, 200, and 300 are planar type transistors in which the channel formation region, source region, and drain region are provided separately on the XY plane.
  • a semiconductor device that can be miniaturized or highly integrated can be realized.
  • Each layer constituting the semiconductor device of this embodiment may have a single-layer structure or a stacked structure.
  • FIGS. 2A and 2B show an example in which the conductive layer 120a, the conductive layer 220a, and the conductive layer 320a have a single-layer structure.
  • FIGS. 4A and 4B show an example in which the conductive layer 120a, the conductive layer 220a, and the conductive layer 320a have a stacked structure.
  • the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330 each have a channel formation region.
  • the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330 each further have a source region and a drain region.
  • the source region and the drain region are low-resistance regions having a higher carrier concentration than the channel formation region.
  • the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330 may each have a stacked structure of two or more layers. In the following, materials that can be used for the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330 when the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330 are oxide semiconductor layers will be described.
  • the crystallinity of the semiconductor material used in the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used.
  • the use of a single crystal semiconductor or a semiconductor having crystallinity is preferable because it can suppress deterioration of the transistor characteristics.
  • the band gap of a metal oxide that functions as a semiconductor is preferably 2.0 eV or more, and more preferably 2.5 eV or more.
  • Embodiment 2 For an oxide semiconductor layer that can be used as a semiconductor layer of a transistor of one embodiment of the present invention, the description in Embodiment 2 can be referred to. A detailed description thereof is omitted here.
  • the semiconductor device of this embodiment may also be applied to a transistor using another semiconductor material in the channel formation region.
  • another semiconductor material include semiconductors made of single elements, or compound semiconductors.
  • semiconductors made of single elements include silicon and germanium.
  • compound semiconductors include gallium arsenide and silicon germanium.
  • Other examples of compound semiconductors include organic semiconductors and nitride semiconductors.
  • the aforementioned oxide semiconductor is also a type of compound semiconductor. Note that these semiconductor materials may contain impurities as dopants.
  • Silicon that can be used as a semiconductor material for transistors includes single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon.
  • An example of polycrystalline silicon is low temperature polysilicon (LTPS).
  • the semiconductor layer of the transistor may have a layered material that functions as a semiconductor.
  • a layered material is a general term for a group of materials that have a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds.
  • a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Examples of the layered material include graphene, silicene, and chalcogenides.
  • Chalcogenides are compounds containing chalcogen (an element belonging to Group 16).
  • Examples of the chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
  • transition metal chalcogenides that can be used as the semiconductor layer of a transistor include molybdenum sulfide (representatively MoS 2 ), molybdenum selenide (representatively MoSe 2 ), molybdenum tellurium (representatively MoTe 2 ), tungsten sulfide (representatively WS 2 ), tungsten selenide (representatively WSe 2 ), tungsten tellurium (representatively WTe 2 ), hafnium sulfide (representatively HfS 2 ), hafnium selenide (representatively HfSe 2 ), zirconium sulfide (representatively ZrS 2 ), and zirconium selenide (representatively ZrSe 2 ).
  • MoS 2 molybdenum sulfide
  • MoSe 2 molybdenum selenide
  • MoTe 2 molybdenum tellurium
  • Insulating layer For the insulating layers (insulating layer 110, insulating layer 135, insulating layer 180a, insulating layer 180b, insulating layer 181, insulating layer 181A, insulating layer 183, insulating layer 183A, insulating layer 250, insulating layer 280, insulating layer 335, insulating layer 350, insulating layer 380a, insulating layer 380b, etc.) of the semiconductor device, it is preferable to use an inorganic insulating film.
  • the inorganic insulating film include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film.
  • oxide insulating film examples include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film.
  • nitride insulating film examples include a silicon nitride film and an aluminum nitride film.
  • Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film.
  • Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film.
  • An organic insulating film may be used for an insulating layer included in a semiconductor device.
  • Examples of materials with a high dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.
  • materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin.
  • inorganic insulating materials with a low relative dielectric constant include silicon oxide with added fluorine, silicon oxide with added carbon, and silicon oxide with added carbon and nitrogen. Another example is silicon oxide with vacancies. These silicon oxides may contain nitrogen.
  • a material that can have ferroelectricity may be used for the insulating layer of the semiconductor device.
  • materials that can have ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and HfZrO x (where X is a real number greater than 0).
  • materials that can have ferroelectricity include materials in which an element J1 (here, the element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide.
  • the ratio of the number of atoms of hafnium to the number of atoms of the element J1 can be set appropriately, and for example, the ratio of the number of atoms of hafnium to the number of atoms of the element J1 can be set to 1:1 or close thereto.
  • materials that can have ferroelectricity include materials in which an element J2 (here, the element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide.
  • the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set to or near 1: 1.
  • piezoelectric ceramics having a perovskite structure such as lead titanate (PbTiO x ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuthate tantalate (SBT), bismuth ferrite (BFO), or barium titanate may be used.
  • examples of materials that may have ferroelectricity include metal nitrides having element M1, element M2, and nitrogen.
  • element M1 is one or more selected from aluminum, gallium, and indium.
  • element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, and chromium.
  • the ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set appropriately.
  • metal oxides having element M1 and nitrogen may have ferroelectricity even if they do not contain element M2.
  • examples of materials that may have ferroelectricity include materials in which element M3 is added to the above metal nitride.
  • element M3 is one or more selected from magnesium, calcium, strontium, zinc, and cadmium.
  • the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set appropriately.
  • examples of materials that may have ferroelectric properties include perovskite-type oxynitrides such as SrTaO 2 N and BaTaO 2 N, and GaFeO 3 having a ⁇ -alumina structure.
  • metal oxides and metal nitrides are given as examples, but the present invention is not limited to these.
  • metal oxide nitrides in which nitrogen is added to the above-mentioned metal oxides, or metal nitride oxides in which oxygen is added to the above-mentioned metal nitrides, etc. may be used.
  • the insulating layer can have a laminated structure made of multiple materials selected from the materials listed above.
  • the crystal structure (characteristics) of the materials listed above can change not only depending on the film formation conditions but also on various processes, so in this specification, not only materials that exhibit ferroelectricity are called ferroelectrics, but also materials that can have ferroelectricity.
  • Metal oxides containing hafnium and/or zirconium can have ferroelectricity even in thin films of a few nm. Metal oxides containing hafnium and/or zirconium can also have ferroelectricity even in very small areas. Therefore, by using metal oxides containing hafnium and/or zirconium, it is possible to miniaturize semiconductor devices.
  • a layer of a material that may have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film.
  • a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device in this specification.
  • Ferroelectricity is believed to be manifested by the displacement of oxygen or nitrogen in the crystals contained in the ferroelectric layer by an external electric field. It is also presumed that the manifestation of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, in order for the insulating layer to manifest ferroelectricity, the insulating layer must contain crystals. In particular, it is preferable for the insulating layer to contain crystals having an orthorhombic crystal structure, since ferroelectricity is manifested.
  • the crystal structure of the crystals contained in the insulating layer may be one or more selected from the cubic, tetragonal, orthorhombic, monoclinic, and hexagonal crystal systems.
  • the insulating layer may have an amorphous structure. In this case, the insulating layer may be a composite structure having an amorphous structure and a crystalline structure.
  • a Group 3 element also called a IIIa element
  • the oxygen vacancy concentration in the oxide increases, making it easier to form crystals having an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals having an orthorhombic crystal structure and increases the amount of residual polarization.
  • the amount of Group 3 element added is too large, the crystallinity of the oxide may decrease and ferroelectricity may not be easily expressed.
  • the content of Group 3 element in an oxide having one or both of hafnium and zirconium is preferably 0.1 atomic% or more and 10 atomic% or less, more preferably 0.1 atomic% or more and 5 atomic% or less, and even more preferably 0.1 atomic% or more and 3 atomic% or less.
  • the content of Group 3 element refers to the ratio of the number of atoms of Group 3 element to the sum of the number of atoms of all metal elements contained in the layer.
  • the Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.
  • an insulating layer having a function of suppressing the permeation of impurities and oxygen for example, an insulating layer containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or a stacked layer.
  • metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide
  • metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.
  • examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide.
  • examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate).
  • Examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon oxide nitride, and silicon nitride.
  • an insulating layer such as a gate insulating layer that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter, may be referred to as excess oxygen).
  • an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, whereby oxygen vacancies in the oxide semiconductor layer can be reduced.
  • Examples of insulating layers that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.
  • the dielectric constant be low.
  • the parasitic capacitance that occurs between wiring can be reduced. Silicon oxide and silicon oxynitride are both thermally stable, and therefore are suitable for the insulating layer 110.
  • the concentration of impurities such as water and hydrogen in the insulating layer 110 is reduced. This makes it possible to suppress the intrusion of impurities such as water and hydrogen into the channel formation region of the semiconductor layer 130.
  • a barrier insulating layer against hydrogen as the insulating layer 110.
  • the insulating layer 110 provided on the outside of the semiconductor layer 130 have barrier properties against hydrogen, it is possible to suppress the diffusion of hydrogen into the semiconductor layer 130.
  • Materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon oxynitride.
  • a barrier insulating layer refers to an insulating layer having a barrier property.
  • the barrier property refers to a property that a corresponding substance is difficult to diffuse (also referred to as a property that a corresponding substance is difficult to permeate, a property that the permeability of a corresponding substance is low, or a function of suppressing the diffusion of a corresponding substance).
  • hydrogen when described as a corresponding substance refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, and a substance bonded to hydrogen such as a water molecule and OH ⁇ .
  • impurities when described as a corresponding substance refer to impurities in a channel formation region or a semiconductor layer unless otherwise specified, and refer to at least one of, for example, a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N 2 O, NO, and NO 2, etc.), a copper atom, etc.
  • oxygen when described as a corresponding substance refers to at least one of, for example, an oxygen atom, an oxygen molecule, etc.
  • a silicon nitride film as the insulating layer 110.
  • the insulating layer 180a, the insulating layer 180b, the insulating layer 280a, the insulating layer 280b, the insulating layer 380a, and the insulating layer 380b each have the aforementioned barrier insulating layer against hydrogen.
  • the insulating layer 180a and the insulating layer 180b are provided so as to surround the semiconductor layer 130.
  • the insulating layer 180a and the insulating layer 180b provided on the outside of the semiconductor layer 130 have a barrier property against hydrogen, so that the diffusion of hydrogen into the semiconductor layer 130 can be suppressed.
  • the insulating layer 280a and the insulating layer 280b have a barrier property against hydrogen, so that the diffusion of hydrogen into the semiconductor layer 230 can be suppressed.
  • each of insulating layer 180a, insulating layer 180a, insulating layer 180b, insulating layer 280a, insulating layer 280b, insulating layer 380a, and insulating layer 380b has, for example, one or both of an aluminum oxide film and a silicon nitride film.
  • Silicon nitride also has a barrier property against oxygen. Therefore, by using silicon nitride for insulating layer 180a, insulating layer 180b, insulating layer 280a, insulating layer 280b, insulating layer 380a, and insulating layer 380b, oxygen is extracted from semiconductor layer 130, semiconductor layer 230, and semiconductor layer 330, and the formation of an excessive amount of oxygen vacancies in semiconductor layer 130, semiconductor layer 230, and semiconductor layer 330 can be suppressed.
  • the insulating layer 180a, the insulating layer 180b, the insulating layer 280a, the insulating layer 280b, the insulating layer 380a, and the insulating layer 380b it is possible to prevent excess oxygen from being supplied to the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330. Therefore, it is possible to prevent the channel formation regions of the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330 from becoming excessively oxygenated, thereby improving the reliability of the transistor 100, the transistor 200, and the transistor 300.
  • insulating layer 180a, insulating layer 180b, insulating layer 280a, insulating layer 280b, insulating layer 380a, and insulating layer 380b each have the above-mentioned oxide insulating film, oxynitride insulating film, or insulating layer having a region containing excess oxygen.
  • an insulating layer having a region containing excess oxygen can be formed by deposition using a sputtering method in an atmosphere containing oxygen.
  • a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas, the hydrogen concentration in the insulating layer 180a, the insulating layer 180b, the insulating layer 280a, the insulating layer 280b, the insulating layer 380a, and the insulating layer 380b can be reduced.
  • oxygen can be supplied from the insulating layer 180a, the insulating layer 180b, the insulating layer 280a, the insulating layer 280b, the insulating layer 380a, and the insulating layer 380b to the channel formation region of the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330, thereby reducing oxygen deficiency and VoH.
  • the concentrations of impurities such as water and hydrogen in the insulating layers 180a, 180b, 280a, 280b, 380a, and 380b are reduced. This can suppress the intrusion of impurities such as water and hydrogen into the channel formation regions of the semiconductor layers 130, 230, and 330.
  • a single layer structure of a silicon nitride film, a silicon nitride oxide film, or an aluminum oxide film for the insulating layer 180a, the insulating layer 180b, the insulating layer 280a, the insulating layer 280b, the insulating layer 380a, and the insulating layer 380b, respectively.
  • a three-layer structure in which a silicon nitride film, a silicon oxide film, and a silicon nitride film are stacked in this order for the insulating layer 180a, the insulating layer 180b, the insulating layer 280a, the insulating layer 280b, the insulating layer 380a, and the insulating layer 380b, respectively.
  • insulating layer 180a it is preferable to use a three-layer structure in which an aluminum oxide film, a silicon oxide film, and an aluminum oxide film are stacked in this order for the insulating layer 180a, the insulating layer 180b, the insulating layer 280a, the insulating layer 280b, the insulating layer 380a, and the insulating layer 380b, respectively.
  • the insulating layer 250 and the insulating layer 350 preferably have a function of capturing hydrogen and fixing hydrogen. This can reduce the hydrogen concentration in the semiconductor layer 230 and the semiconductor layer 330, particularly in the channel formation region of the transistor. As a result, VOH in the channel formation region can be reduced, and the channel formation region can be made i-type or substantially i-type.
  • the material of the insulating layer having the function of capturing or fixing hydrogen includes metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, for example, oxides containing hafnium and zirconium.
  • these metal oxides preferably have an amorphous structure.
  • the amorphous structure may be realized by including silicon in these oxides.
  • the metal oxide may have one or both of a crystalline region and a crystal grain boundary in a part.
  • the ability to capture or adhere to the corresponding substance can also be said to have the property of making the corresponding substance less likely to diffuse. Therefore, the ability to capture or adhere to the corresponding substance can be rephrased as barrier properties.
  • the layer in contact with the semiconductor layer 230 and the layer in contact with the semiconductor layer 330 have the function of capturing and fixing hydrogen. This makes it possible to more effectively capture or fix hydrogen contained in the semiconductor layer 230 and the semiconductor layer 330. Therefore, the hydrogen concentration in the semiconductor layer 230 and the semiconductor layer 330 can be reduced.
  • hafnium silicate or the like may be used as the layer of the insulating layer 250 in contact with the semiconductor layer 230 and the layer of the insulating layer 350 in contact with the semiconductor layer 330.
  • the layer has an amorphous structure.
  • the layer By making the layer an amorphous structure, the formation of grain boundaries can be suppressed. By suppressing the formation of grain boundaries, the flatness of the layer can be improved. This makes the film thickness distribution of the insulating layer 250 and the insulating layer 350 uniform, and reduces the number of extremely thin film thickness portions, thereby improving the breakdown voltage of the insulating layer 250 and the insulating layer 350. In addition, the film thickness distribution of the film provided on the insulating layer 250 and the film provided on the insulating layer 350 can be made uniform.
  • the insulating layer 250 and the insulating layer 350 can function as insulating films with low leakage current.
  • hafnium oxide is a high dielectric constant (high-k) material
  • hafnium silicate can also be a high dielectric constant (high-k) material depending on the silicon content. Therefore, when hafnium oxide or hafnium silicate is used for the gate insulation layer, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulation layer. It is also possible to reduce the equivalent oxide thickness (EOT) of the gate insulation layer.
  • EOT equivalent oxide thickness
  • an oxide containing one or both of aluminum and hafnium as the insulating layer 250 and the insulating layer 350, it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use aluminum oxide having an amorphous structure.
  • the aforementioned barrier insulating layer against hydrogen is preferable to use as the insulating layer 250 and the insulating layer 350.
  • a barrier insulating layer against hydrogen for the insulating layer 250 and the insulating layer 350, it is possible to suppress the diffusion of impurities contained in the conductive layer 320 and the conductive layer 365 to the semiconductor layer 230 and the semiconductor layer 330.
  • silicon nitride has high barrier properties against hydrogen and is therefore suitable for the insulating layer 250 and the insulating layer 350.
  • the insulating layer 250 and the insulating layer 350 may have an insulating layer having a structure that is stable against heat, such as silicon oxide or silicon oxynitride.
  • insulating layer 250 and insulating layer 350 may have an insulating layer having a thermally stable structure, such as silicon oxide or silicon oxynitride.
  • insulating layer 250 and insulating layer 350 may have an insulating layer with a heat-stable structure between a pair of insulating layers that have the function of capturing and fixing hydrogen.
  • the insulating layer 250 and the insulating layer 350 preferably have a barrier insulating layer against oxygen. This can suppress oxidation of the conductive layer 240, the conductive layer 320, the conductive layer 340, the conductive layer 365, and the like.
  • the insulating layer 250 and the insulating layer 350 have a stacked structure, it is preferable that the layer in contact with the conductive layer 240 and the layer in contact with the conductive layer 340 are barrier insulating layers against oxygen.
  • the layer in contact with the conductive layer 240, the layer in contact with the conductive layer 320, the layer in contact with the conductive layer 340, and the layer in contact with the conductive layer 365 are each preferably a barrier insulating layer against oxygen.
  • the layer of the insulating layer 250 and the layer of the insulating layer 350 that contacts the conductive layer 320 and the layer that contacts the conductive layer 365 it is possible to suppress oxidation of the conductive layer 320 and the conductive layer 365.
  • Examples of the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide.
  • Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).
  • the layer in the insulating layer 250 that contacts the conductive layer 240 is preferably less permeable to oxygen than at least the insulating layer 280 and the insulating layer 380a.
  • the layer has a barrier property against oxygen, which can prevent the side surface of the conductive layer 240 from being oxidized and an oxide film from being formed on the side surface. This can prevent a decrease in the on-current or a decrease in the field effect mobility of the transistor 200.
  • the layer in the insulating layer 350 that contacts the conductive layer 340 is preferably less permeable to oxygen than at least the insulating layer 380b. This can prevent a decrease in the on-current or a decrease in the field effect mobility of the transistor 300.
  • each layer constituting the insulating layer 250 and each layer constituting the insulating layer 350 are preferably thin films.
  • the insulating layer 250 and the insulating layer 350 are each 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, respectively, so that the subthreshold swing value (also called S value), which is one of the transistor characteristics, can be reduced.
  • S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with a constant drain voltage in the subthreshold region.
  • each layer constituting the insulating layer 250 and the insulating layer 350 is preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5 nm or less, more preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and less than 5 nm, and even more preferably 1 nm or more and 3 nm or less. Note that it is preferable that each layer constituting the insulating layer 250 and the insulating layer 350 has a region with the above-mentioned thickness in at least a part.
  • the insulating layer 250 and the insulating layer 350 it is preferable to use a three-layer structure in which a first insulating layer having a material with a low dielectric constant, a second insulating layer having a function of capturing or fixing hydrogen, and a third insulating layer having a barrier property against hydrogen and oxygen are stacked in this order from the semiconductor layer 230 side and the semiconductor layer 330 side, respectively.
  • a material with a low dielectric constant of the first insulating layer it is preferable to use silicon oxide or silicon oxynitride.
  • the first insulating layer is a layer in contact with the semiconductor layer 230 or the semiconductor layer 330.
  • oxygen can be supplied to the semiconductor layer 230 and the semiconductor layer 330.
  • the third insulating layer it is possible to suppress the diffusion of oxygen contained in the first insulating layer to the conductive layer 320 and the conductive layer 365, and to suppress the oxidation of the conductive layer 320 and the conductive layer 365.
  • the insulating layer 250 and the insulating layer 350 it is preferable to use a four-layer structure in which a fourth insulating layer having a barrier property against oxygen, a first insulating layer having a material with a low dielectric constant, a second insulating layer having a function of capturing or fixing hydrogen, and a third insulating layer having a barrier property against hydrogen and oxygen are stacked in this order from the semiconductor layer 230 side and the semiconductor layer 330 side, respectively.
  • the first insulating layer to the third insulating layer can be applied with a configuration similar to that of the layer used in the above-mentioned three-layer structure.
  • the fourth insulating layer is a layer in contact with the semiconductor layer 230 or the semiconductor layer 330.
  • the fourth insulating layer has a barrier property against oxygen, so that oxygen can be suppressed from being released from the semiconductor layer 230 and the semiconductor layer 330.
  • aluminum oxide may be used as the fourth insulating layer.
  • Aluminum oxide has a function of capturing or fixing hydrogen, and is therefore suitable as the fourth insulating layer in contact with the semiconductor layer 230 or the semiconductor layer 330.
  • the film thicknesses of the fourth insulating layer, the first insulating layer, the second insulating layer, and the third insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively.
  • a three-layer structure for the insulating layer 250 and the insulating layer 350 in which a fourth insulating layer having a barrier property against oxygen, a first insulating layer having a material with a low relative dielectric constant, and a second insulating layer having a function of capturing or fixing hydrogen are stacked in this order from the semiconductor layer 230 side and the semiconductor layer 330 side, respectively.
  • a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the semiconductor layer 230 side or the semiconductor layer 330 side.
  • the insulating layer 110 may be an insulating layer having the above-mentioned function of capturing or fixing hydrogen. This allows hydrogen in the semiconductor layer 130 to diffuse into the insulating layer 110 via the conductive layer 120a and the conductive layer 120b, and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 130 can be reduced.
  • the insulating layer 110 may have a two-layer structure of a silicon nitride film and a hafnium silicate film on the silicon nitride film.
  • the insulating layer 135 and the insulating layer 335 can also be referred to as a sidewall, a sidewall insulating layer, a sidewall protective layer, etc.
  • the insulating layer 135 and the insulating layer 335 preferably have an insulating layer having a region containing oxygen that is released by heating. This allows oxygen to be supplied from the insulating layer 135 and the insulating layer 335 to the semiconductor layer 130 and the semiconductor layer 330.
  • the insulating layer 135 and the insulating layer 335 preferably have a barrier insulating layer against hydrogen. This can suppress the diffusion of hydrogen into the semiconductor layer 130 and the semiconductor layer 330, and can improve the reliability of the transistor 100 and the transistor 300.
  • a barrier insulating layer against hydrogen For example, it is preferable to use aluminum oxide, hafnium oxide, silicon nitride, or silicon nitride oxide for the insulating layer 135 and the insulating layer 335.
  • the insulating layer 135 and the insulating layer 335 can also be made of a material that can have the aforementioned ferroelectric properties.
  • the insulating layer 135 and the insulating layer 335 may be formed using a single-layer structure of a silicon oxide film, a single-layer structure of a silicon nitride film, a two-layer structure of a silicon oxide film and a silicon nitride film, a three-layer structure of a silicon oxide film, a silicon nitride film and a silicon oxide film, or a three-layer structure of a silicon nitride film, a silicon oxide film and a silicon nitride film.
  • a silicon oxide film on the semiconductor layer 230 side and the semiconductor layer 330 side, and a silicon nitride film on the conductive layer 155 side and the conductive layer 355 side.
  • This allows oxygen to be efficiently supplied to the semiconductor layer 130 and the semiconductor layer 330, and prevents impurities such as hydrogen from diffusing into the semiconductor layer 130 and the semiconductor layer 330.
  • a silicon nitride film may be provided on the semiconductor layer 230 side and the semiconductor layer 330 side, and a silicon oxide film may be provided on the conductive layer 155 side and the conductive layer 355 side.
  • the insulating layer 181 preferably has a barrier insulating layer against hydrogen. This can suppress the diffusion of hydrogen into the semiconductor layer 130, thereby improving the reliability of the transistor 100.
  • a barrier insulating layer against hydrogen For example, it is preferable to use silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide for the insulating layer 181.
  • the insulating layer 181 may have an insulating layer having a region that contains oxygen that is desorbed by heating. This allows oxygen to be supplied from the insulating layer 181 to the semiconductor layer 130.
  • the insulating layer 181 may be made of silicon oxide or silicon oxynitride.
  • the insulating layer 183 is subjected to a planarization process ending at the insulating layer 181, which will be described in detail later. Therefore, if a material that reduces the thickness loss of the insulating layer 181 in the planarization process ending at the insulating layer 181 is used for the insulating layer 183, the insulating layer 181 can be thinned while preventing the semiconductor layer 130 from being subjected to the planarization process, for example.
  • the insulating layer 181 is formed by processing the insulating layer 181A using the insulating layer 183 as a mask.
  • the insulating layer 183 can be prevented from being processed when the insulating layer 181A is processed, which is preferable.
  • silicon nitride is used for the insulating layer 181
  • silicon oxide is preferably used for the insulating layer 183.
  • the insulating layer 183 may be made of, for example, silicon oxynitride, aluminum oxide, hafnium oxide, silicon nitride oxide, or silicon nitride.
  • the insulating layer 181A can be made of the same material as the insulating layer 181.
  • the insulating layer 183A can be made of the same material as the insulating layer 183.
  • conductive layer For the conductive layers (conductive layer 120, conductive layer 140, conductive layer 155, conductive layer 220, conductive layer 240, conductive layer 320, conductive layer 340, conductive layer 355, conductive layer 365, etc.) included in the semiconductor device, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, an alloy combining the above-mentioned metal elements, etc.
  • a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molyb
  • a nitride of the alloy or an oxide of the alloy may be used.
  • a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • conductive materials containing nitrogen such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum
  • conductive materials containing oxygen such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel
  • materials containing metal elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are difficult to oxidize, conductive materials that have a function of suppressing oxygen diffusion, or materials that maintain conductivity even when oxygen is absorbed.
  • examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide with added silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide.
  • ITO indium oxide containing titanium oxide
  • ITSO indium tin oxide with added silicon
  • IZO indium zinc oxide
  • a conductive film formed using a conductive material containing oxygen may be called an oxide conductive film.
  • Conductive materials based on tungsten, copper, or aluminum are preferred because they have high conductivity.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.
  • a metal oxide is used for the channel formation region of a transistor, it is preferable to use a stacked structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined for the conductive layer that functions as a gate electrode. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.
  • the conductive layer 120 and the conductive layer 140 are each a conductive layer in contact with the semiconductor layer 130, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also called an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion.
  • the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 120 and the conductive layer 140.
  • the conductive layer 120 or the conductive layer 140 can maintain its conductivity even if it absorbs oxygen.
  • the conductive layer 120 is preferable because it can maintain its conductivity.
  • the conductive layer 220 and the conductive layer 320 can each use a material that can be used for the conductive layer 120.
  • the conductive layer 240 and the conductive layer 340 can each use a material that can be used for the conductive layer 140.
  • the conductive layer 120 has a three-layer structure including a conductive layer 120a1, a conductive layer 120a2 on the conductive layer 120a1, and a conductive layer 120b on the conductive layer 120a2.
  • a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen as the conductive layer 120a1, a material with high conductivity as the conductive layer 120a2, and a conductive material containing oxygen (more preferably an oxide conductor) as the conductive layer 120b.
  • titanium nitride as the conductive layer 120a1, tungsten as the conductive layer 120a2, and an oxide conductor (for example, ITO, ITSO, or IZO (registered trademark)) as the conductive layer 120b.
  • titanium nitride is in contact with the insulating layer 110, and the oxide conductor is in contact with the semiconductor layer 130.
  • an oxide conductor is used in the layer closest to the channel formation region of the semiconductor layer 130. Compared to tungsten, the oxide conductor has a lower contact resistance with the semiconductor layer 130, so the current path between the source and drain can be shortened, and the on-current of the transistor can be increased.
  • the conductive layer 120 can maintain conductivity even when in contact with the semiconductor layer 130.
  • the conductive layer 120 can be prevented from being excessively oxidized by the insulating layer 110.
  • the conductive layer 120a2 can be made more conductive by using a metal material (here, tungsten) that has a higher conductivity than the oxide conductor and titanium nitride.
  • FIG. 4A shows an example in which the conductive layer 220 has a three-layer structure of a conductive layer 220a1, a conductive layer 220a2 on the conductive layer 220a1, and a conductive layer 220b on the conductive layer 220a2.
  • FIG. 4B shows an example in which the conductive layer 320 has a three-layer structure of a conductive layer 320a1, a conductive layer 320a2 on the conductive layer 320a1, and a conductive layer 320b on the conductive layer 320a2.
  • the conductive layer 220a1 and the conductive layer 320a1 can each use a material that can be used for the conductive layer 120a1.
  • the conductive layer 220a2 and the conductive layer 320a2 can each use a material that can be used for the conductive layer 120a2.
  • the conductive layer 220b and the conductive layer 320b can each use a material that can be used for the conductive layer 120b.
  • the conductive layer 220 may have a single-layer structure. In this case, the conductive layer 220 can be made of a material that can be used for the conductive layer 120b.
  • the conductive layer 140 has a two-layer structure of a conductive layer 140a and a conductive layer 140b on the conductive layer 140a.
  • a conductive material containing oxygen as the conductive layer 140b
  • a material having a higher conductivity than the conductive layer 140b as the conductive layer 140a.
  • an oxide conductor for example, ITO, ITSO, or IZO (registered trademark)
  • Ruthenium, titanium nitride, tantalum nitride, or the like may also be used as the conductive layer 140a.
  • the layer that is mainly in contact with the semiconductor layer 130 is the conductive layer 140b.
  • the contact resistance with the semiconductor layer 130 can be reduced, which is preferable.
  • the conductivity of the conductive layer 140 can be increased, which is preferable.
  • a conductive material containing oxygen can be used as the conductive layer 140a, and a material having a higher conductivity than the conductive layer 140a can be used as the conductive layer 140b.
  • an oxide conductor is used for the layer of the conductive layer 140 that is closest to the channel formation region of the semiconductor layer 130. This makes it possible to shorten the current path between the source and drain, and increase the on-current of the transistor.
  • the conductive layer 240a and the conductive layer 340a can each be made of a material that can be used for the conductive layer 140a.
  • the conductive layer 240b and the conductive layer 340b can each be made of a material that can be used for the conductive layer 140b.
  • the conductive layer 155, the conductive layer 355, and the conductive layer 365 are each preferably made of a material having high conductivity, such as tungsten.
  • the conductive layer 155, the conductive layer 355, and the conductive layer 365 are each preferably made of a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen.
  • examples of the conductive material include a conductive material containing nitrogen (e.g., titanium nitride or tantalum nitride), a conductive material containing oxygen (e.g., ruthenium oxide), and the like. This can suppress a decrease in the conductivity of the conductive layer 155, the conductive layer 355, and the conductive layer 365.
  • a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed for the conductive layer 365 may be used.
  • the conductive material containing the metal element and nitrogen described above for example, titanium nitride, tantalum nitride, etc.
  • one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon may be used.
  • Indium gallium zinc oxide containing nitrogen may also be used.
  • FIG. 4B shows an example in which the conductive layer 365 has a two-layer structure of a conductive layer 365a and a conductive layer 365b on the conductive layer 365a.
  • the conductive layer 365 has a two-layer structure of a conductive layer 365a and a conductive layer 365b on the conductive layer 365a.
  • tantalum nitride as the conductive layer 365a and copper as the conductive layer 365b. With such a structure, the conductivity of the conductive layer 365 can be increased.
  • the conductive layer 365 may also have a laminated structure of three or more layers.
  • the conductive layer 365 may have a three-layer structure of tantalum nitride, titanium nitride on the tantalum nitride, and tungsten on the titanium nitride.
  • the conductive layer 365 preferably has high conductivity because it functions as a gate wiring. It is preferable to use tungsten for the conductive layer 365. For example, a two-layer structure of titanium nitride and tungsten may be applied.
  • tungsten or tantalum nitride for the conductive layer 155 and the conductive layer 355.
  • the substrate on which the transistor is formed for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used.
  • a insulating substrate for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (for example, an yttria stabilized zirconia substrate), and a resin substrate are available.
  • a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide are available.
  • a semiconductor substrate having an insulator region inside the aforementioned semiconductor substrate for example, an SOI (Silicon On Insulator) substrate.
  • the conductive substrate there are a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • a substrate in which a conductor or a semiconductor is provided on an insulating substrate a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductive substrate, and the like.
  • a substrate having elements provided thereon may be used.
  • the elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.
  • ⁇ Configuration Example 2 of Semiconductor Device> The structure of a semiconductor device according to another embodiment of the present invention will be described below. Specifically, another structural example of the memory cell 10 included in the semiconductor device according to one embodiment of the present invention and the transistor included in the memory cell 10 will be described.
  • FIG. 5A is a plan view showing a configuration example of a transistor 100A.
  • FIG. 5B is a plan view showing a configuration example of a transistor 200A.
  • FIG. 5C is a cross-sectional view taken along dashed lines A1-A2 shown in FIG. 5A and FIG. 5B.
  • FIG. 5D is a cross-sectional view taken along dashed lines B1-B2 shown in FIG. 5A and FIG. 5B.
  • FIG. 5C and FIG. 5D show a configuration example of a memory cell 10A.
  • the transistor 100, the transistor 200, and the transistor 300 included in the memory cell 10A are referred to as the transistor 100A, the transistor 200A, and the transistor 300A, respectively.
  • FIG. 1D can be referred to for the configuration of the transistor 300A in a plan view.
  • transistor 100A and transistor 200A do not have conductive layer 220.
  • semiconductor layer 230 is provided to cover the upper surface of insulating layer 183 and the side surface located outside opening 190 of insulating layer 181.
  • semiconductor layer 230 is provided to be in contact with the region of semiconductor layer 130 that overlaps with conductive layer 140. As described above, even if transistor 100A and transistor 200A do not have conductive layer 220, the other of the source and drain of transistor 100A can be electrically connected to one of the source and drain of transistor 100B.
  • the number of manufacturing steps of the semiconductor device can be reduced compared to a configuration in which the conductive layer 220 is provided in the memory cell. This reduces the manufacturing cost of the semiconductor device, and a low-cost semiconductor device can be provided.
  • the width of the opening 290 can be made smaller than a configuration in which the conductive layer 220 is not provided in the memory cell.
  • FIGS. 6A and 6B are cross-sectional views showing a configuration example of a memory cell 10B.
  • Figures 6A and 6B show an example in which the opening 290 shown in Figures 5C and 5D does not overlap with the insulating layer 183.
  • the transistors 100, 200, and 300 included in the memory cell 10B are referred to as transistors 100B, 200B, and 300B, respectively.
  • opening 290 in plan view is, for example, circular or rectangular
  • at least the center of opening 290 in plan view does not overlap insulating layer 183.
  • a portion of opening 290 may overlap insulating layer 183. Even in this case, the entire upper surface of insulating layer 183 should not overlap opening 290.
  • FIGS. 6A and 6B show an example in which the opening 390 overlaps with the opening 290 but does not overlap with the opening 190, but the opening 390 may overlap with the opening 190 or may not overlap with the opening 290.
  • the shape of the opening 390 in a plan view is, for example, a circle or a rectangle
  • the center of the opening 390 in a plan view may overlap with the opening 190 or may overlap with the opening 290, or may not overlap with either the opening 190 or the opening 290.
  • the center of the opening 390 in a plan view may be located, for example, between the opening 190 and the opening 290 in a plan view.
  • the opening 290 and the opening 390 may be located at positions facing each other across the insulating layer 183 in a plan view.
  • the contact area between semiconductor layer 130 and semiconductor layer 230 can be made larger than in memory cell 10A. This allows the contact resistance between semiconductor layer 130 and semiconductor layer 230 to be lower. On the other hand, memory cell 10A can occupy a smaller area than memory cell 10B.
  • [Memory cell 10C] 7A is a circuit diagram showing a configuration example of a memory cell 10C.
  • the transistor 100, the transistor 200, and the transistor 300 included in the memory cell 10C are referred to as a transistor 100C, a transistor 200C, and a transistor 300C, respectively.
  • transistor 200C and transistor 300C are dual-gate transistors.
  • the first gate of transistor 200C is electrically connected to one of the source and drain of transistor 300C.
  • the second gate of transistor 200C is electrically connected to wiring BGL1.
  • the first gate of transistor 300C is electrically connected to wiring WWL.
  • the second gate of transistor 300C is electrically connected to wiring BGL2.
  • the first gate of transistor 200C is simply referred to as the gate of transistor 200C
  • the second gate of transistor 200C is referred to as the backgate of transistor 200C.
  • the first gate of transistor 300C is referred to as the backgate of transistor 300C
  • the second gate of transistor 300C is referred to as the backgate of transistor 300C.
  • the threshold voltage of the transistor 200C can be controlled by controlling the potential of the wiring BGL1 electrically connected to the backgate of the transistor 200C.
  • the on-current of the transistor 200C can be increased by supplying a potential higher than the source potential or a positive potential to the wiring BGL1. This allows data stored in the memory cell 10C to be read at high speed.
  • the wiring BG1 may be supplied with the same potential as the gate of the transistor 200C, for example. In this case, the gate of the transistor 200C and the backgate of the transistor 200C can be electrically connected.
  • the threshold voltage of the transistor 300C can be controlled by controlling the potential of the wiring BGL2 electrically connected to the back gate of the transistor 300C.
  • the threshold voltage of the transistor 300C can be shifted in the positive direction by supplying a potential lower than the source potential or a potential lower than 0 V (preferably a negative potential) to the wiring BGL2, thereby making the transistor 300C have normally-off characteristics. This allows the gate potential of the transistor 200C to be held for a long period of time. Therefore, data written to the memory cell 10C can be held for a long period of time.
  • Figure 7B is a plan view showing an example of the configuration of transistor 200C.
  • Figure 7C is a cross-sectional view taken along dashed lines A1-A2 in Figure 7B.
  • Figure 7D is a cross-sectional view taken along dashed lines B1-B2 in Figure 7B.
  • Figures 7C and 7D show an example of the configuration of memory cell 10C.
  • the configurations of transistor 100 and transistor 300 in plan view can be seen in Figures 1B and 1D, respectively.
  • Transistor 200C has a conductive layer 255 that functions as a back gate electrode and an insulating layer 235 that functions as a back gate insulating layer.
  • conductive layer 255 functions as wiring BGL1 shown in FIG. 7A.
  • conductive layer 355 functions as wiring BGL2 shown in FIG. 7A.
  • the conductive layer 255 is located on the insulating layer 280a.
  • the insulating layer 280b is located on the conductive layer 255 and on the insulating layer 280a.
  • the insulating layer 280b is provided so as to cover the upper surface of the conductive layer 255, the side surface of the conductive layer 255, and the upper surface of the insulating layer 280a.
  • the conductive layer 255 has an opening 290.
  • FIGS. 7C and 7D show an example in which the conductive layer 220b has a first recess and a second recess that is located outside the first recess and has a shallow depth.
  • the second recess is provided in the conductive layer 220b, and then, when processing the insulating layer 235, the first recess is provided in the conductive layer 220b. Therefore, in FIGS. 7C and 7D, the side of the first recess in the conductive layer 220b is aligned with the surface of the insulating layer 235 facing the semiconductor layer 230.
  • the side of the second recess in the conductive layer 220b is aligned with, for example, the side of the insulating layer 280a facing the opening 290.
  • the insulating layer 235 is arranged so that at least a portion of it is located inside the opening 290.
  • the insulating layer 235 has at least a region that is located between the semiconductor layer 230 and the conductive layer 255.
  • the insulating layer 235 contacts the side of the conductive layer 255 inside the opening 290.
  • the insulating layer 235 contacts the bottom and side of the recess (specifically, the second recess) of the conductive layer 220b, and contacts the side of the insulating layer 280a, the side of the conductive layer 255, the side of the insulating layer 280b, the side of the conductive layer 240a, and the side of the conductive layer 240b inside the opening 290.
  • the semiconductor layer 230 contacts the bottom and side of the recess (specifically, the first recess) of the conductive layer 220b, the insulating layer 235, and the upper surface of the conductive layer 240b.
  • the conductive layer 220b has a recess, so that the area in which the semiconductor layer 230 contacts the conductive layer 220b can be increased. Therefore, the contact resistance between the semiconductor layer 230 and the conductive layer 220b can be reduced.
  • the insulating layer 235 is provided along at least a portion of the sidewall of the opening 290.
  • the semiconductor layer 230 has a region inside the opening 290 that faces the conductive layer 255 with the insulating layer 235 in between. At least a portion of this region of the semiconductor layer 230 is in contact with the insulating layer 235.
  • the conductive layer 255 is provided to surround the semiconductor layer 230 with the insulating layer 235 in between.
  • the conductive layer 255 is provided to face the conductive layer 320 that functions as the gate electrode of the transistor 200C, sandwiching the insulating layer 235, the semiconductor layer 230, and the insulating layer 250.
  • the semiconductor layer 230 has a region that faces the conductive layer 320 across the insulating layer 250 and faces the conductive layer 255 across the insulating layer 235.
  • the conductive layer 255 is provided to surround at least a part of the channel formation region of the transistor 200C with the insulating layer 235 sandwiched therebetween. As described above, the conductive layer 255 functions as a back gate electrode of the transistor 200C. Therefore, the threshold voltage of the transistor 200C can be controlled by controlling the potential of the conductive layer 255. The on-current of the transistor 200C can be increased by supplying a potential higher than the source potential or a positive potential to the conductive layer 255, for example. This allows data stored in the memory cell 10C to be read at high speed. Note that the conductive layer 255 may be supplied with the same potential as the conductive layer 320, for example. In this case, the conductive layer 255 and the conductive layer 320 can be electrically connected.
  • an opening reaching the conductive layer 255 is provided in the insulating layer 280b and the insulating layer 250, a conductive layer functioning as a plug is filled in the opening, and the conductive layer 320 is provided so as to be in contact with the conductive layer, thereby electrically connecting the conductive layer 255 and the conductive layer 320.
  • the conductive layer 255 can be made of a material that can be used for the conductive layer 355.
  • the insulating layer 235 can be made of a material that can be used for the insulating layer 335.
  • the insulating layer 235 preferably has an insulating layer having a region that contains oxygen that is desorbed by heating, for example.
  • the insulating layer 235 preferably has a barrier insulating layer against hydrogen, for example. Note that the insulating layer 235 can also be called a sidewall, a sidewall insulating layer, a sidewall protective layer, or the like, like the insulating layer 335.
  • FIG. 7B to 7D show an example in which the conductive layer 255 extends in a direction parallel to the conductive layer 355, but one embodiment of the present invention is not limited to this, and the conductive layer 255 may extend in a direction different from that of the conductive layer 355.
  • the conductive layer 355 may extend in the X direction
  • the conductive layer 255 may extend in the Y direction.
  • [Memory cell 10D] 8A and 8B are cross-sectional views showing a configuration example of a memory cell 10D.
  • the insulating layer 180a shown in FIGS. 2A and 2B has a three-layered structure of an insulating layer 180a1, an insulating layer 180a2 on the insulating layer 180a1, and an insulating layer 180a3 on the insulating layer 180a2.
  • the insulating layer 180b has a three-layered structure of an insulating layer 180b1, an insulating layer 180b2 on the insulating layer 180b1, and an insulating layer 180b3 on the insulating layer 180b2.
  • the insulating layer 280 has a three-layered structure of an insulating layer 280_1, an insulating layer 280_2 on the insulating layer 280_1, and an insulating layer 280_3 on the insulating layer 280_2.
  • Insulating layer 380a has a three-layered structure of insulating layer 380a1, insulating layer 380a2 on insulating layer 380a1, and insulating layer 380a3 on insulating layer 380a2.
  • Insulating layer 380b has a three-layered structure of insulating layer 380b1, insulating layer 380b2 on insulating layer 380b1, and insulating layer 380b3 on insulating layer 380b2.
  • transistors 100, 200, and 300 in the memory cell 10D are referred to as transistors 100D, 200D, and 300D, respectively.
  • transistors 100D, 200D, and 300D in plan view refer to Figures 1B, 1C, and 1D, respectively.
  • Insulating layer 180a2 and insulating layer 180b2 are closer to the channel formation region of semiconductor layer 130 than insulating layer 180a1 and insulating layer 180b3.
  • oxygen can be supplied to semiconductor layer 130.
  • the insulating layer 180a2 preferably has a region with a higher oxygen content than at least one of the insulating layers 180a1 and 180a3.
  • the insulating layer 180b2 preferably has a region with a higher oxygen content than at least one of the insulating layers 180b1 and 180b3.
  • oxygen can be supplied to the semiconductor layer 130.
  • oxygen vacancies and VOH in the semiconductor layer 130 can be reduced, and a transistor with good electrical characteristics and high reliability can be obtained.
  • the channel length of a transistor when the channel length of a transistor is short, the influence of oxygen vacancies in the channel formation region and VOH on the electrical characteristics and reliability becomes particularly large. Therefore, by optimizing the amount of oxygen supplied to the semiconductor layer 130 after sufficiently reducing the hydrogen concentration in the semiconductor layer 130, a transistor with a short channel length having good electrical characteristics and high reliability can be realized.
  • the insulating layer 180a2 and the insulating layer 180b2 are preferably formed by a deposition method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method.
  • a deposition method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method.
  • PECVD plasma enhanced chemical vapor deposition
  • hydrogen is not required as a deposition gas, and therefore a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the semiconductor layer 130 can be suppressed, and the electrical characteristics of the transistor can be stabilized.
  • oxygen supplied to the semiconductor layer 130 when the amount of oxygen supplied to the semiconductor layer 130 is increased, for example, after the insulating layer 180a2 or the insulating layer 180b2 is formed, heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere may be performed.
  • oxygen may be supplied by forming an oxide film in an oxygen atmosphere on the upper surface of the insulating layer 180a2 or the insulating layer 180b2 by a sputtering method. The oxide film may then be removed. By performing such a treatment, oxygen can be supplied to the insulating layer 180a2 or the insulating layer 180b2, and the amount of oxygen supplied to the semiconductor layer 130 can be increased.
  • an insulating layer suitable for the insulating layer 180a2 and the insulating layer 180b2 to the insulating layer 135. This allows oxygen to be supplied to the semiconductor layer 130 more efficiently.
  • a material with a low dielectric constant for the insulating layer 180a2 and the insulating layer 180b2. This can reduce the parasitic capacitance that occurs between the wirings.
  • silicon oxide or silicon oxynitride can be used for the insulating layer 180a2 and the insulating layer 180b2.
  • the insulating layer 180a1, the insulating layer 180a3, the insulating layer 180b1, and the insulating layer 180b3 may each be a barrier insulating layer against hydrogen. This configuration is preferable because it can suppress the diffusion of impurities such as hydrogen into the semiconductor layer 130.
  • a silicon nitride film or an aluminum oxide film as the insulating layers 180a1, 180a3, 180b1, and 180b3 that satisfy the above conditions. It is also preferable to use a silicon oxide film as the insulating layers 180a2 and 180b2.
  • the insulating layer 280_1, the insulating layer 280_2, and the insulating layer 280_3 have the same structure as the insulating layer 180a1, the insulating layer 180a2, and the insulating layer 180a3, respectively, and can be deposited by the same method.
  • the insulating layer 280_1, the insulating layer 280_2, and the insulating layer 280_3 have the same structure as the insulating layer 180b1, the insulating layer 180b2, and the insulating layer 180b3, respectively, and can be deposited by the same method.
  • the insulating layer 380a1, the insulating layer 380a2, and the insulating layer 380a3 have the same structure as the insulating layer 180a1, the insulating layer 180a2, and the insulating layer 180a3, respectively, and can be deposited by the same method.
  • Insulating layer 380b1, insulating layer 380b2, and insulating layer 380b3 have the same configuration as insulating layer 180b1, insulating layer 180b2, and insulating layer 180b3, respectively, and can be formed by the same method.
  • FIG. 9A and 9B are cross-sectional views showing a configuration example of a memory cell 10E.
  • FIG. 9A and FIG. 9B show an example in which an insulating layer 235 is disposed inside the opening 290 shown in FIG. 8A and FIG. 8B, respectively.
  • the transistors 100, 200, and 300 included in the memory cell 10E are referred to as a transistor 100E, a transistor 200E, and a transistor 300E, respectively.
  • the insulating layer 235 has a region located between the semiconductor layer 230 and the insulating layer 280.
  • the insulating layer 235 contacts the semiconductor layer 230 inside the opening 290. Specifically, the insulating layer 235 contacts at least a part of the channel formation region of the semiconductor layer 230. Note that although the transistor 200E shown in Figures 9A and 9B does not have a conductive layer 255, the transistor 200E may have a conductive layer 255.
  • the entire outer surface (opposite the conductive layer 320) of the channel formation region of the semiconductor layer 230 can be in contact with the same insulating layer.
  • the insulating layer 235 can supply oxygen uniformly to the entire channel formation region of the semiconductor layer 230 by forming a region containing oxygen that is desorbed by heat.
  • the insulating layer 235 has a barrier insulating layer against hydrogen, it can suppress the diffusion of hydrogen to the entire channel formation region of the semiconductor layer 230. As a result, a highly reliable semiconductor device can be provided.
  • the insulating layer 180a, the insulating layer 180b, the insulating layer 280, the insulating layer 380a, and the insulating layer 380b each have a three-layer laminated structure, but the insulating layer 180a, the insulating layer 180b, the insulating layer 280, the insulating layer 380a, and the insulating layer 380b may each have a two-layer laminated structure or a four-layer or more laminated structure.
  • the insulating layer 180a, the insulating layer 180b, the insulating layer 380a, and the insulating layer 380b may have a two-layer laminated structure, and the insulating layer 280 may have a three-layer laminated structure.
  • the insulating layer 180a3, the insulating layer 180b1, the insulating layer 380a3, and the insulating layer 380b1 may not be provided.
  • [Memory cell 10F] 10A and 10B are cross-sectional views showing a configuration example of a memory cell 10F.
  • the memory cell 10F only one recess is provided in the conductive layer 120b and the conductive layer 320b shown in FIGS. 2A and 2B.
  • the transistor 100, the transistor 200, and the transistor 300 included in the memory cell 10F are referred to as the transistor 100F, the transistor 200F, and the transistor 300F, respectively.
  • the configurations of the transistor 100F, the transistor 200F, and the transistor 300F in a plan view can be seen in FIGS. 1B, 1C, and 1D, respectively.
  • the conductive layer 120b may have a recess formed in one or both of the steps of forming the opening 190 and the step of forming the insulating layer 135.
  • a recess is formed in the conductive layer 120b in both steps.
  • a recess is not formed in the conductive layer 120b in the step of forming the opening 190, but is formed in the step of forming the insulating layer 135.
  • the conductive layer 320b may have a recess formed in one or both of the steps of forming the opening 390 and the step of forming the insulating layer 335.
  • a recess is formed in the conductive layer 320b in both steps.
  • a recess is not formed in the conductive layer 320b in the step of forming the opening 390, but is formed in the step of forming the insulating layer 335.
  • the insulating layer 135 contacts the side of the insulating layer 180a, the side of the conductive layer 155, the side of the insulating layer 180b, the side of the conductive layer 140a, the side of the conductive layer 140b, and the top surface of the conductive layer 120b inside the opening 190.
  • the semiconductor layer 130 also contacts the bottom and side of the recess of the conductive layer 120b.
  • the insulating layer 335 contacts the side of the insulating layer 380a, the side of the conductive layer 355, the side of the insulating layer 380b, the side of the conductive layer 340a, the side of the conductive layer 340b, and the top surface of the conductive layer 320b inside the opening 390.
  • the semiconductor layer 330 also contacts the bottom and side of the recess of the conductive layer 320b.
  • the transistor 300F can be a transistor with good electrical characteristics.
  • the area in which the semiconductor layer 130 contacts the conductive layer 120b can be increased as described above. Therefore, the contact resistance between the semiconductor layer 130 and the conductive layer 120b can be reduced.
  • the area in which the semiconductor layer 330 contacts the conductive layer 320b can be increased as described above. Therefore, the contact resistance between the semiconductor layer 330 and the conductive layer 320b can be reduced.
  • [Memory cell 10G] 11A and 11B are cross-sectional views showing a configuration example of a memory cell 10G.
  • the insulating layer 135 shown in FIGS. 2A and 2B does not cover the side surface of the conductive layer 140b, and the insulating layer 335 does not cover the side surface of the conductive layer 340b.
  • the transistors 100, 200, and 300 included in the memory cell 10G are referred to as the transistors 100G, 200G, and 300G, respectively.
  • the configurations of the transistors 100G, 200G, and 300G in a plan view can be seen in FIGS. 1B, 1C, and 1D, respectively.
  • the insulating layer 135 is in contact with the bottom and side of the recess of the conductive layer 120, and is in contact with the side of the insulating layer 180a, the side of the conductive layer 155, and the side of the insulating layer 180b inside the opening 190.
  • the insulating layer 135 is in contact with the side of the conductive layer 140a, but is not in contact with the side of the conductive layer 140b. Note that, in FIG. 11A and FIG.
  • FIG. 11B an example is shown in which the insulating layer 135 is in contact with the entire side of the conductive layer 140a on the opening 190 side, but a part of the side of the conductive layer 140a on the opening 190 side may not be in contact with the insulating layer 135. Also, in FIG. 11A and FIG. 11B, an example is shown in which the insulating layer 335 is in contact with the entire side of the conductive layer 340a on the opening 390 side, but a part of the side of the conductive layer 340a on the opening 390 side may not be in contact with the insulating layer 335.
  • the insulating layer 135 functions as a gate insulating layer of the transistor 100G. Therefore, the insulating layer 135 covers at least the entire side surface of the conductive layer 155 on the opening 190 side, electrically insulating the conductive layer 155 from the semiconductor layer 130.
  • the insulating layer 135 may be in contact with one or more of the side surfaces of the insulating layer 180a, the side surfaces of the insulating layer 180b, the side surfaces of the conductive layer 140a, and the side surfaces of the conductive layer 140b inside the opening 190, and may cover part or all of each side surface.
  • the insulating layer 335 may be in contact with one or more of the side surfaces of the insulating layer 380a, the side surfaces of the insulating layer 380b, the side surfaces of the conductive layer 340a, and the side surfaces of the conductive layer 340b inside the opening 390, and may cover part or all of each side surface.
  • the insulating layer 1335 does not cover the side of the conductive layer 140b and does not cover at least a portion of the side of the conductive layer 140a, that portion is in contact with the semiconductor layer 130. This allows the contact area between the semiconductor layer 130 and the conductive layer 140 to be increased. This allows the contact resistance between the semiconductor layer 130 and the conductive layer 140 to be reduced, which is preferable.
  • the insulating layer 135 does not cover the side of the conductive layer 140b and does not cover at least a portion of the side of the conductive layer 140a, that portion is in contact with the semiconductor layer 130. This allows the contact area between the semiconductor layer 130 and the conductive layer 140 to be increased. This allows the contact resistance between the semiconductor layer 130 and the conductive layer 140 to be reduced, which is preferable.
  • the contact area between the semiconductor layer 330 and the conductive layer 340 can be increased. This makes it possible to reduce the contact resistance between the semiconductor layer 330 and the conductive layer 340, which is preferable.
  • the configuration of the insulating layer 335 shown in Figures 10A to 11B can also be applied to the insulating layer 235 shown in Figures 7C, 7D, 9A, and 9B, for example.
  • FIG. 12A and 12B are cross-sectional views showing a configuration example of a memory cell 10H.
  • an insulating layer 383 and an insulating layer 385 on the insulating layer 383 are provided between the insulating layer 350 and the conductive layer 365a shown in Fig. 2A and 2B.
  • Fig. 12A and 12B show the width D2 of the opening 390.
  • the transistor 100, the transistor 200, and the transistor 300 in the memory cell 10H are referred to as the transistor 100H, the transistor 200H, and the transistor 300H, respectively.
  • the configurations of the transistor 100H, the transistor 200H, and the transistor 300H in a plan view can be seen in Figures 1B, 1C, and 1D, respectively.
  • the insulating layer 383 and the insulating layer 385 function as an interlayer film.
  • the insulating layer 383 has an opening 370 that reaches the insulating layer 350 at a position that overlaps with the opening 390.
  • the conductive layer 365a is arranged so that at least a portion of it is located inside the opening 370.
  • the conductive layer 365b may also be arranged so that at least a portion of it is located inside the opening 370.
  • the conductive layer 365a contacts the insulating layer 350 inside the opening 370.
  • the conductive layer 365a is provided so as to fill at least a portion of the opening 390 and the opening 370.
  • At least one layer constituting the conductive layer 365 is provided inside the opening 390 and inside the opening 370.
  • the conductive layer 365 has a stacked structure, it becomes more difficult to arrange all layers constituting the conductive layer 365 in the opening 390 and the opening 370 as the diameter of the opening 390 and the diameter of the opening 370 become smaller with the progress of miniaturization of the transistor.
  • FIG. 12A and FIG. 12B an example is shown in which the conductive layer 365 has a two-layer structure, only the conductive layer 365a is provided inside the opening 390, and the conductive layer 365a and the conductive layer 365b are provided in the opening 370.
  • both the conductive layer 365a and the conductive layer 365b may be located inside the opening 390 depending on the diameter of the opening 390 and the thickness of the conductive layer 365a.
  • only the conductive layer 365a may be located inside the opening 370 depending on the diameter of the opening 370, the thickness of the conductive layer 365a, and the thickness of the conductive layer 365b.
  • conductive layer 365 mainly overlaps with conductive layer 340 via insulating layer 383 and insulating layer 385. This allows the physical distance between conductive layer 365 and conductive layer 340 to be increased, and the parasitic capacitance generated between conductive layer 365 and conductive layer 340 to be reduced. Note that conductive layer 340 and conductive layer 365 may have overlapping portions without via insulating layer 385.
  • the width of the opening 370 is narrower than the width D2 of the opening 390.
  • the narrower the width of the opening 370 the narrower the area in which the conductive layer 340 and the conductive layer 365 overlap without the insulating layer 385 can be, and the smaller the parasitic capacitance that occurs between the conductive layer 340 and the conductive layer 365 can be.
  • the width of the opening 370 is preferably the same as or smaller than the width of the opening 390.
  • the width of the opening 370 may be larger than the width of the opening 390.
  • the relationship between the two widths in the semiconductor device of one embodiment of the present invention can be confirmed by a cross section parallel to the Z direction.
  • the width of the opening 370 is preferably smaller than the width of the short side of the conductive layer 365 (the maximum width of the conductive layer 365a and the conductive layer 365b in FIG. 12B).
  • the maximum width of the conductive layer 365 is preferably equal to or smaller than the width of the short side of the conductive layer 355 (the maximum width of the conductive layer 355 in the Y direction in FIG. 12B).
  • the transistor 300H has a configuration in which the parasitic capacitance between the other of the source electrode and the drain electrode and the gate wiring is reduced. Therefore, a semiconductor device with high operating speed can be provided.
  • the shape of the opening 370 in a plan view can be the same as the shape applicable to the opening 390 in a plan view.
  • the shape of the opening 370 in a plan view can be, for example, circular.
  • the width of the opening 370 may vary in the depth direction.
  • the width of the opening 370 used here is the maximum width of the opening 370 provided in the insulating layer 383 in a cross-sectional view.
  • the insulating layer 383 is preferably a barrier insulating layer against hydrogen. This can prevent hydrogen from diffusing from above the insulating layer 383 into the semiconductor layer 330. Silicon nitride films and silicon nitride oxide films each have the characteristics of releasing little impurities (e.g., water and hydrogen) from themselves and being less permeable to oxygen and hydrogen, and therefore can be suitably used for the insulating layer 383.
  • impurities e.g., water and hydrogen
  • silicon nitride deposited by sputtering As the insulating layer 383. Sputtering does not require the use of hydrogen-containing molecules in the deposition gas, and therefore the hydrogen concentration in the insulating layer 383 can be reduced. Furthermore, by depositing the insulating layer 383 by sputtering, silicon nitride with high density can be formed.
  • an insulating layer having a function of capturing or fixing hydrogen may be used as the insulating layer 383. With such a configuration, it is possible to suppress the diffusion of hydrogen from above the insulating layer 383 to the semiconductor layer 330, and further to capture or fix the hydrogen contained in the semiconductor layer 330. Therefore, it is possible to reduce the hydrogen concentration in the semiconductor layer 330.
  • the insulating layer 383 aluminum oxide, hafnium oxide, hafnium silicate, or the like can be used.
  • the insulating layer 383 may also have a laminated structure of an insulating layer having a function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen.
  • the insulating layer 383 may be a laminated film of aluminum oxide and silicon nitride on the aluminum oxide.
  • the insulating layer 385 functions as an interlayer film, it is preferable to use a material with a low dielectric constant as described above. For example, it is preferable that the insulating layer 385 has a silicon oxide film.
  • FIGS. 13A and 13B are cross-sectional views showing a configuration example of a memory cell 10I.
  • the conductive layer 365a shown in FIGS. 12A and 12B is not provided, and a conductive layer 360 is provided over an insulating layer 350.
  • the transistors 100, 200, and 300 included in the memory cell 10I are referred to as the transistors 100I, 200I, and 300I, respectively.
  • FIGS. 1B, 1C, and 1D can be referred to for the configurations of the transistors 100I, 200I, and 300I in a plan view, respectively.
  • the conductive layer 360 functions as a gate electrode (first gate electrode) of the transistor 300I.
  • the conductive layer 365 functions as a gate wiring as described above.
  • a material that can be used for the conductive layer 365a can be used.
  • a material that can be used for the conductive layer 365b can be used.
  • the conductive layer 360 is included as a component of the transistor 300I.
  • the conductive layer 365 may not be included as a component of the transistor 300I. Note that the conductive layer 365 may be included as a component of the transistor 300I.
  • an opening 370 is provided in the insulating layer 383 at a position overlapping the opening 390, reaching the semiconductor layer 330. At least some of the components of the transistor 300I are disposed inside the opening 370. Specifically, the insulating layer 350 and the conductive layer 360 are disposed such that at least a portion of each is located inside the opening 370. The insulating layer 350 contacts the semiconductor layer 330 and the insulating layer 383 inside the opening 370.
  • the portion of the insulating layer 350 that is disposed inside the opening 370 is provided to reflect the shape of the opening 370.
  • the insulating layer 350 is provided so as to cover the sidewall of the opening 370 (the side surface of the insulating layer 383).
  • the conductive layer 360 is provided so as to fill at least a portion of the recess in the insulating layer 350 that reflects the shape of the opening 370.
  • the conductive layer 360 does not overlap the upper surface of the conductive layer 340, so that the parasitic capacitance occurring between the conductive layer 340 and the conductive layer 360 can be reduced.
  • the maximum value of the width of the conductive layer 360 is smaller than the width D2 of the opening 390. In this way, when the maximum value of the width of the conductive layer 360 is smaller than the width D2 of the opening 390, the parasitic capacitance occurring between the conductive layer 360 and the conductive layer 340 can be reduced, which is preferable.
  • 13A and 13B show an example in which the width of opening 370 is the same as the width of opening 390 (same as width D2). It is more preferable that the width of opening 370 is the same as or smaller than the width of opening 390. This is preferable because conductive layer 360 does not overlap the upper surface of conductive layer 340 and the parasitic capacitance generated between conductive layer 360 and conductive layer 340 can be reduced.
  • the conductive layer 360 does not overlap with the upper surface of the conductive layer 340, but the conductive layer 360 may have a portion that overlaps with the upper surface of the conductive layer 340.
  • the smaller the overlapping portion the smaller the parasitic capacitance that occurs between the conductive layer 360 and the conductive layer 340, which is preferable.
  • the width of the opening 370 is preferably smaller than the width of the short side of the conductive layer 365 (the maximum width of the conductive layer 365 in FIG. 13B).
  • the maximum width of the conductive layer 365 is preferably the same as or smaller than the width of the short side of the conductive layer 355 (the maximum width of the conductive layer 355 in the Y direction in FIG. 13B).
  • the height of the upper surface of the conductive layer 360 and the height of the upper surface of the insulating layer 385 are the same or approximately the same.
  • the conductive layer 365 is provided on the insulating layer 385, the insulating layer 383, and the conductive layer 360, and is in contact with the upper surface of the conductive layer 360. It can also be said that the conductive layer 360 and the conductive layer 365 are electrically connected to each other.
  • the insulating layer 383 and the insulating layer 385 are located between the conductive layer 365 and the conductive layer 340. This makes it possible to increase the physical distance between the conductive layer 365 and the conductive layer 340, and to reduce the parasitic capacitance generated between the conductive layer 365 and the conductive layer 340.
  • the transistor 300I has a configuration in which the parasitic capacitance between the other of the source electrode and the drain electrode and the gate electrode, and the parasitic capacitance between the other of the source electrode and the drain electrode and the gate wiring are reduced. Therefore, a semiconductor device with a high operating speed can be provided.
  • [Memory cell 10J] 14A and 14B are cross-sectional views showing a configuration example of a memory cell 10J.
  • the conductive layer 365 shown in FIGS. 2A and 2B has a single-layer structure.
  • the transistors 100, 200, and 300 included in the memory cell 10J are referred to as the transistors 100J, 200J, and 300J, respectively.
  • the configurations of the transistors 100J, 200J, and 300J in a plan view can be seen in FIGS. 1B, 1C, and 1D, respectively.
  • the conductive layer that functions as a gate electrode such as the conductive layer 365 of the transistor 300J, may have a single-layer structure.
  • the conductive layer 365 is preferably provided so as to fill the opening 390.
  • [Memory cell 10K] 15A and 15B are cross-sectional views showing a configuration example of a memory cell 10K.
  • both the conductive layer 365a and the conductive layer 365b are located inside the opening 390 shown in FIGS. 2A and 2B.
  • the transistors 100, 200, and 300 included in the memory cell 10K are referred to as the transistors 100K, 200K, and 300K, respectively.
  • FIGS. 1B, 1C, and 1D can be referred to for the configurations of the transistors 100K, 200K, and 300K in a plan view, respectively.
  • conductive layer 365b is located inside opening 390. As described above, depending on the diameter of opening 390 and the thickness of conductive layer 365a, conductive layer 365b as well as conductive layer 365a may be provided inside opening 290.
  • the configurations of the memory cells 10A to 10K described above can be combined as appropriate.
  • the insulating layer 235 and the conductive layer 255 may be provided in the memory cells 10A, 10B, and 10F to 10K.
  • the insulating layers 180a, 180b, 280, 380a, and 380b of the memory cells 10A, 10B, and 10F to 10K may each have a stacked structure similar to the memory cells 10D and 10E.
  • the configuration of the gate electrode and the gate insulating layer of the transistor 300 shown in FIG. 12A to FIG. 15B may be applied to the transistors 300A to 300G.
  • Transistor 100L and Transistor 100M below, other configuration examples of the transistor 100 will be described. Note that the configuration of the transistor 100L described below can also be applied to the transistor 200 and the transistor 300. Similarly, the configuration of the transistor 100M described below can also be applied to the transistor 200 and the transistor 300.
  • Figure 16A is a cross-sectional view showing a configuration example of a semiconductor device including a transistor 100L, and shows an example in which the insulating layer 135 shown in Figure 4A has a two-layer structure.
  • the insulating layer 135 may have a stacked structure of three or more layers.
  • the insulating layer 235 and the insulating layer 335 can also have a stacked structure of two or more layers like the insulating layer 135.
  • the insulating layer 135 and the insulating layer 335 of the memory cells 10A to 10K, and the insulating layer 235 of the memory cells 10C and 10E can also have a stacked structure of two or more layers.
  • the insulating layer 135 of the transistor 100L has an insulating layer 135a and an insulating layer 135b on the insulating layer 135a. It is preferable that one of the insulating layer 135a or the insulating layer 135b has an insulating layer having a region containing oxygen that is desorbed by heating. It is also preferable that the other of the insulating layer 135a or the insulating layer 135b has a barrier insulating layer against hydrogen.
  • the transistor 100L can be a highly reliable transistor.
  • a silicon nitride film for the insulating layer 135a and a silicon oxide film for the insulating layer 135b it is preferable to use a silicon oxide film for the insulating layer 135a and a silicon nitride film for the insulating layer 135b.
  • the insulating layer 135a is provided in contact with the bottom and side surfaces of the recess of the conductive layer 120b, and the insulating layer 135b is provided on the insulating layer 135a.
  • an insulating film that will become the insulating layer 135a and an insulating film that will become the insulating layer 135b are stacked, and then the two insulating films are processed to form the insulating layer 135a and the insulating layer 135b having the structure shown in FIG. 16A.
  • Figure 16B is a cross-sectional view showing a configuration example of a semiconductor device including transistor 100M, and shows an example in which the sidewall of opening 190 shown in Figure 4A is tapered.
  • the sidewall of opening 290 and the sidewall of opening 390 may also be tapered like the sidewall of opening 190.
  • the sidewalls of openings 190, openings 290, and openings 390 of memory cells 10A to 10K may also be tapered.
  • the taper angle ⁇ 180 of the side of the insulating layer 180a inside the opening 190 is preferably 45 degrees or more and less than 90 degrees. Specifically, if it is 80 degrees or more and less than 90 degrees, it is preferable to achieve miniaturization or high integration of the semiconductor device. In addition, if it is 45 degrees or more or 50 degrees or more and less than 80 degrees, 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less, it is preferable to improve the coverage of the film formed inside the opening 190.
  • the sidewall of the opening 190 may have an inverse tapered shape.
  • the taper angle ⁇ 180 of the side surface of the insulating layer 180a inside the opening 190 may be greater than 90 degrees.
  • the thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum deposition, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), and atomic layer deposition (ALD).
  • CVD chemical vapor deposition
  • MBE molecular beam epitaxy
  • PLD pulsed laser deposition
  • ALD atomic layer deposition
  • Sputtering methods include RF sputtering, which uses a high-frequency power source as the sputtering power source, DC sputtering, which uses a direct current power source, and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner.
  • RF sputtering is mainly used when depositing insulating films
  • DC sputtering is mainly used when depositing metal conductive films.
  • Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, or carbides using reactive sputtering.
  • CVD methods can also be classified into plasma CVD (PECVD), which uses plasma, thermal CVD (TCVD: Thermal CVD), which uses heat, and photo CVD (Photo CVD), which uses light. They can also be further classified into metal CVD (MCVD: Metal CVD) and metal organic CVD (MOCVD: Metal CVD) depending on the source gas used.
  • PECVD plasma CVD
  • TCVD Thermal CVD
  • Photo CVD Photo CVD
  • MCVD Metal CVD
  • MOCVD Metal CVD
  • the plasma CVD method can obtain high-quality films at relatively low temperatures.
  • the thermal CVD method is a film formation method that can reduce plasma damage to the workpiece because it does not use plasma.
  • wiring, electrodes, and elements (transistors, capacitive elements, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, or elements included in the semiconductor device.
  • the thermal CVD method which does not use plasma, such plasma damage does not occur, so the yield of semiconductor devices can be increased.
  • plasma damage does not occur during film formation, so a film with fewer defects can be obtained.
  • the ALD method can be a thermal ALD method in which the reaction between the precursor and reactant is carried out using only thermal energy, or a PEALD method in which a plasma-excited reactant is used.
  • the ALD method can deposit atoms one layer at a time, and therefore has the following advantages: extremely thin films can be formed; films can be formed on structures with high aspect ratios or surfaces with large steps; films can be formed with few defects such as pinholes; films can be formed with excellent coverage; and films can be formed at low temperatures.
  • the PEALD method may be preferable because it can form films at lower temperatures by using plasma.
  • some precursors used in the ALD method contain elements such as carbon or chlorine.
  • films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. Note that the quantification of these elements can be performed using XPS or SIMS.
  • the metal oxide film formation method of one embodiment of the present invention uses the ALD method, but adopts one or both of the conditions of a high substrate temperature during film formation and the implementation of an impurity removal process, and therefore the amount of carbon and chlorine contained in the film may be smaller than when the ALD method is used without applying these.
  • the ALD method is a film formation method in which a film is formed by a reaction on the surface of the workpiece, unlike film formation methods in which particles emitted from a target are deposited. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for example for coating the surface of an opening with a high aspect ratio.
  • the CVD and ALD methods are different from sputtering methods in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio, for example.
  • the ALD method since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.
  • a film of any composition can be formed by changing the flow rate ratio of the raw material gases.
  • a film with a continuously changing composition can be formed by changing the flow rate ratio of the raw material gases while forming the film.
  • a film of any composition can be formed by simultaneously introducing multiple different types of precursors. Or, when multiple different types of precursors are introduced, a film of any composition can be formed by controlling the number of cycles of each precursor.
  • the thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by wet film formation methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.
  • the thin film When processing the thin film that constitutes the semiconductor device, for example, a photolithography method can be used.
  • the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like.
  • a thin film of the desired shape may also be directly formed by a film formation method using a shielding mask such as a metal mask.
  • the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these.
  • ultraviolet light, KrF laser light, ArF laser light, etc. can also be used.
  • Exposure can also be performed by immersion exposure technology.
  • Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure.
  • Electron beams can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or electron beams are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.
  • the thin film can be etched by dry etching, wet etching, sandblasting, or other methods.
  • FIG. 17A to Fig. 24 show a cross-sectional view taken along dashed line A1-A2 in Fig. 2A and a cross-sectional view taken along dashed line B1-B2 in Fig. 2B side by side.
  • an insulating layer 110 is formed on a substrate (not shown), a conductive layer 120a is formed on the insulating layer 110, and a conductive layer 120b is formed on the conductive layer 120a.
  • an insulating layer 180a is formed on the conductive layer 120b and on the insulating layer 110, and a conductive layer 155 is formed on the insulating layer 180a.
  • planarization treatment it is preferable to perform planarization treatment after the insulating layer 180a is formed to planarize the top surface of the insulating layer 180a.
  • CMP treatment is preferable.
  • a planarization treatment using etching also referred to as an etch-back treatment
  • the planarization treatment does not have to be performed, and in that case, the manufacturing cost can be reduced.
  • insulating layer 180b is formed on conductive layer 155 and insulating layer 180a, conductive layer 140a is formed on insulating layer 180b, and conductive layer 140b is formed on conductive layer 140a.
  • an opening 190 is formed in the conductive layer 140b, the conductive layer 140a, the insulating layer 180b, the conductive layer 155, and the insulating layer 180a, reaching the conductive layer 120.
  • a recess is provided in the conductive layer 120b at a position overlapping the opening 190. It is preferable that the bottom and side surfaces of the recess in the conductive layer 120b are exposed by forming the opening 190.
  • the opening 190 it is preferable to process a part of the conductive layer 120b, a part of the conductive layer 140a, a part of the conductive layer 140b, a part of the conductive layer 155, a part of the insulating layer 180a, and a part of the insulating layer 180b using highly anisotropic etching.
  • processing by a dry etching method is preferable because it is suitable for microfabrication.
  • the opening 190 may be formed under different processing conditions depending on the layer.
  • the inclination of the side surface of the conductive layer 120b, the conductive layer 140a, the conductive layer 140b, the conductive layer 155, the insulating layer 180a, and the insulating layer 180b may differ from each other.
  • a region containing a halogen element may be provided on at least one of the bottom and side surfaces of the recess in the conductive layer 120b, the side surfaces of the insulating layer 180a, the side surfaces of the insulating layer 180b, the side surfaces of the conductive layer 155, the side surfaces of the conductive layer 140a, and the top and side surfaces of the conductive layer 140b.
  • regions include a region containing fluorine, a region containing chlorine, or a region containing fluorine and chlorine.
  • halogen elements derived from the etching gas used in the dry etching may remain in such regions.
  • the heat treatment is performed, for example, at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower.
  • the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • an atmosphere of nitrogen gas or an inert gas or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • the heat treatment may be performed under reduced pressure.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.
  • the gas used in the heat treatment is preferably highly purified.
  • the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less.
  • insulating layer 135 is formed so as to cover opening 190 and have a region located on conductive layer 140b. Insulating layer 135 is provided in contact with the bottom and side surfaces of the recess of conductive layer 120b, the side surfaces of insulating layer 180a, the side surfaces of conductive layer 155, the side surfaces of insulating layer 180b, the side surfaces of conductive layer 140a, and the top and side surfaces of conductive layer 140b.
  • the insulating layer 135 is a layer provided inside the opening 190, it is preferable to form it by the CVD method or the ALD method, and it is more preferable to form it by the ALD method. This allows the insulating layer 135 to be provided with good coverage.
  • the insulating layer 135 is processed to expose the upper surface of the conductive layer 140 and to expose the conductive layer 120 in the opening 190. It is preferable that the bottom surface of the recess of the conductive layer 120b is exposed in the opening 190.
  • the insulating layer 135 can be processed without using photolithography.
  • the insulating layer 135 is processed by anisotropic etching, for example, over the entire surface, without forming a resist mask.
  • the insulating layer 135 is processed by anisotropic etching until the top surface of the conductive layer 140b is exposed.
  • the region of the insulating layer 135 located on the top surface of the conductive layer 140 and the region located on the bottom surface of the opening 190 are removed, and the insulating layer 135 can be left only on the inside side surface of the opening 190. It is preferable to process the insulating layer 135 by performing highly anisotropic etching using a dry etching method.
  • the insulating layer 135 after forming the conductive layer 140, it is possible to suppress the anisotropic etching of the insulating layer 135 from continuing even after the region of the insulating layer 135 located outside the opening 190 is removed, compared to the case where the insulating layer 135 is formed without forming the conductive layer 140. Therefore, for example, it is possible to prevent the side surface of the conductive layer 155 on the opening 190 side from being exposed. Therefore, for example, it is possible to prevent the conductive layer 155 from contacting the semiconductor layer 130 to be formed later. As a result, a method for manufacturing a semiconductor device with a high yield can be realized.
  • a portion of the conductive layer 120b may be removed to provide a recess in the conductive layer 120b.
  • a semiconductor layer 130 is formed so as to cover the opening 190 and to be in contact with the upper surface of the conductive layer 140 and the conductive layer 120.
  • the semiconductor layer 130 is formed so as to cover the insulating layer 135 inside the opening 190.
  • the semiconductor layer 130 can be formed so as to be in contact with the bottom and side surfaces of the recess of the conductive layer 120b, the insulating layer 135, and the upper surface of the conductive layer 140b.
  • the semiconductor layer 130 can be formed using, for example, a sputtering method, an ALD method, a CVD method, a vacuum deposition method, an MBE method, or a PLD method.
  • the semiconductor layer 130 is preferably formed as a film with as uniform a thickness as possible along the bottom and side surfaces of the recess in the conductive layer 120b, the insulating layer 135, and the top surface of the conductive layer 140b.
  • a thin film can be formed with good controllability. Therefore, it is preferable to form the semiconductor layer 130 using the ALD method.
  • the semiconductor layer 130 has high crystallinity, the diffusion of impurities in the semiconductor layer 130 is suppressed, so that the electrical characteristics of the transistor are less likely to fluctuate and reliability can be improved.
  • the semiconductor layer 130 is formed by a sputtering method, it is easier to form a layer with high crystallinity than when an ALD method is used, which is preferable.
  • the semiconductor layer 130 is formed by a sputtering method
  • oxygen or a mixed gas of oxygen and a noble gas is used as the sputtering gas.
  • the proportion of oxygen contained in the sputtering gas By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.
  • an In-M-Zn oxide target can be used.
  • an oxygen-excessive oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is set to more than 30% and not more than 100%, preferably 70% to 100%.
  • a transistor using an oxygen-excessive oxide semiconductor in a channel formation region can have relatively high reliability.
  • one embodiment of the present invention is not limited thereto.
  • An oxygen-deficient oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%, when the semiconductor layer 130 is formed.
  • a transistor using an oxygen-deficient oxide semiconductor in a channel formation region can have relatively high field-effect mobility.
  • the crystallinity of the semiconductor layer 130 can be improved by forming the film while heating the substrate.
  • the heat treatment is preferably performed in a temperature range in which the semiconductor layer 130 does not become polycrystallized.
  • the temperature of the heat treatment is preferably 100°C or higher and 650°C or lower, more preferably 250°C or higher and 600°C or lower, and even more preferably 350°C or higher and 550°C or lower.
  • the gas used in the above heat treatment is preferably highly purified.
  • a highly purified gas By performing the heat treatment using a highly purified gas, it is possible to prevent, for example, moisture from being absorbed into the semiconductor layer 130 as much as possible.
  • the heat treatment is performed at a temperature of 450° C. for 1 hour with a flow rate ratio of nitrogen gas and oxygen gas of 4:1.
  • This heat treatment including oxygen gas can reduce impurities such as carbon, water, and hydrogen in the semiconductor layer 130.
  • impurities such as carbon, water, and hydrogen in the semiconductor layer 130.
  • the crystallinity of the semiconductor layer 130 can be improved, and a denser and more compact structure can be obtained.
  • This increases the crystalline region in the semiconductor layer 130, and reduces the in-plane variation of the crystalline region in the semiconductor layer 130. Therefore, the in-plane variation of the electrical characteristics of the transistor can be reduced.
  • the insulating layer 180a, the insulating layer 180b, and the insulating layer 135 contains oxygen
  • oxygen also called excess oxygen
  • excess oxygen has the function of trapping electrons, negative charges are easily formed. Therefore, the threshold voltage of the transistor is shifted in the positive direction, making it possible to realize a transistor with normally-off characteristics.
  • the semiconductor layer 130, the conductive layer 140a, and the conductive layer 140b are processed to remove parts of the semiconductor layer 130, the conductive layer 140a, and the conductive layer 140b. This exposes a part of the upper surface of the insulating layer 180b.
  • the semiconductor layer 130, the conductive layer 140a, and the conductive layer 140b can be processed using the same mask. This is preferable because it reduces the number of masks required to manufacture a semiconductor device.
  • an insulating layer 181A is formed so as to cover the semiconductor layer 130. Specifically, the insulating layer 181A is formed so as to cover the semiconductor layer 130, the side surfaces of the conductive layer 140b, the side surfaces of the conductive layer 140a, and the upper surface of the insulating layer 180b.
  • the insulating layer 181A is formed along the opening 190, which has a large aspect ratio. Specifically, the insulating layer 181A is formed along the recess of the semiconductor layer 130 formed at a position overlapping the opening 190. For the above reasons, it is preferable to use a film formation method with good coverage for forming the insulating layer 181A.
  • the insulating layer 181A is preferably formed using, for example, a CVD method or an ALD method, and is more preferably formed using an ALD method.
  • the insulating layer 181A can be formed to have a recess at a position overlapping the opening 190.
  • Insulating layer 183A is formed on insulating layer 181A so as to have a region located inside opening 190.
  • Insulating layer 183A can be formed using, for example, a CVD method, an ALD method, a sputtering method, a vacuum deposition method, an MBE method, or a PLD method.
  • a planarization process is performed on the insulating layer 183A until at least a portion of the upper surface of the insulating layer 181A is exposed.
  • a planarization process is performed on the insulating layer 183A, with the insulating layer 181A as the end point.
  • the insulating layer 183 is formed having a region located inside the recess of the insulating layer 181A.
  • the insulating layer 183 can be formed so as to fill the recess of the insulating layer 181A.
  • a CMP process is preferable as the planarization process.
  • the insulating layer 183A remains in an area that does not overlap with either the opening 190 or the conductive layer 140.
  • the insulating layer 183A remains so as to surround the semiconductor layer 130 and the conductive layer 140.
  • the insulating layer 183A remains so as to surround the side of the semiconductor layer 130 located outside the opening 190 and the side of the conductive layer 140 opposite to the side on the opening 190 side in a planar view.
  • an opening 191 that overlaps with the semiconductor layer 130 is formed, and an island-shaped insulating layer 183 is formed inside the opening 191, as shown in Figures 3A and 3B.
  • an opening 191 that overlaps with the conductive layer 140 and the opening 190 is formed, and an island-shaped insulating layer 183 is formed inside the opening 191.
  • the insulating layer 181A is processed to remove a portion of the insulating layer 181A.
  • This forms the insulating layer 181 having a region located inside the opening 190.
  • at least a portion of the upper surface of the semiconductor layer 130 is exposed.
  • the insulating layer 181A can be processed using, for example, the insulating layer 183 and the insulating layer 183A as a mask. In this case, at least a portion of the region of the insulating layer 181A that does not overlap with the insulating layer 183 can be removed. Specifically, the region of the insulating layer 181A that does not overlap with either the insulating layer 183A or the insulating layer 183 can be removed. As a result, the insulating layer 181 is formed to overlap with the insulating layer 183, and the region of the semiconductor layer 130 that overlaps with the conductive layer 140 can be exposed.
  • the insulating layer 181A Even after the insulating layer 181A is processed to form the insulating layer 181, a part of the insulating layer 181A remains. Specifically, the insulating layer 181A remains in the area overlapping the insulating layer 183A.
  • an opening 191 that overlaps with the semiconductor layer 130 is formed in the insulating layer 181A, as shown in Figures 3A and 3B, and an island-shaped insulating layer 181 is formed inside the opening 191.
  • an opening 191 that overlaps with the conductive layer 140 and the opening 190 is formed, and an island-shaped insulating layer 181 is formed inside the opening 191.
  • the insulating layer 183 can be formed by performing a planarization process on the insulating layer 183A, ending at the insulating layer 181A.
  • the upper surfaces of the insulating layer 183 and the insulating layer 183A can be positioned higher than the upper surface of the region where the insulating layer 183 and the conductive layer 140 of the semiconductor layer 130 overlap.
  • the upper surfaces of the insulating layer 183 and the insulating layer 183A can be positioned higher than the upper surface of the region where the semiconductor layer 130 overlaps with the conductive layer 140 by, for example, the thickness of the insulating layer 181 and the insulating layer 181A, respectively.
  • the planarization may be performed not only on the insulating layer 183A but also on the semiconductor layer 130.
  • the region of the semiconductor layer 130 that is in contact with the conductive layer 140 may be removed.
  • the insulating layer 183A is formed after the insulating layer 181A is formed, and then the insulating layer 183A is planarized until at least a part of the upper surface of the insulating layer 181A is exposed, thereby preventing the planarization of the semiconductor layer 130. Therefore, a method for manufacturing a semiconductor device with a high yield can be realized.
  • the insulating layer 181 and the insulating layer 183 can be formed without using a photolithography method. That is, the insulating layer 183 is formed by a planarization process, and the insulating layer 181 can be formed by processing using the insulating layer 183 as a mask. This allows the number of manufacturing steps of the semiconductor device to be reduced compared to the case where the insulating layer 181 and the insulating layer 183 are formed by using a photolithography method, for example. Therefore, the manufacturing cost of the semiconductor device can be reduced, and a low-cost semiconductor device can be provided. Note that the insulating layer 181 and the insulating layer 183 may be formed by using a photolithography method.
  • the insulating layer 181A and the insulating layer 183A can be processed so that the insulating layer 181A and the insulating layer 183A do not remain outside the conductive layer 140 (the opposite side to the opening 190), for example.
  • the insulating layer 183A is subjected to planarization treatment ending at the insulating layer 181A. Therefore, it is preferable to use a material for the insulating layer 183A that reduces the thickness of the insulating layer 181A in the planarization treatment ending at the insulating layer 181A, because it is possible to prevent the planarization treatment from being performed on the semiconductor layer 130, for example, while reducing the thickness of the insulating layer 181A during deposition.
  • the insulating layer 181A is processed using the insulating layer 183 and the insulating layer 183A as masks.
  • the insulating layer 181A for the insulating layer 183A, because it is possible to prevent the insulating layer 183 and the insulating layer 183A from being processed when the insulating layer 181A is processed.
  • silicon nitride when silicon nitride is used for the insulating layer 181A, it is preferable to use silicon oxide for the insulating layer 183A.
  • the insulating layer 181A before processing can be called the first insulating layer
  • the insulating layer 183A before the planarization process can be called the second insulating layer.
  • a conductive layer 220a is formed on the insulating layer 183, the insulating layer 183A, and the semiconductor layer 130, and a conductive layer 220b is formed on the conductive layer 220a.
  • the conductive layer 220a and the conductive layer 220b are processed. For example, the conductive layer 220a and the conductive layer 220b are partially removed so that a part of the upper surface of the semiconductor layer 130 and the upper surface of the insulating layer 183A are exposed. In this manner, the conductive layer 220 is formed.
  • the conductive layer 220 can be formed so as to contact the upper surface of the insulating layer 183, the side surface of the insulating layer 181, and the upper surface of the semiconductor layer 130.
  • a transistor 100 having a conductive layer 120, a conductive layer 140, a conductive layer 155, a conductive layer 220, a semiconductor layer 130, and an insulating layer 135 can be formed.
  • an insulating layer 280 is formed on the conductive layer 220, the semiconductor layer 130, and the insulating layer 183A, a conductive layer 240a is formed on the insulating layer 280, and a conductive layer 240b is formed on the conductive layer 240a.
  • an opening 290 is formed in the conductive layer 240b, the conductive layer 240a, and the insulating layer 280, reaching the conductive layer 220.
  • a recess is provided in the conductive layer 220b at a position overlapping the opening 290. It is preferable that the bottom and side surfaces of the recess in the conductive layer 220b are exposed by forming the opening 290.
  • the opening 290 can be formed in the same manner as the opening 190.
  • the processing of the conductive layer 240b and the processing of the conductive layer 240a can be performed under the same conditions as the processing of the conductive layer 140b and the processing of the conductive layer 140a, respectively.
  • the processing of the insulating layer 280 can be performed under the same conditions as the processing of the insulating layer 180a or the processing of the insulating layer 180b, for example.
  • the semiconductor layer 230 is formed so as to cover the opening 290 and to be in contact with the conductive layer 220 and the conductive layer 240.
  • the semiconductor layer 230 can be formed so as to be in contact with the bottom and side of the recess of the conductive layer 220, the side of the insulating layer 280 and the conductive layer 240 on the opening 290 side, and the upper surface of the conductive layer 240.
  • the semiconductor layer 230 can be formed so as to be in contact with the bottom and side of the recess of the conductive layer 220b, the side of the insulating layer 280, the conductive layer 240a, and the conductive layer 240b on the opening 290 side, and the upper surface of the conductive layer 240b.
  • the semiconductor layer 230 can be formed in the same manner as the semiconductor layer 130.
  • the semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b are processed to remove parts of the semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b. This exposes a part of the upper surface of the insulating layer 280.
  • the semiconductor layer 230, the conductive layer 240a, and the conductive layer 240b can be processed using the same mask. This is preferable because it reduces the number of masks required to manufacture a semiconductor device.
  • an insulating layer 250 is formed so as to cover the semiconductor layer 230. Specifically, the insulating layer 250 is formed so as to cover the semiconductor layer 230, the side surfaces of the conductive layer 240b, the side surfaces of the conductive layer 240a, and the upper surface of the insulating layer 280b.
  • the insulating layer 250 is formed along the opening 290, which has a large aspect ratio. Specifically, the insulating layer 250 is formed along the recess of the semiconductor layer 230 formed at a position overlapping the opening 290. For the above reasons, it is preferable to use a film formation method with good coverage for forming the insulating layer 250.
  • the insulating layer 250 is preferably formed using, for example, a CVD method or an ALD method, and is more preferably formed using an ALD method.
  • the insulating layer 250 can be formed to have a recess at a position overlapping the opening 290.
  • a conductive layer 320a is formed on the insulating layer 250 so as to have a region located inside the opening 290.
  • a conductive layer 320b is also formed on the conductive layer 320a. It is preferable that the conductive layer 320a is formed so as to fill the opening 290. Specifically, it is preferable that the conductive layer 320a is formed so as to fill the recess of the insulating layer 250. Note that depending on the diameter of the opening 290 and the thickness of the conductive layer 320a, the conductive layer 320b may also be formed inside the opening 290.
  • the conductive layer 320a is formed inside the opening 290, which has a large aspect ratio. Therefore, it is preferable to use a film formation method with good coverage to form the conductive layer 320a, and it is more preferable to use a CVD method, an ALD method, or the like.
  • a transistor 200 having a conductive layer 220, a conductive layer 240, a conductive layer 320, a semiconductor layer 230, and an insulating layer 250 can be formed.
  • an insulating layer 380a is formed over the conductive layer 320 and the insulating layer 250, and a conductive layer 355 is formed over the insulating layer 380a.
  • a planarization treatment it is preferable to perform a planarization treatment after the insulating layer 380a is formed to planarize the top surface of the insulating layer 380a.
  • a CMP treatment is preferable.
  • an etch-back treatment may be performed.
  • insulating layer 380b is formed on conductive layer 355 and insulating layer 380a, conductive layer 340a is formed on insulating layer 380b, and conductive layer 340b is formed on conductive layer 340a.
  • an opening 390 is formed in the conductive layer 340b, the conductive layer 340a, the insulating layer 380b, the conductive layer 355, and the insulating layer 380a, reaching the conductive layer 320.
  • a recess is provided in the conductive layer 320b at a position overlapping with the opening 390. It is preferable that the bottom and side surfaces of the recess in the conductive layer 320b are exposed by forming the opening 390.
  • the opening 390 can be formed in the same manner as the opening 190.
  • the processing of the conductive layer 340b, the processing of the conductive layer 340a, the processing of the insulating layer 380b, the processing of the conductive layer 355, and the processing of the insulating layer 380a can be performed under the same conditions as the processing of the conductive layer 140b, the processing of the conductive layer 140a, the processing of the insulating layer 180b, the processing of the conductive layer 155, and the processing of the insulating layer 180a, respectively.
  • an insulating layer 335 is formed so as to cover the opening 390 and have a region located on the conductive layer 340b.
  • the insulating layer 335 is provided in contact with the bottom and side surfaces of the recess of the conductive layer 320b, the side surfaces of the insulating layer 380a, the side surfaces of the conductive layer 355, the side surfaces of the insulating layer 380b, the side surfaces of the conductive layer 340a, and the top and side surfaces of the conductive layer 340b.
  • the insulating layer 335 is preferably formed by the CVD method or the ALD method, like the insulating layer 135, and more preferably by the ALD method.
  • the insulating layer 335 is processed to expose the upper surface of the conductive layer 340 and to expose the conductive layer 320 in the opening 390. It is preferable that the bottom surface of the recess of the conductive layer 320b is exposed in the opening 390.
  • the insulating layer 335 can be processed in the same manner as the insulating layer 135.
  • a semiconductor layer 330 is formed so as to cover the opening 390 and to be in contact with the upper surface of the conductive layer 340 and the conductive layer 320.
  • the semiconductor layer 330 is formed so as to cover the insulating layer 335 inside the opening 390.
  • the semiconductor layer 330 can be formed so as to be in contact with the bottom and side surfaces of the recess of the conductive layer 320b, the insulating layer 335, and the upper surface of the conductive layer 340b.
  • the semiconductor layer 330 can be formed in the same manner as the semiconductor layer 130.
  • the semiconductor layer 330, the conductive layer 340a, and the conductive layer 340b are processed to remove parts of the semiconductor layer 330, the conductive layer 340a, and the conductive layer 340b. This exposes a part of the top surface of the insulating layer 380b.
  • the semiconductor layer 330, the conductive layer 340a, and the conductive layer 340b can be processed using the same mask as the semiconductor layer 130, the conductive layer 140a, and the conductive layer 140b. This is preferable because it reduces the number of masks required to manufacture a semiconductor device.
  • an insulating layer 350 is formed so as to cover the semiconductor layer 330.
  • the insulating layer 350 is formed so as to cover the semiconductor layer 330, the side surfaces of the conductive layer 340b, the side surfaces of the conductive layer 340a, and the top surface of the insulating layer 380b.
  • the insulating layer 350 can be formed in the same manner as the insulating layer 250.
  • a conductive layer 365a is formed on the insulating layer 350 so as to have a region located inside the opening 390.
  • a conductive layer 365b is also formed on the conductive layer 365a.
  • the conductive layer 365a is preferably formed so as to fill the opening 390.
  • the conductive layer 365a is preferably formed so as to fill the recess of the insulating layer 350.
  • the conductive layer 365b may also be formed inside the opening 390.
  • the conductive layer 365 can be formed in the same manner as the conductive layer 320.
  • a transistor 300 can be formed, which includes a conductive layer 320, a conductive layer 340, a conductive layer 355, a conductive layer 365, a semiconductor layer 330, an insulating layer 335, and an insulating layer 350.
  • a memory cell 10 including a transistor 100, a transistor 200, and a transistor 300 can be manufactured.
  • a semiconductor device including a memory cell 10 can be manufactured.
  • the steps are performed up to the formation of the insulating layer 350 by the same method as the above manufacturing method. Then, a sacrificial layer is formed so as to have a region located inside the opening 390. Then, an insulating layer 383 is formed so as to cover the insulating layer 350 and the sacrificial layer, and an insulating layer 385 is formed on the insulating layer 383. Then, a planarization process is performed on the insulating layer 385, the insulating layer 383, and the sacrificial layer.
  • the steps up to the formation of the semiconductor layer 330 are performed by the same method as the above manufacturing method. Then, a sacrificial layer is formed so as to have a region located inside the opening 390. Then, an insulating layer 383 is formed so as to cover the insulating layer 380b, the conductive layer 240, the semiconductor layer 330, and the sacrificial layer, and an insulating layer 385 is formed on the insulating layer 383. Then, a planarization process is performed on the insulating layer 385, the insulating layer 383, and the sacrificial layer.
  • an insulating layer 350 is formed so as to cover the openings 370 and 390, and a conductive layer 360 is formed on the insulating layer 350.
  • a planarization process is performed on the conductive layer 360 and the insulating layer 350.
  • the upper surfaces of the insulating layer 383 and the insulating layer 385 are exposed, and the upper surfaces of the conductive layer 360, the insulating layer 350, the insulating layer 383, and the insulating layer 385 are planarized.
  • a conductive layer 365 is formed on the insulating layer 383, the insulating layer 385, and the conductive layer 360. In this manner, the memory cell 10I can be manufactured.
  • the oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having crystallinity.
  • a metal oxide having crystallinity examples include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure.
  • CAAC c-axis aligned crystal
  • nc nanocrystalline
  • the oxide semiconductor layer of one embodiment of the present invention preferably has a metal oxide having a CAAC structure.
  • the CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have a c-axis orientation and are connected without being oriented in the a-b plane.
  • TEM transmission electron microscope
  • the crystallinity of the oxide semiconductor layer can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.
  • XRD X-ray diffraction
  • TEM TEM
  • ED electron diffraction
  • the crystallinity of the semiconductor material of the oxide semiconductor layer is not particularly limited.
  • the oxide semiconductor layer may contain one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part).
  • an amorphous semiconductor a semiconductor having an amorphous structure
  • a single crystal semiconductor a semiconductor having a single crystal structure
  • a semiconductor having crystallinity other than single crystal a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part.
  • Examples of the metal oxide contained in the oxide semiconductor layer of one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide.
  • the metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn).
  • the metal oxide preferably contains two or three elements selected from indium, element M, and zinc.
  • element M is a metal element or semimetal element having a high bond energy with oxygen, for example, a metal element or semimetal element having a bond energy with oxygen higher than that of indium.
  • element M examples include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.
  • the element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium.
  • the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc.
  • metal elements and metalloid elements may be collectively referred to as “metal elements", and the "metal element” described in this specification may include metalloid elements.
  • metal oxides examples include indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), and indium zinc oxide (In-Ga-Sn oxide, also referred to as IGTO).
  • In-Zn oxide indium zinc oxide
  • In-Sn oxide indium titanium oxide
  • In-Ti oxide indium gallium oxide
  • In-Ga oxide indium gallium aluminum oxide
  • In-Ga-Al oxide indium gallium tin oxide
  • IGTO gallium zinc oxide
  • GZO gallium zinc oxide
  • Al-Zn oxide also referred to
  • Indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO or IAGZO), etc.
  • indium tin oxide containing silicon also called ITSO
  • gallium tin oxide Ga-Sn oxide
  • aluminum tin oxide Al-Sn oxide
  • the transistor By increasing the ratio of the number of indium atoms to the sum of the number of atoms of all metal elements contained in the metal oxide, the transistor can obtain a large on-current and high frequency characteristics.
  • the metal oxide may have one or more metal elements having a higher period number in the periodic table instead of indium.
  • the metal oxide may have one or more metal elements having a higher period number in the periodic table in addition to indium.
  • the greater the overlap of the orbits of the metal elements the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element having a higher period number in the periodic table, the field effect mobility of the transistor may be increased.
  • Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and metal elements belonging to the sixth period.
  • the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may also contain one or more nonmetallic elements.
  • the field effect mobility of the transistor may be increased.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the metal oxide becomes highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed. Therefore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • In-Ga-Zn oxide may be used as an example of a metal oxide.
  • the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide using two types of film formation methods.
  • the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide using a first film formation method and a second film formation method.
  • a hybrid OS an oxide semiconductor layer formed using two types of film formation methods may be called a hybrid OS.
  • the oxide semiconductor layer of one embodiment of the present invention has crystallinity.
  • the oxide semiconductor layer of one embodiment of the present invention preferably has a CAAC structure.
  • a metal oxide film having crystallinity is formed by using the first film formation method.
  • the metal oxide film formed at this time has a CAAC structure.
  • a metal oxide film formed by a sputtering method is likely to have crystallinity.
  • a mixed layer may be formed at the interface between the metal oxide and the layer on which it is formed.
  • the mixed layer may be formed by particles (also called sputtering particles) emitted from a target or the like, or by energy imparted to the substrate by the sputtering particles or the like. There is a concern that the mixed layer may hinder the crystallization of the metal oxide.
  • silicon oxide when an insulating layer having silicon, such as silicon oxide, is used as the surface to be formed, there is a risk that silicon may be mixed into the metal oxide when a metal oxide is formed on the silicon oxide using the first film formation method. There is a concern that the crystallization of the metal oxide may be inhibited due to the mixing of impurities such as silicon into the metal oxide.
  • a metal oxide is formed using the second film formation method. That is, after forming a metal oxide as a first layer using the second film formation method, a metal oxide is formed as a second layer on the first layer using the first film formation method. At this time, it is preferable to use a film formation method that causes less damage to the surface to be formed compared to the first film formation method as the second film formation method. By using a film formation method that causes less damage to the surface to be formed as the second film formation method, it is possible to suppress the formation of a mixed layer at the interface between the oxide semiconductor layer and the layer that is the surface to be formed of the oxide semiconductor layer.
  • atomic layer deposition ALD
  • chemical vapor deposition CVD
  • the first layer may be, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than the CAAC structure.
  • the crystallinity of the first layer may be increased with the second layer as a nucleus. This may increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which it is formed.
  • the oxide semiconductor layer of one embodiment of the present invention it is preferable to first form a metal oxide on a surface to be formed by using the second film formation method, and then form a metal oxide above the metal oxide by using the first film formation method.
  • Examples of the first film formation method include the sputtering method and the PLD method.
  • the second film formation method may be, for example, the ALD method, the plasma enhanced CVD (PECVD) method, the thermal CVD method, the photo-CVD method, the metal organic CVD (MOCVD) method, and the molecular beam epitaxy (MBE) method.
  • the MBE method is a film formation method that grows a thin film with a crystal structure that reflects the crystal system of the substrate, and can be said to be one of the film formation methods that cause less damage to the surface on which the film is formed.
  • a wet method can be used as the second film formation method.
  • the wet method is one of the film formation methods that cause less damage to the surface on which the film is formed.
  • An example of the wet method is the spray coating method.
  • the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by using the second film formation method, and then forming a metal oxide as a second layer by using the first film formation method.
  • an ALD method can be used as the second film formation method
  • a sputtering method can be used as the first film formation method.
  • the metal oxide formed by using the first film formation method preferably has a CAAC structure.
  • a third layer can be formed on the second layer. Since the second layer has high crystallinity, the third layer can grow crystals using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that is likely to give crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized.
  • the oxide semiconductor layer can have both high crystallinity and high coverage throughout the entire layer.
  • the second layer has excellent crystallinity because the effect of the surface on which it is formed is reduced by providing the first layer, and the crystallinity is increased. Therefore, it is expected that a layer with excellent crystallinity will also be formed in the third layer, which is crystallized using the second layer as a nucleus or seed.
  • the third layer is the top layer of the oxide semiconductor layer, and when the oxide semiconductor layer is used as a semiconductor layer of a transistor, it is, for example, a layer in contact with the gate insulating film. By increasing the crystallinity of the layer in contact with the gate insulating film, it is possible to increase carrier mobility when the transistor is in an on-state.
  • the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer using the second film formation method, forming a metal oxide as a second layer using the first film formation method, and forming a metal oxide as a third layer using the second film formation method.
  • the ALD method can be used as the second film formation method
  • the sputtering method can be used as the first film formation method.
  • the metal oxide formed using the first film formation method preferably has a CAAC structure.
  • the ALD method is a film formation method with better coverage than the sputtering method, and the coverage of the oxide semiconductor layer can be improved by using the ALD method as the film formation method for the first layer and the third layer. Therefore, the oxide semiconductor layer can be well covered on steps or openings with a high aspect ratio.
  • the oxide semiconductor layer 430 can be used for the semiconductor layer 130, the semiconductor layer 230, and the semiconductor layer 330 described in the above embodiments, for example.
  • the oxide semiconductor layer 430 can be manufactured, for example, by forming an oxide semiconductor 430a on a layer 429 that is a surface to be formed by an ALD method, forming an oxide semiconductor 430b on the oxide semiconductor 430a by a sputtering method, and forming an oxide semiconductor 430c on the oxide semiconductor 430b by an ALD method.
  • the heat treatment here is not limited to heating treatment. For example, it may be heat applied during the manufacturing process.
  • the layer 429 is an insulating film, and is, for example, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film.
  • the layer 429 corresponds to one or more of the conductive layer 120, the insulating layer 135, the conductive layer 140, the conductive layer 220, the conductive layer 240, the conductive layer 320, the insulating layer 335, and the conductive layer 340 shown in the previous embodiment.
  • the layer 429 does not have to be crystalline. If the layer 429 is crystalline, it may have a crystal structure with low lattice matching with the metal oxide of the oxide semiconductor layer 430.
  • an oxide semiconductor 430a is formed on the layer 429 (FIG. 25A). Then, an oxide semiconductor 430b is formed on the oxide semiconductor 430a (FIG. 25B).
  • the oxide semiconductor 430b is preferably formed by using a sputtering method.
  • the oxide semiconductor 430b preferably has a composition suitable for forming a CAAC structure.
  • the oxide semiconductor 430a is preferably formed using a deposition method that causes less damage to the surface on which it is formed compared to the deposition method for the oxide semiconductor 430b.
  • the oxide semiconductor 430a is formed using the ALD method.
  • an oxide semiconductor 430b is formed by a sputtering method.
  • the oxide semiconductor 430a is preferably formed by a deposition method that causes little damage to a surface on which the oxide semiconductor 430a is to be formed.
  • the thickness of the alloyed region can be made thin, or can be made thin enough that the alloyed region cannot be observed.
  • the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.
  • Figures 25A and 25B show an example in which no alloyed region is formed between the layer 429 and the oxide semiconductor 430a.
  • the thickness of the alloyed region may be calculated by performing a line analysis of the composition of the region and its surroundings using SIMS or Energy Dispersive X-ray Spectroscopy (EDX).
  • an EDX line analysis is performed on the above region and its periphery with the direction perpendicular to the surface of the oxide semiconductor 430a as the depth direction.
  • the depth at which the quantitative value of a metal (In when the oxide semiconductor 430a contains In) that is the main component of the oxide semiconductor 430a and is not the main component of the layer that will be the surface to be formed (here, layer 429) becomes half-value is defined as the depth (position) of the interface between the above region and the oxide semiconductor 430a.
  • the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that will be the surface to be formed and is not the main component of the oxide semiconductor 430a becomes half-value is defined as the depth (position) of the interface between the above region and the layer that will be the surface to be formed. From the above, the thickness of the alloyed region can be calculated.
  • an element e.g., Si
  • the thickness of the alloyed region in the oxide semiconductor layer of one embodiment of the present invention is observed by EDX analysis, the thickness is, for example, 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.
  • the interface is defined as a depth at which the silicon concentration becomes 50% of the maximum concentration of the layer 429, and the distance between the interface and the depth at which the silicon concentration decreases to 1.0 ⁇ 10 21 atoms/cm 3 , preferably 5.0 ⁇ 10 20 atoms/cm 3 , more preferably 1.0 ⁇ 10 20 atoms/cm 3 is defined as thickness t_s2.
  • the thickness t_s2 is preferably 3 nm or less, more preferably 2 nm or less.
  • the thickness t_s2 can be set to a value within the above range.
  • the vicinity of the surface to be formed refers to, for example, a region that is more than 0 nm and not more than 3 nm, preferably more than 0 nm and not more than 2 nm, and more preferably 1 nm or more and not more than 2 nm, approximately perpendicular to the surface to be formed of the oxide semiconductor layer 430.
  • the CAAC structure near the surface to be formed may be observed by observation using a TEM.
  • a TEM For example, in cross-sectional observation of the oxide semiconductor layer 430 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the surface to be formed are observed near the surface to be formed.
  • an oxide semiconductor layer having a microcrystalline structure or an amorphous structure with lower crystallinity than the CAAC structure may be formed. That is, at the manufacturing stage shown in FIG. 25A, the oxide semiconductor 430a may have a region with lower crystallinity than the oxide semiconductor 430b.
  • an In-M-Zn oxide is formed as the oxide semiconductor 430b on the oxide semiconductor 430a using the sputtering method.
  • the mixed layer 431 is formed on or near the surface of the oxide semiconductor 430a.
  • minute crystal regions may be formed in the mixed layer 431 due to sputtering particles or energy provided to the substrate by the sputtering particles when the oxide semiconductor 430b is formed.
  • the mixed layer 431 or the minute crystal regions formed in the mixed layer 431 may become nuclei, and at least a part of the oxide semiconductor 430a may crystallize.
  • In-Mn-Zn oxide can be used as a target for the sputtering method.
  • oxygen or a mixed gas of oxygen and a noble gas can be used as the sputtering gas.
  • the proportion of oxygen contained in the sputtering gas the amount of excess oxygen in the oxide film to be formed can be increased.
  • the higher the ratio of the flow rate of oxygen gas to the total deposition gas used during deposition (hereinafter also referred to as the oxygen flow rate ratio), the more crystalline the metal oxide may be formed.
  • an oxygen-excess metal oxide may be formed when the ratio of oxygen contained in the sputtering gas is set to more than 30% and not more than 100%, preferably 70% to 100%.
  • a transistor using an oxygen-excess oxide semiconductor layer in a channel formation region can have relatively high reliability.
  • one embodiment of the present invention is not limited thereto.
  • An oxygen-deficient metal oxide is formed when the ratio of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%, when the transistor is formed.
  • a relatively high field effect mobility can be obtained when an oxygen-deficient metal oxide is used in a channel formation region.
  • the substrate heating temperature is preferably, for example, 100° C. or higher and 400° C. or lower, and more preferably 200° C. or higher and 300° C. or lower.
  • an oxide semiconductor 430a and an oxide semiconductor 430b on the oxide semiconductor 430a can be formed on the layer 429.
  • oxide semiconductor 430c is formed on oxide semiconductor 430b (FIG. 25C).
  • oxide semiconductor 430c is formed using an ALD method.
  • the method for forming oxide semiconductor 430a can be referred to.
  • the oxide semiconductor 430c When the oxide semiconductor 430c is formed on the oxide semiconductor 430b having the CAAC structure by the ALD method, the oxide semiconductor 430c may grow epitaxially with the oxide semiconductor 430b as a nucleus. Therefore, when the oxide semiconductor 430c is formed, the oxide semiconductor 430c may have a region having the CAAC structure. In addition, the region having the CAAC structure is preferably formed over the entire oxide semiconductor 430c.
  • a heat treatment process may be performed.
  • the temperature of the heat treatment can be, for example, 100°C to 800°C, preferably 250°C to 650°C, more preferably 350°C to 550°C. Typically, it can be 400°C ⁇ 25°C (375°C to 425°C).
  • the treatment time can be 10 hours or less, or 1 minute to 5 hours, or 1 minute to 2 hours. When an RTA apparatus is used, the treatment time can be, for example, 1 second to 5 minutes. It is expected that the heat treatment will repair the gaps in the atomic level crystal parts of the CAAC structure of the oxide semiconductor 430b by the oxide semiconductor 430c (in other words, the crystal molecules formed by the ALD method).
  • the heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element.
  • a heating element such as a resistance heating element.
  • an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device may be used.
  • An LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp.
  • a GRTA device is a device that performs heat treatment using high-temperature gas.
  • the heat treatment process may increase the crystallinity of the region having the CAAC structure in the oxide semiconductor 430c. Furthermore, if the region is formed only below the oxide semiconductor 430c after film formation by the ALD method, the heat treatment process may cause the region to expand upward ( FIG. 25D ). That is, by performing the heat treatment, a region having the CAAC structure may be formed throughout the entire layer in the oxide semiconductor 430c.
  • the oxide semiconductor 430a is converted into CAAC by this heat treatment process (FIG. 25D). It is expected that the conversion into CAAC is facilitated by the mixed layer 431 formed in the oxide semiconductor 430a during the deposition of the oxide semiconductor 430b acting as a nucleus or seed. It is preferable that the region in the oxide semiconductor 430a that is converted into CAAC is large, and it is preferable that the conversion into CAAC extends to the vicinity of the layer 429.
  • the oxide semiconductor 430a is converted into CAAC from the top to the bottom, the CAAC can be converted into CAAC up to the vicinity of the layer 429 without being limited by the material or crystallinity of the layer 429.
  • the oxide semiconductor 430a can be formed with high crystallinity. Therefore, the method for manufacturing an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where the layer on which the oxide semiconductor layer is to be formed has an amorphous structure.
  • 25A to 25D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention.
  • 25A to 25D can also be regarded as conceptual diagrams illustrating a model for forming a metal oxide film according to one embodiment of the present invention.
  • the oxide semiconductor 430a and the oxide semiconductor 430c each have high crystallinity using the oxide semiconductor 430b, which has high crystallinity, as a nucleus or seed.
  • the crystallinity of the oxide semiconductor 430a may be increased by heat treatment during the formation of the oxide semiconductor 430b or after the formation of the oxide semiconductor 430c.
  • the crystallinity of the oxide semiconductor 430c may be increased by heat treatment during the formation of the oxide semiconductor 430c or after the formation of the oxide semiconductor 430c.
  • the heat treatment has an assisting effect of increasing the crystallinity.
  • the crystallinity of the upper and lower oxide semiconductors can be increased by using the oxide semiconductor 430b (i.e., CAAC) with high crystallinity as a nucleus or seed.
  • the oxide semiconductor 430b i.e., CAAC
  • the upper and lower oxide semiconductors can be grown in a solid phase using the oxide semiconductor 430b as a nucleus or seed to form an oxide semiconductor with high crystallinity.
  • the oxide semiconductor formed by such a film formation method that is, the CAAC film here, can be called an axial growth CAAC (AG CAAC).
  • the present invention is not limited to this.
  • the AG CAAC can also be obtained in the configuration including the oxide semiconductor 430a and the oxide semiconductor 430b.
  • FIG. 26A shows the state in which the oxide semiconductor 430a, the oxide semiconductor 430b, and the oxide semiconductor 430c are each crystallized.
  • the region having the CAAC structure is connected to the region having the CAAC structure in the oxide semiconductor 430b through crystals.
  • the oxide semiconductor 430c the region having the CAAC structure is connected to the region having the CAAC structure in the oxide semiconductor 430b through crystals.
  • the oxide semiconductor layer 430 may be expressed as a single layer whose interface is not clearly observed.
  • the oxide semiconductor layer 430 may be expressed as a single layer.
  • a portion of the oxide semiconductor 430a or the oxide semiconductor 430c may not be crystallized.
  • the example shown in FIG. 26B shows that the oxide semiconductor 430a is not crystallized near the interface with the layer 429.
  • FIG. 26C shows that the oxide semiconductor 430c is not crystallized near the surface.
  • FIG. 26D shows that the oxide semiconductor 430a is not crystallized near the interface with the layer 429 and near the surface of the oxide semiconductor 430c.
  • the oxide semiconductor layer By increasing the crystallinity of the oxide semiconductor layer, it is expected that the increase in electrical resistance of the semiconductor layer of a transistor using the oxide semiconductor layer can be suppressed, or the initial characteristics (particularly the on-current) of the transistor can be improved, making the transistor suitable for high-speed operation. In addition, the reliability of the transistor can be increased, and the on-current can be increased.
  • the oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the layer. Therefore, in the oxide semiconductor layer 430, the boundaries between the stacked films of the oxide semiconductor 430a, the oxide semiconductor 430b, and the oxide semiconductor 430c may not be visible. In particular, after heat treatment, it may be difficult to confirm the boundaries between the stacked films. The presence or absence of the boundaries between the stacked films can be confirmed by, for example, cross-sectional TEM or cross-sectional STEM.
  • the field effect mobility of the transistor can be increased.
  • an oxide semiconductor with a high In content tends to become polycrystalline.
  • Using a metal oxide with a polycrystalline structure for a transistor adversely affects the initial characteristics or reliability of the transistor. Therefore, by using an oxide semiconductor with a high In content for one or both of the oxide semiconductors 430a and 430c, crystals that reflect the crystal orientation of the oxide semiconductor 430b are formed, and polycrystallization can be suppressed.
  • the degree of lattice mismatch between the crystals of the oxide semiconductor 430b and the crystals of the oxide semiconductor 430a or the oxide semiconductor 430c is small.
  • the oxide semiconductor 430a or the oxide semiconductor 430c can form a crystal that reflects the orientation of the crystals of the oxide semiconductor 430b.
  • bright spots arranged in layers in a direction parallel to the formation surface are confirmed in the oxide semiconductor 430a or the oxide semiconductor 430c.
  • the crystal structure of the oxide semiconductor 430a or the oxide semiconductor 430c is not particularly limited.
  • the crystal structure of the oxide semiconductor 430a or the oxide semiconductor 430c may be any of a cubic system, a tetragonal system, an orthorhombic system, a hexagonal system, a monoclinic system, and a trigonal system.
  • the oxide semiconductor 430b preferably has a composition suitable for forming a CAAC structure.
  • the oxide semiconductor 430b can be formed by, for example, a sputtering method.
  • the oxide semiconductor 430b preferably contains, for example, zinc. When the oxide semiconductor 430b contains zinc, it becomes a metal oxide with high crystallinity.
  • the oxide semiconductor 430b preferably contains an element M in addition to zinc. When the oxide semiconductor 430b contains the element M, for example, it is possible to suppress the formation of oxygen vacancies in the metal oxide. Therefore, the reliability of a transistor to which an oxide semiconductor layer is applied can be improved.
  • the composition in the vicinity includes a range of ⁇ 30% of the desired atomic ratio.
  • the oxide semiconductor 430b may be configured not to include the element M.
  • it may be an In-Zn oxide.
  • indium oxide may be used. It may also be configured to include a trace amount of the element M.
  • the oxide semiconductor 430a and the oxide semiconductor 430c can be metal oxides having a high ratio of In.
  • the oxide semiconductor 430a and the oxide semiconductor 430c can be formed by, for example, an ALD method.
  • a metal oxide having a high ratio of In when the oxide semiconductor layer is used in a transistor, the on-current can be increased and the frequency characteristics can be improved.
  • the oxide semiconductor 430a and the oxide semiconductor 430c may not contain the element M.
  • they may be In-Zn oxide.
  • indium oxide may be used.
  • the oxide semiconductor 430a and the oxide semiconductor 430c may have a composition containing a trace amount of the element M.
  • the oxide semiconductor 430a and the oxide semiconductor 430c can be metal oxides having a higher proportion of In than the oxide semiconductor 430b.
  • a metal oxide having a higher Ga ratio than the oxide semiconductor 430b can be used as the oxide semiconductor 430a and the oxide semiconductor 430c.
  • the band gaps of the oxide semiconductor 430a and the oxide semiconductor 430c can be made larger than that of the oxide semiconductor 430b in some cases.
  • the oxide semiconductor 430b is sandwiched between the oxide semiconductor 430a and the oxide semiconductor 430c, which have a larger band gap, and the oxide semiconductor 430b mainly functions as a current path (channel).
  • the trap levels at the interface of the oxide semiconductor 430b and in its vicinity can be reduced. This makes it possible to realize a buried channel type transistor in which the channel is away from the insulating layer interface, and the field effect mobility can be increased.
  • the influence of the interface states that may be formed on the back channel side can be reduced, and the light deterioration (e.g., negative bias light deterioration) of the transistor can be suppressed, thereby improving the reliability of the transistor.
  • the oxide semiconductor layer of one embodiment of the present invention uses compositions for the oxide semiconductor 430a and the oxide semiconductor 430c that make it difficult to form a CAAC structure when a single layer is formed, crystal growth occurs with the oxide semiconductor 430b as a nucleus, so that the entire oxide semiconductor layer including the oxide semiconductor 430a and the oxide semiconductor 430c can have the CAAC structure.
  • the CAAC structure can be formed in a region including at least a part of each of the oxide semiconductor 430a and the oxide semiconductor 430c and a region including the oxide semiconductor 430b.
  • the oxide semiconductor layer can have suitable crystallinity for use as a semiconductor layer of a transistor.
  • the increase in the In content can improve the on-state characteristics of the transistor, and the CAAC structure with high crystallinity can improve reliability.
  • oxide semiconductor 430a and oxide semiconductor 430c may be different.
  • the oxide semiconductor 430a and the oxide semiconductor 430c may be made of a metal oxide having the same composition as the oxide semiconductor 430b. By using the same composition, CAAC may be easily formed after heat treatment.
  • an oxide semiconductor layer having a CAAC structure formed using the above-mentioned two types of film formation methods may have a higher film relative dielectric constant, film density, and film hardness, or both, compared to an oxide semiconductor layer having a CAAC structure formed using one type of film formation method.
  • an oxide semiconductor layer having a CAAC structure formed using the above-mentioned two types of film formation methods in the channel formation region of a transistor it is possible to realize a transistor with excellent characteristics (e.g., a transistor with a large on-state current, a transistor with a high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also called f characteristics), a highly reliable transistor, etc.).
  • a transistor with excellent characteristics e.g., a transistor with a large on-state current, a transistor with a high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also called f characteristics), a highly reliable transistor, etc.
  • the composition of the metal oxide used in the oxide semiconductor layer 430 can be analyzed using, for example, EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.
  • the oxide semiconductor layer of one embodiment of the present invention can be used as a semiconductor layer of a transistor.
  • the thickness of the oxide semiconductor layer 430 is, for example, preferably 3 nm or more and 200 nm or less, more preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 100 nm or less, more preferably 10 nm or more and 70 nm or less, more preferably 15 nm or more and 70 nm or less, more preferably 15 nm or more and 50 nm or less, and more preferably 20 nm or more and 50 nm or less.
  • the thickness of the oxide semiconductor layer 430 is preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less.
  • the oxide semiconductor 430b is preferably, for example, 200 nm or less. Furthermore, when the oxide semiconductor 430b is in a layer shape, it is preferably, for example, 1 nm or more and 200 nm or less, more preferably 1 nm or more and 100 nm or less, and more preferably 2 nm or more and 100 nm or less.
  • the oxide semiconductor 430b may not exist as a layer, but may be an aggregate of island-shaped regions. In such a case, for example, the island-shaped regions of the oxide semiconductor 430b exist discretely.
  • the oxide semiconductor 430a and the oxide semiconductor 430c are each, for example, preferably 1 nm or more and 50 nm or less, more preferably 1 nm or more and 30 nm or less, more preferably 1 nm or more and 20 nm or less, and more preferably 2 nm or more and 20 nm or less.
  • the channel formation region of a transistor using an oxide semiconductor for the semiconductor layer has fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, and metal elements than the source and drain regions.
  • impurities such as hydrogen, nitrogen, and metal elements
  • the electrical characteristics are likely to fluctuate and the reliability may be reduced.
  • hydrogen near the oxygen vacancies may form V O H and generate electrons that serve as carriers.
  • the transistor is likely to have normally-on characteristics. Therefore, it is preferable that V O H is also reduced in the channel formation region.
  • the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, it can be said that the channel formation region of the transistor is i-type (intrinsic) or substantially i-type.
  • an impurity in an oxide semiconductor refers to, for example, anything other than the main component that constitutes the oxide semiconductor.
  • an element with a concentration of less than 0.1 atomic % can be considered an impurity.
  • the carbon concentration in a channel formation region of the oxide semiconductor measured by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, and further preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, and still more preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the nitrogen concentration in a channel formation region of an oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 5 ⁇ 10 18 atoms/cm 3 or less, more preferably 1 ⁇ 10 18 atoms/cm 3 or less, and further preferably 5 ⁇ 10 17 atoms/cm 3 or less.
  • Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy.
  • an electron serving as a carrier may be generated.
  • some of the hydrogen may bond to oxygen bonded to a metal atom to generate an electron serving as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable that hydrogen in a channel formation region of the oxide semiconductor is reduced as much as possible.
  • the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 1 ⁇ 10 20 atoms/cm 3 , preferably less than 5 ⁇ 10 19 atoms/cm 3 , more preferably less than 1 ⁇ 10 19 atoms/cm 3 , more preferably less than 5 ⁇ 10 18 atoms/cm 3 , more preferably less than 1 ⁇ 10 18 atoms/cm 3 , and further preferably less than 1 ⁇ 10 17 atoms/cm 3 .
  • the concentration of the alkali metal or the alkaline earth metal in a channel formation region of the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms/cm 3 or less, preferably 2 ⁇ 10 16 atoms/cm 3 or less.
  • the oxide semiconductor layer of one embodiment of the present invention has a CAAC structure.
  • the crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated using crystal orientation, for example.
  • Crystal orientation can be obtained from the Fast Fourier Transform (FFT) pattern obtained by performing FFT processing on the TEM image. Specifically, the direction of the crystal axis can be obtained using the FFT pattern.
  • the FFT pattern obtained by FFT processing reflects reciprocal lattice space information similar to that of an electron beam diffraction pattern.
  • the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation of each region within a certain area, a map showing the crystal orientation can be formed. Specifically, two spots with high intensity are observed in the FFT pattern of a region having layered crystal parts. The direction of the crystal axis of the region can be obtained from the angle of the line segment connecting the two spots.
  • the c-axis orientation rate can be calculated by calculating the percentage of c-axis oriented regions in a map showing crystal orientation. Note that c-axis oriented regions are defined here as regions whose orientation coincides with the c-axis and regions whose orientation differs from the c-axis by 20 degrees or less.
  • the c-axis orientation rate can be calculated, for example, by TEM observation of a cross section or a plan view of the oxide semiconductor layer.
  • the region where FFT is performed (also referred to as an FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region where FFT is performed is not limited to a circle.
  • the c-axis orientation rate is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more.
  • the c-axis orientation rates of the region where the oxide semiconductor 430a is formed, the region where the oxide semiconductor 430b is formed, and the region where the oxide semiconductor 430c is formed are Rc1, Rc2, and Rc3, respectively.
  • Rc2 is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more.
  • Rc3 is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more.
  • Rc3/Rc1 is preferably greater than 1.
  • Rc2/Rc1 is preferably greater than 1.
  • the boundaries between the oxide semiconductor 430a, the oxide semiconductor 430b, and the oxide semiconductor 430c may not be clearly observed.
  • the oxide semiconductor layer 430 of one embodiment of the present invention can be divided into three regions, a first region, a second region, and a third region, in this order from the top of the layer 429. Each region is a layer-like region.
  • the first region, the second region, and the third region each have a CAAC structure.
  • the c-axis orientation rate of the third region is preferably higher than the c-axis orientation rate of the first region.
  • the c-axis orientation rate of the second region is preferably higher than the c-axis orientation rate of the first region.
  • the c-axis orientation rate of the third region is 80% or more, more preferably 90% or more, and even more preferably 95% or more.
  • the c-axis orientation rate of the second region is 80% or more, more preferably 90% or more, and even more preferably 95% or more.
  • the first region is located at a distance of 0 nm to 3 nm from the top surface of the layer 429, and the third region is located at a distance of 0 nm to 3 nm from the top surface of the oxide semiconductor layer 430.
  • the layer thickness of each region may be, for example, approximately the same.
  • Figure 27 is a cross-sectional view showing a configuration example of a semiconductor device.
  • Figure 27 shows an example in which a memory cell 10 is provided above a transistor 500.
  • the memory cell 10 has a transistor 100, a transistor 200 on the transistor 100, and a transistor 300 on the transistor 200, as shown in the previous embodiment.
  • the transistor 500 can be a transistor provided in a drive circuit, which is a circuit for driving the memory cell 10.
  • the transistor 500 can be a transistor provided in, for example, a sense amplifier.
  • the bit line can be shortened by providing, for example, a transistor 500 so that it overlaps with the memory cell 10. This reduces the bit line capacitance, allowing the semiconductor device to operate at high speed.
  • the semiconductor device shown in FIG. 27 can correspond to the semiconductor device 900 described in the fourth embodiment.
  • the transistor 500 corresponds to the transistor included in the sense amplifier 927 in the semiconductor device 900.
  • the transistor 500 is provided on a substrate 511 and has a conductive layer 516 that functions as a gate electrode, an insulating layer 515 that functions as a gate insulating layer, a semiconductor region 513 that is a part of the substrate 511, a low-resistance region 514a that functions as one of the source region and drain region, and a low-resistance region 514b that functions as the other of the source region and drain region.
  • the transistor 500 may be either a p-channel type or an n-channel type.
  • the substrate 511 preferably contains a silicon-based semiconductor, and more specifically, preferably contains single crystal silicon.
  • the semiconductor region 513 (part of the substrate 511) in which the channel is formed has a convex shape.
  • a conductive layer 516 is provided so as to cover the side and top surface of the semiconductor region 513 via an insulating layer 515.
  • the conductive layer 516 may be made of a material that adjusts the work function.
  • Such a transistor 500 is also called a FIN type transistor because it uses the convex portion of the semiconductor substrate.
  • an insulating layer that is in contact with the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided.
  • a semiconductor film having a convex shape may be formed by processing an SOI substrate.
  • transistor 500 shown in FIG. 27 is just an example, and the structure is not limited thereto, and an appropriate transistor can be used depending on the circuit configuration or driving method.
  • a wiring layer having an interlayer film, wiring, plugs, etc. may be provided between each structure. Also, multiple wiring layers may be provided depending on the design.
  • the conductive layer functioning as a plug or wiring may be given the same reference symbol as a group of multiple structures. Also, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.
  • an insulating layer 520, an insulating layer 522, an insulating layer 524, and an insulating layer 526 are stacked in this order as an interlayer film on the transistor 500.
  • a conductive layer 528 is embedded in the insulating layer 520 and the insulating layer 522, and a conductive layer 530 is embedded in the insulating layer 524 and the insulating layer 526.
  • the conductive layer 528 and the conductive layer 530 function as a plug or wiring.
  • the insulating layer that functions as an interlayer film may also function as a planarizing film that covers the uneven shape below it.
  • the top surface of the insulating layer 522 may be planarized by a planarization process using a CMP method or the like to improve the planarity.
  • a wiring layer may be provided on the insulating layer 526 and the conductive layer 530.
  • an insulating layer 550, an insulating layer 552, and an insulating layer 554 are stacked in this order.
  • a conductive layer 556 is formed on the insulating layer 550, the insulating layer 552, and the insulating layer 554.
  • the conductive layer 556 functions as a plug or wiring.
  • the insulating layer 552 and insulating layer 554, which function as interlayer films, can be made of insulating layers that can be used in the semiconductor device described above.
  • a conductive material applicable to at least one of the conductive layers 140a, 140b, 240a, 240b, 340a, and 340b can be used. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to form the conductive layers from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced.
  • An insulating layer 648 is provided on the insulating layer 554 and the conductive layer 556.
  • insulating layer 180a, insulating layer 180b, insulating layer 181A, insulating layer 183A, insulating layer 280, insulating layer 250, insulating layer 380a, and insulating layer 380b are stacked in this order on the insulating layer 648.
  • the low-resistance region 514a which functions as one of the source and drain regions of the transistor 500, is electrically connected to the conductive layer 340, which functions as the other of the source and drain electrodes of the transistor 300, via the conductive layer 528, the conductive layer 530, the conductive layer 556, the conductive layer 646, the conductive layer 651, the conductive layer 652, the conductive layer 653, the conductive layer 654, the conductive layer 655, and the conductive layer 656.
  • the conductive layer 646 is embedded in the insulating layer 648 and is provided on the conductive layer 556.
  • the conductive layer 646 is in contact with, for example, the upper surface of the conductive layer 556.
  • the conductive layer 651 is provided on the conductive layer 646 and on the insulating layer 648.
  • the conductive layer 651 is in contact with, for example, the upper surface of the conductive layer 646 and the upper surface of the insulating layer 648.
  • the conductive layer 651 can have a two-layer structure including, for example, a layer (lower layer) that can be manufactured using the same material and process as the conductive layer 120a, and a layer (upper layer) that can be manufactured using the same material and process as the conductive layer 120b.
  • the conductive layer 652 is embedded in the insulating layers 180a, 180b, 181A, and 183A, and is provided on the conductive layer 651.
  • FIG. 27 shows an example in which the conductive layer 652 is embedded in the upper layer of the conductive layer 651. In this case, the conductive layer 652 can be in contact with the upper surface of the lower layer of the conductive layer 651 and the side surface of the upper layer of the conductive layer 651.
  • the conductive layer 653 is provided on the conductive layer 652 and on the insulating layer 183A.
  • the conductive layer 653 is in contact with, for example, the upper surface of the conductive layer 652 and the upper surface of the insulating layer 183A.
  • the conductive layer 653 can have a two-layer structure including, for example, a layer (lower layer) that can be made of the same material and in the same process as the conductive layer 220a, and a layer (upper layer) that can be made of the same material and in the same process as the conductive layer 220b.
  • the conductive layer 654 is embedded in the insulating layer 280 and the insulating layer 250, and is provided on the conductive layer 653.
  • FIG. 27 shows an example in which the conductive layer 654 is embedded in the upper layer of the conductive layer 653. In this case, the conductive layer 654 can be in contact with the upper surface of the lower layer of the conductive layer 653 and the side surface of the upper layer of the conductive layer 653.
  • the conductive layer 655 is provided on the conductive layer 654 and on the insulating layer 250.
  • the conductive layer 655 is in contact with, for example, the upper surface of the conductive layer 654 and the upper surface of the insulating layer 250.
  • the conductive layer 655 can have a two-layer structure including, for example, a layer (lower layer) that can be manufactured using the same material and process as the conductive layer 320a, and a layer (upper layer) that can be manufactured using the same material and process as the conductive layer 320b.
  • the conductive layer 656 is embedded in the insulating layer 380a and the insulating layer 380b, and is provided on the conductive layer 655.
  • FIG. 27 shows an example in which the conductive layer 656 is embedded in the upper layer of the conductive layer 655. In this case, the conductive layer 656 can be in contact with the upper surface of the lower layer of the conductive layer 655 and the side surface of the upper layer of the conductive layer 655.
  • the conductive layer 340a is provided on the conductive layer 656 and on the insulating layer 380b.
  • the conductive layer 340a is in contact with, for example, the upper surface of the conductive layer 656 and the upper surface of the insulating layer 380b.
  • the low resistance region 514a and the conductive layer 340a are electrically connected via the conductive layer 528, the conductive layer 530, the conductive layer 556, the conductive layer 646, the conductive layer 651, the conductive layer 652, the conductive layer 653, the conductive layer 654, the conductive layer 655, and the conductive layer 656.
  • An insulating layer 387 is provided as an interlayer film on the transistor 300. Specifically, the insulating layer 387 is provided on the conductive layer 365b and the insulating layer 350.
  • Figure 28 is a cross-sectional view showing an example in which the memory cells 10 shown in Figure 27 are stacked in n layers (n is an integer of 3 or more).
  • the semiconductor device shown in FIG. 28 has n memory layers 160. Specifically, memory layer 160[2] is provided on memory layer 160[1], and (n-2) memory layers are further provided on memory layer 160[2], with the topmost memory layer being memory layer 160[n].
  • the number of memory cells 10 in one memory layer 160 is not particularly limited, and two or more memory cells 10 can be included.
  • the memory cells 10 in n memory layers 160 are electrically connected to a drive circuit, specifically, for example, a sense amplifier, provided below memory layer 160.
  • FIG. 28 shows layer 170 in which the drive circuit is provided.
  • the above-mentioned transistor 500 is provided in layer 170.
  • the memory cells 10 can be integrated and arranged without increasing the area occupied by the memory array in which the memory cells 10 are arranged in a matrix.
  • a 3D memory array can be configured.
  • the semiconductor device 900 can function as a memory device.
  • FIG. 29 shows a block diagram illustrating a configuration example of a semiconductor device 900.
  • the semiconductor device 900 shown in FIG. 29 has a driver circuit 910 and a memory array 920.
  • the memory array 920 has one or more memory cells 10.
  • FIG. 29 shows an example in which the memory array 920 has a plurality of memory cells 10 arranged in a matrix.
  • the memory cell 10 shown in the previous embodiment can be applied to the memory cell 10.
  • the drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915.
  • the peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.
  • each circuit, signal, and voltage can be selected or removed as needed. Alternatively, other circuits or signals may be added.
  • Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • Signal CLK is a clock signal.
  • signals BW, CE, and GW are control signals.
  • Signal CE is a chip enable signal
  • signal GW is a global write enable signal
  • signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • Signal WDA is write data
  • signal RDA is read data.
  • Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 912.
  • the control circuit 912 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.
  • the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900.
  • the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.
  • the voltage generation circuit 928 has a function of generating a negative voltage.
  • the signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.
  • the peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 10.
  • the peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.
  • the row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR.
  • the row decoder 941 is a circuit for specifying the row to be accessed
  • the column decoder 942 is a circuit for specifying the column to be accessed.
  • the row driver 923 has the function of selecting the row specified by the row decoder 941.
  • the column driver 924 has the function of writing data to the memory cell 10, the function of reading data from the memory cell 10, and the function of retaining the read data.
  • the input circuit 925 has a function of holding a signal WDA.
  • the data held by the input circuit 925 is output to the column driver 924.
  • the output data of the input circuit 925 is data (Din) to be written to the memory cell 10.
  • the data (Dout) read from the memory cell 10 by the column driver 924 is output to the output circuit 926.
  • the output circuit 926 has a function of holding Dout.
  • the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900.
  • the data output from the output circuit 926 is the signal RDA.
  • the PSW 931 has a function of controlling the supply of V DD to the peripheral circuit 915.
  • the PSW 932 has a function of controlling the supply of V HM to the row driver 923.
  • the high power supply potential of the semiconductor device 900 is V DD
  • the low power supply potential is GND (ground potential).
  • V HM is a high power supply potential used to set the word line to a high level, and is higher than V DD .
  • the on/off of the PSW 931 is controlled by a signal PON1, and the on/off of the PSW 932 is controlled by a signal PON2.
  • the number of power supply domains to which V DD is supplied in the peripheral circuit 915 is one, but it may be more than one. In this case, a power switch can be provided for each power supply domain.
  • the driving circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Also, as shown in FIG. 30A, the driving circuit 910 and memory array 920 may be provided overlapping each other. By providing the driving circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Also, as shown in FIG. 30B, the memory array 920 may be provided in multiple layers on the driving circuit 910.
  • Figure 31 shows a block diagram of the arithmetic unit 960.
  • the arithmetic unit 960 shown in Figure 31 can be applied to, for example, a CPU.
  • the arithmetic unit 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), or an NPU (Neural Processing Unit) that have a large number (several tens to several hundreds) of processor cores capable of parallel processing more than a CPU.
  • processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), or an NPU (Neural Processing Unit) that have a large number (several tens to several hundreds) of processor cores capable of parallel processing more than a CPU.
  • the arithmetic device 960 shown in FIG. 31 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990.
  • the substrate 990 is a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may have a rewritable ROM and a ROM interface.
  • the cache 999 and the cache interface 989 may be provided on a separate chip.
  • the cache 999 is connected to a main memory provided on a separate chip via a cache interface 989.
  • the cache interface 989 has a function of supplying a portion of the data held in the main memory to the cache 999.
  • the cache interface 989 also has a function of outputting a portion of the data held in the cache 999 to the ALU 991 or register 996, etc. via the bus interface 998.
  • a memory array 920 can be provided by stacking it on the arithmetic unit 960.
  • the memory array 920 can be used as a cache.
  • the cache interface 989 may have a function of supplying data held in the memory array 920 to the cache 999.
  • a drive circuit 910 is included as part of the cache interface 989.
  • the arithmetic device 960 shown in FIG. 31 is merely an example of a simplified configuration, and the actual arithmetic device 960 has a wide variety of configurations depending on the application.
  • the more cores there are, the more preferable it is, but for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more.
  • the number of bits that the arithmetic device 960 can handle in the internal arithmetic circuit or data bus can be, for example, 8 bits, 16 bits, 32 bits, or 64 bits.
  • Instructions input to the arithmetic unit 960 via the bus interface 998 are input to the instruction decoder 993, decoded, and then input to the ALU controller 992, the interrupt controller 994, the register controller 997, or the timing controller 995.
  • the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates a signal for controlling the operation of the ALU 991. In addition, the interrupt controller 994 determines and processes interrupt requests from external input/output devices or peripheral circuits, etc., based on their priority and mask state, etc., while the arithmetic device 960 is executing a program. The register controller 997 generates an address for the register 996, and reads and writes to the register 996 depending on the state of the arithmetic device 960.
  • the timing controller 995 also generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997.
  • the timing controller 995 includes an internal clock generating unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.
  • the register controller 997 selects the holding operation in the register 996 according to instructions from the ALU 991. That is, it selects whether the memory cells in the register 996 will hold data using flip-flops or using capacitive elements. If holding data using flip-flops is selected, a power supply potential is supplied to the memory cells in the register 996. If holding data in capacitive elements is selected, the data is rewritten to the capacitive elements, and the supply of power supply potential to the memory cells in the register 996 can be stopped.
  • Figs. 32A and 32B show perspective views of a semiconductor device 970A.
  • the semiconductor device 970A has a layer 930 in which a memory array is provided on the arithmetic device 960.
  • the layer 930 has memory arrays 920L1, 920L2, and 920L3.
  • the arithmetic device 960 and each memory array have overlapping areas.
  • Fig. 32B shows the arithmetic device 960 and layer 930 separated.
  • connection distance between them can be shortened. This allows the communication speed between them to be increased. In addition, the short connection distance allows for reduced power consumption.
  • a method for stacking the layer 930 having a memory array and the arithmetic device 960 As a method for stacking the layer 930 having a memory array and the arithmetic device 960, a method of stacking the layer 930 having a memory array directly on the arithmetic device 960 (also called monolithic stacking) may be used, or a method of forming the arithmetic device 960 and the layer 930 on different substrates, bonding the two substrates, and electrically connecting them using a through via or conductive film bonding technology (Cu-Cu bonding, etc.) may be used.
  • the former method does not require consideration of misalignment during bonding, so not only can the chip size be reduced, but also the manufacturing costs can be reduced.
  • the arithmetic device 960 does not have a cache 999, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache.
  • the memory array 920L1 can be used as an L1 cache (also called a level 1 cache)
  • the memory array 920L2 can be used as an L2 cache (also called a level 2 cache)
  • the memory array 920L3 can be used as an L3 cache (also called a level 3 cache).
  • the memory array 920L3 has the largest capacity and is accessed the least frequently.
  • the memory array 920L1 has the smallest capacity and is accessed the most frequently.
  • each memory array provided in the layer 930 can be used as a lower-level cache or a main memory.
  • the main memory has a larger capacity than the cache and is accessed less frequently.
  • a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided.
  • the driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1.
  • the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2
  • the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.
  • the drive circuit 910L1 may function as part of the cache interface 989, or the drive circuit 910L1 may be configured to be connected to the cache interface 989.
  • the drive circuit 910L2 and the drive circuit 910L3 may also function as part of the cache interface 989, or may be configured to be connected to it.
  • the control circuit 912 can cause some of the multiple memory cells 10 in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.
  • the semiconductor device 900 can cause some of the multiple memory cells 10 to function as a cache, and the other part to function as a main memory. In other words, the semiconductor device 900 can function both as a cache and as a main memory.
  • the semiconductor device 900 according to one aspect of the present invention can function, for example, as a universal memory.
  • a layer 930 having one memory array 920 may be provided on top of the computing device 960.
  • Figure 33A shows a perspective view of the semiconductor device 970B.
  • one memory array 920 can be divided into multiple areas, each of which can be used for different functions.
  • Figure 33A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.
  • the capacity of each of areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of area L1. With such a configuration, it is possible to improve the efficiency of calculation processing and increase the processing speed.
  • Figure 33B shows a perspective view of semiconductor device 970C.
  • the semiconductor device 970C has a layer 930L1 having a memory array 920L1 stacked on top of a layer 930L2 having a memory array 920L2, and a layer 930L3 having a memory array 920L3 stacked on top of that.
  • the memory array 920L1 which is physically closest to the computing device 960, can be used as a higher-level cache, and the memory array 920L3, which is the furthest, can be used as a lower-level cache or main memory. With this configuration, the capacity of each memory array can be increased, thereby further improving processing power.
  • Figure 34A shows the hierarchy of a conventional storage device.
  • Figure 34A shows a register as memory integrated into a processor such as a CPU or GPU, and shows an example in which SRAM is used for cache memory, DRAM for main memory, and NAND memory and HDD (Hard Disk Drive) for storage.
  • SRAM static random access memory
  • HDD Hard Disk Drive
  • Memories embedded in processors such as CPUs and GPUs are used for temporary storage of calculation results, and are therefore accessed frequently by the arithmetic processing unit. Therefore, faster operating speeds are required rather than memory capacity. Registers also have the function of storing setting information for the arithmetic processing unit.
  • a cache has the function of duplicating and storing a portion of the data stored in the main memory. By duplicating frequently used data and storing it in the cache, the speed of accessing the data can be increased.
  • the storage capacity required for a cache is less than that of the main memory, but it is required to operate at a faster speed than the main memory.
  • data that is rewritten in the cache is duplicated and supplied to the main memory.
  • the main memory has the function of holding programs, data, etc. read from storage.
  • Storage has the function of holding data that requires long-term storage and various programs used by the processing unit. Therefore, storage requires a larger memory capacity and a higher recording density than an operating speed.
  • NAND memory such as 3D NAND
  • high-capacity, non-volatile storage devices such as HDDs can be used.
  • At least the DRAM used as the main memory is replaced with a storage device using an oxide semiconductor (OS memory).
  • OS memory oxide semiconductor
  • DRAM requires a refresh operation and is a destructive readout storage device, and therefore consumes much more power than other storage devices. Therefore, by not using DRAM, power consumption can be significantly reduced.
  • the range of various storage devices that is targeted for replacement with OS memory is indicated by a dashed line. In other words, not only the DRAM used as the main memory, but also part of the SRAM used as the cache and the NAND memory used as storage can be replaced with OS memory.
  • Figure 34B shows an example of a semiconductor device according to one embodiment of the present invention.
  • Figure 34B is a schematic diagram showing various memory devices used in the semiconductor device by hierarchy.
  • L1 cache L1 cache
  • L2 cache Last Level cache
  • L1 cache L2 cache.
  • Higher-level caches are required to operate faster because they are accessed more frequently by the processor. Operating speed can also be increased by reducing the data capacity, so it is preferable to reduce the data capacity of higher-level caches.
  • Higher-level caches are preferably located closer physically to the processor and have shorter wiring lengths, so they are preferably provided in a mixed-insertion configuration in the same layer as the processor.
  • Lower-level caches may be provided in a different layer from the processor.
  • the lowest level of cache can be called the LLC.
  • an LLC is not required to operate faster than higher level caches, it is desirable for it to have a large storage capacity.
  • the OS memory of one embodiment of the present invention described below has a fast operating speed and is capable of retaining data for a long period of time, and is therefore suitable for use as an LLC. Note that the OS memory of one embodiment of the present invention can also be applied to a FLC (Final Level cache).
  • SRAM can be used for the various caches.
  • OS memory can be suitably used for the LLC and main memory.
  • Such storage devices have high operating speeds and can retain data for long periods of time.
  • the configuration illustrated here does not use DRAM, which has traditionally been used as main memory, etc. Instead, the DRAM is replaced with an OS memory according to one embodiment of the present invention.
  • This configuration makes it possible to dramatically reduce power consumption (for example, to 1/100 or 1/1000 or less), and it is expected that by deploying information processing devices including computers, servers, etc. to which this configuration is applied all over the world, it will be possible to make a significant contribution to curbing global warming.
  • the semiconductor device of one embodiment of the present invention can be used in, for example, electronic components, mainframe computers, space equipment, data centers (also referred to as Data Centers: DCs), and various electronic devices.
  • DCs Data Centers
  • the electronic device of this embodiment may have a sensor (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • a sensor including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • the electronic device of this embodiment can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.
  • a function to display various information still images, videos, text images, etc.
  • a touch panel function a function to display a calendar, date or time, etc.
  • a function to execute various software (programs) a wireless communication function
  • a function to read out programs or data recorded on a recording medium etc.
  • FIG. 35A shows a perspective view of a substrate (mounting substrate 704) on which an electronic component 700 is mounted.
  • the electronic component 700 shown in FIG. 35A has a semiconductor device 710 in a mold 711. In FIG. 35A, some parts are omitted in order to show the inside of the electronic component 700.
  • the electronic component 700 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 710 via wires 714.
  • the electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.
  • the semiconductor device 710 also has a drive circuit layer 715 and a memory layer 716.
  • the memory layer 716 is configured by stacking a plurality of memory cell arrays.
  • the stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In the monolithic stacked configuration, each layer can be connected without using a through electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding.
  • TSV Through Silicon Via
  • a bonding technology such as Cu-Cu direct bonding.
  • the memory as an on-chip memory, it is possible to reduce the size of the connection wiring, for example, compared to technologies that use through electrodes such as TSVs, and therefore to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, making it possible to improve the memory bandwidth (also called memory bandwidth).
  • the memory cell arrays in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked.
  • OS transistors By forming the memory cell arrays in a monolithic stacked configuration, it is possible to improve one or both of the memory bandwidth and the memory access latency.
  • the bandwidth is the amount of data transferred per unit time
  • the access latency is the time from access to the start of data exchange.
  • Si transistors when Si transistors are used for the memory layer 716, it is difficult to form a monolithic stacked configuration compared to OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked configuration.
  • the semiconductor device 710 may also be referred to as a die.
  • a die refers to a chip piece obtained during the manufacturing process of a semiconductor chip, for example, by forming a circuit pattern on a disk-shaped substrate (also called a wafer) and cutting it into cubes.
  • Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN).
  • Si silicon
  • SiC silicon carbide
  • GaN gallium nitride
  • a die obtained from a silicon substrate also called a silicon wafer
  • a silicon die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.
  • Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module).
  • Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple semiconductor devices 710 provided on interposer 731.
  • Electronic component 730 shows an example in which semiconductor device 710 is used as a high bandwidth memory (HBM).
  • Semiconductor device 735 can be used in integrated circuits such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).
  • the package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate.
  • the interposer 731 may be, for example, a silicon interposer or a resin interposer.
  • the interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches.
  • the multiple wirings are provided in a single layer or multiple layers.
  • the interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732.
  • the interposer may be called a "rewiring substrate” or "intermediate substrate.”
  • a through electrode may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrode.
  • a TSV may be used as the through electrode.
  • the interposer on which the HBM is mounted is required to have fine, high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.
  • silicon interposers In addition, in SiP and MCM using silicon interposers, deterioration in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is unlikely to occur. In addition, since the surface of the silicon interposer is highly flat, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged horizontally on the interposer.
  • a composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithic stacking memory cell array.
  • a heat sink may be provided overlapping the electronic component 730.
  • electrodes 733 may be provided on the bottom of the package substrate 732.
  • FIG. 35B shows an example in which the electrodes 733 are formed from solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved.
  • the electrodes 733 may also be formed from conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.
  • the electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA.
  • mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).
  • Fig. 36A shows a perspective view of a large scale computer 5600.
  • the large scale computer 5600 shown in Fig. 36A has a rack 5610 housing a plurality of rack-mounted computers 5620.
  • the large scale computer 5600 may also be called a supercomputer.
  • the computer 5620 can have the configuration shown in the perspective view of FIG. 36B, for example.
  • the computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals.
  • a PC card 5621 is inserted into the slot 5631.
  • the PC card 5621 has connection terminals 5623, 5624, and 5625, each of which is connected to the motherboard 5630.
  • the PC card 5621 shown in FIG. 36C is an example of a processing board equipped with a CPU, a GPU, a storage device, and the like.
  • the PC card 5621 has a board 5622.
  • the board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629.
  • FIG. 36C illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, but for those semiconductor devices, the following description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 can be referred to.
  • connection terminal 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630.
  • An example of the standard for the connection terminal 5629 is PCIe.
  • connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621 or inputting signals. They can also be, for example, interfaces for outputting signals calculated by the PC card 5621.
  • Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface).
  • Examples of the standards for each include HDMI (registered trademark).
  • the semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.
  • the semiconductor device 5627 has multiple terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622.
  • Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU.
  • the electronic component 730 can be used as the semiconductor device 5627.
  • the semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method.
  • An example of the semiconductor device 5628 is a memory device.
  • the electronic component 700 can be used as the semiconductor device 5628.
  • the mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for artificial intelligence learning and inference, for example.
  • the semiconductor device of one embodiment of the present invention can be suitably used in space equipment.
  • the semiconductor device of one embodiment of the present invention includes an OS transistor.
  • the OS transistor has small changes in electrical characteristics due to radiation exposure.
  • the OS transistor has high resistance to radiation and can be suitably used in an environment where radiation may be incident.
  • the OS transistor can be suitably used when used in outer space.
  • the OS transistor can be used as a transistor constituting a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe.
  • Examples of radiation include X-rays and neutron rays.
  • outer space refers to an altitude of 100 km or higher, for example, and the outer space described in this specification may include one or more of the thermosphere, the mesosphere, and the stratosphere.
  • Figure 36D shows an artificial satellite 6800 as an example of space equipment.
  • the artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Figure 36D also shows a planet 6804 in space.
  • the secondary battery 6805 may be provided with a battery management system (also called BMS) or a battery control circuit.
  • BMS battery management system
  • the use of OS transistors in the battery management system or battery control circuit described above is preferable because it consumes low power and has high reliability even in space.
  • outer space is an environment with radiation levels 100 times higher than on Earth.
  • radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, meson rays, etc.
  • the solar panel 6802 When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where the solar panel is not irradiated with sunlight, or where the amount of sunlight irradiating the solar panel is small, the amount of power generated is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is advisable to provide the satellite 6800 with a secondary battery 6805. Note that the solar panel may be called a solar cell module.
  • the artificial satellite 6800 can generate a signal.
  • the signal is transmitted via the antenna 6803, and can be received, for example, by a receiver installed on the ground or by another artificial satellite.
  • the position of the receiver that received the signal can be measured.
  • the artificial satellite 6800 can constitute a satellite positioning system.
  • the control device 6807 has a function of controlling the artificial satellite 6800.
  • the control device 6807 is configured using, for example, one or more of a CPU, a GPU, and a storage device.
  • a semiconductor device including an OS transistor which is one embodiment of the present invention, is preferably used for the control device 6807.
  • the OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. In other words, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.
  • the artificial satellite 6800 can also be configured to have a sensor.
  • the artificial satellite 6800 can have the function of detecting sunlight reflected off an object on the ground.
  • the artificial satellite 6800 can have a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. From the above, the artificial satellite 6800 can have the function of, for example, an earth observation satellite.
  • an artificial satellite is illustrated as an example of space equipment, but the present invention is not limited to this.
  • the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, and a space probe.
  • OS transistors As explained above, compared to Si transistors, OS transistors have the advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance.
  • the semiconductor device can be suitably used in a storage system applied to a data center or the like.
  • the data center is required to perform long-term management of data, such as ensuring the immutability of the data.
  • it is necessary to increase the size of the building, for example, by installing storage and servers for storing a huge amount of data, by securing a stable power source for holding the data, or by securing cooling equipment required for holding the data.
  • a semiconductor device By using a semiconductor device according to one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and to miniaturize the semiconductor device that stores the data. This makes it possible to miniaturize the storage system, miniaturize the power source for storing data, and reduce the scale of cooling equipment. This makes it possible to save space in the data center.
  • the semiconductor device of one embodiment of the present invention consumes less power, and therefore heat generation from the circuit can be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.
  • Figure 36E shows a storage system applicable to a data center.
  • the storage system 7010 shown in Figure 36E has multiple servers 7001sb as hosts 7001 (illustrated as Host computer). It also has multiple storage devices 7003md as storage 7003 (illustrated as Storage).
  • the host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).
  • SAN Storage Area Network
  • the host 7001 corresponds to a computer that accesses data stored in the storage 7003.
  • the hosts 7001 may be connected to each other via a network.
  • Storage 7003 uses flash memory to reduce data access speed, i.e. the time required to store and output data, but this time is significantly longer than the time required by DRAM, which can be used as cache memory within the storage.
  • storage systems typically provide cache memory within the storage to reduce the time required to store and output data.
  • the above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.
  • OS transistors as transistors for storing data in the cache memory, which hold a potential corresponding to the data
  • the frequency of refreshing can be reduced and power consumption can be reduced.
  • miniaturization is possible.
  • the semiconductor device of one embodiment of the present invention can be reduced by applying the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, mainframe computers, space equipment, data centers, and electronic devices. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can also reduce emissions of greenhouse gases such as carbon dioxide (CO 2 ). In addition, the semiconductor device of one embodiment of the present invention is effective as a measure against global warming because of its low power consumption.
  • CO 2 greenhouse gases

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  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
PCT/IB2024/057484 2023-08-09 2024-08-02 半導体装置、及び半導体装置の作製方法 Pending WO2025032444A1 (ja)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP2017168764A (ja) * 2016-03-18 2017-09-21 株式会社ジャパンディスプレイ 半導体装置
JP2022049605A (ja) * 2020-09-16 2022-03-29 キオクシア株式会社 半導体装置及び半導体記憶装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP2017168764A (ja) * 2016-03-18 2017-09-21 株式会社ジャパンディスプレイ 半導体装置
JP2022049605A (ja) * 2020-09-16 2022-03-29 キオクシア株式会社 半導体装置及び半導体記憶装置

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