WO2025032416A1 - 半導体装置、表示装置、及び半導体装置の作製方法 - Google Patents

半導体装置、表示装置、及び半導体装置の作製方法 Download PDF

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Publication number
WO2025032416A1
WO2025032416A1 PCT/IB2024/057293 IB2024057293W WO2025032416A1 WO 2025032416 A1 WO2025032416 A1 WO 2025032416A1 IB 2024057293 W IB2024057293 W IB 2024057293W WO 2025032416 A1 WO2025032416 A1 WO 2025032416A1
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Prior art keywords
insulating layer
layer
conductive layer
transistor
insulating
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PCT/IB2024/057293
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English (en)
French (fr)
Japanese (ja)
Inventor
佐藤学
土橋正佳
神長正美
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to KR1020267000272A priority Critical patent/KR20260045778A/ko
Priority to CN202480044815.1A priority patent/CN121444616A/zh
Priority to JP2025538904A priority patent/JPWO2025032416A1/ja
Publication of WO2025032416A1 publication Critical patent/WO2025032416A1/ja
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/35—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being liquid crystals

Definitions

  • One aspect of the present invention relates to a transistor.
  • One aspect of the present invention relates to a semiconductor device having a transistor.
  • One aspect of the present invention relates to a display device having a transistor.
  • One aspect of the present invention relates to a method for manufacturing a semiconductor device having a transistor.
  • one embodiment of the present invention is not limited to the above technical field.
  • Examples of technical fields of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, lighting devices, input devices, input/output devices, electronic devices having them, driving methods thereof, or manufacturing methods thereof.
  • a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.
  • One type of display device is a liquid crystal display device that uses liquid crystal elements as the display element.
  • liquid crystal display devices that uses liquid crystal elements as the display element.
  • active matrix type liquid crystal display devices in which pixel electrodes are arranged in a matrix and switching elements are connected to each pixel electrode, are used in a variety of devices such as smartphones, tablet terminals, monitors, televisions, and digital signage.
  • LCD devices transmissive and reflective.
  • Patent Document 1 discloses a liquid crystal display device that uses transistors with metal oxide in the channel formation region to increase the aperture ratio.
  • one object of one embodiment of the present invention is to provide a transistor that can be miniaturized. Another object is to provide a transistor with good electrical characteristics. Another object is to provide a transistor with a short channel length. Another object is to provide a transistor that occupies a small area.
  • Another object of one embodiment of the present invention is to provide a liquid crystal display device with a high aperture ratio.
  • an object of the present invention is to provide a high-definition liquid crystal display device.
  • an object of the present invention is to provide a liquid crystal display device with low power consumption.
  • an object of the present invention is to provide a liquid crystal display device that can be driven at high speed.
  • an object of the present invention is to provide a display device with high display quality.
  • One aspect of the present invention is a semiconductor device having a first transistor, a second transistor, a first insulating layer, and a second insulating layer, the first transistor having a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a third insulating layer, a fourth insulating layer, and a semiconductor layer, the second transistor having a first conductive layer, a fifth conductive layer, a sixth conductive layer, a fourth conductive layer, a fifth insulating layer, a fourth insulating layer, and a semiconductor layer, the first insulating layer having a first region and a second region separated from the first region, and the second insulating layer the first conductive layer has a fifth region and a sixth region separated from the fifth region, the first region, the second conductive layer, the third region, and the third conductive layer are provided on the fifth region in a superimposed manner in this order, the second region, the fifth conductive layer, the fourth region, and the sixth conductive layer are
  • the fifth insulating layer is provided in contact with a side surface of the second region, a side surface of the fifth conductive layer, a side surface of the fourth region, and a side surface of the sixth conductive layer;
  • the semiconductor layer is provided in contact with an upper surface of the first conductive layer between the fifth region and the sixth region, a side surface of the third insulating layer, a side surface of the fifth insulating layer, an upper surface of the third conductive layer, and an upper surface of the sixth conductive layer;
  • the fourth insulating layer is provided in contact with an upper surface and a side surface of the semiconductor layer, an upper surface and a side surface of the first conductive layer, an upper surface and a side surface of the third conductive layer, and an upper surface and a side surface of the sixth conductive layer;
  • the conductive layer is provided in contact with the upper surface of the fourth insulating layer, and in the first transistor, one surface of the part of the semiconductor layer faces a part of the fourth conductive layer through a part of the fourth insulating
  • the semiconductor layer contains a metal oxide
  • the first insulating layer, the second insulating layer, the third insulating layer, and the fifth insulating layer each contain one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide.
  • the first insulating layer has a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer
  • the second insulating layer has a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer
  • the sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer each have one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon oxynitride
  • the seventh insulating layer and the tenth insulating layer each preferably have one or both of silicon oxide and silicon oxynitride.
  • Another embodiment of the present invention is a display device that includes the above-mentioned semiconductor device, a first liquid crystal element, and a second liquid crystal element, in which the first liquid crystal element has a third conductive layer, liquid crystal, and a seventh conductive layer, and the second liquid crystal element has a sixth conductive layer, liquid crystal, and a seventh conductive layer, in which the liquid crystal is provided on the third conductive layer or the sixth conductive layer, and the seventh conductive layer is provided on the liquid crystal.
  • one aspect of the present invention includes a first transistor, a second transistor, a first insulating layer, and a second insulating layer
  • the first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a third insulating layer, a fourth insulating layer, and a semiconductor layer
  • the second transistor includes a first conductive layer, a fourth conductive layer, a third conductive layer, a fifth insulating layer, a fourth insulating layer, and a semiconductor layer
  • the first insulating layer includes a first region and a second region separated from the first region.
  • the second insulating layer has a third region and a fourth region spaced apart from the third region
  • the first conductive layer has a fifth region and a sixth region spaced apart from the fifth region
  • the first region, the second conductive layer, and the third region are provided on the fifth region in this order, overlapping each other
  • the second region, the fourth conductive layer, and the fourth region are provided on the sixth region, overlapping each other in this order
  • the third insulating layer has a side surface of the first region, a side surface of the second conductive layer, and a side surface of the third region.
  • the semiconductor device is provided in contact with the first surface of the semiconductor layer, the fifth insulating layer is provided in contact with the side of the second region, the side of the fourth conductive layer, and the side of the fourth region, the semiconductor layer is provided in contact with the top surface of the first conductive layer between the fifth region and the sixth region, the side of the third insulating layer, the side of the fifth insulating layer, the top surface of a portion of the second insulating layer, and the top surface of another portion of the second insulating layer, the fourth insulating layer is provided in contact with the top surface of the semiconductor layer, and the third conductive layer is provided in contact with the top surface of the fourth insulating layer, and in the first transistor, one surface of the part of the semiconductor layer faces a part of the third conductive layer through a part of the fourth insulating layer, and the other surface of the part of the semiconductor layer faces the second conductive layer through the third insulating layer, and in the second transistor, one surface of the other part of the semiconductor layer faces the other part of the third
  • the semiconductor layer contains a metal oxide
  • the first insulating layer, the second insulating layer, the third insulating layer, and the fifth insulating layer each contain one or more of silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide.
  • the first insulating layer has a sixth insulating layer, a seventh insulating layer on the sixth insulating layer, and an eighth insulating layer on the seventh insulating layer
  • the second insulating layer has a ninth insulating layer, a tenth insulating layer on the ninth insulating layer, and an eleventh insulating layer on the tenth insulating layer
  • the sixth insulating layer, the eighth insulating layer, the ninth insulating layer, and the eleventh insulating layer each have one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon oxynitride
  • the seventh insulating layer and the tenth insulating layer each preferably have one or both of silicon oxide and silicon oxynitride.
  • Another embodiment of the present invention is a display device that includes the above-described semiconductor device and a liquid crystal element, where the liquid crystal element includes a semiconductor layer, a liquid crystal, and a fifth conductive layer, the liquid crystal is provided on the semiconductor layer, and the fifth conductive layer is provided on the liquid crystal.
  • one embodiment of the present invention includes forming a first conductive layer, forming a first insulating film and a first conductive film in this order on the first conductive layer, processing the first conductive film to form a second conductive layer in a region overlapping with the first conductive layer, forming a second insulating film and a second conductive film in this order on the first insulating film and on the second conductive layer, processing the second conductive film to form a third conductive layer having a region overlapping with the first conductive layer and the second conductive layer, and forming the first insulating film, the second conductive layer, the second insulating film, and a third conductive layer is removed to form an opening reaching the first conductive layer, and a first insulating layer is formed from the first insulating film, a fourth conductive layer and a fifth conductive layer are formed from the second conductive layer, a second insulating layer is formed from the second insulating film, and a sixth conductive layer and a seventh conductive layer are formed from
  • a third insulating film in contact with a side surface of the fifth conductive layer in the opening, a side surface of the sixth conductive layer in the opening, a side surface of the sixth conductive layer in the opening, a side surface of the seventh conductive layer in the opening, a top surface of the sixth conductive layer, and a top surface of the seventh conductive layer; a part of the third insulating film is removed to form a third insulating layer in contact with one side surface of the first insulating layer in the opening, a side surface of the fourth conductive layer in the opening, one side surface of the second insulating layer in the opening, and a side surface of the sixth conductive layer in the opening; and a fourth insulating layer in contact with the other side surface of the first insulating layer in the opening, the side surface of the fifth conductive layer in the opening, the other side surface of the second insulating layer in the opening, and a side surface of the seventh conductive layer in the opening; and a semiconductor layer in contact with the top surface and side surfaces of
  • One aspect of the present invention can provide a transistor that can be miniaturized. Or, a transistor with good electrical characteristics can be provided. Or, a transistor with a short channel length can be provided. Or, a transistor with a small occupying area can be provided.
  • one embodiment of the present invention can provide a small-sized semiconductor device having fine transistors.
  • a highly integrated semiconductor device having fine transistors can be provided.
  • a liquid crystal display device with a high aperture ratio can be provided.
  • a high-definition liquid crystal display device can be provided.
  • a liquid crystal display device with low power consumption can be provided.
  • a liquid crystal display device capable of high-speed operation can be provided.
  • a display device with high display quality can be provided.
  • a transistor, a semiconductor device, a display device, an electronic device, and a manufacturing method thereof each having a novel structure can be provided.
  • a highly reliable transistor, a semiconductor device, a display device, an electronic device, and a manufacturing method thereof can be provided.
  • at least one of the problems of the prior art can be alleviated.
  • FIG 1A is a plan view of an example of a semiconductor device
  • FIG 1B is a cross-sectional view of the example of the semiconductor device
  • 2A and 2B are cross-sectional views showing an example of a semiconductor device
  • FIG 2C is a circuit diagram for explaining the semiconductor device.
  • 3A and 3B are plan views showing an example of a semiconductor device.
  • 4A and 4B are plan views showing an example of a semiconductor device.
  • 5A and 5B are cross-sectional views showing an example of a semiconductor device.
  • 6A and 6B are cross-sectional views showing an example of a semiconductor device.
  • 7A and 7B are cross-sectional views showing an example of a semiconductor device.
  • 8A and 8B are cross-sectional views showing an example of a semiconductor device.
  • FIG. 9A is a plan view showing an example of a display device
  • FIG 9B is a cross-sectional view showing the example of the display device.
  • 10A is a plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 11A is a plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 12A is a plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 12B to 12D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device
  • 13A is a plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 13B to 13D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • FIGS. 14A is a plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 14B to 14D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 15A is a plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 15B to 15D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 16A is a plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 16B to 16D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 17A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and FIGS.
  • FIGS. 18B to 18D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 18A is a plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 18B to 18D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • FIG. 19 shows an example of the configuration of a display device.
  • FIG. 20 shows an example of the configuration of a display device.
  • Fig. 21A is a block diagram of a display device, and Fig. 21B and Fig. 21C are circuit diagrams of the display device. 22A, 22C, and 22D are circuit diagrams of the display device, and Fig. 22B is a timing chart.
  • FIG. 23 is a block diagram of the touch panel module.
  • 24A to 24C show configuration examples of a touch panel module.
  • 25A to 25F show configuration examples of electronic devices.
  • connection includes “electrical connection.”
  • a and B are electrically connected means that, among A and B that are connected without an insulator (A and B that are connected via a conductor or semiconductor, or A and B that are in contact), there is a time when an exchange of electrical signals or an interaction of potential occurs between A and B during circuit operation. In other words, even if there is a time when an exchange of electrical signals or an interaction of potential does not occur between A and B during circuit operation, if there is a time when an exchange of electrical signals or an interaction of potential occurs between A and B, it can be said that "A and B are electrically connected.”
  • Electrical connection includes a connection that does not involve a circuit element (e.g., a transistor, but excluding wiring) (direct connection), and a connection that involves one or more circuit elements (indirect connection).
  • a circuit element e.g., a transistor, but excluding wiring
  • indirect connection includes a connection that involves one or more circuit elements
  • Examples of "A and B being electrically connected” include when A and B are connected without a circuit element, and when A and B are connected via the source and drain of one or more transistors. However, this is subject to the premise that there is a timing when an electrical signal is exchanged or potential interaction occurs between A and B.
  • a and B are connected via an insulator and therefore it cannot be said that "A and B are electrically connected" is when there is a dielectric of a capacitive element, a gate insulating film of a transistor, etc. between A and B.
  • a and B are connected without an insulator, but there is no timing when an electrical signal is sent or received between A and B, or when potential interaction occurs between A and B, so it cannot be said that "A and B are electrically connected.” Examples include when a potential V is supplied to the path from A to B from a power source, signal source, etc. (however, this does not include when potential V is supplied via a circuit element), or when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, but there is no timing when both transistor TrP and transistor TrQ are on at the same time.
  • the top surface shapes roughly match means that at least a portion of the contours of the stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, there are also cases where the contours do not overlap, and the upper layer is located inside the lower layer, or outside the lower layer, and in these cases, it may also be said that "the top surface shapes roughly match.”
  • film and “layer” can be interchanged.
  • conductive layer and “insulating layer” can be interchanged with the terms “conductive film” and “insulating film”.
  • a display panel which is one aspect of a display device, has the function of displaying (outputting) images, etc. on a display surface. Therefore, a display panel is one aspect of an output device.
  • a display panel having a connector such as an FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package) attached to the substrate, or an IC mounted on the substrate using a method such as COG (Chip On Glass), may be referred to as a display panel module, display module, or simply a display panel.
  • a touch panel which is one aspect of a display device, has a function of displaying an image or the like on a display surface, and a function as a touch sensor that detects when a detectable object such as a finger or stylus touches, presses, or approaches the display surface. Therefore, a touch panel is one aspect of an input/output device.
  • a touch panel can also be called, for example, a display panel (or display device) with a touch sensor or a display panel (or display device) with a touch sensor function.
  • a touch panel can also be configured to have a display panel and a touch sensor panel.
  • the touch panel can be configured to have a touch sensor function inside or on the surface of the display panel.
  • a touch panel substrate on which a connector or IC is mounted may be referred to as a touch panel module, display module, or simply a touch panel.
  • a semiconductor device has a first transistor, a second transistor, a first insulating layer, and a second insulating layer.
  • the first transistor and the second transistor are vertical transistors in which the source electrode and the drain electrode are overlapped at different heights relative to the substrate surface, and the drain current flows in a direction approximately perpendicular to the substrate surface.
  • the gate electrode of the first transistor (first gate electrode) and the gate electrode of the second transistor (first gate electrode) are provided between the source electrode and the drain electrode, respectively, overlapping therewith. That is, the first transistor and the second transistor each have a configuration in which one of the source electrode or the drain electrode, the gate electrode, and the other of the source electrode or the drain electrode are provided overlapping in this order.
  • a first insulating layer is provided between the gate electrode and one of the source electrode or drain electrode of each of the first transistor and the second transistor, and a second insulating layer is provided between the gate electrode and the other of the source electrode or drain electrode.
  • the first transistor and the second transistor share a conductive layer that serves as one of the source electrode and the drain electrode.
  • Other components of the first transistor (gate electrode, the other of the source electrode or the drain electrode, etc.) are provided on a first region of the conductive layer, and other components of the second transistor (gate electrode, the other of the source electrode or the drain electrode, etc.) are provided on a second region separated from the first region.
  • the first insulating layer has a third region overlapping with the first region, and a fourth region separated from the third region and overlapping with the second region.
  • the second insulating layer has a fifth region overlapping with the first region, and a sixth region separated from the fifth region and overlapping with the second region.
  • a third region, a gate electrode of the first transistor, a fifth region, and the other of the source electrode or drain electrode of the first transistor are provided on a first region so as to overlap
  • a fourth region, a gate electrode of the second transistor, a sixth region, and the other of the source electrode or drain electrode of the second transistor are provided on a second region so as to overlap.
  • the first region functions as one of the source electrode or drain electrode of the first transistor
  • the second region functions as one of the source electrode or drain electrode of the second transistor. It can be said that the first transistor and the second transistor are provided opposite each other with the midpoint between the first region and the second region as an axis.
  • the third region on the first region, the gate electrode of the first transistor, the fifth region, and the side surface (first side surface) of the other of the source electrode or drain electrode of the first transistor facing the second transistor are generally aligned.
  • the fourth region on the second region, the gate electrode of the second transistor, the sixth region, and the side surface (second side surface) of the other of the source electrode or drain electrode of the second transistor facing the first transistor are generally aligned.
  • the gate insulation layer (first gate insulation layer) of the first transistor is provided in contact with the first side surface.
  • the gate insulation layer (first gate insulation layer) of the second transistor is provided in contact with the second side surface. Note that the gate insulation layer of the first transistor and the gate insulation layer of the second transistor may be a continuous film.
  • the first transistor and the second transistor share a semiconductor layer having their respective channel formation regions.
  • the semiconductor layer is provided to cover the conductive layer that becomes one of the source electrodes or drain electrodes of each transistor, the gate insulating layer of each transistor, and the other of the source electrode or drain electrode of each transistor.
  • the semiconductor layer contacts the top surface of the conductive layer that becomes one of the source electrodes or drain electrodes of each transistor (the top surface in the region between the first region and the second region), the side surface of the gate insulating layer of each transistor, and the top surface of the other of the source electrode or drain electrode of each transistor.
  • the semiconductor layer has a region facing the gate electrode of the first transistor via the gate insulating layer of the first transistor, and a region facing the gate electrode of the second transistor via the gate insulating layer of the second transistor.
  • the former functions as the channel formation region of the first transistor, and the latter functions as the channel formation region of the second transistor.
  • the region in contact with the source electrode or drain electrode of the first transistor functions as the source region and drain region of the first transistor, and the region in contact with the source electrode or drain electrode of the second transistor functions as the source region and drain region of the second transistor.
  • the first transistor and the second transistor each have a source electrode and a drain electrode that are provided at different heights relative to the substrate surface, and the drain current flows vertically (approximately perpendicular to the substrate surface) through the channel formation region located between them. Therefore, the area occupied by the transistor on the substrate surface can be reduced, for example, compared to a planar type transistor.
  • the first transistor and the second transistor may each have a backgate insulating layer (second gate insulating layer) and a backgate electrode (second gate electrode).
  • the insulating layer that becomes the backgate insulating layer and the conductive layer that becomes the backgate electrode are provided in this order to cover the semiconductor layer.
  • the insulating layer that becomes the backgate insulating layer has an area that contacts the upper surface and side surface of the semiconductor layer and the other upper surface of the source electrode or drain electrode of each transistor. Of the area of the insulating layer that overlaps with the semiconductor layer, the part located on the first side surface side functions as the backgate insulating layer of the first transistor, and the part located on the second side surface side functions as the backgate insulating layer of the second transistor.
  • the conductive layer that becomes the backgate electrode contacts the upper surface of the insulating layer that becomes the backgate insulating layer.
  • the part located on the first side surface side functions as the backgate electrode of the first transistor
  • the part located on the second side surface side functions as the backgate electrode of the second transistor.
  • the potential of the back gate electrode can be set to ground potential or any potential, thereby fixing the potential of the region of the semiconductor layer on the back gate electrode side. Therefore, the threshold voltage of the transistor can be made normally off more than in the case of a configuration having only one gate electrode. In addition, the variation in the electrical characteristics of the transistor can be suppressed.
  • the semiconductor device of one embodiment of the present invention has two vertical transistors (a first transistor and a second transistor), and these have a configuration in which other components (a gate electrode, the other of the source electrode or the drain electrode, a gate insulating layer) are provided facing each other so as to be sandwiched between some common components (one of the source electrode or the drain electrode, a semiconductor layer). Therefore, by narrowing the gap between these two facing vertical transistors, it is possible to achieve high integration of the transistors in the substrate surface.
  • the two facing transistors share a conductive layer that serves as one of the source electrode or the drain electrode, so that the semiconductor device as a whole can be made smaller than when each transistor has the conductive layer individually.
  • a line-shaped opening is provided in a layer (e.g., three layers of an insulating layer, a conductive layer, and an insulating layer) stacked on a conductive layer using a conventional exposure device for mass production of flat panel displays (minimum line width of about 1.5 ⁇ m or 1.25 ⁇ m) and a vertical transistor is formed using the sidewall depth direction of the opening as the channel length direction.
  • a conventional exposure device for mass production of flat panel displays minimum line width of about 1.5 ⁇ m or 1.25 ⁇ m
  • a vertical transistor is formed using the sidewall depth direction of the opening as the channel length direction.
  • two vertical transistors whose channel length direction is the depth direction of the opposing sidewalls of the opening can be formed by simply forming one opening in the layer stacked on the conductive layer. Therefore, the distance between the two vertical transistors can be made extremely narrow. For example, a resolution of 2000 ppi or more can be achieved by applying a semiconductor device having the two vertical transistors to a display device.
  • FIG. 1A shows a plan view (also referred to as a top view) of the semiconductor device 100.
  • FIG. 1B shows a cross-sectional view taken along dashed dotted line A1-A2 shown in FIG. 1A.
  • FIG. 2A shows a cross-sectional view taken along dashed dotted line B1-B2 shown in FIG. 1A.
  • FIG. 2B shows a cross-sectional view taken along dashed dotted line C1-C2 shown in FIG. 1A.
  • FIG. 2C shows an equivalent circuit diagram of the semiconductor device 100.
  • FIG. 1A omits some of the components of the semiconductor device 100 (insulating layers, etc.). As with FIG. 1A, some of the components may be omitted from the plan views of the semiconductor device in the following drawings.
  • the semiconductor device 100 includes a transistor 10_1, a transistor 10_2, an insulating layer 110a, and an insulating layer 110b.
  • the semiconductor device 100 is provided on a substrate 102.
  • the transistors 10_1 and 10_2 share some components and are provided opposite each other on the substrate 102.
  • the transistors 10_1 and 10_2 can be said to have the same structure.
  • the transistors 10_1 and 10_2 can be formed at the same time using the same material and through the same process.
  • Transistor 10_1 has conductive layer 112a, conductive layer 112b1, conductive layer 116_1, insulating layer 110s1, semiconductor layer 108, insulating layer 106, and conductive layer 104.
  • a part of conductive layer 112a functions as one of a source electrode and a drain electrode.
  • Conductive layer 112b1 functions as the other of a source electrode and a drain electrode.
  • Conductive layer 116_1 functions as a gate electrode (first gate electrode).
  • Insulating layer 110s1 functions as a gate insulating layer (first gate insulating layer).
  • a part of semiconductor layer 108 functions as a channel formation region.
  • a part of insulating layer 106 functions as a back gate insulating layer (second gate insulating layer).
  • a part of conductive layer 104 functions as a back gate electrode (second gate electrode).
  • the transistor 10_2 has a conductive layer 112a, a conductive layer 112b2, a conductive layer 116_2, an insulating layer 110s2, a semiconductor layer 108, an insulating layer 106, and a conductive layer 104.
  • another part of the conductive layer 112a functions as one of a source electrode and a drain electrode.
  • the conductive layer 112b2 functions as the other of the source electrode and the drain electrode.
  • the conductive layer 116_2 functions as a gate electrode (first gate electrode).
  • the insulating layer 110s2 functions as a gate insulating layer (first gate insulating layer).
  • Another part of the semiconductor layer 108 functions as a channel formation region.
  • Another part of the insulating layer 106 functions as a back gate insulating layer (second gate insulating layer).
  • Another part of the conductive layer 104 functions as a back gate electrode (second gate electrode).
  • Each layer constituting transistor 10_1 and transistor 10_2 can have a single layer structure or a stacked structure.
  • Transistor 10_1 and transistor 10_2 share the following components: a conductive layer (conductive layer 112a) that functions as one of the source and drain electrodes, a semiconductor layer (semiconductor layer 108) having a channel formation region, an insulating layer (insulating layer 106) that functions as the backgate insulating layer, and a conductive layer (conductive layer 104) that functions as the backgate electrode.
  • the other components are provided separately for transistor 10_1 and transistor 10_2.
  • transistor 10_1 and transistor 10_2 may be configured without a backgate electrode and a backgate insulating layer.
  • An insulating layer 195 is provided to cover the transistors 10_1 and 10_2.
  • the insulating layer 195 functions as a protective layer for the transistors 10_1 and 10_2.
  • the configuration of transistor 10_1 and transistor 10_2 will be described.
  • the conductive layer 112a is provided on the substrate 102.
  • FIG. 3A shows a plan view showing only the conductive layer 112a.
  • the conductive layer 112a is provided extending in a direction parallel to the dashed dotted line A1-A2.
  • the conductive layer 112a has a shape in which a part of it protrudes to the B1 side.
  • FIG. 1A, FIG. 3A, etc. the intersection of the dashed dotted line A1-A2 and the dashed dotted line B1-B2 is shown to be located at the center of the protrusion.
  • the protruding portion of the conductive layer 112a is a portion that overlaps with the channel formation regions of the transistors 10_1 and 10_2. In other words, the conductive layers 112b1 and 112b2 are provided overlapping the protruding portions.
  • Insulating layer 110a has a three-layer structure of insulating layer 110a1, insulating layer 110a2 on insulating layer 110a1, and insulating layer 110a3 on insulating layer 110a2. Insulating layer 110a has an area in contact with the upper and side surfaces of conductive layer 112a and the upper surface of substrate 102. It can also be said that insulating layer 110a is provided so as to cover the upper and side surfaces of conductive layer 112a.
  • a conductive layer 116_1 is provided on a part of the insulating layer 110a, and a conductive layer 116_2 is provided on the other part of the insulating layer 110a.
  • FIG. 3B shows a plan view of the conductive layer 116_1 and the conductive layer 116_2 superimposed on the conductive layer 112a.
  • the conductive layer 116_1 extends in a direction parallel to the dashed line B1-B2 and is provided so as to overlap with the region on the A1 side of the protruding portion of the conductive layer 112a.
  • the conductive layer 116_1 has a region that overlaps with a part of the conductive layer 112a via the insulating layer 110a.
  • the conductive layer 116_2 extends in a direction parallel to the dashed line B1-B2 and is provided so as to overlap with the region on the A2 side of the protruding portion of the conductive layer 112a.
  • the conductive layer 116_2 has a region that overlaps with the other part of the conductive layer 112a via the insulating layer 110a.
  • a part of the insulating layer 110b is provided on a part of the insulating layer 110a and the conductive layer 116_1, and another part of the insulating layer 110b is provided on the other part of the insulating layer 110a and the conductive layer 116_2.
  • the insulating layer 110b has a three-layer structure of an insulating layer 110b3, an insulating layer 110b2 on the insulating layer 110b3, and an insulating layer 110b1 on the insulating layer 110b2.
  • a part of the insulating layer 110b has an area that contacts the upper surface and side surface of the conductive layer 116_1 and the upper surface of a part of the insulating layer 110a.
  • a part of the insulating layer 110b is provided so as to cover the upper surface and side surface of the conductive layer 116_1. It can also be said that the conductive layer 116_1 is sandwiched between a part of the insulating layer 110a and a part of the insulating layer 110b. Similarly, the other part of the insulating layer 110b has an area that contacts the top surface and side surfaces of the conductive layer 116_2 and the top surface of the other part of the insulating layer 110a. It can also be said that the other part of the insulating layer 110b is provided so as to cover the top surface and side surfaces of the conductive layer 116_2. It can also be said that the conductive layer 116_2 is sandwiched between the other part of the insulating layer 110a and the other part of the insulating layer 110b.
  • insulating layer 110a and insulating layer 110b may be collectively referred to as insulating layer 110.
  • a conductive layer 112b1 is provided on a portion of the insulating layer 110b, and a conductive layer 112b2 is provided on another portion of the insulating layer 110b.
  • Figure 4A shows a plan view in which the conductive layer 112b1 and the conductive layer 112b2 are superimposed on the plan view shown in Figure 3B.
  • Conductive layer 112b1 extends toward the A1 side in a direction parallel to the dashed dotted line A1-A2 direction, and has an area overlapping with a part of conductive layer 112a and conductive layer 116_1.
  • the end of conductive layer 112b1 on the dashed dotted line B1-B2 side roughly coincides with the end of conductive layer 116_1 on the dashed dotted line B1-B2 side.
  • Conductive layer 112b1 has an area overlapping with conductive layer 116_1 via a part of insulating layer 110b.
  • Conductive layer 112b1 also has an area overlapping with a part of conductive layer 112a via a part of insulating layer 110 and conductive layer 116_1.
  • the part of insulating layer 110 and conductive layer 116_1 have an area sandwiched between a part of conductive layer 112a and conductive layer 112b1.
  • the side surfaces (hereinafter also referred to as the first side surfaces) of a portion of the insulating layer 110, the conductive layer 116_1, and the conductive layer 112b1 on the dashed dotted line B1-B2 side are generally aligned.
  • the conductive layer 112b2 extends toward the A2 side in a direction parallel to the dashed dotted line A1-A2 direction, and has an area overlapping with another part of the conductive layer 112a and the conductive layer 116_2.
  • the end of the conductive layer 112b2 on the dashed dotted line B1-B2 side roughly coincides with the end of the conductive layer 116_2 on the dashed dotted line B1-B2 side.
  • the conductive layer 112b2 has an area overlapping with the conductive layer 116_2 via another part of the insulating layer 110b.
  • the conductive layer 112b2 also has an area overlapping with another part of the conductive layer 112a via the other part of the insulating layer 110 and the conductive layer 116_2. It can also be said that the other part of the insulating layer 110 and the conductive layer 116_2 have an area sandwiched between the other part of the conductive layer 112a and the conductive layer 112b2.
  • the side surfaces (hereinafter also referred to as second side surfaces) of the other part of the insulating layer 110, the conductive layer 116_2, and the conductive layer 112b2 on the dashed dotted line B1-B2 side are generally aligned.
  • the conductive layer 112b1 is disposed so as to overlap only the protruding portion of the conductive layer 112a. In other words, it is preferable that the conductive layer 112b1 does not overlap with the region other than the protruding portion (the region extending in the direction of the dashed line A1-A2 of the conductive layer 112a). Since the insulating layer 110 is provided between the conductive layer 112a and the conductive layer 112b1, the region sandwiched between the conductive layer 112a and the conductive layer 112b1 can function as a parasitic capacitance of the semiconductor device 100. Therefore, it is preferable that the area of the region is as small as possible.
  • the conductive layer 112b1 By configuring the conductive layer 112b1 so as to overlap only the protruding portion of the conductive layer 112a, the above-mentioned parasitic capacitance can be reduced. The same applies to the arrangement of the conductive layer 112b2 with respect to the conductive layer 112a.
  • first side and the second side can also be said to correspond to the side walls of the opening 143 provided so as to reach the conductive layer 112a with respect to the insulating layer 110, the conductive layer that becomes the conductive layer 116_1 and the conductive layer 116_2, and the conductive layer that becomes the conductive layer 112b1 and the conductive layer 112b2, as shown in FIG. 1B.
  • the insulating layer 110s1 is provided in contact with the first side surface.
  • the insulating layer 110s1 has an area in contact with a part of the side surface of the insulating layer 110, the side surface of the conductive layer 116_1, and the side surface of the conductive layer 112b1.
  • the insulating layer 110s2 is provided in contact with the second side surface.
  • the insulating layer 110s2 has an area in contact with another part of the side surface of the insulating layer 110, the side surface of the conductive layer 116_2, and the side surface of the conductive layer 112b2.
  • the upper ends of the insulating layer 110s1 and the insulating layer 110s2 have a curved shape.
  • the insulating layer 110s1 and the insulating layer 110s2 may be called a sidewall, a sidewall insulating layer, or a sidewall protective layer.
  • the insulating layer 110s1 and the insulating layer 110s2 may be considered as one insulating layer.
  • FIG. 4B shows a plan view in which the semiconductor layer 108 is superimposed on the plan view shown in FIG. 4A.
  • a part of the semiconductor layer 108 overlaps with a part of the conductive layer 112a, the conductive layer 116_1, and the conductive layer 112b1, and another part of the semiconductor layer 108 overlaps with another part of the conductive layer 112a, the conductive layer 116_2, and the conductive layer 112b2.
  • the semiconductor layer 108 has a region in contact with the upper surface of the conductive layer 112a, the side of the insulating layer 110s1, the curved portion of the insulating layer 110s1, the side of the insulating layer 110s2, and the curved portion of the insulating layer 110s2 within the opening 143, and has a region in contact with the upper surface of the conductive layer 112b1 and the upper surface of the conductive layer 112b2 outside the opening 143.
  • the semiconductor layer 108 has a shape that conforms to the shapes of the upper surface of the conductive layer 112b1, the curved portion of the insulating layer 110s1, the side of the insulating layer 110s1, the upper surface of the conductive layer 112a, the side of the insulating layer 110s2, the curved portion of the insulating layer 110s2, and the upper surface of the conductive layer 112b2.
  • a part of the semiconductor layer 108 overlaps with a part of the conductive layer 112a through the conductive layer 112b1, the conductive layer 116_1, and a part of the insulating layer 110. It can also be said that the part of the semiconductor layer 108 faces the side of the part of the insulating layer 110, the side of the conductive layer 116_1, and the side of the conductive layer 112b1 through the insulating layer 110s1 in the opening 143. Another part of the semiconductor layer 108 overlaps with the other part of the conductive layer 112a through the conductive layer 112b2, the conductive layer 116_2, and another part of the insulating layer 110.
  • the other part of the semiconductor layer 108 faces the side of the other part of the insulating layer 110, the side of the conductive layer 116_2, and the side of the conductive layer 112b2 through the insulating layer 110s2 in the opening 143.
  • the semiconductor layer 108 has a region in contact with the conductive layer 112a, a region in contact with the conductive layer 112b1, and a region in contact with the conductive layer 112b2.
  • the region of the semiconductor layer 108 in contact with the conductive layer 112a functions as one of the source region or drain region of the transistor 10_1 and the transistor 10_2.
  • the region of the semiconductor layer 108 in contact with the conductive layer 112b1 functions as the other of the source region or drain region of the transistor 10_1.
  • the region of the semiconductor layer 108 in contact with the conductive layer 112b2 functions as the other of the source region or drain region of the transistor 10_2.
  • the same semiconductor layer is used for the semiconductor layer having the channel formation region of transistor 10_1 and the semiconductor layer having the channel formation region of transistor 10_2.
  • the same conductive layer is used for the conductive layer functioning as one of the source electrode or drain electrode of transistor 10_1 and the conductive layer functioning as one of the source electrode or drain electrode of transistor 10_2. Therefore, it can be said that one of the source region or drain region of transistor 10_1 is connected to one of the source region or drain region of transistor 10_2.
  • the channel formation regions of each transistor are provided between the source region and drain region of transistor 10_1 and transistor 10_2.
  • the insulating layer 106 is provided so as to cover the opening 143 via the insulating layer 110s1, the insulating layer 110s2, and the semiconductor layer 108.
  • the insulating layer 106 has a region in contact with the upper surface and side surfaces of the semiconductor layer 108, the upper surface and side surfaces of the conductive layer 112b1, the upper surface and side surfaces of the conductive layer 112b2, the upper surface and side surfaces of the conductive layer 112a, the upper surface of the insulating layer 110, and the upper surface of the substrate 102.
  • the insulating layer 106 has a shape that follows the shapes of the upper surface and side surfaces of the semiconductor layer 108, the upper surface and side surfaces of the conductive layer 112b1, the upper surface and side surfaces of the conductive layer 112b2, the upper surface and side surfaces of the conductive layer 112a, the upper surface of the insulating layer 110, and the upper surface of the substrate 102.
  • the conductive layer 104 is provided on the insulating layer 106, and has a region in contact with the upper surface of the insulating layer 106.
  • the conductive layer 104 has a region that overlaps with the semiconductor layer 108 via the insulating layer 106.
  • the conductive layer 104 also has a region that faces the semiconductor layer 108 via the insulating layer 106 within the opening 143.
  • FIG. 1B and other figures show an example in which the conductive layer 104 has a shape that matches the shape of the upper surface of the insulating layer 106.
  • the conductive layer 104 may be provided so that a portion of it is embedded in the opening 143.
  • the source and drain electrodes are located at different heights with respect to the surface of the substrate 102 on which they are formed, and the drain current flows perpendicularly or approximately perpendicularly to the surface of the substrate 102. It can also be said that the drain current flows vertically or approximately vertically in transistors 10_1 and 10_2. Therefore, the transistor of one embodiment of the present invention can be called a vertical transistor, a vertical channel transistor, or a VFET (Vertical Field Effect Transistor).
  • VFET Very Field Effect Transistor
  • the channel length of the transistor 10_1 can be controlled by the thickness of the conductive layer 116_1 and the insulating layer 110 provided between the conductive layer 112a and the conductive layer 112b1.
  • the channel length of the transistor 10_2 can be controlled by the thickness of the conductive layer 116_2 and the insulating layer 110 provided between the conductive layer 112a and the conductive layer 112b2. Therefore, a transistor having a channel length smaller than the minimum dimension of an exposure device used to manufacture the transistor can be manufactured with high precision. This also reduces the characteristic variation between multiple transistors included in the semiconductor device. Therefore, the operation of the semiconductor device including the transistor can be stabilized and the reliability can be improved. Furthermore, when the characteristic variation between multiple transistors is reduced, the degree of freedom in circuit design is increased, and the operating voltage of the semiconductor device can be reduced. Therefore, the power consumption of the semiconductor device can be reduced.
  • the source electrode, the layer having the channel formation region, and the drain electrode can be provided in a stacked manner, respectively, so that the occupied area can be significantly reduced compared to a so-called planar type transistor in which the layer having the channel formation region is arranged in a planar shape.
  • the conductive layer 112a, the conductive layer 112b1, the conductive layer 112b2, the conductive layer 116_1, the conductive layer 116_2, and the conductive layer 104 can each function as wiring, and the transistor 10_1 and the transistor 10_2 can be provided in a region where these wirings overlap. That is, in a circuit having the transistor 10_1, the transistor 10_2, and the wiring, the area occupied by the transistor 10_1, the transistor 10_2, and the wiring can be reduced. Therefore, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be obtained.
  • one surface of a part of the semiconductor layer 108 faces a part of the conductive layer 104 through a part of the insulating layer 106, and the other surface of the part of the semiconductor layer 108 faces the conductive layer 116_1 through the insulating layer 110s1.
  • the part of the conductive layer 104 functions as a back gate electrode
  • the conductive layer 116_1 functions as a gate electrode.
  • one surface of the other part of the semiconductor layer 108 faces the other part of the conductive layer 104 through the other part of the insulating layer 106, and the other surface of the other part of the semiconductor layer 108 faces the conductive layer 116_2 through the insulating layer 110s2.
  • the other part of the conductive layer 104 functions as a back gate electrode, and the conductive layer 116_2 functions as a gate electrode.
  • the same conductive layer (conductive layer 104) is used for the conductive layer that functions as the back gate electrode of transistor 10_1 and the conductive layer that functions as the back gate electrode of transistor 10_2.
  • the same conductive layer (conductive layer 112a) is used for the conductive layer that functions as one of the source electrode or drain electrode of transistor 10_1 and the conductive layer that functions as one of the source electrode or drain electrode of transistor 10_2. Therefore, as shown in FIG. 2C, the semiconductor device 100 can be said to have transistors 10_1 and 10_2 in which one of the source electrode or drain electrode (conductive layer 112a) is connected to each other and the back gate electrodes (conductive layer 104) are also connected to each other.
  • the potential of the backgate electrode can be ground potential or any potential. This allows the potential of the region of the semiconductor layer 108 facing the backgate electrode to be fixed, so that the threshold voltages of the transistors 10_1 and 10_2 can be normally-off. In addition, the variation in the electrical characteristics of the transistors 10_1 and 10_2 can be suppressed.
  • a common wiring may be provided to connect the backgate electrodes of multiple transistors 10_1 and 10_2, and a potential may be applied to the common wiring.
  • transistor 10_1 and transistor 10_2 can be transistors with extremely short channel lengths. Therefore, it can be said that these transistors are prone to defects such as short channel effects.
  • transistor 10_1 and transistor 10_2 By providing transistor 10_1 and transistor 10_2 with a backgate electrode, it becomes easier to control the threshold voltage than when the transistor does not have a backgate electrode, and this makes it possible to suppress the short channel effect from becoming apparent.
  • the back gate electrodes of the transistors 10_1 and 10_2 can also function as, for example, capacitance electrodes. In this case, since there is no need to separately form a capacitance electrode, the number of steps required to manufacture the display device can be reduced.
  • the transistors 10_1 and 10_2 are provided facing each other with an opening 143 therebetween. Therefore, by narrowing the width of the opening 143 in the direction of the dashed line A1-A2 in a plan view (corresponding to the width D143 shown in FIG. 1A), the distance between the transistors 10_1 and 10_2 can be shortened.
  • an opening 143 having a width D143 which is the minimum line width of the exposure device, is formed in the layer stacked on the conductive layer 112a (specifically, the conductive layer that becomes the insulating layer 110a, the conductive layer 116_1 and the conductive layer 116_2, and the insulating layer 110b), and the transistors 10_1 and 10_2 having the above-mentioned configuration are provided in the opening, thereby realizing an extremely small and highly integrated semiconductor device 100.
  • the semiconductor device 100 By applying the semiconductor device 100 to a display device, it is possible to achieve a resolution of, for example, 2000 ppi or more.
  • the semiconductor material used for the semiconductor layer 108 is not particularly limited.
  • a semiconductor made of a single element or a compound semiconductor can be used.
  • semiconductors made of a single element include silicon and germanium.
  • compound semiconductors include gallium arsenide and silicon germanium.
  • Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS: oxide semiconductor). Note that these semiconductor materials may contain impurities as dopants.
  • the crystallinity of the semiconductor material used for the semiconductor layer 108 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) can be used.
  • the use of a single crystal semiconductor or a semiconductor having crystallinity is preferable because it can suppress deterioration of the transistor characteristics.
  • Silicon can be used for the semiconductor layer 108.
  • Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon.
  • Examples of polycrystalline silicon include low temperature polysilicon (LTPS).
  • Transistors using amorphous silicon in the channel formation region can be formed on a large glass substrate and can be manufactured at low cost. Transistors using polycrystalline silicon in the channel formation region have high field effect mobility and can operate at high speed. Furthermore, transistors using microcrystalline silicon in the channel formation region have higher field effect mobility and can operate at high speed than transistors using amorphous silicon.
  • the semiconductor layer 108 preferably contains a metal oxide (also called an oxide semiconductor) that exhibits semiconductor properties.
  • a metal oxide also called an oxide semiconductor
  • the band gap of the metal oxide used in the semiconductor layer 108 is preferably 2.0 eV or more, and more preferably 2.5 eV or more.
  • OS transistors have extremely high field-effect mobility compared to transistors using amorphous silicon.
  • OS transistors have an extremely small off-state current and can retain charge accumulated in a capacitor connected in series with the transistor for a long period of time.
  • the use of OS transistors can reduce the power consumption of a semiconductor device.
  • the insulating layer 110 one or both of an inorganic insulating layer and an organic insulating layer can be used.
  • examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin.
  • the insulating layer 110 has one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxynitrides, and nitride oxides.
  • oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate.
  • nitrides include silicon nitride and aluminum nitride.
  • oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride.
  • nitride oxides include silicon nitride oxide and aluminum nitride oxide.
  • an oxynitride refers to a material whose composition contains more oxygen than nitrogen.
  • An oxynitride refers to a material whose composition contains more nitrogen than oxygen.
  • the insulating layer 110 preferably has a laminated structure.
  • FIG. 1B and other figures show an example in which the insulating layer 110 has an insulating layer 110a1, an insulating layer 110a2 on the insulating layer 110a1, an insulating layer 110a3 on the insulating layer 110a2, an insulating layer 110b3 on the insulating layer 110a3, an insulating layer 110b2 on the insulating layer 110b3, and an insulating layer 110b1 on the insulating layer 110b2.
  • Each of these insulating layers can be made of the same material as that used for the insulating layer 110.
  • sputtering or plasma enhanced chemical vapor deposition can be suitably used to form the insulating layers 110a1, 110a2, 110a3, 110b1, 110b2, and 110b3.
  • the flow rate of hydrogen-containing gas e.g., hydrogen gas and ammonia gas
  • the partial pressure of the gas in the processing chamber of the deposition apparatus is low. This can reduce the amount of hydrogen contained in the insulating layers 110a1, 110a2, 110a3, 110b1, 110b2, and 110b3.
  • the amount of hydrogen contained in these layers can be extremely reduced.
  • a sputtering method can be suitably used for forming these layers.
  • the hydrogen content of the insulating layers 110a1, 110a2, 110a3, 110b1, 110b2, and 110b3 it is possible to suppress the supply of hydrogen to the channel formation region of the semiconductor layer 108, and to stabilize the electrical characteristics of the transistors 10_1 and 10_2.
  • the insulating layer 110s1 and the insulating layer 110s2 have a region in contact with the semiconductor layer 108.
  • a region in contact with the insulating layer 110s1 can function as a channel formation region of the transistor 10_1
  • a region in contact with the insulating layer 110s2 can function as a channel formation region of the transistor 10_2. Therefore, when a metal oxide is used for the semiconductor layer 108, the insulating layer 110s1 and the insulating layer 110s2 preferably contain oxygen. This can improve the interface characteristics between the semiconductor layer 108 and the insulating layer 110s1 and the interface characteristics between the semiconductor layer 108 and the insulating layer 110s2.
  • the insulating layer 110s1 and the insulating layer 110s2 are films that release oxygen by heating.
  • the insulating layer 110s1 and the insulating layer 110s2 release oxygen by heat applied during the manufacturing process of the transistor 10_1 and the transistor 10_2, and oxygen can be supplied to the semiconductor layer 108.
  • oxygen vacancies VO
  • the transistors 10_1 and 10_2 can have favorable electrical characteristics and high reliability.
  • the insulating layers 110s1 and 110s2 for example, one or more of an oxide and an oxynitride that can be used for the insulating layer 110 can be suitably used.
  • the insulating layers 110s1 and 110s2 preferably contain silicon and oxygen, and one or both of silicon oxide and silicon oxynitride can be suitably used.
  • the insulating layer 110 it is preferable that the insulating layer 110a2 sandwiched between the insulating layer 110a1 and the insulating layer 110a3, and the insulating layer 110b2 sandwiched between the insulating layer 110b1 and the insulating layer 110b3 contain oxygen. It is more preferable to use a film that releases oxygen when heated for the insulating layer 110a2 and the insulating layer 110b2. In other words, it is preferable to use the same material for the insulating layer 110a2 and the insulating layer 110b2 as the material that can be used for the insulating layer 110s1 and the insulating layer 110s2.
  • both the oxygen contained in the insulating layer 110s1 or the insulating layer 110s2 and the oxygen contained in the insulating layer 110a2 and the insulating layer 110b2 can be supplied to the channel formation region of the semiconductor layer 108, which can further improve the reliability of the transistors 10_1 and 10_2.
  • oxygen can be supplied to the insulating layer 110s1, insulating layer 110s2, insulating layer 110a2, or insulating layer 110b2 by performing heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere on the insulating layer.
  • oxygen can be supplied to the insulating layer by forming an oxide film on the upper surface of the insulating layer 110a2 or insulating layer 110b2 by a sputtering method in an oxygen-containing atmosphere. The oxide film may then be removed.
  • substances e.g., atoms, molecules, and ions
  • the diffusion coefficient of the substance in the insulating layers 110s1, 110s2, 110a2, and 110b2 is large.
  • oxygen is easily diffused in the insulating layers 110s1, 110s2, 110a2, and 110b2.
  • the diffusion coefficient of oxygen is large in the insulating layers 110s1, 110s2, 110a2, and 110b2.
  • oxygen contained in the insulating layer 110s1 diffuses through the insulating layer 110s1 and is supplied to the semiconductor layer 108 through the interface between the insulating layer 110s1 and the semiconductor layer 108.
  • oxygen contained in the insulating layer 110s2 diffuses in the insulating layer 110s2 and is supplied to the semiconductor layer 108 through the interface between the insulating layer 110s2 and the semiconductor layer 108.
  • oxygen contained in the insulating layer 110a2 diffuses in the insulating layer 110a2 and is supplied to the insulating layer 110s1 and the insulating layer 110s2, and is supplied to the semiconductor layer 108 through the interface between the insulating layer 110s1 and the semiconductor layer 108 and the interface between the insulating layer 110s2 and the semiconductor layer 108.
  • oxygen contained in the insulating layer 110b2 diffuses in the insulating layer 110b2 and is supplied to the insulating layer 110s1 and the insulating layer 110s2, and is supplied to the semiconductor layer 108 through the interface between the insulating layer 110s1 and the semiconductor layer 108 and the interface between the insulating layer 110s2 and the semiconductor layer 108.
  • the oxygen contained in the insulating layers can be efficiently supplied to the semiconductor layer 108 (particularly the channel formation region).
  • the region in contact with the conductive layer 112a of the semiconductor layer 108 functions as one of the source region or drain region of the transistor 10_1 and the transistor 10_2, the region in contact with the conductive layer 112b1 of the semiconductor layer 108 functions as the other of the source region or drain region of the transistor 10_1, and the region in contact with the conductive layer 112b2 of the semiconductor layer 108 functions as the other of the source region or drain region of the transistor 10_2.
  • the source region and the drain region are regions with lower electrical resistance than the channel formation region.
  • the source region and the drain region can also be said to be regions with higher carrier concentration and higher oxygen defect density than the channel formation region.
  • the insulating layer 110a1 is provided between the conductive layer 112a and the insulating layer 110a2.
  • the insulating layer 110a3 is provided between the insulating layer 110a2 and the conductive layer 116_1, and between the insulating layer 110a2 and the conductive layer 116_2.
  • the insulating layer 110b3 is provided between the conductive layer 116_1 and the insulating layer 110b2, and between the conductive layer 116_2 and the insulating layer 110b2.
  • the insulating layer 110b1 is provided between the insulating layer 110b2 and the conductive layer 112b1, and between the insulating layer 110b2 and the conductive layer 112b2.
  • the amount of impurities (e.g., hydrogen and water) released from the insulating layer 110a1, the insulating layer 110a3, the insulating layer 110b1, and the insulating layer 110b3 is small. Furthermore, it is preferable that the insulating layer 110a1, the insulating layer 110a3, the insulating layer 110b1, and the insulating layer 110b3 are each impermeable to substances. It can also be said that the insulating layer 110a1, the insulating layer 110a3, the insulating layer 110b1, and the insulating layer 110b3 function as a barrier film.
  • impurities e.g., hydrogen and water
  • the insulating layer 110a1, the insulating layer 110a3, the insulating layer 110b1, and the insulating layer 110b3 are each impermeable to impurities. This can suppress the diffusion of impurities contained in the insulating layer 110a1, the insulating layer 110a3, the insulating layer 110b1, and the insulating layer 110b3 into the channel formation region of the semiconductor layer 108. Therefore, the transistor 10_1 and the transistor 10_2 can have good electrical characteristics and high reliability.
  • This can suppress the oxygen contained in the insulating layer 110a2 and the oxygen contained in the insulating layer 110b2 from diffusing to the conductive layer 112a side through the insulating layer 110a1 and the insulating layer 110b3, respectively.
  • it can suppress the oxygen contained in the insulating layer 110a2 and the oxygen contained in the insulating layer 110b2 from diffusing to the conductive layer 112b1 side and the conductive layer 112b2 side through the insulating layer 110a3 and the insulating layer 110b1, respectively.
  • the transistors 10_1 and 10_2 can have favorable electrical characteristics and high reliability.
  • the conductive layer 112a can be prevented from being oxidized by oxygen contained in the insulating layer 110a2 and oxygen contained in the insulating layer 110b2, and the electrical resistance of the conductive layer 112a can be prevented from being increased.
  • the conductive layer 112b1 or the conductive layer 112b2 can be prevented from being oxidized by oxygen contained in the insulating layer 110a2 and oxygen contained in the insulating layer 110b2, and the electrical resistance of the conductive layer 112b1 or the conductive layer 112b2 can be prevented from being increased. Therefore, the transistors 10_1 and 10_2 can have large on-state current.
  • a barrier film refers to a film that has barrier properties.
  • Barrier properties refer to one or both of the function of suppressing the diffusion of a target substance (also called low permeability) and the function of capturing or fixing the substance (also called gettering).
  • a target substance also called low permeability
  • gettering the function of capturing or fixing the substance
  • an insulating layer that has barrier properties can be called a barrier insulating layer.
  • insulating layer 110a1, insulating layer 110a3, insulating layer 110b1, and insulating layer 110b3 that function as a barrier film one or more of an oxide having one or both of aluminum and hafnium, an oxide having magnesium, an oxide having gallium, a nitride having silicon, and a nitride oxide having silicon can be used.
  • one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide can be preferably used.
  • the same material can be used for the insulating layer 110a1, insulating layer 110a3, insulating layer 110b1, and insulating layer 110b3.
  • the equipment used to form each insulating layer can be shared, thereby increasing productivity and reducing manufacturing costs.
  • different materials can be used for the insulating layer 110a1, the insulating layer 110a3, the insulating layer 110b1, and the insulating layer 110b3.
  • different materials refer to materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.
  • insulating layer 110a1, insulating layer 110a3, insulating layer 110b1, and insulating layer 110b3 are formed by a method that does not use a gas containing hydrogen.
  • a sputtering method can be suitably used to form insulating layer 110a1, insulating layer 110a3, insulating layer 110b1, and insulating layer 110b3.
  • insulating layer 110a1, insulating layer 110a3, insulating layer 110b1, and insulating layer 110b3, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, and gallium zinc oxide can be particularly suitably used, respectively.
  • the insulating layer 110a3 provided on the insulating layer 110a2 and the insulating layer 110b1 provided on the insulating layer 110b2 are preferably formed in an atmosphere containing oxygen. This allows oxygen to be supplied to the insulating layer 110a2 when the insulating layer 110a3 is formed. Similarly, oxygen can be supplied to the insulating layer 110b2 when the insulating layer 110b1 is formed. A material containing oxygen can be particularly preferably used for the insulating layer 110a3 and the insulating layer 110b1.
  • oxygen flow rate ratio the ratio of the flow rate of oxygen gas to the total film-forming gas used to form the insulating layer 110a3
  • the oxygen flow rate ratio the oxygen partial pressure in the processing chamber of the film-forming apparatus
  • each of insulating layer 110a1 and insulating layer 110b3 is preferably 3 nm or more and 500 nm or less, more preferably 5 nm or more and 400 nm or less, more preferably 10 nm or more and 300 nm or less, more preferably 20 nm or more and 300 nm or less, more preferably 50 nm or more and 300 nm or less, more preferably 100 nm or more and 300 nm or less, more preferably 100 nm or more and 250 nm or less, and more preferably 150 nm or more and 250 nm or less.
  • oxygen contained in the insulating layer 110a2 may diffuse to the conductive layer 112a side through the insulating layer 110a1, and the amount of oxygen supplied to the channel formation region of the semiconductor layer 108 may decrease.
  • oxygen contained in the insulating layer 110b3 may diffuse to the conductive layer 112a side through the insulating layer 110b3, and the amount of oxygen supplied to the channel formation region of the semiconductor layer 108 may decrease.
  • the insulating layer 110a1 is thick, the amount of impurities released from the insulating layer 110a1 may increase, and the amount of impurities diffused to the channel formation region of the semiconductor layer 108 may increase.
  • the insulating layer 110b3 when the insulating layer 110b3 is thick, the amount of impurities released from the insulating layer 110b3 may increase, and the amount of impurities diffused to the channel formation region of the semiconductor layer 108 may increase.
  • the amount of oxygen supplied to the channel formation region of the semiconductor layer 108 can be increased, and oxygen vacancies ( VO ) and VOH in the channel formation region can be reduced.
  • the conductive layer 112a can be prevented from being oxidized by oxygen contained in the insulating layers 110a2 and 110b2, and the electrical resistance of the conductive layer 112a can be prevented from increasing. Note that the thicknesses of the insulating layers 110a1 and 110b3 are not limited to the above-described ranges.
  • each of insulating layer 110a3 and insulating layer 110b1 is preferably 3 nm or more and 500 nm or less, more preferably 5 nm or more and 400 nm or less, more preferably 10 nm or more and 300 nm or less, more preferably 20 nm or more and 300 nm or less, more preferably 20 nm or more and 200 nm or less, more preferably 30 nm or more and 200 nm or less, more preferably 50 nm or more and 200 nm or less, and more preferably 50 nm or more and 150 nm or less.
  • the amount of impurities released from the insulating layer 110a3 increases, and the amount of impurities diffusing to the channel formation region of the semiconductor layer 108 may increase.
  • the insulating layer 110b1 is thick, the amount of impurities released from the insulating layer 110b1 increases, and the amount of impurities diffusing to the channel formation region of the semiconductor layer 108 may increase.
  • the insulating layer 110a3 is thin, oxygen contained in the insulating layer 110a2 may diffuse to the conductive layer 112b1 side and the conductive layer 112b2 side through the insulating layer 110a3, and the amount of oxygen supplied to the channel formation region of the semiconductor layer 108 may decrease.
  • oxygen contained in the insulating layer 110b2 may diffuse to the conductive layer 112b1 side and the conductive layer 112b2 side through the insulating layer 110b1, and the amount of oxygen supplied to the channel formation region of the semiconductor layer 108 may decrease.
  • Setting the thicknesses of the insulating layers 110a3 and 110b1 within the above-described ranges can reduce oxygen vacancies ( VO ) and VOH in the channel formation region of the semiconductor layer 108.
  • the thicknesses of the insulating layers 110a3 and 110b1 are not limited to the above-described ranges.
  • transistors 10_1 and 10_2 when the channel lengths of transistors 10_1 and 10_2 are short, the influence of impurities diffusing into the channel formation region on the electrical characteristics of each transistor becomes greater. Therefore, it is preferable to use materials that release less impurities (especially hydrogen) from themselves for insulating layer 110a1, insulating layer 110a3, insulating layer 110b1, and insulating layer 110b3. Furthermore, it is more preferable that insulating layer 110a1, insulating layer 110a3, insulating layer 110b1, and insulating layer 110b3 are thin. This can reduce the amount of impurities diffusing into the channel formation region, and can result in transistors 10_1 and 10_2 that exhibit good electrical characteristics and are highly reliable even when the channel length is short.
  • the thicknesses of the insulating layers 110a1, 110a3, 110b1, and 110b3 are each preferably 3 nm or more and 100 nm or less, more preferably 3 nm or more and 50 nm or less, more preferably 3 nm or more and 30 nm or less, more preferably 3 nm or more and 20 nm or less, more preferably 3 nm or more and 10 nm or less, and more preferably 5 nm or more and 10 nm or less.
  • the insulating layer 110 has a six-layer stacked structure, one embodiment of the present invention is not limited to this.
  • the insulating layer 110 can also be a single layer, a two-layer stacked structure, a three-layer stacked structure, a four-layer stacked structure, a five-layer stacked structure, or a seven or more layer stacked structure.
  • each of transistors 10_1 and 10_2 will be described with reference to FIG. 1A and FIG. 1B.
  • the region of the semiconductor layer 108 in contact with the insulating layer 110s1 functions as the channel formation region of transistor 10_1
  • the region of the semiconductor layer 108 in contact with the insulating layer 110s2 functions as the channel formation region of transistor 10_2.
  • the channel length L10_1 of transistor 10_1 and the channel length L10_2 of transistor 10_2 are indicated by dashed double-headed arrows. Note that the channel length L10_1 of transistor 10_1 will be described below, but it can also be applied to the channel length L10_2 of transistor 10_2 by replacing conductive layer 112b1 with conductive layer 112b2, insulating layer 110s1 with insulating layer 110s2, and conductive layer 116_1 with conductive layer 116_2.
  • the channel length L10_1 of transistor 10_1 corresponds to the distance along insulating layer 110s1 between the top surface of conductive layer 112a and the top surface of conductive layer 112b1 in semiconductor layer 108.
  • the channel length L10_1 of the transistor 10_1 may be a total thickness T110 (in FIG. 1B, the thickness T110 is indicated by a dashed line with a double arrow) of the insulating layer 110a1, the insulating layer 110a2, the insulating layer 110a3, the conductive layer 116_1, the insulating layer 110b3, the insulating layer 110b2, and the insulating layer 110b1 in the region sandwiched between the upper surface of the conductive layer 112a and the lower surface of the conductive layer 112b1 in the semiconductor layer 108.
  • the channel length L10_1 of the transistor 10_1 may be a sum of the thickness T110 and the thickness of the conductive layer 112b1.
  • the channel length L10_1 is determined by the thickness T110, the thickness of the conductive layer 112b1, and the angle (angle ⁇ 110) between the surface on which the insulating layer 110s1 is formed (here, the side of the insulating layer 110a1, the side of the insulating layer 110a2, the side of the insulating layer 110a3, the side of the conductive layer 116_1, the side of the insulating layer 110b3, the side of the insulating layer 110b2, the side of the insulating layer 110b1, and the side of the conductive layer 112b1) and the surface on which the insulating layer 110a1 is formed (here, the upper surface of the conductive layer 112a1), and is not affected by the performance of the exposure device used to manufacture the transistor.
  • the channel length L10_1 can be made smaller than the minimum dimension of the exposure device, and a transistor of a fine size can be realized.
  • a transistor with an extremely short channel length that could not be realized with a conventional exposure device for mass production of flat panel displays for example, a minimum dimension of about 1.5 ⁇ m or 1.25 ⁇ m
  • the channel length L10_1 can be, for example, 5 nm or more and less than 3 ⁇ m, 7 nm or more and less than 2.5 ⁇ m, 10 nm or more and less than 2 ⁇ m, 10 nm or more and less than 1.5 ⁇ m, 10 nm or more and less than 1.2 ⁇ m, 10 nm or more and less than 1 ⁇ m, 10 nm or more and less than 500 nm, 10 nm or more and less than 300 nm, 10 nm or more and less than 200 nm, 10 nm or more and less than 100 nm, 10 nm or more and less than 50 nm, 10 nm or more and less than 30 nm, or 10 nm or more and less than 20 nm.
  • the channel length L10_1 can be 100 nm or more and less than 1 ⁇ m.
  • the on-state current of the transistor 10_1 can be increased.
  • the transistor 10_1 By shortening the channel length L10_1, the on-state current of the transistor 10_1 can be increased.
  • the transistor 10_1 By using the transistor 10_1, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small-sized semiconductor device can be obtained. For example, when the semiconductor device of one embodiment of the present invention is applied to a large display device or a high-definition display device, even if the number of wirings is increased, the signal delay in each wiring can be reduced and display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.
  • the channel length L10_1 can be controlled by adjusting the thickness T110 and the angle ⁇ 110, etc.
  • the thickness T110 can be, for example, 5 nm or more but less than 3 ⁇ m, 7 nm or more but less than 2.5 ⁇ m, 10 nm or more but less than 2 ⁇ m, 10 nm or more but less than 1.5 ⁇ m, 10 nm or more but less than 1.2 ⁇ m, 10 nm or more but less than 1 ⁇ m, 10 nm or more but less than 500 nm, 10 nm or more but less than 300 nm, 10 nm or more but less than 200 nm, 10 nm or more but less than 100 nm, 10 nm or more but less than 50 nm, 10 nm or more but less than 30 nm, or 10 nm or more but less than 20 nm.
  • the side of the insulating layer 110 on the opening 143 side is preferably tapered.
  • the angle ⁇ 110 is preferably less than 90 degrees. By reducing the angle ⁇ 110, the coverage of the layer (e.g., the semiconductor layer 108) formed on the insulating layer 110 can be improved. Furthermore, the smaller the angle ⁇ 110, the longer the channel length L10_1 can be, and the larger the angle ⁇ 110, the shorter the channel length L10_1 can be.
  • the angle ⁇ 110 can be, for example, 30 degrees or more and 90 degrees or less, 35 degrees or more and 85 degrees or less, 40 degrees or more and 80 degrees or less, 45 degrees or more and 80 degrees or less, 50 degrees or more and 80 degrees or less, 55 degrees or more and 80 degrees or less, 60 degrees or more and 80 degrees or less, 65 degrees or more and 80 degrees or less, or 70 degrees or more and 80 degrees or less.
  • the angle ⁇ 110 is shown as less than 90 degrees, but this is not a limitation of one embodiment of the present invention.
  • the angle ⁇ 110 can also be 90 degrees or approximately 90 degrees. This allows the channel length L10_1 of the transistor 10_1 to be shortened.
  • Figure 1B etc. shows an example in which the sidewalls of the opening 143 (side of insulating layer 110a1, side of insulating layer 110a2, side of insulating layer 110a3, side of conductive layer 116_1, side of insulating layer 110b3, side of insulating layer 110b2, side of insulating layer 110b1, and side of conductive layer 112b1) are formed in a straight line, but one embodiment of the present invention is not limited to this.
  • angles between the side surfaces of the insulating layers 110a1, 110a2, and 110a3 and the upper surface of the conductive layer 112a, the angles between the side surfaces of the conductive layer 116_1 and the upper surface of the insulating layer 110a3, the angles between the side surfaces of the insulating layers 110b3, 110b2, and 110b1 and the upper surface of the conductive layer 116_1, and the angles between the side surfaces of the conductive layer 112b1 and the upper surface of the insulating layer 110b1 may be different from each other.
  • the channel width W10_1 of the transistor 10_1 and the channel width W10_2 of the transistor 10_2 are each indicated by a solid double-headed arrow.
  • the channel width W10_1 corresponds to the length of the region where the end of the conductive layer 116_1 on the opening 143 side overlaps with the semiconductor layer 108 in a plan view. This length also corresponds to the length of the region where the semiconductor layer 108 overlaps with at least one of the conductive layer 112a (one of the source electrode or drain electrode of the transistor 10_1) or the conductive layer 112b1 (the other of the source electrode or drain electrode of the transistor 10_1).
  • this length can be said to be the length of the region through which the drain current of the transistor 10_1 can flow in a plan view.
  • this length direction is also approximately perpendicular to the channel length L10_1 of the transistor 10_1. Therefore, this length can be considered to be the channel width W10_1 of the transistor 10_1.
  • the above can also be applied to the channel width W10_2 of transistor 10_2 by replacing conductive layer 116_1 with conductive layer 116_2 and conductive layer 112b1 with conductive layer 112b2.
  • the channel width W10_1 of transistor 10_1 may be the length of the region where the semiconductor layer 108 overlaps with both the conductive layer 112a (one of the source electrode or drain electrode of transistor 10_1) and the conductive layer 112b1 (the other of the source electrode or drain electrode of transistor 10_1).
  • the channel width W10_2 of transistor 10_2 may be the length of the region where the semiconductor layer 108 overlaps with both the conductive layer 112a (one of the source electrode or drain electrode of transistor 10_2) and the conductive layer 112b2 (the other of the source electrode or drain electrode of transistor 10_2).
  • FIG. 5A shows a cross-sectional view of a structure in which only the transistor 10_2 side is cut out from the semiconductor device 100 shown in FIG. 1B.
  • the cross section of the structure is shown as the XZ plane.
  • FIG. 5B shows a view of the structure shown in FIG. 5A from the YZ plane side.
  • FIG. 5B shows only the conductive layer 112a, the conductive layer 112b2, the conductive layer 116_2, and the semiconductor layer 108.
  • the channel width W10_2 of the transistor 10_2 when the channel width W10_2 of the transistor 10_2 is the length of the region where the semiconductor layer 108 overlaps with at least one of the conductive layer 112a and the conductive layer 112b2, the channel width W10_2 corresponds to the width W10_2A shown in FIG. 5B.
  • the channel width W10_2 of the transistor 10_2 when the channel width W10_2 of the transistor 10_2 is the length of the region where the semiconductor layer 108 overlaps with both the conductive layer 112a and the conductive layer 112b2, the channel width W10_2 corresponds to the width W10_2B shown in FIG. 5B.
  • the width D143 of the opening 143 may vary in the depth direction.
  • the width D143 of the opening 143 may be the average value of the diameter at the highest point of the opening 143 in a cross-sectional view, the diameter at the lowest point, and the diameter at the midpoint between these three.
  • the width D143 of the opening 143 is equal to or larger than the minimum dimension of the exposure device.
  • the width D143 can be, for example, 200 nm or more and less than 5 ⁇ m, 300 nm or more and less than 4.5 ⁇ m, 400 nm or more and less than 4 ⁇ m, 500 nm or more and less than 3.5 ⁇ m, 500 nm or more and less than 3 ⁇ m, 500 nm or more and less than 2.5 ⁇ m, 500 nm or more and less than 2 ⁇ m, 500 nm or more and less than 1.5 ⁇ m, or 500 nm or more and less than 1 ⁇ m.
  • Metal oxides that can be used for the semiconductor layer 108 will be specifically described.
  • metal oxides include indium oxide, gallium oxide, and zinc oxide.
  • the metal oxide preferably contains at least indium or zinc.
  • the metal oxide preferably contains one or more elements selected from indium, element M, and zinc.
  • the element M is a metal element or semimetal element having a high bond energy with oxygen, for example, a metal element or semimetal element having a bond energy with oxygen higher than that of indium.
  • the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.
  • the element M of the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin.
  • metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal elements" described in this specification may include metalloid elements.
  • the semiconductor layer 108 may be, for example, indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide, also referred to as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also referred to as IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide), Indium aluminum zinc oxide (In-Al-Zn oxide, also written as AZO), indium tin zinc oxide (In-Sn-Zn oxide, also written as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga
  • the metal oxide may have one or more metal elements having a higher periodic number in the periodic table instead of or in addition to indium.
  • Examples of metal elements having a higher periodic number in the periodic table include metal elements belonging to the fifth period and metal elements belonging to the sixth period.
  • the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide can have one or more nonmetallic elements.
  • the carrier concentration can be increased or the band gap can be narrowed, which may increase the field effect mobility of the transistor.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the field effect mobility of the transistor can be increased.
  • a transistor with a large on-current can be realized.
  • the ratio of the number of indium atoms to the sum of the numbers of atoms of all contained metal elements may be referred to as the indium content.
  • the sum of the ratios of the number of atoms of element M to the sum of the numbers of atoms of all contained metal elements can be taken as the content of element M.
  • Increasing the zinc content in the metal oxide results in a highly crystalline metal oxide, which can suppress the diffusion of impurities in the metal oxide. This suppresses fluctuations in the electrical characteristics of the transistor, and increases reliability.
  • the metal oxide By increasing the content of element M in the metal oxide, the metal oxide can have a large band gap. Furthermore, by suppressing the formation of oxygen vacancies (V 2 O 3 ) in the metal oxide, carrier generation due to oxygen vacancies (V 2 O 3 ) can be suppressed, and a shift in the threshold voltage of the transistor can be suppressed. As a result, the cutoff current can be reduced, and a normally-off transistor can be obtained. Furthermore, a transistor with a small off-current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide applied to the semiconductor layer 108. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, it is possible to obtain a semiconductor device that has both excellent electrical characteristics and high reliability.
  • the metal oxide is an In-M-Zn oxide
  • the atomic ratio of In in the In-M-Zn oxide is equal to or greater than the atomic ratio of element M.
  • the atomic ratio of In in the In-M-Zn oxide can be less than the atomic ratio of element M.
  • the on-current or field effect mobility of the transistor can be increased. Furthermore, by having the element M, the generation of oxygen vacancies (V 0 ) can be suppressed.
  • the content of the element M (the ratio of the number of atoms of the element M to the sum of the number of atoms of all metal elements contained) is preferably 0.1% to 25% or less, more preferably 0.1% to 20% or less, more preferably 0.1% to 10% or less, more preferably 0.1% to 8% or less, more preferably 0.1% to 6% or less, and even more preferably 0.1% to 4% or less. This allows a transistor with good electrical characteristics to be obtained.
  • the element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium.
  • the grain boundaries become recombination centers, and carriers are captured, which may reduce the on-current of the transistor.
  • a polycrystalline metal oxide is used for the semiconductor layer 108, the surface of the semiconductor layer 108 may become uneven. This increases the step on the surface on which a layer (e.g., the insulating layer 106) is formed on the semiconductor layer 108, and defects such as breaks or pores may occur in the layer.
  • a metal oxide having a composition that is likely to form a polycrystalline structure is used for the semiconductor layer 108, it is preferable to include an element that inhibits crystallization.
  • the coverage of a layer (e.g., the insulating layer 106) formed on the semiconductor layer 108 can be improved, and defects such as breaks or pores in the layer can be prevented.
  • indium tin oxide (ITSO) containing silicon is less likely to have a polycrystalline structure than indium tin oxide (ITO), and therefore can be suitably used for the semiconductor layer 108.
  • the silicon content (the ratio of the number of silicon atoms to the sum of the numbers of atoms of all metal elements contained) is preferably 1% or more and 20% or less, more preferably 3% or more and 20% or less, even more preferably 3% or more and 15% or less, and even more preferably 5% or more and 15% or less.
  • indium tin oxide (ITSO) containing silicon is used for the semiconductor layer 108, it is preferable that it has crystallinity.
  • the semiconductor layer 108 may have an amorphous region or be amorphous.
  • a metal oxide that does not contain element M can be applied to the semiconductor layer 108.
  • the metal oxide is an In-Zn oxide
  • the atomic ratio of In is equal to or greater than the atomic ratio of Zn.
  • the composition of the semiconductor layer 108 can be analyzed using, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS or ESCA), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Analysis can also be performed by combining a number of these techniques. It is preferable to separate the peaks of the spectrum obtained by the analysis and identify and quantify the elements. In addition, for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, may be difficult to quantify, or may be below the detection limit.
  • EDX energy dispersive X-ray spectrometry
  • XPS or ESCA X-ray photoelectron spectrometry
  • ICP-MS inductively coupled plasma mass spectrometry
  • the metal oxide can be formed preferably by sputtering or atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • the composition of the formed metal oxide may differ from the composition of the sputtering target.
  • the zinc content in the formed metal oxide may decrease to about 50% compared to the sputtering target.
  • a crystalline metal oxide for the semiconductor layer 108.
  • Examples of the structure of a crystalline metal oxide include a CAAC (C-Axis Aligned Crystal) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc: nano-crystal) structure.
  • CAAC C-Axis Aligned Crystal
  • poly-crystal polycrystalline
  • nanocrystalline nanocrystalline
  • the CAAC structure is a crystal structure in which multiple microcrystals (typically multiple IGZO microcrystals) have a c-axis orientation, and the multiple microcrystals are connected without being oriented in the a-b plane.
  • the CAAC structure has fewer crystal grain boundaries and grains in the a-b plane than the polycrystalline structure, and therefore a highly reliable semiconductor device can be realized.
  • CAAC-OS or nc-OS for the semiconductor layer 108.
  • CAAC-OS has multiple layered crystals.
  • the c-axis of the crystals is oriented in the normal direction of the surface on which it is formed.
  • the semiconductor layer 108 preferably has layered crystals parallel or approximately parallel to the surface on which it is formed.
  • the semiconductor layer 108 preferably has layered crystals parallel or approximately parallel to the upper surface in the region in contact with the upper surface of the conductive layer 112b1 and the upper surface of the conductive layer 112b2, and has layered crystals parallel or approximately parallel to the side surface in the region in contact with the side surface of the insulating layer 110s1 and the side surface of the insulating layer 110s2.
  • the semiconductor layer 108 preferably has layered crystals parallel or approximately parallel to the side surface of the insulating layer 110s1 and the side surface of the insulating layer 110s2, which are the surface on which it is formed, in the opening 143.
  • the layered crystals of the semiconductor layer 108 are formed approximately parallel to the channel length direction of the transistor 10_1 and the channel length direction of the transistor 10_2, so that the transistors 10_1 and 10_2 can have large on-currents.
  • the density of defect states in the channel formation region can be reduced.
  • a metal oxide with low crystallinity a transistor capable of passing a large current can be realized.
  • the substrate temperature during formation can be adjusted, for example, by the temperature of the stage on which the substrate is placed during formation. Also, the higher the oxygen flow rate ratio of the deposition gas used in formation, or the oxygen partial pressure in the processing chamber, the more crystalline the metal oxide that can be formed.
  • the crystallinity of the semiconductor layer 108 can be analyzed, for example, by X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). In addition, the analysis can be performed by combining a plurality of these techniques.
  • XRD X-ray diffraction
  • TEM transmission electron microscope
  • ED electron diffraction
  • V O H When a metal oxide is used for the semiconductor layer 108, it is preferable to reduce V O H in the channel formation region as much as possible to make it highly pure or substantially highly pure.
  • it is important to remove impurities such as water and hydrogen in the metal oxide (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the metal oxide to repair oxygen vacancies (V O ).
  • a metal oxide with sufficiently reduced defects such as V O H for the channel formation region of a transistor, stable electrical characteristics can be imparted.
  • oxygen addition treatment supplying oxygen to a metal oxide to repair oxygen vacancies (V O ) may be referred to as oxygen addition treatment.
  • the carrier concentration of the channel formation region is preferably 1 ⁇ 10 18 cm ⁇ 3 or less, more preferably less than 1 ⁇ 10 17 cm ⁇ 3 , even more preferably less than 1 ⁇ 10 16 cm ⁇ 3 , even more preferably less than 1 ⁇ 10 13 cm ⁇ 3 , and even more preferably less than 1 ⁇ 10 12 cm ⁇ 3 .
  • the carrier concentration of the channel formation region can be, for example, 1 ⁇ 10 ⁇ 9 cm ⁇ 3 .
  • OS transistors have small variations in electrical characteristics due to radiation exposure, i.e., they have high resistance to radiation, and therefore can be suitably used in environments where radiation may be present. It can also be said that OS transistors have high reliability against radiation.
  • OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors.
  • OS transistors can also be suitably used in semiconductor devices used in outer space.
  • radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).
  • the semiconductor layer 108 may have a layered material that functions as a semiconductor.
  • a layered material is a general term for a group of materials that have a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds.
  • a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Examples of the layered material include graphene, silicene, and chalcogenides.
  • Chalcogenides are compounds containing chalcogen (an element belonging to Group 16).
  • Examples of the chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
  • MoS 2 molybdenum sulfide
  • MoSe 2 molybdenum selenide
  • MoTe 2 molybdenum
  • the semiconductor layer 108 can have a stacked structure having two or more metal oxide layers.
  • the compositions of the two or more metal oxide layers in the semiconductor layer 108 can be the same or approximately the same. By using a stacked structure of metal oxide layers with the same composition, for example, they can be formed using the same sputtering target, which can reduce manufacturing costs. When the compositions of the two or more metal oxide layers in the semiconductor layer 108 are the same or approximately the same, the boundaries (interfaces) of these metal oxide layers may not be clearly identified.
  • the conductive layer 112a, the conductive layer 112b1, the conductive layer 112b2, the conductive layer 116_1, the conductive layer 116_2, and the conductive layer 104 can each have a single layer structure or a stacked structure.
  • Examples of materials that can be used for the conductive layer 112a, the conductive layer 112b1, the conductive layer 112b2, the conductive layer 116_1, the conductive layer 116_2, and the conductive layer 104 include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, and alloys containing one or more of the above-mentioned metals.
  • the conductive layer 112a, the conductive layer 112b1, the conductive layer 112b2, the conductive layer 116_1, the conductive layer 116_2, and the conductive layer 104 can each be preferably made of a conductive material having low electrical resistivity, including one or more of copper, silver, gold, and aluminum. In particular, copper or aluminum is preferable because of its excellent mass productivity.
  • the conductive layer 112a, the conductive layer 112b1, the conductive layer 112b2, the conductive layer 116_1, the conductive layer 116_2, and the conductive layer 104 can each be made of a metal oxide (oxide conductor) having electrical conductivity.
  • oxide conductors include indium oxide, zinc oxide, In-Sn oxide (ITO), In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide (also called ITO containing silicon, ITSO), zinc oxide to which gallium is added, and In-Ga-Zn oxide.
  • oxide conductors containing indium are preferred because of their high electrical conductivity.
  • the conductive layer 112a, the conductive layer 112b1, the conductive layer 112b2, the conductive layer 116_1, the conductive layer 116_2, and the conductive layer 104 can each have a stacked structure of a conductive film containing the oxide conductor described above and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, the wiring resistance can be reduced.
  • a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can be applied to each of the conductive layers 112a, 112b1, 112b2, 116_1, 116_2, and 104.
  • X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti
  • the conductive layer 112a, the conductive layer 112b1, the conductive layer 112b2, the conductive layer 116_1, the conductive layer 116_2, and the conductive layer 104 can be made of the same material. Alternatively, different materials can be used for some or all of these layers.
  • the conductive layer 112a, the conductive layer 112b1, and the conductive layer 112b2 have a region in contact with the semiconductor layer 108.
  • a metal oxide e.g., aluminum
  • an insulating oxide e.g., aluminum oxide
  • a conductive material that is not easily oxidized a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductive material for the conductive layer 112a, the conductive layer 112b1, and the conductive layer 112b2.
  • conductive layer 112a, conductive layer 112b1, and conductive layer 112b2 it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel, respectively. These are preferable because they are conductive materials that are not easily oxidized, or materials that maintain low electrical resistance even when oxidized.
  • the conductive layer 112a, the conductive layer 112b1, and the conductive layer 112b2 can each be made of the oxide conductors described above. Specifically, metal oxides such as indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn oxide containing silicon, and zinc oxide doped with gallium can be used.
  • metal oxides such as indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn oxide containing silicon, and zinc oxide doped with gallium can be used.
  • the conductive layer 112a, the conductive layer 112b1, and the conductive layer 112b2 may each be made of a nitride conductor.
  • nitride conductors include tantalum nitride and titanium nitride.
  • the conductive layer 112a, the conductive layer 112b1, the conductive layer 112b2, the conductive layer 116_1, the conductive layer 116_2, and the conductive layer 104 can each have a stacked structure.
  • the conductive layer 112a has a stacked structure, it is preferable to use a conductive material that is not easily oxidized for at least the layer in contact with the semiconductor layer 108. The same applies to the conductive layer 112b1 and the conductive layer 112b2.
  • the insulating layer 106 preferably includes one or more inorganic insulating layers.
  • the insulating layer 106 can be formed using the same material as that used for the insulating layer 110, the insulating layer 110s1, and the insulating layer 110s2.
  • the insulating layer 106 has regions in contact with the semiconductor layer 108, the conductive layer 112b1, the conductive layer 112b2, the conductive layer 104, and the insulating layer 110.
  • a metal oxide is used for the semiconductor layer 108, it is preferable to use any of the above-mentioned oxides and oxynitrides for at least the film that is in contact with the semiconductor layer 108 among the films that constitute the insulating layer 106.
  • the insulating layer 106 has a single-layer structure, silicon oxide, silicon oxynitride, or aluminum oxide can be suitably used for the insulating layer 106.
  • the leakage current may become large.
  • a material with a high relative dielectric constant also called a high-k material
  • examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.
  • a material that can have ferroelectricity can be used for the gate insulating layer.
  • materials that can have ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and HfZrO x (X is a real number greater than 0).
  • materials that may have ferroelectricity include materials in which an element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide.
  • the ratio of the number of hafnium atoms to the number of element J1 atoms may be 1:1 or close thereto.
  • Examples of materials that may have ferroelectricity include materials in which an element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide.
  • element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.
  • the ratio of the number of zirconium atoms to the number of element J2 atoms may be 1:1 or close thereto.
  • examples of materials that can have ferroelectricity include piezoelectric ceramics having a perovskite structure, such as lead titanate ( PbTiOx ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate.
  • PbTiOx lead titanate
  • BST barium strontium titanate
  • PZT lead zirconate titanate
  • SBT strontium bismuth tantalate
  • BFO bismuth ferrite
  • the insulating layer 106 is shown as having a single-layer structure, but one embodiment of the present invention is not limited to this.
  • the insulating layer 106 can have a stacked structure.
  • the insulating layer 195 functioning as a protective layer is preferably made of a material from which impurities do not easily diffuse. By providing the insulating layer 195, diffusion of impurities from the outside into the transistors 10_1 and 10_2 can be effectively suppressed, thereby improving the reliability of the semiconductor device 100. Examples of impurities include water and hydrogen.
  • the insulating layer 195 can be an insulating layer having an inorganic material or an insulating layer having an organic material.
  • an inorganic material such as oxide, oxynitride, nitride oxide, or nitride can be suitably used for the insulating layer 195.
  • silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used.
  • one or more of acrylic resin and polyimide resin can be used as the organic material.
  • a photosensitive material can be used as the organic material. Two or more of the above insulating films can be stacked.
  • the insulating layer 195 can have a stacked structure of an insulating layer having an inorganic material and an insulating layer having an organic material.
  • the material of the substrate 102 it is necessary that the material has at least a heat resistance sufficient to withstand subsequent heat treatment.
  • a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate can be used as the substrate 102.
  • the substrate 102 may be provided with a semiconductor element. Note that the shape of the semiconductor substrate and the insulating substrate may be circular or rectangular.
  • a flexible substrate can be used as the substrate 102, and the semiconductor device 100, etc. can be formed directly on the flexible substrate.
  • a peeling layer can be provided between the substrate 102 and the semiconductor device 100, etc. By providing a peeling layer, after a part or whole of the semiconductor device is completed on the substrate, it can be separated from the substrate 102 and transferred to another substrate. In this case, the semiconductor device 100, etc. can also be transferred to a substrate with low heat resistance or a flexible substrate.
  • ⁇ Configuration Example 2 of Semiconductor Device> 6A shows a configuration example of a semiconductor device 100A according to one embodiment of the present invention, which is a cross-sectional view of the semiconductor device 100A taken along dashed dotted line A1-A2 in the plan view of the semiconductor device 100 shown in FIG.
  • the semiconductor device 100A has a transistor 10A_1, a transistor 10A_2, an insulating layer 110a, and an insulating layer 110b.
  • the semiconductor device 100A differs from the semiconductor device 100 shown in FIG. 1B in that the semiconductor device 100A has a transistor 10A_1 instead of a transistor 10_1, and a transistor 10A_2 instead of a transistor 10_2.
  • Transistor 10A_1 differs from transistor 10_1 in that insulating layer 110s1 has a layered structure of insulating layer 110s1a and insulating layer 110s1b on insulating layer 110s1a.
  • Insulating layer 110s1a is provided in contact with the top surface of conductive layer 112a, the side of insulating layer 110, the side of conductive layer 116_1, and the side of conductive layer 112b1.
  • Insulating layer 110s1b is provided to face the top surface of conductive layer 112a, the side of insulating layer 110, the side of conductive layer 116_1, and the side of conductive layer 112b1 via insulating layer 110s1a.
  • Transistor 10A_2 differs from transistor 10_2 in that insulating layer 110s2 has a stacked structure of insulating layer 110s2a and insulating layer 110s2b on insulating layer 110s2a.
  • Insulating layer 110s2a is provided in contact with the top surface of conductive layer 112a, the side of insulating layer 110, the side of conductive layer 116_2, and the side of conductive layer 112b2.
  • Insulating layer 110s2b is provided to face the top surface of conductive layer 112a, the side of insulating layer 110, the side of conductive layer 116_2, and the side of conductive layer 112b2 via insulating layer 110s2a.
  • the materials and manufacturing methods used for insulating layers 110a1, 110a3, 110b1, and 110b3 can be applied to insulating layers 110s1a and 110s2a.
  • the materials and manufacturing methods used for insulating layers 110a2 and 110b2 can be applied to insulating layers 110s1b and 110s2b. That is, a material that is difficult for oxygen to permeate can be used for insulating layers 110s1a and 110s2a, and a material that contains oxygen and releases oxygen when heated can be used for insulating layers 110s1b and 110s2b.
  • the conductive layer 112a and the conductive layer 112b1 are oxidized by the oxygen released from the insulating layer 110s1, and there is a concern that the amount of oxygen supplied from the insulating layer 110s1 to the semiconductor layer 108 is reduced.
  • the insulating layer 110s1 As in the transistor 10A_1, by forming the insulating layer 110s1 into a stacked structure of the insulating layer 110s1a and the insulating layer 110s1b, it is possible to configure the insulating layer 110s1b that releases oxygen to be not in contact with the conductive layer 112a and the conductive layer 112b1. This makes it possible to suppress the oxidation of the conductive layer 112a and the conductive layer 112b1 by the oxygen released from the insulating layer 110s1b. In addition, it is possible to suppress a decrease in the amount of oxygen supplied from the insulating layer 110s1b to the semiconductor layer 108.
  • the insulating layer 110s2 that releases oxygen is in contact with the conductive layer 112a and the conductive layer 112b2
  • the conductive layer 112a and the conductive layer 112b2 are oxidized by the oxygen released from the insulating layer 110s2, and the amount of oxygen supplied from the insulating layer 110s2 to the semiconductor layer 108 is reduced.
  • the transistor 10A_2 by forming the insulating layer 110s2 into a stacked structure of the insulating layer 110s2a and the insulating layer 110s2b, the insulating layer 110s2b that releases oxygen is not in contact with the conductive layer 112a and the conductive layer 112b2.
  • semiconductor device 100A for anything other than the above, the contents described for semiconductor device 100 can be referred to.
  • ⁇ Configuration Example 3 of Semiconductor Device> 6B shows a configuration example of a semiconductor device 100B according to one embodiment of the present invention, which is a cross-sectional view of the semiconductor device 100B taken along dashed dotted line A1-A2 in the plan view of the semiconductor device 100 shown in FIG.
  • the semiconductor device 100B has a transistor 10B_1, a transistor 10B_2, an insulating layer 110a, and an insulating layer 110b.
  • the semiconductor device 100B differs from the semiconductor device 100 shown in FIG. 1B in that the semiconductor device 100B has a transistor 10B_1 instead of a transistor 10_1, and a transistor 10B_2 instead of a transistor 10_2.
  • Transistor 10B_1 differs from transistor 10_1 in that it has an insulating layer 110g1 between conductive layer 116_1 and insulating layer 110s1.
  • Transistor 10B_2 differs from transistor 10_2 in that it has an insulating layer 110g2 between conductive layer 116_2 and insulating layer 110s2.
  • the insulating layer 110g1 and the insulating layer 110g2 each have, for example, an oxide of an element contained in the conductive layer 116_1 and the conductive layer 116_2. If the conductive layer 116_1 and the conductive layer 116_2 are metal, the insulating layer 110g1 and the insulating layer 110g2 are, for example, an oxide of the metal. If the conductive layer 116_1 and the conductive layer 116_2 are silicon, the insulating layer 110g1 and the insulating layer 110g2 are, for example, a silicon oxide. For the insulating layer 110g1 and the insulating layer 110g2, for example, a metal oxide such as aluminum oxide or tantalum oxide can be used, and it is particularly preferable to use aluminum oxide.
  • the insulating layer 110g1 can function as a gate insulating layer for the transistor 10B_1.
  • a stacked structure of the insulating layer 110s1 and the insulating layer 110g1 functions as a gate insulating layer for the transistor 10B_1.
  • the insulating layer 110g2 can function as a gate insulating layer for the transistor 10B_2.
  • a stacked structure of the insulating layer 110s2 and the insulating layer 110g2 functions as a gate insulating layer for the transistor 10B_2.
  • the transistor 10B_1 since a laminated structure of the insulating layer 110s1 and the insulating layer 110g1 is used as the gate insulating layer, even if the insulating property of the insulating layer 110g1 is lower than that of the insulating layer 110s1, if sufficient insulating property is obtained by laminating the insulating layer 110s1, the electrical characteristics and reliability of the transistor 10B_1 may be sufficiently ensured.
  • the transistor 10B_2 since a laminated structure of the insulating layer 110s2 and the insulating layer 110g2 is used as the gate insulating layer, even if the insulating property of the insulating layer 110g2 is lower than that of the insulating layer 110s2, if sufficient insulating property is obtained by laminating the insulating layer 110s2, the electrical characteristics and reliability of the transistor 10B_2 may be sufficiently ensured.
  • the thickness of the insulating layer 110s1 may be reduced.
  • the effect of the electric field applied from the gate electrode (conductive layer 116_1) of the transistor 10B_1 to the semiconductor layer 108 may be strengthened.
  • the thickness of the insulating layer 110s2 may be reduced.
  • the effect of the electric field applied from the gate electrode (conductive layer 116_2) of the transistor 10B_2 to the semiconductor layer 108 may be strengthened.
  • a material having a higher relative dielectric constant than the material used for the insulating layer 110s1 and the insulating layer 110s2 may be preferably used as the insulating layer 110g1 and the insulating layer 110g2.
  • the insulating layer 110g1 can be formed in a self-aligning manner, for example, by forming a layer capable of supplying oxygen so as to be in contact with the surface of the conductive layer 116_1, and oxidizing the surface of the conductive layer 116_1 by oxygen supply from the insulating layer 110a2 and the insulating layer 110b2 through the layer.
  • the transistor 10B_1 can suppress leakage between the semiconductor layer 108 and the conductive layer 116_1 by having the insulating layer 110g1.
  • the insulating layer 110g2 can be formed in a self-aligned manner, for example, by forming a layer capable of supplying oxygen so as to be in contact with the surface of the conductive layer 116_2, and oxidizing the surface of the conductive layer 116_2 by oxygen supply from the insulating layer 110a2 and the insulating layer 110b2 through the layer.
  • the transistor 10B_2 can suppress leakage between the semiconductor layer 108 and the conductive layer 116_2 by having the insulating layer 110g2.
  • semiconductor device 100B other than the above, the contents described for semiconductor device 100 can be referred to.
  • ⁇ Configuration Example 4 of Semiconductor Device> 7A shows a configuration example of a semiconductor device 100C according to one embodiment of the present invention, which is a cross-sectional view of the semiconductor device 100C taken along dashed dotted line A1-A2 in the plan view of the semiconductor device 100 shown in FIG.
  • the semiconductor device 100C has a transistor 10C_1, a transistor 10C_2, an insulating layer 110a, and an insulating layer 110b.
  • the semiconductor device 100C differs from the semiconductor device 100 shown in FIG. 1B in that it has a transistor 10C_1 instead of a transistor 10_1, and a transistor 10C_2 instead of a transistor 10_2.
  • Transistor 10C_1 differs from transistor 10_1 in the configuration of insulating layer 110s1.
  • Transistor 10C_2 differs from transistor 10_2 in the configuration of insulating layer 110s2.
  • transistor 10C_1 the bottom surface of insulating layer 110s1 is in contact with the top surface of insulating layer 110a1, and the side surface of insulating layer 110a1 is in contact with semiconductor layer 108. That is, in transistor 10C_1, insulating layer 110s1 is not in contact with conductive layer 112a.
  • transistor 10C_2 the bottom surface of insulating layer 110s2 is in contact with the top surface of insulating layer 110a1, and the side surface of insulating layer 110a1 is in contact with semiconductor layer 108. That is, in transistor 10C_2, insulating layer 110s2 is not in contact with conductive layer 112a.
  • the insulating layer 110s1 and the insulating layer 110s2, together with the insulating layer 110a2 and the insulating layer 110b2, can have the function of supplying oxygen to the semiconductor layer 108. Therefore, in the case of a configuration in which the bottom surfaces of the insulating layer 110s1 and the insulating layer 110s2 are in contact with the conductive layer 112a, as in the case of the transistors 10_1 and 10_2, the oxygen diffused from the insulating layer 110s1 and the insulating layer 110s2 may oxidize a part of the top surface of the conductive layer 112a, causing the conductive layer 112a to become highly resistant, which may induce a defect that reduces the on-current of the transistor.
  • semiconductor device 100C other than the above, the contents described for semiconductor device 100 can be referred to.
  • ⁇ Configuration Example 5 of Semiconductor Device> 7B shows a configuration example of a semiconductor device 100D according to one embodiment of the present invention, which is a cross-sectional view of the semiconductor device 100D taken along dashed dotted line A1-A2 in the plan view of the semiconductor device 100 shown in FIG.
  • the semiconductor device 100D has a transistor 10D_1, a transistor 10D_2, an insulating layer 110a, and an insulating layer 110b.
  • the contents described above for the transistors 10A_1 and 10A_2 can be applied to the transistors 10D_1 and 10D_2, respectively.
  • the semiconductor device 100D differs from the semiconductor device 100 shown in FIG. 1B in the configuration of the insulating layer 110.
  • the semiconductor device 100D differs from the semiconductor device 100 in that the insulating layer 110a and the insulating layer 110b each have a single-layer structure.
  • the single-layer insulating layer 110a and the insulating layer 110b it is preferable to use a material that can be used for the insulating layer 110a1, the insulating layer 110a3, the insulating layer 110b1, and the insulating layer 110b3, respectively. That is, it is preferable to use a material that has high blocking properties against oxygen and hydrogen. This can prevent the conductive layer 116_1 and the conductive layer 116_2 from being oxidized due to the diffusion of oxygen from the outside of the insulating layer 110a and the insulating layer 110b.
  • the insulating layers 110s1 and 110s2 have the function of releasing oxygen, even if the insulating layer 110 has the above-mentioned configuration, oxygen can be supplied to the semiconductor layer 108.
  • the number of insulating layers constituting the insulating layer 110 can be significantly reduced, and therefore, compared to the semiconductor device 100 and the like, the number of steps related to the formation of the insulating layer 110 can be reduced.
  • semiconductor device 100D other than the above, the contents described for semiconductor device 100 can be referred to.
  • ⁇ Configuration Example 6 of Semiconductor Device> 8A shows a configuration example of a semiconductor device 100E according to one embodiment of the present invention, which is a cross-sectional view of the semiconductor device 100E taken along dashed dotted line A1-A2 in the plan view of the semiconductor device 100 shown in FIG.
  • the semiconductor device 100E has a transistor 10E_1, a transistor 10E_2, an insulating layer 110a, and an insulating layer 110b.
  • the semiconductor device 100E differs from the semiconductor device 100 shown in FIG. 1B in that the semiconductor device 100E has a transistor 10E_1 instead of a transistor 10_1, and a transistor 10E_2 instead of a transistor 10_2.
  • Transistor 10E_1 differs from transistor 10_1 in that it does not have conductive layer 112b1 and that the end of the semiconductor layer 108 on the A1 side extends to the outside of conductive layer 116_1 and conductive layer 112a.
  • Transistor 10E_2 differs from transistor 10_2 in that it does not have conductive layer 112b2 and that the end of the semiconductor layer 108 on the A2 side extends to the outside of conductive layer 116_2 and conductive layer 112a.
  • the semiconductor layer 108 has a region in contact with the top surface of the conductive layer 112a, the side surface of the insulating layer 110s1, the curved portion of the insulating layer 110s1, and the top surface of the insulating layer 110.
  • the semiconductor layer 108 can function as a semiconductor layer having a channel formation region and as the other of the source electrode and drain electrode.
  • the region of the semiconductor layer 108 that overlaps with the insulating layer 110s1 can function as the channel formation region.
  • the region located outside the opening 143 can function as the other of the source electrode and drain electrode.
  • the semiconductor layer 108 has a region in contact with the top surface of the conductive layer 112a, the side surface of the insulating layer 110s2, the curved portion of the insulating layer 110s2, and the top surface of the insulating layer 110.
  • the semiconductor layer 108 can function as a semiconductor layer having a channel formation region and as the other of the source electrode and drain electrode.
  • the region of the semiconductor layer 108 that overlaps with the insulating layer 110s2 can function as the channel formation region.
  • the region located outside the opening 143 can function as the other of the source electrode and drain electrode.
  • the semiconductor layer 108 can be made low-resistance by supplying impurities such as boron to the semiconductor layer 108 from a direction perpendicular to the substrate surface using ion implantation, ion doping, plasma immersion ion implantation, plasma treatment, or the like.
  • impurities such as boron
  • a silicon nitride film or the like can be formed on a region of the semiconductor layer 108 that does not overlap with the opening 143 to make the region an oxide conductor (OC), thereby forming a low-resistance region in the semiconductor layer 108.
  • OC oxide conductor
  • the channel formation region and the source region and drain region having lower resistance than the channel formation region can be separately formed in the semiconductor layer 108.
  • regions corresponding to the source electrode and drain electrode can be formed in the semiconductor layer 108 without providing the conductive layers 112b1 and 112b2, respectively. Therefore, since the conductive layers 112b1 and 112b2 are not provided in the transistors 10E_1 and 10E_2, respectively, the number of steps required for manufacturing the transistors can be reduced.
  • semiconductor device 100E other than the above, the contents described for semiconductor device 100 can be referred to.
  • ⁇ Configuration Example 7 of Semiconductor Device> 8B shows a configuration example of a semiconductor device 100F according to one embodiment of the present invention, which is a cross-sectional view of the semiconductor device 100F taken along dashed dotted line A1-A2 in the plan view of the semiconductor device 100 shown in FIG.
  • the semiconductor device 100F has a transistor 10F_1, a transistor 10F_2, an insulating layer 110a, and an insulating layer 110b.
  • the semiconductor device 100F differs from the semiconductor device 100 shown in FIG. 1B in that the semiconductor device 100F has a transistor 10F_1 instead of a transistor 10_1, and a transistor 10F_2 instead of a transistor 10_2.
  • Transistors 10F_1 and 10F_2 differ from transistors 10_1 and 10_2, respectively, in that they do not have a conductive layer 104 that functions as a backgate electrode. That is, transistor 10F_1 can be said to be a transistor that has only one conductive layer (conductive layer 116_1) that functions as a gate electrode. Similarly, transistor 10F_2 can be said to be a transistor that has only one conductive layer (conductive layer 116_2) that functions as a gate electrode. Therefore, since transistors 10F_1 and 10F_2 do not have a conductive layer 104, the number of steps involved in manufacturing the transistors can be reduced.
  • semiconductor device 100F other than the above, the contents described for semiconductor device 100 can be referred to.
  • the semiconductor device of one embodiment of the present invention can be applied to a display device.
  • the semiconductor device can be applied to a liquid crystal display device.
  • a specific configuration example in which the semiconductor device 100 shown in FIG. 1A and FIG. 1B is applied to a liquid crystal display device will be described.
  • Note that a configuration example in which the semiconductor device of one embodiment of the present invention is applied to a display device will also be described in detail in Embodiment 2.
  • FIG. 9A shows a plan view of a portion of a pixel of a display device.
  • FIG. 9B shows a cross-sectional view taken along dashed line P1-P2 shown in FIG. 9A. Note that some of the components of the display device (insulating layers, etc.) are omitted in FIG. 9A.
  • the display device of one embodiment of the present invention is a liquid crystal display device having a semiconductor device 100 and a liquid crystal element 30 between a substrate 102 and a substrate 12.
  • a part of the semiconductor device 100 overlaps with an intersection between the conductive layer 116_1 and the conductive layer 112a, and another part of the semiconductor device 100 is provided to have an area that overlaps with an intersection between the conductive layer 116_2 and the conductive layer 112a.
  • the conductive layer 112a which functions as one of the source electrodes or drain electrodes of the transistor 10_1 and the transistor 10_2, functions as a signal line.
  • the details of the transistor 10_1, the transistor 10_2, the insulating layer 110a (insulating layer 110a1, insulating layer 110a2, and insulating layer 110a3), and the insulating layer 110b (insulating layer 110b1, insulating layer 110b2, and insulating layer 110b3) included in the semiconductor device 100 can be referred to in the above description.
  • the details of the configuration of the semiconductor device 100 can be referred to in the above description, and therefore may not be described below.
  • the liquid crystal element 30 includes one of the conductive layers 112b1 and 112b2 (each of which also functions as the other of the source electrode or drain electrode of the transistor 10_1 and the transistor 10_2) functioning as a pixel electrode, a conductive layer 32 functioning as a common electrode, a conductive layer 104 (which also functions as the backgate electrode of the transistor 10_1 and the transistor 10_2) functioning as a capacitance electrode, and a liquid crystal 33.
  • the liquid crystal element 30 shown in FIG. 9B is a liquid crystal element to which the VA mode is applied.
  • FIG. 9B only the liquid crystal element 30 composed of the conductive layer 112b2, the liquid crystal 33, and the conductive layer 32 is shown, but since the semiconductor device 100 has two transistors, one semiconductor device 100 can have two liquid crystal elements. That is, in addition to the liquid crystal element described above, a liquid crystal element (not shown) composed of the conductive layer 112b1, the liquid crystal 33, and the conductive layer 32 can be included.
  • An insulating layer 46 that functions as a spacer is provided on the region of the insulating layer 195 that overlaps with the semiconductor device 100.
  • a photosensitive resin can be used as the insulating layer 46.
  • the insulating layer 46 can be formed by forming a photosensitive resin on the insulating layer 195, exposing it to light, and developing it.
  • the photosensitive resin can be a resin that has either negative or positive photosensitivity.
  • the insulating layer 46 has the function of controlling the distance between the substrate 102 and the substrate 12, and controlling the thickness of the liquid crystal 33. Furthermore, it is preferable that the insulating layer 46 is provided so as to fill the depression in the upper surface of the insulating layer 195 caused by the opening 143. By providing the insulating layer 46 so as to overlap the semiconductor device 100, it is possible to prevent a decrease in the aperture ratio caused by providing the insulating layer 46.
  • the area of the semiconductor device 100 in plan view can be made extremely small, the area of the insulating layer 46 disposed in the area overlapping with the semiconductor device 100 is also made small. Therefore, if the strength as a spacer is insufficient, it is preferable to dispose the insulating layer 46 in all subpixels. This ensures sufficient strength even with an insulating layer 46 having a small area.
  • the insulating layer 46 is provided on the substrate 102 side, but it may be provided on the substrate 12 side. In this case, the alignment film 41 may be provided in contact with the portion of the insulating layer 195 that overlaps with the semiconductor device 100. The insulating layer 46 may also be provided on both the substrate 102 side and the substrate 12 side.
  • the conductive layer 104 which functions as a capacitance electrode, has an area that overlaps with the conductive layer 112b1 or the conductive layer 112b2 via the insulating layer 106.
  • the area where the conductive layer 104, the insulating layer 106, and the conductive layer 112b1 (or the conductive layer 112b2) are stacked functions as a storage capacitance of the pixel.
  • the conductive layer 104 and the conductive layer 112b1 (or the conductive layer 112b2) function as a pair of electrodes of the capacitance
  • the insulating layer 106 functions as a dielectric of the capacitance.
  • An alignment film 41 is provided covering the insulating layer 46 and the insulating layer 195.
  • the conductive layer 104 of the semiconductor device 100 functions as a backgate electrode of the transistors 10_1 and 10_2 and as a capacitor electrode of the liquid crystal element 30.
  • the insulating layer 106 of the semiconductor device 100 functions as a backgate insulating layer of the transistors 10_1 and 10_2 and as a dielectric of the capacitor of the liquid crystal element 30.
  • the pixel electrode of the liquid crystal element 30 is required to have light-transmitting properties. Therefore, it is preferable to use a conductor that is transparent to visible light for the conductive layer 112b1 and the conductive layer 112b2 of the semiconductor device 100.
  • conductive oxides such as indium oxide, zinc oxide, In-Sn oxide, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn oxide containing silicon, and zinc oxide doped with gallium can be used.
  • conductive oxides containing indium are preferable because of their high conductivity.
  • the capacitor electrode having an area overlapping with the pixel electrode is also required to have light-transmitting properties. Therefore, it is preferable to use a conductor that is light-transmitting to visible light for the conductive layer 104 of the semiconductor device 100.
  • a conductor that is light-transmitting to visible light for the conductive layer 104 of the semiconductor device 100.
  • the above-mentioned conductive material having light-transmitting properties that can be used for the conductive layer 112b1 and the conductive layer 112b2 can be used.
  • a colored layer 43, a light-shielding layer 44, an insulating layer 45, a conductive layer 32, and an alignment film 42 are provided on the surface of the substrate 12 facing the substrate 102.
  • the alignment film 42 may have a portion that contacts the alignment film 41 in a portion that overlaps with the insulating layer 46. Note that either or both of the alignment films 41 and 42 may not be provided if they are not required.
  • the portion where the light-shielding layer 44 is provided becomes a non-light-emitting region.
  • the light-shielding layer 44 can be provided in the region that covers the semiconductor device 100.
  • the area of the non-light-emitting region where the light-shielding layer 44 is provided can be significantly reduced compared to the conventional art.
  • the colored layer 43 can also be called a color filter, and converts light from a light source such as a backlight into light exhibiting a specific color.
  • a full-color display can be achieved by applying colored layers 43 corresponding to red, green, and blue to each pixel (sub-pixel) as the colored layer. It is preferable to provide pixels (sub-pixels) corresponding to colors such as yellow and white in addition to these three colors, as this can reduce power consumption. In the case of white pixels, a configuration without providing a color filter to the pixel can be adopted.
  • blue or purple light may be used as the light source, and a color conversion material that converts the blue or purple light to another color (e.g., red, green, etc.) may be applied to the colored layer 43.
  • the color conversion material may be a fluorescent material, a phosphorescent material, or a resin material with quantum dots dispersed therein.
  • the colored layer 43 has a laminated structure of a color conversion material and a color filter from the backlight side so as to absorb the light that has passed through the color conversion material.
  • the insulating layer 45 functions as an overcoat that prevents the components contained in the colored layer 43, etc. from diffusing into the liquid crystal 33.
  • the insulating layer 45 also functions as a planarizing film.
  • the insulating layer 45 can be formed using an organic resin that is translucent.
  • the conductive layer 32 that functions as a common electrode is required to have light-transmitting properties.
  • the conductive layer 32 can be made of a conductive material having light-transmitting properties that can be used for the conductive layer 112b1, the conductive layer 112b2, and the conductive layer 104 described above.
  • Substrate 102 and substrate 12 are bonded together by an adhesive layer (not shown) that is provided outside the display section.
  • the distance between substrate 102 and substrate 12 is controlled by insulating layer 46, which functions as a spacer.
  • the liquid crystal element 30 is shown to have pixel electrodes disposed on the substrate 102 side, and an electric field is applied to the liquid crystal 33 in a direction perpendicular to the thickness direction.
  • the method of arranging the electrodes is not limited to this, and a method of applying an electric field to the liquid crystal 33 in a direction parallel to the thickness direction may also be used.
  • liquid crystal element 30 elements of various configurations can be used. Representative examples include VA (Vertical Alignment) mode, FFS (Fringe Field Switching) mode, and IPS (In-Plane Switching) mode.
  • VA Vertical Alignment
  • FFS Flexible Field Switching
  • IPS In-Plane Switching
  • the liquid crystal display device may be not only a transmissive type, but also a reflective type or semi-transmissive type.
  • VA modes that can be used for the liquid crystal element 30 include MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, and ASV (Advanced Super View) mode.
  • liquid crystal elements 30 may be used that use various other modes.
  • liquid crystal elements that use TN (Twisted Nematic) mode, ASM (Axially Symmetrically Aligned Micro-cell) mode, OCB (Opticaly Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, ECB (Electrically Controlled Birefringence) mode, guest host mode, etc. may be used.
  • the liquid crystal display device is a display device that controls the transmission or non-transmission of light by utilizing the optical modulation action of polarized light and liquid crystal.
  • the optical modulation action of liquid crystal is controlled by an electric field (including a horizontal electric field, a vertical electric field, or an oblique electric field) applied to the liquid crystal.
  • Examples of liquid crystals that can be used in liquid crystal elements include thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, polymer dispersed liquid crystals (PDLC: Polymer Dispersed Liquid Crystal), polymer network liquid crystals (PNLC: Polymer Network Liquid Crystal), ferroelectric liquid crystals, and antiferroelectric liquid crystals.
  • liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, and the like, depending on the conditions.
  • positive liquid crystals or negative liquid crystals may be used as the liquid crystal material, and the most suitable liquid crystal material may be used depending on the mode or design to be applied.
  • a polarizing plate is provided on each of the outer surfaces of substrate 102 and substrate 12. Furthermore, a backlight is provided on the outer side of substrate 102. In this case, the substrate 12 side becomes the display surface side.
  • a light-shielding conductive material for either the conductive layer 112a or the conductive layer 104, light reaching the channel formation region of the transistors (transistor 10_1 and transistor 10_2) included in the semiconductor device 100 can be blocked, thereby improving the reliability of the transistors. In particular, the variation in threshold voltage in the NBTIS test can be reduced.
  • the conductive layer 112a and the conductive layer 104 it is preferable to use a light-shielding conductive material for at least the conductive layer on the side where the backlight is provided.
  • the display device of one embodiment of the present invention has such a configuration, making it possible to realize a liquid crystal display device with an extremely high aperture ratio.
  • the transistors 10_1 and 10_2 included in the semiconductor device 100 can each be applied to a transistor connected to a pixel electrode of a pixel.
  • the transistors 10_1 and 10_2 included in the semiconductor device 100 can also each be applied to a scanning line driver circuit, a signal line driver circuit, a protection circuit, and other circuits other than pixel circuits.
  • the semiconductor device according to one embodiment of the present invention can be applied to, for example, a display device.
  • the semiconductor device according to one embodiment of the present invention has a configuration in which two vertical transistors that share a part of the components (one of the source electrode or drain electrode, the semiconductor layer, etc.) are provided facing each other. Therefore, by narrowing the interval between the transistors, it is possible to achieve a higher integration of the transistors in the substrate surface than when a plurality of vertical transistors each having an individual component are formed.
  • a line-shaped opening is provided in a layer (for example, three layers of an insulating layer, a conductive layer, and an insulating layer) stacked on a conductive layer, and two vertical transistors that use the opposing sidewall depth direction of the opening as the channel length direction are formed, so that the interval between the two vertical transistors can be made extremely narrow.
  • a layer for example, three layers of an insulating layer, a conductive layer, and an insulating layer
  • two vertical transistors that use the opposing sidewall depth direction of the opening as the channel length direction are formed, so that the interval between the two vertical transistors can be made extremely narrow.
  • the thin films (insulating films, semiconductor films, conductive films, etc.) that make up the semiconductor device can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, etc.
  • CVD chemical vapor deposition
  • PLD pulsed laser deposition
  • ALD atomic layer deposition
  • Sputtering methods include RF sputtering, which uses a high-frequency power source as the sputtering power source, DC sputtering, which uses a direct current power source, and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner.
  • RF sputtering is mainly used when depositing insulating films
  • DC sputtering is mainly used when depositing metal conductive films.
  • Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, or carbides using the reactive sputtering method.
  • CVD methods can be classified into plasma CVD (PECVD) which uses plasma, thermal CVD (TCVD: Thermal CVD) which uses heat, and photo CVD (Photo CVD) which uses light. Furthermore, depending on the source gas used, they can be divided into metal CVD (MCVD: Metal CVD) and metal organic CVD (MOCVD: Metal Organic CVD).
  • PECVD plasma CVD
  • TCVD Thermal CVD
  • Photo CVD Photo CVD
  • MCVD Metal CVD
  • MOCVD Metal Organic CVD
  • the plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is a film formation method that can reduce plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, in the case of thermal CVD method, which does not use plasma, such plasma damage does not occur, and therefore the yield of semiconductor devices can be increased. Furthermore, because no plasma damage occurs during film formation with thermal CVD method, films with fewer defects can be obtained.
  • the ALD method can be a thermal ALD method in which the reaction between the precursor and reactant is carried out using only thermal energy, or a PEALD method in which a plasma-excited reactant is used.
  • the CVD and ALD methods are different from sputtering methods in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable, for example, for coating the surface of an opening with a high aspect ratio.
  • the ALD method since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.
  • a film of any composition can be formed by changing the flow rate ratio of the raw material gases.
  • a film with a continuously changing composition can be formed by changing the flow rate ratio of the raw material gases while forming the film.
  • the ALD method by simultaneously introducing multiple different types of precursors, it is possible to deposit a film of any composition. Or, when multiple different types of precursors are introduced, it is possible to deposit a film of any composition by controlling the number of cycles of each precursor.
  • the thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.
  • the thin film that constitutes the semiconductor device When processing the thin film that constitutes the semiconductor device, it can be processed using a photolithography method or the like.
  • the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method, or the like.
  • island-shaped thin films may be directly formed using a film formation method that uses a shielding mask such as a metal mask.
  • the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light such as ultraviolet light, KrF laser light, or ArF laser light can also be used.
  • Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. Electron beams can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or electron beams are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.
  • etching the thin film for example, dry etching, wet etching, or sandblasting can be used.
  • FIGS 10A to 18D are diagrams for explaining a method for manufacturing the semiconductor device 100.
  • a in each figure shows a plan view corresponding to Figure 1A.
  • B in each figure shows a cross-sectional view taken along dashed line A1-A2 in the plan view shown in Figure 1A.
  • C in each figure shows a cross-sectional view taken along dashed line B1-B2 in the plan view shown in Figure 1A.
  • D in each figure shows a cross-sectional view taken along dashed line C1-C2 in the plan view shown in Figure 1A.
  • a conductive film that will become the conductive layer 112a is formed on the substrate 102, and then a part of the conductive film is removed to form the conductive layer 112a (FIGS. 10A to 10D).
  • the conductive film can be formed by, for example, a sputtering method.
  • the conductive film can be processed by one or both of a wet etching method and a dry etching method.
  • insulating film 110a1f is formed on conductive layer 112a and substrate 102
  • insulating film 110a2f is formed on insulating film 110a1f
  • insulating film 110a3f is formed on insulating film 110a2f.
  • the insulating film 110a1f and insulating film 110a3f can be made of any of the materials that can be used for the insulating layer 110a1 and insulating layer 110a3 described above.
  • the insulating film 110a1f and the insulating film 110a3f for example, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, or the like can be suitably used.
  • a silicon nitride film can be formed as the insulating film 110a1f and the insulating film 110a3f by using a sputtering method.
  • a silicon nitride film can be formed by using a PEALD method.
  • an aluminum oxide film can be formed by using a sputtering method.
  • a laminated structure of aluminum oxide and silicon nitride can be used.
  • a laminated structure of aluminum oxide formed by sputtering and silicon nitride formed by PEALD can be used.
  • the insulating film 110a2f can be made of any of the materials that can be used for the insulating layer 110a2 described above.
  • silicon oxide, silicon oxynitride, etc. can be suitably used as the insulating film 110a2f.
  • a silicon oxide film can be formed, for example, by using a sputtering method.
  • a silicon oxide film can be formed, for example, by using a PECVD method.
  • a silicon oxynitride film can be formed, for example, by using a PECVD method.
  • a silicon oxide film formed by sputtering and a silicon oxide or silicon oxynitride film formed by PECVD can be stacked together.
  • a heat treatment may be performed. By performing the heat treatment, water and hydrogen can be removed from the surface and inside of the insulating film 110a2f.
  • the temperature of the heat treatment is preferably 150°C or higher and lower than the distortion point of the substrate, more preferably 200°C or higher and 450°C or lower, even more preferably 250°C or higher and 450°C or lower, even more preferably 300°C or higher and 450°C or lower, even more preferably 300°C or higher and 400°C or lower, and even more preferably 350°C or higher and 400°C or lower.
  • the heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. Dry air (CDA: Clean Dry Air) may be used as the atmosphere containing nitrogen or the atmosphere containing oxygen. It is preferable that the content of hydrogen, water, etc. in the atmosphere is as small as possible.
  • a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere.
  • an atmosphere containing as little hydrogen, water, etc. as possible it is possible to prevent hydrogen, water, etc. from being taken into the insulating film 110a2f as much as possible.
  • an oven or a rapid thermal annealing (RTA) device can be used for the heat treatment. By using an RTA device, the heat treatment time can be shortened.
  • a step of supplying oxygen to the insulating film 110a2f may be performed.
  • a metal oxide layer may be formed over the insulating film 110a2f to supply oxygen to the insulating film 110a2f.
  • heat treatment may be performed after the metal oxide layer is formed.
  • oxygen can be effectively supplied from the metal oxide layer to the insulating film 110a2f and oxygen can be contained in the insulating film 110a2f.
  • the oxygen supplied to the insulating film 110a2f is supplied to the semiconductor layer 108 in a later step, whereby oxygen vacancies ( VO ) and VOH in the semiconductor layer 108 can be reduced.
  • oxygen may be further supplied to the insulating film 110a2f through the metal oxide layer.
  • an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or a plasma treatment can be used as a method for supplying oxygen.
  • an apparatus that turns oxygen gas into plasma by high-frequency power can be preferably used.
  • a plasma etching apparatus and a plasma ashing apparatus can be used as an apparatus that turns gas into plasma by high-frequency power.
  • the metal oxide layer may be an insulating layer or a conductive layer.
  • aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-doped indium tin oxide (ITSO) may be used for the metal oxide layer.
  • the metal oxide layer it is preferable to use an oxide material that contains one or more of the same elements as the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material that can be applied to the semiconductor layer 108.
  • a material having a higher gallium composition (content) than the semiconductor layer 108 can be used.
  • a material having a higher gallium composition (content) for the metal oxide layer the blocking property against oxygen can be further improved. This is preferable because it can prevent oxygen supplied to the insulating film 110a2f from being released to the outside through the metal oxide layer.
  • the metal oxide layer is preferably formed, for example, in an atmosphere containing oxygen.
  • it is preferably formed by a sputtering method in an atmosphere containing oxygen. This allows oxygen to be suitably supplied to the insulating film 110a2f when the metal oxide layer is formed.
  • the metal oxide layer is removed.
  • a wet etching method can be suitably used for removing the metal oxide layer.
  • the process of supplying oxygen to the insulating film 110a2f is not limited to the above-mentioned method.
  • oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, and the like are supplied to the insulating film 110a2f by ion doping, ion implantation, plasma treatment, or the like.
  • oxygen may be supplied to the insulating film 110a2f through the film. It is preferable to remove the film after supplying oxygen.
  • a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten can be used.
  • a conductive film 116f is formed on the insulating film 110a3f (FIGS. 11A to 11D).
  • a sputtering method can be suitably used to form the conductive film 116f.
  • the conductive film 116f is processed to form a conductive layer 116e on the insulating film 110a3f so as to have an area overlapping with the conductive layer 112a (FIGS. 12A to 12D).
  • a wet etching method can be suitably used to form the conductive layer 116e.
  • insulating film 110b3f is formed on insulating film 110a3f and conductive layer 116e
  • insulating film 110b2f is formed on insulating film 110b3f
  • insulating film 110b1f is formed on insulating film 110b2f.
  • the insulating film 110b2f may be made of any of the materials that can be used for the insulating layer 110b2 described above.
  • the insulating film 110b1f and the insulating film 110b3f may be made of any of the materials that can be used for the insulating layer 110b1 and the insulating layer 110b3 described above.
  • insulating film 110b2f For materials and deposition methods that can be used for the insulating film 110b2f, refer to the description of the insulating film 110a2f.
  • materials and deposition methods that can be used for the insulating films 110b1f and 110b3f refer to the descriptions of the insulating films 110a1f and 110a3f.
  • a step of supplying oxygen to the insulating film 110b2f may be performed.
  • the description of the step of supplying oxygen to the insulating film 110a2f described above can be referred to.
  • a conductive film 112bf is formed on the insulating film 110b1f (FIGS. 13A to 13D).
  • a sputtering method can be suitably used to form the conductive film 112bf.
  • the conductive film 112bf any of the materials that can be used for the conductive layer 112b1 and the conductive layer 112b2 described above can be appropriately used.
  • the conductive film 112bf is processed to form the conductive layer 112be (FIGS. 14A to 14D).
  • the conductive layer 112be is formed to have an area overlapping with the conductive layer 116e and the conductive layer 112a.
  • wet etching can be suitably used to form the conductive layer 112be.
  • Opening 143 is formed in a line shape in a direction parallel to dashed line B1-B2 in a plan view.
  • the conductive layer 112b1 and the conductive layer 112b2 are formed from the conductive layer 112be, the insulating layer 110b1 is formed from the insulating film 110b1f, the insulating layer 110b2 is formed from the insulating film 110b2f, the insulating layer 110b1 is formed from the insulating film 110b1f, the conductive layer 116_1 and the conductive layer 116_2 are formed from the conductive layer 116e, the insulating layer 110a3 is formed from the insulating film 110a3f, the insulating layer 110a2 is formed from the insulating film 110a2f, and the insulating layer 110a1 is formed from the insulating film 110a1f.
  • a dry etching method can be suitably used to form the opening 143.
  • the conductive layer 112a may have a recess in a region overlapping with the opening 143. This allows the semiconductor layer 108 and the conductive layer 104 to be provided even in the recess, and therefore the electric field of the back gate electrode applied to the semiconductor layer 108 in the vicinity of the conductive layer 112a can be strengthened. This allows the on-current of the transistors 10_1 and 10_2 to be increased. For example, when the opening 143 is formed, etching is performed so that a part of the top surface of the conductive layer 112a is removed, thereby forming the conductive layer 112a having the recess.
  • an insulating film 110sf is formed so as to cover the opening 143 (FIGS. 16A to 16D).
  • the insulating film 110sf is provided in contact with the upper surface of the conductive layer 112b1, the upper surface of the conductive layer 112b2, the side surface of the conductive layer 112b1 in the opening 143, the side surface of the conductive layer 112b2 in the opening 143, the side surface of the insulating layer 110 (insulating layer 110a and insulating layer 110b) in the opening 143, the side surface of the conductive layer 116_1 in the opening 143, the side surface of the conductive layer 116_2 in the opening 143, the upper surface of the conductive layer 112a in the opening 143, the side surface of the conductive layer 112a in the opening 143, and the upper surface of the substrate 102 in the opening 143.
  • the insulating film 110sf can be made of any of the materials that can be used for the insulating layer 110s1 and the insulating layer 110s2 described above.
  • the insulating film 110sf By forming the insulating film 110sf using a CVD method, an ALD method, or the like, the insulating film 110sf can be effectively coated on the sidewall of the opening 143, which is preferable.
  • insulating film 110sf is removed by etching to form insulating layers 110s1 and 110s2 (FIGS. 17A to 17D). Specifically, the region of the insulating film 110sf that contacts the upper surface of the conductive layer 112a, the region that contacts the upper surface of the conductive layer 112b1, the region that contacts the upper surface of the conductive layer 112b2, and the region that contacts the upper surface of the substrate 102 are removed by etching to form insulating layer 110s1 that contacts the side of the conductive layer 112b1 in the opening 143, one side of the insulating layer 110 (insulating layer 110a and insulating layer 110b) in the opening 143, and the side of the conductive layer 116_1 in the opening 143, and insulating layer 110s2 that contacts the side of the conductive layer 112b2 in the opening 143, the other side of the insulating layer 110 in the opening 143, and the side of the conductive layer 116_
  • anisotropic etching can be used to etch the insulating film 110sf. More specifically, for example, highly anisotropic etching can be performed in dry etching to form the insulating layers 110s1 and 110s2.
  • a portion of the insulating film 110sf may remain on the side surfaces of the steps of the conductive layers 112b1 and 112b2 outside the opening 143.
  • a semiconductor film that will become the semiconductor layer 108 is formed so as to cover the opening 143.
  • the semiconductor film is provided in contact with the upper and side surfaces of the conductive layer 112a in the opening 143, the upper surface of the substrate 102 in the opening 143, the side surface of the insulating layer 110s1 in the opening 143, the side surface of the insulating layer 110s2 in the opening 143, the curved portion of the insulating layer 110s1, the curved portion of the insulating layer 110s2, the upper and side surfaces of the conductive layer 112b1, the upper and side surfaces of the conductive layer 112b2, and the upper surface of the insulating layer 110.
  • the semiconductor film that becomes the semiconductor layer 108 is preferably formed by a sputtering method using a metal oxide target.
  • the semiconductor film is preferably formed by an ALD method.
  • the ALD method has high coverage and can be suitably used to form the semiconductor film that covers the opening 143.
  • the semiconductor film can be formed with good coverage on the side surface of the insulating layer 110s1 and the side surface of the insulating layer 110s2.
  • the ALD method makes it easy to control the film formation speed, so a thin film can be formed with good yield.
  • the semiconductor film that becomes the semiconductor layer 108 is preferably a dense film with as few defects as possible.
  • the semiconductor film is preferably a high-purity film in which impurities including hydrogen elements are reduced as much as possible.
  • oxygen gas oxygen can be suitably supplied to the insulating layer 110s1 and the insulating layer 110s2.
  • oxygen gas oxygen can be suitably supplied to the insulating layer 110s1 and the insulating layer 110s2.
  • oxygen can be supplied to the channel formation region of the semiconductor layer 108 in a later step, and oxygen vacancies ( VO ) and VOH in the channel formation region can be reduced.
  • oxygen gas and an inert gas e.g., helium gas, argon gas, xenon gas, etc.
  • an inert gas e.g., helium gas, argon gas, xenon gas, etc.
  • the lower the oxygen flow ratio or the oxygen partial pressure the lower the crystallinity and the higher the electrical conductivity of the metal oxide film can be, and the higher the on-current of the transistor can be.
  • the metal oxide film may become polycrystalline.
  • the grain boundaries become the recombination center, and carriers may be captured, resulting in a small on-current of the transistor. Therefore, it is preferable to adjust the oxygen flow ratio or oxygen partial pressure so that the semiconductor film that becomes the semiconductor layer 108 does not become polycrystalline. Since the ease with which the metal oxide film becomes a polycrystalline structure differs depending on the composition, the oxygen flow ratio or oxygen partial pressure may be adjusted according to the composition of the semiconductor film.
  • the higher the substrate temperature when forming the metal oxide film the higher the crystallinity and the denser the metal oxide film will be.
  • the lower the substrate temperature the lower the crystallinity and the higher the electrical conductivity of the metal oxide film will be.
  • the substrate temperature during the formation of the semiconductor film that will become the semiconductor layer 108 is preferably from room temperature to 250°C, more preferably from room temperature to 200°C, and even more preferably from room temperature to 140°C.
  • a substrate temperature of from room temperature to 140°C is preferable because it increases productivity.
  • the crystallinity can be reduced.
  • the metal oxide film may have a polycrystalline structure. It is preferable to adjust the substrate temperature so that the semiconductor film that becomes the semiconductor layer 108 does not have a polycrystalline structure.
  • the substrate temperature can be adjusted according to the composition to be applied to the semiconductor film.
  • the thermal ALD method is preferable because it shows extremely high coating properties.
  • the PEALD method is preferable because it shows high coating properties and allows low-temperature film formation.
  • the metal oxide film can be formed, for example, by the ALD method using a precursor containing the constituent metal elements and an oxidizing agent.
  • three precursors can be used: a precursor containing indium, a precursor containing gallium, and a precursor containing zinc.
  • two precursors can be used: a precursor containing indium, and a precursor containing gallium and zinc.
  • precursors containing indium include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amide]-indium.
  • precursors containing gallium include trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, and diethylchlorogallium.
  • aluminum-containing precursors examples include aluminum chloride and trimethylaluminum.
  • precursors containing tin include tin(IV) chloride and tetrakis(dimethylamido)tin.
  • Examples of zinc-containing precursors include dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.
  • Oxidizing agents include, for example, ozone, oxygen, and water.
  • Methods for controlling the composition of the resulting film include adjusting one or more of the type of source gas, the flow rate ratio of the source gas, the time for which the source gas is flowed, and the order in which the source gas is flowed. By adjusting these, it is possible to control the composition of the semiconductor film that will become the semiconductor layer 108. In addition, by adjusting these, it is also possible to form a film whose composition changes continuously. It is also possible to configure the semiconductor film so that its composition changes continuously.
  • a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surfaces of the insulating layers 110s1 and 110s2 and a treatment for supplying oxygen to the insulating layers 110s1 and 110s2.
  • a heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere.
  • a plasma treatment can be performed in an atmosphere containing oxygen.
  • oxygen can be supplied to the insulating layers 110s1 and 110s2 by a plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (N 2 O).
  • oxygen can be supplied to the insulating layers 110s1 and 110s2 while organic substances on the surfaces of the insulating layers 110s1 and 110s2 are suitably removed. After such treatment, it is preferable to form a semiconductor film that will be the semiconductor layer 108 in succession without exposing the surfaces of the insulating layer 110s1 and the insulating layer 110s2 to the air.
  • the semiconductor layer 108 has a laminated structure, it is preferable to deposit a semiconductor film first and then deposit the next semiconductor film in succession without exposing the surface to the air.
  • the semiconductor layer 108 When the semiconductor layer 108 has a laminated structure, all layers constituting the semiconductor layer 108 can be formed by the same film formation method (for example, sputtering or ALD). Alternatively, different film formation methods can be used for different layers.
  • the first semiconductor layer can be formed by sputtering
  • the second semiconductor layer on the first semiconductor layer can be formed by ALD.
  • the first semiconductor layer can be formed by ALD
  • the second semiconductor layer on the first semiconductor layer can be formed by sputtering
  • the third semiconductor layer on the second semiconductor layer can be formed by ALD.
  • the semiconductor film that will become the semiconductor layer 108 is processed into an island shape to form the semiconductor layer 108 (FIGS. 18A to 18D).
  • the semiconductor layer 108 is formed so as to have an area that overlaps with the conductive layer 112a, the conductive layer 112b1, and the conductive layer 112b2 in the opening 143.
  • the semiconductor layer 108 is provided in contact with the upper surface and side surface of the conductive layer 112a in the opening 143, the upper surface of the substrate 102 in the opening 143, the side surface of the insulating layer 110s1 in the opening 143, the side surface of the insulating layer 110s2 in the opening 143, the curved portion of the insulating layer 110s1, the curved portion of the insulating layer 110s2, the upper surface and side surface of the conductive layer 112b1, the upper surface and side surface of the conductive layer 112b2, and the upper surface of the insulating layer 110.
  • wet etching can be suitably used to form the semiconductor layer 108.
  • parts of the substrate 102, insulating layer 110, conductive layer 112b1, and conductive layer 112b2 in regions that do not overlap with the semiconductor layer 108 may be etched and become thinner.
  • the heat treatment can remove hydrogen and water contained in the semiconductor film or the semiconductor layer 108, or adsorbed on the surface.
  • the heat treatment may also improve the film quality of the semiconductor film or the semiconductor layer 108 (for example, defects may be reduced or crystallinity may be improved).
  • oxygen can also be supplied from the insulating layers 110s1 and 110s2 to the semiconductor film that becomes the semiconductor layer 108 or to the semiconductor layer 108. This can reduce oxygen vacancies (V O ) in the channel formation regions of the transistors 10_1 and 10_2. At this time, it is more preferable to perform the heat treatment before processing the semiconductor film that becomes the semiconductor layer 108 into the semiconductor layer 108.
  • the above description can be referred to for the heat treatment, and detailed description thereof will be omitted.
  • oxygen may be supplied to the channel formation region in a process in which heat is applied after the formation of the semiconductor film that becomes the semiconductor layer 108 (for example, a process of forming the insulating layer 106).
  • this heat treatment does not have to be performed if it is not necessary. Also, instead of performing the heat treatment here, it is possible to combine this with a heat treatment performed in a later process. Also, there are cases where a high-temperature process in a later process (e.g., a film formation process) can also serve as the heat treatment.
  • the insulating layer 106 is formed to cover the semiconductor layer 108, the conductive layer 112b1, the conductive layer 112b2, the insulating layer 110, the conductive layer 112a, and the substrate 102.
  • the PECVD method or the ALD method can be suitably used to form the insulating layer 106.
  • the insulating layer 106 When a metal oxide is used for the semiconductor layer 108, the insulating layer 106 preferably functions as a barrier film that suppresses diffusion of oxygen.
  • the insulating layer 106 has a function of suppressing diffusion of oxygen, which suppresses diffusion of oxygen contained in the semiconductor layer 108 above the insulating layer 106, and thus can suppress an increase in oxygen vacancies ( VO ) in the semiconductor layer 108.
  • the transistors 10_1 and 10_2 which have favorable electrical characteristics and high reliability can be realized.
  • the insulating layer 106 can have fewer defects. However, if the temperature during the formation of the insulating layer 106 is high, oxygen is released from the semiconductor layer 108, and oxygen vacancies (V O ) and V O H in the semiconductor layer 108 may increase.
  • the substrate temperature during the formation of the insulating layer 106 is preferably 180° C. to 450° C., more preferably 200° C. to 450° C., further preferably 250° C. to 450° C., further preferably 300° C. to 450° C., and further preferably 300° C. to 400° C.
  • the transistors 10_1 and 10_2 having good electrical characteristics and high reliability can be realized.
  • a plasma treatment can be performed on the surface of the semiconductor layer 108.
  • the plasma treatment can reduce impurities (e.g., water) adsorbed on the surface of the semiconductor layer 108. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating layer 106 can be reduced, and highly reliable transistors 10_1 and 10_2 can be realized. This is particularly suitable for the case where the surface of the semiconductor layer 108 is exposed to the air between the formation of the semiconductor layer 108 and the formation of the insulating layer 106.
  • the plasma treatment can be performed in an atmosphere of, for example, oxygen, ozone, nitrogen, nitrous oxide, argon, or the like. In addition, it is preferable that the plasma treatment and the formation of the insulating layer 106 are performed successively without exposure to the air.
  • a conductive film that will become the conductive layer 104 is formed on the insulating layer 106.
  • sputtering, CVD, MBE, PLD, or ALD can be suitably used to form the conductive film.
  • the conductive film is preferably formed in the opening 143 in contact with the insulating layer 106 that faces the side of the insulating layer 110s1 and the side of the insulating layer 110s2. Therefore, the conductive film is preferably formed using a film formation method that has good coverage or embedding properties, and more preferably using a CVD method, ALD method, or the like.
  • the conductive film that becomes the conductive layer 104 is processed to form the conductive layer 104.
  • the conductive layer 104 is formed to have regions that overlap with the conductive layer 112a, the conductive layer 112b1, and the conductive layer 112b2.
  • the conductive layer 104 may be formed by a photolithography method. The above processing can be performed by a dry etching method or a wet etching method. Processing by a dry etching method is suitable for fine processing.
  • insulating layer 195 is formed to cover conductive layer 104 and insulating layer 106 ( Figures 1A to 2B).
  • Insulating layer 195 can be formed, for example, using the same materials and methods as insulating layers 110a1, 110a3, 110b1, and 110b3.
  • the above steps allow the semiconductor device 100 to be manufactured.
  • the two transistors (transistor 10_1 and transistor 10_2) included in the semiconductor device 100 can be formed simultaneously using the same material and through the same process.
  • This embodiment can be implemented by combining at least a portion of it with other embodiments described in this specification.
  • the semiconductor device according to one embodiment of the present invention can be applied to, for example, a display device.
  • a structural example of a display device according to one embodiment of the present invention will be described.
  • the display device of this embodiment can be a high-resolution display device or a large display device. Therefore, the display device of this embodiment can be used in electronic devices with relatively large screens, such as television devices, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • electronic devices with relatively large screens such as television devices, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • the display device of this embodiment can be a high-definition display device. Therefore, the display device of this embodiment can be used, for example, in the display section of a wristwatch-type or bracelet-type information terminal (wearable device), as well as in the display section of a wearable device that can be worn on the head, such as a head-mounted display (HMD) or other VR device, and a glasses-type AR device.
  • a wearable device such as a head-mounted display (HMD) or other VR device, and a glasses-type AR device.
  • HMD head-mounted display
  • AR device glasses-type AR device
  • the semiconductor device can be used in a display device or a module having the display device.
  • the module having the display device include a module in which a connector such as a flexible printed circuit board (hereinafter referred to as FPC) or TCP is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a COG method or a COF (chip on film) method, etc.
  • FPC flexible printed circuit board
  • IC integrated circuit
  • FIG. 19 shows a perspective view of the display device 50. As shown in FIG.
  • Display device 50 has a configuration in which substrate 152 and substrate 151 are bonded together.
  • substrate 152 is indicated by a dashed line.
  • the display device 50 has a display unit 162, a connection unit 140, a circuit unit 164, wiring 165, etc.
  • FIG. 19 shows an example in which an IC 173 and an FPC 172 are mounted on the display device 50. Therefore, the configuration shown in FIG. 19 can also be said to be a display module having the display device 50, an IC, and an FPC.
  • connection portion 140 is provided on the outside of the display portion 162.
  • the connection portion 140 can be provided along one side or multiple sides of the display portion 162. There may be one or multiple connection portions 140.
  • FIG. 19 shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion.
  • the connection portion 140 connects the common electrode of the display element and the conductive layer, and can supply a potential to the common electrode. Note that if the connection portion 140 is not required, such as when the common electrode is provided on the substrate 151 side, it does not have to be provided.
  • the circuit portion 164 has, for example, a scanning line driver circuit (also called a gate driver).
  • the circuit portion 164 may also have both a scanning line driver circuit and a signal line driver circuit (also called a source driver).
  • the wiring 165 has a function of supplying signals and power to the display unit 162 and the circuit unit 164.
  • the signals and power are input to the wiring 165 from the outside via the FPC 172, or are input to the wiring 165 from the IC 173.
  • FIG. 19 shows an example in which an IC 173 is provided on a substrate 151 by a COG method, a COF method, or the like.
  • an IC having one or both of a scanning line driver circuit and a signal line driver circuit can be used as the IC 173.
  • the display device 50 and the display module may be configured without an IC.
  • the IC may be mounted on an FPC by a COF method, or the like.
  • the vertical transistor included in the semiconductor device of one embodiment of the present invention can be applied to, for example, one or both of the display portion 162 and the circuit portion 164 of the display device 50.
  • the vertical transistor included in the semiconductor device of one embodiment of the present invention can also be applied to the IC 173.
  • the vertical transistor included in the semiconductor device of one embodiment of the present invention can be provided on a silicon wafer. In this case, it is preferable to provide a transistor using single crystal silicon for its semiconductor layer and a vertical transistor included in the semiconductor device of one embodiment of the present invention stacked above the transistor to form a circuit using two types of transistors.
  • a vertical transistor included in a semiconductor device according to one embodiment of the present invention when a vertical transistor included in a semiconductor device according to one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced compared to when a planar transistor is used, and a high-definition display device can be obtained.
  • a vertical transistor included in a semiconductor device according to one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced compared to when a planar transistor is used, and a display device with a narrow frame can be obtained.
  • the vertical transistor included in a semiconductor device according to one embodiment of the present invention has good electrical characteristics, the reliability of the display device can be improved by using the vertical transistor in the display device.
  • the display unit 162 is an area in the display device 50 that displays an image, and has a number of periodically arranged pixels 210.
  • Figure 19 shows an enlarged view of one pixel 210.
  • pixel arrangements there are no particular limitations on the pixel arrangement in the display device of this embodiment, and various methods can be applied. Examples of pixel arrangements include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.
  • the pixel 210 shown in FIG. 19 has a subpixel 210R that emits red light, a subpixel 210G that emits green light, and a subpixel 210B that emits blue light.
  • Each of the subpixels 210R, 210G, and 210B has a display element and a circuit that controls the driving of the display element.
  • the display element for example, a liquid crystal element can be used.
  • the device to be, for example, a transmissive liquid crystal display device, a reflective liquid crystal display device, or a semi-transmissive liquid crystal display device.
  • various elements can be used as display elements.
  • light-emitting elements include self-emitting light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), and semiconductor lasers. Examples of LEDs that can be used include mini LEDs and micro LEDs.
  • a shutter type or optical interference type MEMS (Micro Electro Mechanical Systems) element a display element using a microcapsule type, an electrophoresis type, an electrowetting type, or an electronic liquid powder (registered trademark) type.
  • a QLED (Quantum-dot LED) using a light source and color conversion technology using quantum dot material may be used.
  • FIG. 20 shows an example of a cross section of the display device 50, in which a portion of the area including the FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the area including the end portion are cut away.
  • Figure 20 is a schematic cross-sectional view of a VA mode liquid crystal element.
  • Substrate 151 and substrate 152 are bonded together by adhesive layer 141. Liquid crystal 122 is sealed in the area surrounded by substrate 151, substrate 152, and adhesive layer 141.
  • Substrate 152 has polarizing plate 130a on its outer surface.
  • Substrate 151 has polarizing plate 130b on its outer surface.
  • a backlight can be provided outside polarizing plate 130a or outside polarizing plate 130b.
  • the substrate 151 is provided with a semiconductor layer 108 that functions as a pixel electrode of the liquid crystal element 60, a semiconductor device 201, a plurality of semiconductor devices 202, a connection portion 204, wiring 206, a spacer 124, and the like.
  • the semiconductor device 100 described in the previous embodiment can be applied to the semiconductor device 202. That is, the semiconductor device 202 is a semiconductor device composed of two vertical transistors.
  • the semiconductor device 201 is a semiconductor device provided in the circuit portion 164, and the semiconductor device 202 is a semiconductor device provided in the display portion 162.
  • the semiconductor device 201 does not have the conductive layer 116_1 and the conductive layer 116_2 and has a vertical transistor with the conductive layer 104 as a gate electrode, but this is not limited to the above.
  • the semiconductor device 201 may also have a vertical transistor with a back gate electrode formed of the same material as the conductive layer 116_1 and the conductive layer 116_2.
  • the vertical transistor of the semiconductor device 201 has a shorter channel length than the two vertical transistors of the semiconductor device 202. Therefore, the vertical transistor of the semiconductor device 201 can have a larger on-current than the vertical transistor of the semiconductor device 202, and a display device capable of high-speed operation can be obtained.
  • the vertical transistor of the semiconductor device 201 has only one gate electrode (conductive layer 104), whereas the vertical transistor of the semiconductor device 202 has two gate electrodes (conductive layer 116_1 and conductive layer 104, or conductive layer 116_2 and conductive layer 104).
  • the vertical transistor of the semiconductor device 202 can fix the potential of the back gate electrode side of the semiconductor layer 108 more than the vertical transistor of the semiconductor device 201, and therefore the threshold voltage can be normally off. In addition, it is possible to suppress variation in the electrical characteristics of the transistors in the semiconductor device 202.
  • the substrate 152 is provided with a colored layer 131, a light-shielding layer 132, an insulating layer 123, a common electrode 113, etc.
  • Insulating layers such as insulating layer 110a1, insulating layer 110a2, insulating layer 110a3, insulating layer 110b3, insulating layer 110b2, insulating layer 110b1, insulating layer 106, insulating layer 195, etc. are provided on substrate 151.
  • Insulating layer 110a1, insulating layer 110a2, insulating layer 110a3, insulating layer 110b3, insulating layer 110b2, and insulating layer 110b1 function as interlayer insulating layers (or spacers).
  • a part of insulating layer 106 functions as a gate insulating layer of a transistor included in semiconductor device 201 or a transistor included in semiconductor device 202.
  • Insulating layer 195 functions as a protective layer for semiconductor device 201 and semiconductor device 202.
  • the semiconductor device 202 has a conductive layer 112a, a conductive layer 112b1, a conductive layer 112b2, an insulating layer 110s1, an insulating layer 110s2, a conductive layer 116_1, a conductive layer 116_2, a semiconductor layer 108, a part of the insulating layer 106, and a conductive layer 104.
  • the conductive layer 112b2 of the semiconductor device 202 functions as a part of a pixel electrode.
  • the conductive layer 112a functions as one of a source electrode or a drain electrode of a transistor included in the semiconductor device 201 or a transistor included in the semiconductor device 202, and the conductive layer 112b1 and the conductive layer 112b2 function as the other of a source electrode or a drain electrode of a transistor included in the semiconductor device 201 or a transistor included in the semiconductor device 202.
  • the insulating layer 110s1 and the insulating layer 110s2 function as a gate insulating layer (first gate insulating layer) of a transistor included in the semiconductor device 202.
  • the conductive layer 116_1 and the conductive layer 116_2 function as gate electrodes (first gate electrodes) of the transistors included in the semiconductor device 202.
  • part of the insulating layer 106 functions as a gate insulating layer (second gate insulating layer) of the transistors included in the semiconductor device 201 or the transistors included in the semiconductor device 202.
  • the conductive layer 104 functions as a gate electrode (second gate electrode) of the transistors included in the semiconductor device 201 or the transistors included in the semiconductor device 202.
  • the conductive layer 112a2 is provided on and in contact with the conductive layer 112a1.
  • the conductive layer 112a2 contains a conductive material having a higher conductivity than the conductive layer 112a1 and functions as an auxiliary wiring.
  • a conductive oxide is used for the conductive layer 112a1, it may be difficult to use it as a wiring due to high resistance.
  • the conductive layer 112a2 having a higher conductivity than the conductive layer 112a1 is provided to supplement the conductivity of the conductive layer 112a1. It can be said that the stacked structure combining the conductive layer 112a1 and the conductive layer 112a2 corresponds to the conductive layer 112a in the semiconductor device 100 described above.
  • the conductive layer 112a2 is provided on the conductive layer 112a1 here, the conductive layer 112a2 may be provided below the conductive layer 112a1. Although not shown here, it is preferable to provide a similar conductive layer in contact with the conductive layer 112b1 and the conductive layer 112b2.
  • the liquid crystal element 60 has a part of the conductive layer 112b2 that functions as a pixel electrode, a common electrode 113, and liquid crystal 122 sandwiched between them.
  • FIG. 20 also shows cross sections of two subpixels as an example of the display unit 162.
  • One subpixel has at least a semiconductor device 202, a liquid crystal element 60, and a colored layer 131.
  • a full-color display can be achieved by selectively forming the colored layer 131 and arranging subpixels that exhibit red, green, and blue colors.
  • a pixel circuit (subpixel circuit) is configured by the semiconductor device 202, a portion of the conductive layer 112b2 that functions as a pixel electrode, wiring, etc.
  • the semiconductor device 201 included in the circuit portion 164 and the semiconductor device 202 included in the display portion 162 have different structures, but they may have the same structure.
  • the multiple semiconductor devices included in the circuit portion 164 may all have the same structure, or semiconductor devices with different structures (e.g., semiconductor device 100, any of semiconductor devices 100A to 100F) may be used in combination.
  • the insulating layer 195 covering the semiconductor device 201 and the semiconductor device 202 is preferably made of a material that is difficult for impurities such as water or hydrogen to diffuse into.
  • the insulating layer 195 can function as a barrier film.
  • an insulating layer 123 is provided to cover the colored layer 131 and the light-shielding layer 132.
  • the insulating layer 123 may function as a planarizing film.
  • the insulating layer 123 can make the surface of the common electrode 113 roughly flat, so that the orientation state of the liquid crystal 122 can be made uniform.
  • an alignment film for controlling the alignment of the liquid crystal 122 may be provided on the surfaces of the common electrode 113, the insulating layer 195, etc. that come into contact with the liquid crystal 122.
  • a display device to which the liquid crystal element 60 is applied can be a transmissive liquid crystal display device.
  • a backlight is disposed on the substrate 152 side
  • light from the backlight polarized by the polarizing plate 130a passes through the substrate 152, the common electrode 113, the liquid crystal 122, the conductive layer 112b2, the substrate 151, etc., and reaches the polarizing plate 130b.
  • the orientation of the liquid crystal 122 can be controlled by the voltage applied between the conductive layer 112b2 and the common electrode 113, and the optical modulation of light can be controlled.
  • the intensity of the light emitted through the polarizing plate 130b can be controlled.
  • the light other than the specific wavelength region of the incident light is absorbed by the colored layer 131, so that the extracted light is, for example, red light.
  • a linear polarizing plate may be used as polarizing plate 130b, but a circular polarizing plate may also be used.
  • a circular polarizing plate for example, a linear polarizing plate and a quarter-wave retardation plate stacked together may be used.
  • a circular polarizing plate for polarizing plate 130b it is possible to suppress reflection of external light.
  • polarizer 130b When a circular polarizer is used as polarizer 130b, a circular polarizer may also be used for polarizer 130a, or a normal linear polarizer may be used.
  • the desired contrast can be achieved by adjusting the cell gap, orientation, drive voltage, etc. of the liquid crystal element used in liquid crystal element 60 according to the type of polarizer used for polarizers 130a and 130b.
  • the common electrode 113 is connected to a conductive layer provided on the substrate 151 side at the connection portion 140 by a connector 243. This allows a potential or signal to be supplied to the common electrode 113 from an FPC or IC arranged on the substrate 151 side.
  • conductive particles can be used.
  • the conductive particles particles of organic resin or silica, etc., whose surfaces are coated with a metal material can be used.
  • Nickel or gold is preferably used as the metal material because it can reduce the contact resistance. It is also preferable to use particles coated with two or more metal materials in layers, such as nickel further coated with gold. It is also preferable to use a material that undergoes elastic or plastic deformation as the connector 243. In this case, the conductive particles may be crushed in the vertical direction as shown in FIG. 20. This increases the contact area between the connector 243 and the conductive layer connected thereto, reducing the contact resistance and suppressing the occurrence of defects such as poor connection.
  • the connectors 243 are preferably arranged so that they are covered by the adhesive layer 141.
  • the connectors 243 may be dispersed in the adhesive layer 141 before it hardens.
  • the connectors 243 can be similarly applied to any configuration in which the adhesive layer 141 is used in the periphery, such as a display device with a solid sealing structure or a hollow sealing structure.
  • connection portion 204 is provided in a region near the end of the substrate 151.
  • the wiring 206 is connected to the FPC 172 via a connection layer 242.
  • the wiring 206 has an example of a layered structure similar to that of the conductive layer 112a1 and the conductive layer 112a2.
  • the electrode that connects to the connector 243 in the connection portion 140 and the electrode that connects to the connection layer 242 in the connection portion 204 are formed in the same process using the same conductive film as the conductive layers 112b1 and 112b2. This makes it possible to prevent contact failures caused by the exposed portions of the connection portion 140 and the connection portion 204 being oxidized to form an insulating coating, and to realize a highly reliable display device.
  • This embodiment can be implemented by combining at least a portion of it with other embodiments described in this specification.
  • the display device shown in FIG. 21A has a pixel portion 502, a driver circuit portion 504, a protection circuit 506, and a terminal portion 507. Note that the protection circuit 506 may not be provided.
  • a transistor according to one embodiment of the present invention can be applied to one or both of the pixel portion 502 and the driver circuit portion 504.
  • a transistor according to one embodiment of the present invention can also be applied to the protection circuit 506.
  • the pixel section 502 has a plurality of pixel circuits 501 arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more).
  • Each pixel circuit 501 has a circuit that drives a display element.
  • the driver circuit unit 504 has driver circuits such as a gate driver 504a that outputs scanning signals to the gate lines GL_1 to GL_X, and a source driver 504b that supplies data signals to the data lines DL_1 to DL_Y.
  • the gate driver 504a may have at least a shift register.
  • the source driver 504b may be configured using a shift register, a digital-to-analog conversion circuit, a latch circuit, etc.
  • the terminal section 507 is a section that has terminals for inputting power, control signals, image signals, etc. from an external circuit to the display device.
  • the protection circuit 506 is a circuit that connects a wiring to which it is connected to another wiring when a potential outside a certain range is applied to the wiring.
  • the protection circuit 506 shown in FIG. 21A is connected to various wirings such as a gate line GL and a data line DL. Note that in FIG. 21A, the protection circuit 506 is shown with a hatched pattern to distinguish it from the pixel circuit 501.
  • the gate driver 504a and the source driver 504b may be provided on the same substrate as the pixel section 502, or an IC on which a gate driver circuit or a source driver circuit is separately formed may be mounted on the substrate on which the pixel section 502 is provided, using a COG method or the like.
  • an FPC on which an IC is mounted may be attached to the substrate using an ACF (Anisotropic Conductive Film) or the like.
  • the pixel portion 502 and the gate driver 504a are preferably manufactured over the same substrate and through the same process. At this time, it is preferable to provide a transistor of one embodiment of the present invention in each of the pixel portion 502 and the gate driver 504a. Furthermore, when an IC is used for the source driver 504b, it is preferable to provide a demultiplexer circuit over the substrate because the number of terminals of the IC can be reduced. At this time, it is preferable to apply a transistor of one embodiment of the present invention to the demultiplexer circuit.
  • FIG. 21B shows an example of a pixel circuit configuration that can be applied to pixel circuit 501.
  • the pixel circuit 501 shown in FIG. 21B includes a liquid crystal element 570, a transistor 550, and a capacitor element 560.
  • the pixel circuit 501 is also connected to a data line DL_n, a gate line GL_m, a potential supply line VL, and the like.
  • the vertical transistor of one embodiment of the present invention can be applied to the transistor 550.
  • FIG. 21B shows a configuration in which the transistor 550 has two gates, one of which (the first gate) is connected to the gate line GL_m, and the other (the second gate, back gate) is not explicitly connected to the gate line GL_m.
  • the first gate of the transistor 550 corresponds to the conductive layer 116_1 or the conductive layer 116_2 of the transistor 10_1 or the transistor 10_2 included in the semiconductor device 100 shown in FIG. 1B and the like, and the second gate corresponds to the conductive layer 104.
  • the second gate of the transistor 550 is not explicitly connected to the gate line GL_m, a ground potential or any potential can be applied to the second gate of the transistor 550 as described in embodiment 1.
  • the second gate electrode of the transistor 550 can function as, for example, a capacitance electrode.
  • the potential of one of the pair of electrodes of the liquid crystal element 570 is set appropriately according to the specifications of the pixel circuit 501.
  • the orientation state of the liquid crystal element 570 is set by the data written thereto.
  • a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 in each of the multiple pixel circuits 501.
  • a different potential may be applied to one of the pair of electrodes of the liquid crystal element 570 in the pixel circuit 501 in each row.
  • the pixel circuit 501 shown in FIG. 21C includes a transistor 552, a transistor 554, a capacitor 562, and a light-emitting element 572.
  • the pixel circuit 501 is connected to a data line DL_n, a gate line GL_m, a potential supply line VL_a, a potential supply line VL_b, and the like.
  • a high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b, and a low power supply potential VSS is applied to the other.
  • the current flowing through the light-emitting element 572 is controlled according to the potential applied to the gate of the transistor 554, thereby controlling the light emission brightness from the light-emitting element 572.
  • a vertical transistor according to one embodiment of the present invention can be used for one or both of the transistors 552 and 554. Note that although FIG. 21C shows a configuration in which both the transistors 552 and 554 have second gates, the connection destination of the second gates is not shown. For the second gates of the transistors 552 and 554, the above description of the second gate of the transistor 550 can be referred to.
  • FIG. 22A shows a circuit diagram of a pixel circuit 400.
  • the pixel circuit 400 has a transistor M1, a transistor M2, a capacitor C1, and a circuit 401.
  • the pixel circuit 400 is connected to wiring S1, wiring S2, wiring G1, and wiring G2.
  • Transistor M1 and transistor M2 can be vertical transistors according to one embodiment of the present invention. Note that although FIG. 22A shows a configuration in which both transistor M1 and transistor M2 have a second gate, the connection destination of the second gate is not shown. For the second gates of transistor M1 and transistor M2, the above description of the second gate of transistor 550 can be referred to. The same applies to transistors M1, M2, and M3 shown in FIGS. 22C and 22D.
  • the gate of the transistor M1 is connected to the wiring G1, one of the source or drain is connected to the wiring S1, and the other is connected to one electrode of the capacitance C1.
  • the gate of the transistor M2 is connected to the wiring G2, one of the source or drain is connected to the wiring S2, and the other is connected to the other electrode of the capacitance C1 and the circuit 401.
  • Circuit 401 is a circuit that includes at least one display element.
  • the display element is a liquid crystal element.
  • the node connecting transistor M1 and capacitor C1 is node N1
  • the node connecting transistor M2 and circuit 401 is node N2.
  • the pixel circuit 400 can maintain the potential of node N1 by turning off transistor M1. Also, the pixel circuit 400 can maintain the potential of node N2 by turning off transistor M2. Also, by writing a predetermined potential to node N1 via transistor M1 while transistor M2 is turned off, the potential of node N2 can be changed according to the change in the potential of node N1 due to capacitive coupling via capacitor C1.
  • the transistor using an oxide semiconductor as exemplified in embodiment 1 can be used as one or both of the transistors M1 and M2. Therefore, the potential of the node N1 or the node N2 can be held for a long period of time due to an extremely low off-current. Note that when the period during which the potential of each node is held is short (specifically, when the frame frequency is 30 Hz or more), a transistor using a semiconductor such as silicon may be used.
  • Fig. 22B is a timing chart relating to the operation of the pixel circuit 400. Note that, in order to simplify the description, the influence of various resistances such as wiring resistance, parasitic capacitance, threshold voltage of a transistor, and the like is not taken into consideration here.
  • Period T1 is a period in which a potential is written to node N2
  • period T2 is a period in which a potential is written to node N1.
  • Period T1 In the period T1, a potential that turns on the transistor is applied to both the wiring G1 and the wiring G2. A fixed potential Vref is supplied to the wiring S1, and a first data potential Vw is supplied to the wiring S2.
  • the node N1 is supplied with a potential Vref from the wiring S1 through the transistor M1.
  • the node N2 is supplied with a first data potential Vw from the wiring S2 through the transistor M2. Therefore, the potential difference Vw - Vref is held in the capacitor C1.
  • Period T2 In the next period T2, a potential that turns on the transistor M1 is applied to the wiring G1, and a potential that turns off the transistor M2 is applied to the wiring G2.
  • a second data potential Vdata is supplied to the wiring S1.
  • a predetermined constant potential is applied to the wiring S2, or the wiring S2 may be in a floating state.
  • the second data potential Vdata is applied to the node N1 from the wiring S1 through the transistor M1.
  • the potential of the node N2 changes by a potential dV in response to the second data potential Vdata due to capacitive coupling by the capacitor C1. That is, a potential obtained by adding the first data potential Vw and the potential dV is input to the circuit 401.
  • the potential dV is shown to be a positive value in FIG. 22B, it may be a negative value. That is, the second data potential Vdata may be lower than the potential Vref .
  • the potential dV is roughly determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401.
  • the potential dV becomes close to the second data potential Vdata .
  • the pixel circuit 400 can combine two types of data signals to generate a potential to be supplied to the circuit 401 including the display element, making it possible to perform gradation correction within the pixel circuit 400.
  • the pixel circuit 400 can also generate a potential that exceeds the maximum potential that can be supplied by the source driver connected to the wiring S1 and wiring S2. For example, when a light-emitting element is used, a high dynamic range (HDR) display can be performed. When a liquid crystal element is used, overdrive driving can be realized.
  • HDR high dynamic range
  • Example using liquid crystal element 22C includes a circuit 401LC.
  • the circuit 401LC includes a liquid crystal element LC and a capacitor C2.
  • One electrode of the liquid crystal element LC is connected to the node N2 and one electrode of the capacitor C2, and the other electrode is connected to a wiring to which a potential V com2 is applied.
  • the other electrode of the capacitor C2 is connected to a wiring to which a potential V com1 is applied.
  • Capacitor C2 functions as a storage capacitor. Note that capacitor C2 can be omitted if not required.
  • the pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, which makes it possible, for example, to realize high-speed display by overdriving and to apply liquid crystal materials with high driving voltages.
  • a correction signal to the wiring S1 or wiring S2, it is possible to correct the gradation according to the operating temperature, the deterioration state of the liquid crystal element LC, etc.
  • Example using light-emitting element 22D includes a circuit 401EL.
  • the circuit 401EL includes a light-emitting element EL, a transistor M3, and a capacitor C2.
  • the transistor M3 has a gate connected to the node N2 and one electrode of the capacitor C2, a source or drain connected to a wiring to which a potential VH is applied, and the other connected to one electrode of the light-emitting element EL.
  • the other electrode of the capacitor C2 is connected to a wiring to which a potential Vcom is applied.
  • the other electrode of the light-emitting element EL is connected to a wiring to which a potential VL is applied.
  • Transistor M3 has the function of controlling the current supplied to the light-emitting element EL.
  • Capacitor C2 functions as a storage capacitor. Capacitor C2 can be omitted if not required.
  • the cathode side of the light-emitting element EL may be connected to the transistor M3.
  • the values of the potentials VH and VL can be appropriately changed.
  • the pixel circuit 400EL can achieve, for example, HDR display by applying a high potential to the gate of the transistor M3 to pass a large current through the light-emitting element EL.
  • a correction signal to the wiring S1 or wiring S2, it is also possible to correct variations in the electrical characteristics of the transistor M3, the light-emitting element EL, etc.
  • circuit is not limited to the example circuits shown in Figures 22C and 22D, and may include additional transistors, capacitance, etc.
  • This embodiment can be implemented by combining at least a portion of it with other embodiments described in this specification.
  • FIG. 23 shows a block diagram of the touch panel module 6500.
  • the touch panel module 6500 has a touch panel 6510 and an IC 6520.
  • the touch panel 6510 has a display portion 6511, an input portion 6512, a scanning line driver circuit 6513, a sensor driver circuit 6503, and a detection circuit 6504.
  • the display portion 6511 has a plurality of pixels, a plurality of signal lines, and a plurality of scanning lines, and has a function of displaying an image.
  • the input portion 6512 has a plurality of sensor elements that detect contact or proximity of a detectable object to the touch panel 6510, and has a function as a touch sensor.
  • the scanning line driver circuit 6513 has a function of outputting a scanning signal to the scanning line of the display portion 6511.
  • the sensor driving circuit 6503 has a function of outputting a signal that drives the sensor element of the input unit 6512.
  • the sensor driving circuit 6503 can be configured by combining a shift register circuit and a buffer circuit.
  • the detection circuit 6504 has the function of amplifying the output signal from the sensor element of the input unit 6512 and outputting it to the AD conversion circuit 6507.
  • the touch panel 6510 is shown here as being composed of a separate display section 6511 and input section 6512, but it may be a so-called in-cell type touch panel that has both the function of displaying images and the function of acting as a touch sensor.
  • a capacitance type can be applied as a touch sensor type that can be used as the input unit 6512.
  • capacitance types include a surface capacitance type and a projected capacitance type.
  • projected capacitance types include a self-capacitance type and a mutual capacitance type. The mutual capacitance type is preferable because it allows simultaneous multi-point detection.
  • various types of sensors that can detect the approach, contact, or pressure of a detectable object such as a finger or stylus can also be applied to the input unit 6512.
  • various types of sensors can be used, such as a resistive film type, a surface acoustic wave type, an infrared type, and an optical type.
  • Typical in-cell touch panels include hybrid in-cell and full in-cell.
  • the hybrid in-cell type refers to a configuration in which electrodes constituting a touch sensor are provided on both the substrate supporting the display element and the opposing substrate, or on the opposing substrate.
  • the full in-cell type refers to a configuration in which electrodes constituting a touch sensor are provided on the substrate supporting the display element.
  • a full in-cell touch panel is preferable because it can simplify the configuration of the opposing substrate.
  • a full in-cell type in which the electrodes constituting the display element also serve as the electrodes constituting the touch sensor is preferable because it can simplify the manufacturing process and reduce manufacturing costs.
  • the display unit 6511 preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels). In particular, a resolution of 4K, 8K, or higher is preferable.
  • the pixel density (resolution) of the pixels provided in the display unit 6511 is preferably 300 ppi or more, preferably 500 ppi or more, more preferably 800 ppi or more, more preferably 1000 ppi or more, and more preferably 1200 ppi or more.
  • the display unit 6511 having such high resolution and high resolution makes it possible to enhance the sense of realism and depth.
  • the IC 6520 has a circuit unit 6501, a signal line driver circuit 6502, and an AD conversion circuit 6507.
  • the circuit unit 6501 has a timing controller 6505, an image processing circuit 6506, etc.
  • the signal line driver circuit 6502 has a function of outputting an analog image signal (also called a video signal) to a signal line of the display portion 6511.
  • the signal line driver circuit 6502 can have a configuration in which a shift register, a digital-analog converter (DAC), a latch circuit, a buffer circuit, and the like are combined.
  • the touch panel 6510 may also have a demultiplexer circuit connected to the signal line.
  • the AD conversion circuit 6507 has a function of converting an analog signal input from the detection circuit 6504 into a digital signal and outputting it to the circuit unit 6501.
  • the AD conversion circuit 6507 can have a configuration including an amplifier circuit in addition to an analog-digital conversion circuit (ADC: Analog-Digital Converter).
  • the image processing circuit 6506 of the circuit unit 6501 has a function of generating and outputting a signal that drives the display unit 6511 of the touch panel 6510, a function of generating and outputting a signal that drives the input unit 6512, and a function of analyzing the signal output from the input unit 6512 and outputting it to the CPU 6540.
  • the image processing circuit 6506 has a function of generating a video signal according to an instruction from the CPU 6540.
  • the image processing circuit 6506 also has a function of performing signal processing on the video signal in accordance with the specifications of the display unit 6511, converting it into an analog video signal, and supplying it to the signal line driving circuit 6502.
  • the image processing circuit 6506 also has a function of generating a driving signal to be output to the sensor driving circuit 6503 according to an instruction from the CPU 6540.
  • the image processing circuit 6506 also has a function of analyzing a signal input from the detection circuit 6504 via the AD conversion circuit 6507, and outputting it to the CPU 6540 as position information.
  • the timing controller 6505 has a function of generating and outputting signals (signals such as a clock signal and a start pulse signal) to be output to the scanning line driving circuit 6513 and the sensor driving circuit 6503 based on a synchronization signal included in the video signal processed by the image processing circuit 6506.
  • the timing controller 6505 may also have a function of generating and outputting a signal that specifies the timing at which the detection circuit 6504 outputs a signal.
  • the timing controller 6505 outputs a signal that is synchronized with the signal to be output to the scanning line driving circuit 6513 and the signal to be output to the sensor driving circuit 6503.
  • the touch panel 6510 can be driven by dividing one frame period into a period in which pixel data is rewritten and a period in which sensing is performed. For example, by providing two or more sensing periods in one frame period, the detection sensitivity and detection accuracy can be improved.
  • the image processing circuit 6506 may have a processor, for example.
  • a microprocessor such as a DSP (Digital Signal Processor) or a GPU (Graphics Processing Unit) may be used. These microprocessors may also be implemented using a PLD (Programmable Logic Device) such as an FPGA (Field Programmable Gate Array) or an FPAA (Field Programmable Analog Array).
  • PLD Programmable Logic Device
  • FPGA Field Programmable Gate Array
  • FPAA Field Programmable Analog Array
  • the image processing circuit 6506 performs various data processing, program control, etc. by interpreting and executing commands from various programs using the processor. Programs that can be executed by the processor may be stored in a memory area of the processor, or may be stored in a separately provided storage device.
  • the transistor that uses an oxide semiconductor in a channel formation region and has extremely low off-current in at least one of the display portion 6511, the input portion 6512, the scanning line driver circuit 6513, the sensor driver circuit 6503, and the detection circuit 6504 of the touch panel 6510. Since the off-current of the transistor is extremely low, the data retention period can be secured for a long period by using the transistor as a switch for retaining charge (data) flowing into a capacitor that functions as a memory element.
  • the transistor may be applied to the circuit unit 6501, the signal line driver circuit 6502, the AD conversion circuit 6507, the CPU 6540 provided externally, or the like, which are included in the IC 6520.
  • the image processing circuit 6506 operates only when necessary, and in other cases, the information of the immediately preceding processing is saved in the storage element, thereby enabling so-called normally-off computing, in which the power supply to the image processing circuit 6506 is cut off when not in use, thereby enabling low power consumption of the touch panel module 6500 and the electronic device in which it is implemented.
  • the circuit unit 6501 has a configuration including a timing controller 6505 and an image processing circuit 6506, but the image processing circuit 6506 itself, or a circuit having some of the functions of the image processing circuit 6506, may be provided outside the IC 6520. Alternatively, the functions of the image processing circuit 6506, or some of the functions, may be performed by the CPU 6540.
  • the circuit unit 6501 may have a configuration including a signal line driver circuit 6502, a timing controller 6505, and an AD conversion circuit 6507.
  • the circuit unit 6501 may not be included in the IC 6520.
  • the IC 6520 may have a signal line driver circuit 6502 and an AD conversion circuit 6507.
  • an IC including the circuit unit 6501 may be provided separately, and multiple ICs 6520 that do not have the circuit unit 6501 may be arranged, or the IC 6520 may be combined with an IC that only has the signal line driver circuit 6502.
  • 24A to 24C are schematic diagrams of a touch panel module 6500 incorporating an IC 6520.
  • the touch panel module 6500 shown in FIG. 24A includes a substrate 6531, an opposing substrate 6532, multiple FPCs 6533, an IC 6520, an IC 6530, etc. Also, between the substrate 6531 and the opposing substrate 6532, there are a display section 6511, an input section 6512, a scanning line driving circuit 6513, a sensor driving circuit 6503, and a detection circuit 6504. The IC 6520 and the IC 6530 are mounted on the substrate 6531 by a mounting method such as the COG method.
  • the IC6530 is an IC similar to the IC6520 described above, which has only the signal line driver circuit 6502, or has the signal line driver circuit 6502 and the circuit unit 6501. Signals are supplied to the IC6520 and IC6530 from the outside via the FPC6533. Also, a signal can be output from the IC6520 or IC6530 to the outside via the FPC6533.
  • FIG. 24A shows an example of a configuration in which two scanning line driver circuits 6513 are provided to sandwich the display portion 6511. Also, a configuration having an IC 6530 in addition to an IC 6520 is shown. This type of configuration can be suitably used when the display portion 6511 has extremely high resolution.
  • FIG. 24B shows an example where one IC 6520 and one FPC 6533 are mounted. By consolidating the functions into one IC 6520 in this way, the number of parts can be reduced, which is preferable. Also, FIG. 24B shows an example where the scanning line driver circuit 6513 is arranged along one of the two short sides of the display portion 6511 that is closer to the FPC 6533.
  • FIG. 24C shows an example of a configuration having a PCB (Printed Circuit Board) 6534 on which an image processing circuit 6506 and the like are mounted.
  • ICs 6520 and 6530 on a substrate 6531 are connected to PCB 6534 by an FPC 6533.
  • FPC 6533 a configuration that does not have the image processing circuit 6506 described above can be applied to IC 6520.
  • IC6520 and IC6530 may be mounted on FPC6533 instead of substrate 6531.
  • IC6520 and IC6530 may be mounted on FPC6533 by a mounting method such as COF or TAB.
  • a configuration in which the FPC 6533, IC 6520 (and IC 6530), etc. are arranged on the short side of the display section 6511 allows for a narrow frame, and is therefore suitable for use in electronic devices such as smartphones, mobile phones, and tablet terminals.
  • a configuration using a PCB 6534 as shown in Figure 24C can be suitable for use in television devices, monitor devices, tablet terminals, and notebook personal computers, for example.
  • This embodiment can be implemented by combining at least a portion of it with other embodiments described in this specification.
  • the electronic device of this embodiment has a display device of one embodiment of the present invention in a display portion.
  • the display device of one embodiment of the present invention can easily achieve high definition and high resolution. Therefore, it can be used in the display portion of various electronic devices.
  • the semiconductor device of one embodiment of the present invention can also be applied to portions other than the display portion of electronic devices.
  • portions other than the display portion of electronic devices For example, by using the semiconductor device of one embodiment of the present invention in a control portion of an electronic device, it is possible to reduce power consumption, which is preferable.
  • Electronic devices include, for example, electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • the display device of one embodiment of the present invention can be used in electronic devices having a relatively small display area because it is possible to increase the resolution.
  • electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, glasses-type AR devices, and MR devices.
  • the electronic device of this embodiment may have a sensor (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • a sensor including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • the electronic device of this embodiment can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.
  • a function to display various information still images, videos, text images, etc.
  • a touch panel function a function to display a calendar, date or time, etc.
  • a function to execute various software (programs) a wireless communication function
  • a function to read out programs or data recorded on a recording medium etc.
  • the electronic device 7000 shown in FIG. 25A is a portable information terminal that can be used as a smartphone.
  • the electronic device 7000 includes a housing 7001, a display unit 7002, a power button 7003, a button 7004, a speaker 7005, a microphone 7006, a camera 7007, and a light source 7008.
  • the display unit 7002 has a touch panel function.
  • a display device can be applied to the display portion 7002.
  • FIG. 25B is a schematic cross-sectional view including the end of the housing 7001 on the microphone 7006 side.
  • a translucent protective member 7010 is provided on the display surface side of the housing 7001, and a display panel 7011, optical members 7012, a touch sensor panel 7013, a printed circuit board 7017, a battery 7018, etc. are arranged in the space surrounded by the housing 7001 and the protective member 7010.
  • the display panel 7011, the optical member 7012, and the touch sensor panel 7013 are fixed to the protective member 7010 by an adhesive layer (not shown).
  • a part of the display panel 7011 is folded back in the area outside the display unit 7002, and an FPC 7015 is connected to the folded back part.
  • An IC 7016 is mounted on the FPC 7015.
  • the FPC 7015 is connected to a terminal provided on a printed circuit board 7017.
  • the display device according to one embodiment of the present invention can be applied to the display panel 7011. Therefore, an extremely lightweight electronic device can be realized.
  • the display panel 7011 is extremely thin, a large-capacity battery 7018 can be mounted thereon while keeping the thickness of the electronic device small.
  • an electronic device with a narrow frame can be realized.
  • FIG. 25C shows an example of a television device.
  • a display unit 7002 is built into a housing 7101.
  • the housing 7101 is supported by a stand 7103.
  • the display device of one embodiment of the present invention can be applied to the display portion 7002.
  • the television set 7100 shown in FIG. 25C can be operated using operation switches on the housing 7101 and a separate remote control 7111.
  • the display portion 7002 may be provided with a touch sensor, and the television set 7100 may be operated by touching the display portion 7002 with a finger or the like.
  • the remote control 7111 may have a display portion that displays information output from the remote control 7111.
  • the channel and volume can be operated using operation keys or a touch panel on the remote control 7111, and the image displayed on the display portion 7002 can be operated.
  • the television device 7100 is configured to include a receiver and a modem.
  • the receiver can receive general television broadcasts.
  • by connecting to a wired or wireless communication network via the modem it is also possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.
  • FIG. 25D shows an example of a notebook personal computer.
  • the notebook personal computer 7200 has a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, etc.
  • a display unit 7002 is built into the housing 7211.
  • a display device can be applied to the display portion 7002.
  • Figures 25E and 25F show an example of digital signage.
  • the digital signage 7300 shown in FIG. 25E has a housing 7301, a display unit 7002, and a speaker 7303. It can also have LED lamps, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, etc.
  • FIG. 25F shows digital signage 7400 attached to a cylindrical pole 7401.
  • Digital signage 7400 has a display unit 7002 that is provided along the curved surface of pole 7401.
  • a display device can be applied to the display portion 7002.
  • a touch panel By applying a touch panel to the display unit 7002, not only can images or videos be displayed on the display unit 7002, but the user can also intuitively operate it, which is preferable. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.
  • the digital signage 7300 or the digital signage 7400 can be linked via wireless communication with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user.
  • advertising information displayed on the display unit 7002 can be displayed on the screen of the information terminal 7311 or the information terminal 7411.
  • the display on the display unit 7002 can be switched by operating the information terminal 7311 or the information terminal 7411.
  • the digital signage 7300 or the digital signage 7400 can also be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.
  • This embodiment can be implemented by combining at least a portion of it with other embodiments described in this specification.

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012174836A (ja) * 2011-02-21 2012-09-10 Fujitsu Ltd 縦型電界効果トランジスタとその製造方法及び電子機器
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP2022049605A (ja) * 2020-09-16 2022-03-29 キオクシア株式会社 半導体装置及び半導体記憶装置
CN114792735A (zh) * 2021-01-26 2022-07-26 华为技术有限公司 薄膜晶体管、存储器及制作方法、电子设备

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012174836A (ja) * 2011-02-21 2012-09-10 Fujitsu Ltd 縦型電界効果トランジスタとその製造方法及び電子機器
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP2022049605A (ja) * 2020-09-16 2022-03-29 キオクシア株式会社 半導体装置及び半導体記憶装置
CN114792735A (zh) * 2021-01-26 2022-07-26 华为技术有限公司 薄膜晶体管、存储器及制作方法、电子设备

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